Impress
CMPSC-F353
Architecture of Comp Systems
Microprogrammed Control
1) Control Memory
A memory is part of a control unit : Microprogram
Computer Memory (employs a microprogrammed control unit)
Main Memory : for storing user program (Machine instruction/data)
Control Memory : for storing microprogram (Microinstruction)
2) Control Address Register
Specify the address of the microinstruction
Microprogrammed Control Organization
M..Morris Mano. 1993. Computer System Architecture (3rd ed.). Pearson, Page 214
3) Sequencer (= Next Address Generator)
Determine the address sequence that is read from control memory
Address of the next microinstruction can be specified in several ways depending on the sequencer input
4) Control Data Register (= Pipeline Register )
Hold the microinstruction read from control memory
RISC Architecture Concept
RISC(Reduced Instruction Set Computer) system use hardwired control rather than microprogrammed control : Sec. 8-8
Microprogrammed Control Organization
3
Address Sequencing = Sequencer : Next Address Generator
Selection of address for control memory
Routine
Microinstruction are stored in control memory in groups ( each group specifying a routine)
Mapping
Instruction Code Address in control memory(where the routine is)
Address Sequencing Capabilities : control memory address
1) Incrementing of the control address register
2) Unconditional branch or conditional branch, depending on status bit conditions
3) Mapping process
( bits of the instruction address for control memory )
4) A facility for subroutine return
Address Sequencing
Multiplexer
CAR Increment
JMP/CALL
Mapping
Subroutine Return
CAR : Control Address Register
CAR receive the address from
4 different paths
1) Incrementer
2) Branch address from
control memory
3) Mapping Logic
4) SBR : Subroutine Register
SBR : Subroutine Register
Return Address can not be stored
in ROM
Return Address for a subroutine is
stored in SBR
Selection of address for control memory
Conditional Branching
Status Bits
Control the conditional branch decisions generated in the Branch Logic
Branch Logic
Test the specified condition and Branch to the indicated address if the condition is met ; otherwise, the control address register is just incremented.
Mapping of Instruction :
1 0 1 1 Address
Opcode
Computer Instruction
Microinstruction Address
Mapping bits
0 1 0 1 1 0 0
0 x x x x 0 0
Conditional Branching
4 bit Opcode = specify up to 16 distinct operations
Mapping Process : Converts the 4-bit Opcode to a 7-bit control memory address
1) Place a “0” in the most significant bit of the address
2) Transfer 4-bit Operation code bits
3) Clear the two least significant bits of the CAR
Control Memory Size : 128 words (= 27)
Mapping of Instruction
1 0 1 1 Address
Opcode
Computer Instruction
Microinstruction Address
Mapping bits
0 1 0 1 1 0 0
0 x x x x 0 0
Subroutines are programs that are used by other routines
Subroutine can be called from any point within the main body of the microprogram
Microinstructions can be saved by subroutines that use common section of microcode
Subroutine must have a provision for
storing the return address during a subroutine call
restoring the address during a subroutine return
Subroutine
Microprogram Example
Computer Configuration :
2 Memory : Main memory(instruction/data), Control memory(microprogram)
Data written to memory come from DR, and Data read from memory can go only to DR
4 CPU Register and ALU : DR, AR, PC, AC, ALU
DR can receive information from AC, PC, or Memory (selected by MUX)
AR can receive information from PC or DR (selected by MUX)
PC can receive information only from AR
ALU performs microoperation with data from AC and DR
2 Control Unit Register : SBR, CAR
Microprogram Example
Computer Configuration:
Transfer among registers is done through multiplexers
Microprogram Example
M..Morris Mano. 1993. Computer System Architecture (3rd ed.). Pearson, Page 221
Instruction format
I : 1 bit for indirect addressing
Opcode : 4 bit operation code
Address : 11 bit address for system memory
16 possible memory-reference instructions
For simplicity of example just consider 4 instructions
Microprogram Example
M..Morris Mano. 1993. Computer System Architecture (3rd ed.). Pearson, Page 222
Microinstruction code format:
The fields F1, F2, F3 specify microoperations
The CD field selects status bit conditions
The BR field specifies the type of branch to be used
The AD field contains the branch address
No more than 3 microoperations can be chosen for a microinstruction, one from each field.
Microprogram Example
M..Morris Mano. 1993. Computer System Architecture (3rd ed.). Pearson, Page 223
Two or more conflicting microoperations can not be specified simultaneously
Clear AC to 0 and subtract DR from AC at the same time
E.g. a microinstruction can specify two simultaneous microoperations from F3 and F2 and none from F1 with these 9 bits: 000 100 101
Symbol DRTAC(F1 = 100)
stand for a transfer from DR to AC (T = to)
Microprogram Example
M..Morris Mano. 1993. Computer System Architecture (3rd ed.). Pearson, Page 224
2 bit Condition Fields : CD
00 : Unconditional branch, U = Always 1
01 : Indirect address bit, I = DR(15)
10 : Sign bit of AC, S = AC(15)
11 : Zero value in AC, Z = AC = 0
2 bit Branch Fields : BR
00 : JMP
Condition = 0 :
Condition = 1 :
01 : CALL
Condition = 0 :
Condition = 1 :
10 : RET
11 : MAP
7 bit Address Fields : AD
128 word : 128 X 20 bit
Save Return Address
Restore Return Address
Microprogram Example
Symbolic Microinstruction
Label Field : Terminated with a colon ( : )
Microoperation Field : one, two, or three
symbols, separated by commas
CD Field : U, I, S, or Z
BR Field : JMP, CALL, RET, or MAP
AD Field
a. Symbolic Address : Label ( = Address )
b. Symbol “NEXT” : next address
c. Symbol “RET” or “MAP” : AD field = 0000000
ORG : Pseudoinstruction(define the origin, or first address of routine)
Microprogram Example
Fetch (Sub)Routine
Memory Map(128 words) :
Address 0 to 63 : Routines for the 16 instructions(4 instructions)
Address 64 to 127 : Any other purpose(Subroutines : FETCH, INDRCT)
Microinstructions for FETCH Subroutine
Fetch Subroutine : address 64
Opcode Fetch
Opcode Decode
I Opcode Address
15 14 11 10 …. … 0
Mapping
Operand Address
Instruction Format
Microprogram Example
Symbolic Microprogram :
The execution of MAP microinstruction in FETCH subroutine
Branch to address 0xxxx00 (xxxx = 4 bit Opcode)
ADD : 0 0000 00 = 0
BRANCH : 0 0001 00 = 4
STORE : 0 0010 00 = 8
EXCHANGE : 0 0011 00 = 12, ( 16, 20, … , 60 )
Indirect Address : I = 1
Indirect Addressing :
INDRCT subroutine
Execution of Instruction
Microprogram Example
Symbolic Microprogram
M..Morris Mano. 1993. Computer System Architecture (3rd ed.). Pearson, Page 228
Symbolic microprogram must be translated to binary either by means of an assembler program or by the user
Binary Microprogram
M..Morris Mano. 1993. Computer System Architecture (3rd ed.). Pearson, Page 230
What’s next?
HW#6 is due on Tuesday 29th
Reading:
Chapter 7:
Section 7.1 to 7.4
Instruction code�
Mapping
logic�
Multiplexers�
Control address register
(CAR)�
Control memory�
Incrementer�
Subroutine
regiser
(SBR)�
Branch
logic�
Status
bits�
Clock
�
select�
MUX�
Select a status�
bit�
Branch address�
Microoperations�
1
+
¬
CAR
CAR
1
+
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CAR
CAR
AD
CAR
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1
,
+
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CAR
SBR
AD
CAR
SBR
CAR
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0
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6
,
1
,
0
(
),
14
11
(
)
5
2
(
¬
–
¬
–
CAR
DR
CAR
Sheet1
Label Microoperation CD BR AD
ORG 64
FETCH: PCTAR U JMP NEXT
READ, INCPC U JMP NEXT
DRTAR U MAP 0
0
)
6
,
1
,
0
(
),
14
11
(
)
5
2
(
),
10
0
(
1
],
[
¬
–
¬
–
–
¬
+
¬
¬
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CAR
DR
CAR
DR
AR
PC
PC
AR
M
DR
PC
AR
Sheet1
Label Microoperation CD BR AD
ORG 64
FETCH: PCTAR U JMP NEXT
READ, INCPC U JMP NEXT
DRTAR U MAP 0
]
[
AR
M
AR
¬
DR
AR
AR
M
DR
¬
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]
[
Sheet1
Label Microoperation CD BR AD
INDRCT: READ U JMP NEXT
DRTAR U RET 0
DRTAR U MAP 0