Impress
CMPSC-F353
Architecture of Comp Systems
Sequential Circuits
Flip-Flops
Flip-Flop
The storage elements employed in clocked sequential circuit
A binary cell capable of storing one bit of information
SR(Set/Reset) F/F
Combinational Circuit = Gate
Sequential Circuit = Gate + F/F
D(Data) F/F
“no change” condition: Q(t+1)=D
: 1) Disable Clock
2) Feedback output into input
JK(Jack/King) F/F
JK F/F is a refinement of the SR F/F
The indeterminate condition of the SR type is defined in complement
Flip-Flops
T(Toggle) F/F
T=1(J=K=1), T=0(J=K=0) JK F/F
Q(t+1)= Q(t) T
Edge-triggered Flip-Flops
M..Morris Mano. 1993. Computer System Architecture (3rd ed.). Pearson, Page 26
Excitation Table
Required input combinations for a given change of state
Present State Next State
1 : Clear to 0
0 : No change
0 : Set to 1
1 : Complement
Don’t Care
Excitation Table
Sequential Circuits
A sequential circuit is an interconnection of F/F and Gate
Clocked synchronous sequential circuit
Combinational Circuit = Gate
Sequential Circuit = Gate + F/F
Combinational
Circuit
Flip-Flops
Input
Output
Clock
Sequential Circuits Example
Flip-Flop Input Equation
Boolean expression for F/F input
Example:
Input Equation
DA = Ax + Bx, DB = A’x
Output Equation
y = Ax’ + Bx’
x
DA
DB
A
A’
B
B’
Clock
y
State Table
Presents state, input, next state, output
State Diagram
Graphical representation of state table
Circle(state), Line(transition), I/O(input/output)
State Table and State Diagram
Binary Counter
Excitation Table(2 bit counter = 2 F/F)
x=1: 00, 01, 10, 11,
00, 01, …..
x=0: no change
State Diagram:
4 state (00, 01, 10, 11)
Next State =
Output
Sequential Circuit Design Example
11
10
A
B
x
1
1
X X
X X
Map for simplification
Input variable: A, B, x
A
B
x
A
B
x
A
B
x
JA
KB
KA
JB
JA=Bx
KB=x
JB=x
KA=Bx
X X X X
X X X X
X X
X X
1
1
1
1
Logic Diagram
Sequential Circuit Design Example
Sequential Circuit Design Procedure
Behavior of circuit as a state diagram
Tells number of states, flip flops, inputs,…
Excitation table
Combinational Circuit Design to get flip flop input equations
Truth table is part of the excitation table
Draw the circuit and make connect components
1. The Problem is stated
2. I/O variables are assigned
3. Truth table(I/O relation)
4. Simplified Boolean Function
5. Logic circuit diagram
Sequential Circuit Design Procedure
Digital Components
Decoder
A combinational circuit that converts binary information from the n coded inputs to a maximum of 2n unique outputs
n-to-m line decoder = n x m decoder
n inputs, m outputs
If the n-bit coded information has unused bit combinations, the decoder may have less than 2n outputs
m 2n
3-to-8 Decoder
3-to-8 Decoder
Logic Diagram :
Truth Table :
Commercial decoders
include Enable Input(E)
A2
A1
A0
D0
D1
D2
D3
D4
D5
D6
D7
Enable(E)
NAND Gate Decoder
Constructed with NAND instead of AND gates
Decoder outputs in their complement forms
NAND Gate Decoder
M..Morris Mano. 1993. Computer System Architecture (3rd ed.). Pearson, Page 45
3 X 8 Decoder constructed with two 2 X 4 Decoder
Enable inputs are a convenient way to interconnect circuits
A0
A1
A2
D0
D1
D2
D3
D4
D5
D6
D7
A 3-to-8 Decoder constructed with two with 2-to-4 Decoder
Decoder Expansion
What’s next?
HW1 is due Monday 9/16
Further Reading:
Chapter 1:
1.7 to the end of chapter 1
Chapter 2:
Section 2.2
Sheet1
S R Q(t+1)
0 0 Q(t) no change
0 1 0 clear to 0
1 0 1 set to 1
1 1 ? Indeterminate
Sheet1
D Q(t+1)
0 0 clear to 0
1 1 set to 1
Sheet1
J K Q(t+1)
0 0 Q(t) no change
0 1 0 clear to 0
1 0 1 set to 1
1 1 Q(t)’ Complement
T�
Sheet1
T Q(t+1)
0 Q(t) no change
1 Q'(t) Complement
Q(t) Q(t+1) S R
0 00 X
0 11 0
1 00 1
1 1X 0
SR F/F
Sheet1
SR F/F
Q(t) Q(t+1) S R
0 0 0 X
0 1 1 0
1 0 0 1
1 1 X 0
Sheet1
D F/F
Q(t) Q(t+1) D
0 0 0
0 1 1
1 0 0
1 1 1
Sheet1
JK F/F
Q(t) Q(t+1) J K
0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 0
Sheet1
T F/F
Q(t) Q(t+1) T
0 0 0
0 1 1
1 0 1
1 1 0
Present State
Input
Next State
Output
A B xA By
0 000 00
0 010 10
0 100 01
0 111 10
1 000 01
1 011 00
1 100 01
1 111 00
Sheet1
Present State Input Next State Output
A B x A B y
0 0 0 0 0 0
0 0 1 0 1 0
0 1 0 0 0 1
0 1 1 1 1 0
1 0 0 0 0 1
1 0 1 1 0 0
1 1 0 0 0 1
1 1 1 1 0 0
00�
01�
10�
11�
0/0�
1/0�
1/0�
0/1�
0/1�
1/0�
1/0�
0/1�
00�
01�
10�
11�
x=0�
x=0�
x=1�
x=0�
x=1�
x=1�
x=1�
x=0�
0/00�
1/01�
Sheet1
Present State Input Next State F/F Input Equ.
A B x A B JA KA JB KB
0 0 0 0 0 0 x 0 x
0 0 1 0 1 0 x 1 x
0 1 0 0 1 0 x x 0
0 1 1 1 0 1 x x 1
1 0 0 1 0 x 0 0 x
1 0 1 1 1 x 0 1 x
1 1 0 1 1 x 0 x 0
1 1 1 0 0 x 1 x 1
Sheet1
JK F/F
Q(t) Q(t+1) J K
0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 0
Sheet1
0 1 3 2
4 5 7 6
Sheet1
0 1 3 2
4 5 7 6
Sheet1
0 1 3 2
4 5 7 6
Sheet1
0 1 3 2
4 5 7 6
�
Clock�
x�
B�
A�
Sheet1
Enable Inputs Outputs
E A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
0 x x x 0 0 0 0 0 0 0 0
1 0 0 0 0 0 0 0 0 0 0 1
1 0 0 1 0 0 0 0 0 0 1 0
1 0 1 0 0 0 0 0 0 1 0 0
1 0 1 1 0 0 0 0 1 0 0 0
1 1 0 0 0 0 0 1 0 0 0 0
1 1 0 1 0 0 1 0 0 0 0 0
1 1 1 0 0 1 0 0 0 0 0 0
1 1 1 1 1 0 0 0 0 0 0 0
�
2 X 4
Decoder�
2�
0�
2�
1�
E�
�
2 X 4
Decoder�
2�
0�
2�
1�
E�