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Impress

CMPSC-F353
Architecture of Comp Systems

Basic Computer
Organization and Design

Basic Computer Instructions
M..Morris Mano. 1993. Computer System Architecture (3rd ed.). Pearson, Page 133

Clock pulses
A master clock generator controls the timing for all registers in the basic computer
The clock pulses are applied to all F/Fs and registers in system
The clock pulses do not change the state of a register unless the register is enabled by a control signal
The control signals are generated in the control unit :
The control signals provide control inputs for the multiplexers in the common bus, control inputs in processor registers, and microoperations for the accumulator

Two major types of control organization
Hardwired Control :
The control logic is implemented with gates, F/Fs, decoders, and other digital circuits
+ Fast operation, – Wiring change(if the design has to be modified)
Timing and Control

Microprogrammed Control :
The control information is stored in a control memory, and the control memory is programmed to initiate the required sequence of microoperations
+ Any required change can be done by updating the microprogram in control memory, – Slow operation

Control Unit :
Control Unit = Control Logic Gate + 3 X 8 Decoder + Instruction Register + Timing Signal
Timing Signal = 4 X 16 Decoder + 4-bit Sequence Counter
E.g. Control timing :
Sequence Counter is cleared when D3T4 =1

Timing and Control

E.g. Register transfer statement :
A transfer of the content of PC into AR if timing signal T0 is active
1) During T0 active, the content of PC is placed onto the bus
2) LD(load) input of AR is enabled, the actual transfer occurs at the next positive transition of the clock(T0 rising edge clock)
3) SC(sequence counter) is incremented:

T0 : Inactive
T1 : Active
Timing and Control
M..Morris Mano. 1993. Computer System Architecture (3rd ed.). Pearson, Page 138

Instruction Cycle
Instruction Fetch from Memory
Instruction Decode
Read Effective Address(if indirect addressing mode)
Instruction Execution
Go to step 1) : Next Instruction[PC + 1]

Instruction Fetch : T0, T1

T0 = 1
1) Place the content of PC onto the bus by making the bus selection inputs S2S1S0=010
2) Transfer the content of the bus to AR by enabling the LD input of AR

Instruction Cycle

T1 = 1
Enable the read input memory

2) Place the content of memory onto the bus by making S2S1S0= 111

3) Transfer the content of the bus to IR by enable the LD input of IR

4) Increment PC by enabling the INR input of PC

T1=1
T0=1
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Instruction Cycle

Op.code
Address
Di/Indirect
Instruction Cycle
Instruction Decode : T2

During time T3 , the control unit determines if this is a memory-reference, register-reference or input/output instruction.
The latter two are distinguished by the I (indirect indicator) bit.
If it is a memory-reference instruction, the I bit will determine direct or indirect addressing.
There are 4 possible cases:
D’7 I T3 : AR  M[AR]
D’7 I’ T3 : Nothing
D7 I’ T3 : Execute a register-reference instruction
D7 I T3 : Execute an input-output instruction

Flowchart for Instruction Cycle
D7

Register Ref. Instruction
r = D7I’T3 :
IR(i) = Bi IR(0 -11)
B0 – B11 : 12 bits Register Ref. Instruction

Address
Register Reference Instructions
M..Morris Mano. 1993. Computer System Architecture (3rd ed.). Pearson, Page 144

Memory Ref. Instruction
D7 : Register or I/O = 1
D6 – D0 : 7 bits Memory Ref. Instruction
Execution of a memory-reference instruction starts at T4
AND to AC

ADD to AC

LDA : memory read

IR(12,13,14)
= 111

3 X 8 Decoder

Memory-Reference Instructions

STA : memory write

BUN : branch unconditionally

BSA : branch and save return address

Example of BSA:

Memory-Reference Instructions
M..Morris Mano. 1993. Computer System Architecture (3rd ed.). Pearson, Page 148

ISZ : increment and skip if zero

Control Flowchart :
Flowchart for the 7 memory reference instruction
The longest instruction : ISZ(T6)

Memory-Reference Instructions

M..Morris Mano. 1993. Computer System Architecture (3rd ed.). Pearson, Page 150

Input-Output Configuration :
Input Register(INPR), Output Register(OUTR)
These two registers communicate with a communication interface serially and with the AC in parallel
Each quantity of information has 8 bits of an alphanumeric code
Input Flag(FGI), Output Flag(FGO)
FGI : set when INPR is ready clear when INPR is empty
FGO : set when operation is completed clear when output device is in the process of printing

1 : Ready
0 : Not ready
Input-Output and Interrupt

M..Morris Mano. 1993. Computer System Architecture (3rd ed.). Pearson, Page 151

Input-Output Instructions :
p = D7IT3 :
IR(i) = Bi IR(6 -11)
B6 – B11 : 6 bit I/O Instruction

Address

Input-Output Instructions
M..Morris Mano. 1993. Computer System Architecture (3rd ed.). Pearson, Page 152

Interrupt Cycle :
During execution, IEN is checked by the control
IEN = 0 : the programmer does not want to use the interrupt, so control continues with the next instruction cycle
IEN = 1 : the control circuit checks the flag bit, If either flag set to 1, R F/F is set to 1
At the end of the execute phase, control checks the value of R
R = 0 : instruction cycle
R = 1 : interrupt cycle
Interrupts

Demonstration of the interrupt cycle :
The memory location at address 0 as the place for storing the return address
Interrupt Branch to memory location 1

The condition for R = 1

Modified Fetch Phase
Modified Fetch and Decode Phase
Save Return
Address(PC) at 0

Jump to 1(PC=1)

Interrupts

M..Morris Mano. 1993. Computer System Architecture (3rd ed.). Pearson, Page 155

Complete Computer Description

M..Morris Mano. 1993. Computer System Architecture (3rd ed.). Pearson, Page 158

What’s next?

HW#4 is due on Tuesday 15th

Reading:
Chapter 5:
Section 5.4 to 5.8

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