x86 Programming III CSE 351 Autumn 2016
More RISC-V, RISC-V Functions
CS295
L09 – RISC V – II
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Summary
RISC Design Principles
Smaller is faster: 32 registers, fewer instructions
Keep it simple: rigid syntax
RISC-V Registers: s0-s11, t0-t6, x0
No data types, just raw bits, operations determine how they are interpreted
Memory is byte-addressed
no types → no automatic pointer arithmetic
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CS295
L09 – RISC V – II
RISC-V Instructions
Arithmetic: add, sub, addi,
mult,div
Data Transfer: lw, sw,
lb, sb, lbu
Branching: beq, bne, j, bge, blt,
jal;
Bitwise: and, or, xor,
andi, ori, xori
Shifting: sll, srl, sra,
slli, srli, srai
Review of Last Lecture (2/2)
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i = “immediate”
(constant integer)
CS295
L09 – RISC V – II
Instructions shown in orange were presented in bonus slides from last lecture.
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So Far:
lw reg, off(bAddr)
sw reg, off(bAddr)
What about characters (1B) and shorts (sometimes 2B), etc?
Want to be able to use interact with memory values smaller than a word.
Memory and Variable Size
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Processor
Computer
Control
(“brain”)
Datapath
Registers
Memory
Devices
Input
Output
lw reg off(bAddr)
sw reg off(bAddr)
CS295
L09 – RISC V – II
lb/sb have same syntax as lw/sw
Aside: also load/store halfword (lh/sh)
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Trading Bytes with Memory
(2 approaches)
Method 1: Move words in and out of memory using bit-masking and shifting
lw s0,0(s1)
andi s0,s0,0xFF # lowest byte
Method 2: Load/store byte instructions
lb s1,1(s0)
sb s1,0(s0)
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00 00 01 80
*(s0) = 0x00000180
CS295
L09 – RISC V – II
If it’s not aligned, which part of the word are we pulling from?!
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Endianness
Big Endian: Most-significant byte at least address of word
word address = address of most significant byte
Little Endian: Least-significant byte at least address of word
word address = address of least significant byte
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msb
lsb
3(s0) 2(s0) 1(s0) 0(s0)
0(s0) 1(s0) 2(s0) 3(s0)
big endian
little endian
00 00 01 80
*(s0) = 0x00000180
RISC-V is Little Endian
CS295
L09 – RISC V – II
Byte Instructions
lb/sb utilize the least significant byte of the register
On sb, upper 24 bits are ignored
On lb, upper 24 bits are filled by sign-extension
For example, let *(s0) = 0x00000180:
lb s1,1(s0)
lb s2,0(s0)
sb s2,2(s0)
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# s1=0x00000001
# s2=0xFFFFFF80
# *(s0)=0x00800180
CS295
L09 – RISC V – II
Half-Word Instructions
lh reg, off(bAddr) “load half”
sh reg, off(bAddr) “store half”
On sh, upper 16 bits are ignored
On lh, upper 16 bits are filled by sign-extension
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Unsigned Instructions
lhu reg, off(bAddr)“load half unsigned”
lbu reg, off(bAddr)“load byte unsigned”
On l(b/h)u, upper bits are filled by zero-extension
Why no s(h/b)u? Why no lwu?
CS295
L09 – RISC V – II
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Agenda
More Memory Instructions
Inequalities
Pseudo-Instructions
Bonus: Memory Address Convention
Bonus: Alternate Register Convention Analogy
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CS295
L09 – RISC V – II
do additional slt stuff
Then do additional memory instructions
then summarize unsigned?
Inequalities in RISC-V
Set Less Than (slt)
slt dst,reg1,reg2
if value in reg1 < value in reg2, dst = 1, else 0
Set Less Than Immediate (slti)
slti dst,reg1,imm
If value in reg1 < imm, dst = 1, else 0
These values are all interpreted as signed values
What if we want to compare unsigned numbers?
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CS295
L09 – RISC V - II
Unsigned Inequalities
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# s0=0xFFFFFFFF
# t0=1 (-1 < 1)
# t1=0 (232-1 >>> 1)
Unsigned versions of slt(i):
sltu dst,src1,src2: unsigned comparison
sltiu dst,src,imm: unsigned comparison against constant
Example:
addi s0,x0,-1
slti t0,s0,1
sltiu t1,s0,1
CS295
L09 – RISC V – II
Do this first
Aside: RISC-V Signed vs. Unsigned
RISC-V terms “signed” and “unsigned” appear in 2 different contexts:
Signed vs. unsigned bit extension
lb,lh
lbu,lhu
Signed vs. unsigned comparison
slt, slti
sltu, sltiu
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CS295
L09 – RISC V – II
j < 2 || j < i (A) j ≥ 2 && j < i (B) j < 2 || j ≥ i (C) j < 2 && j ≥ i (D) Question: What C code properly fills in the following blank? do {i--; } while((z = ____________)); Loop: # i→s0, j→s1 addi s0,s0,-1 # i = i - 1 slti t0,s1,2 # t0 = (j < 2) bne t0,x0 Loop # goto Loop if t0!=0 slt t0,s1,s0 # t1 = (j < i) bne t0,x0 ,Loop # goto Loop if t0!=0 13 CS295 L09 – RISC V - II !False = true comic 13 j < 2 || j < i (A) j ≥ 2 && j < i (B) j < 2 || j ≥ i (C) j < 2 && j ≥ i (D) Question: What C code properly fills in the following blank? do {i--; } while((z = ____________)); Loop: # i→s0, j→s1 addi s0,s0,-1 # i = i - 1 slti t0,s1,2 # t0 = (j < 2) bne t0,x0 Loop # goto Loop if t0!=0 slt t0,s1,s0 # t1 = (j < i) bne t0,x0 ,Loop # goto Loop if t0!=0 14 CS295 L09 – RISC V - II !False = true comic 14 Agenda More Memory Instructions Inequalities Administrivia Pseudo-Instructions Bonus: Memory Address Convention Bonus: Alternate Register Convention Analogy 15 CS295 L09 – RISC V - II do additional slt stuff Then do additional memory instructions then summarize unsigned? Assembler Pseudo-Instructions more intuitive for programmers, but NOT directly implemented in hardware translated later into instructions which are directly implemented in hardware Example: mv dst,reg1 translated into addi dst,reg1,0 or add dst,reg1,x0 Full list of RISC-V supported pseudo instructions are on the greensheet 16 CS295 L09 – RISC V - II More Pseudo-Instructions Load Immediate (li) li dst,imm Loads 32-bit immediate into dst translates to: addi dst x0 imm Load Address (la) la dst,label Loads address of specified label into dst (translation omitted) 6/28/2016 17 CS295 L09 – RISC V - II J is a Pseudo-Instruction Even the j instruction is actually a pseudo-Instruction We will see what this converts to later this lecture Pseudo-Instructions are core to writing RISC assembly code and you will see it in any RISC assembly code you read 18 6/28/2016 CS295 L09 – RISC V - II 18 True Assembly vs RISC-V True Assembly Language The instructions a computer understands and executes (directly implemented in hardware!) RISC-V Assembly Language Instructions the assembly programmer can use (includes pseudo-instructions) Each RISC-V Assembly instruction becomes 1 or more True Assemblt instructions True Assembly ⊂ RISC-V Assembly 19 CS295 L09 – RISC V - II