程序代写代做代考 assembly Bridging Slide

Bridging Slide

1

CPSC 313.203 – 2019W2 Sequential CPU

1

From Assembly to Hardware

2
CPSC 313
%rax %rsp %r8 %r12
%rcx %rbp %r9 %r13
%rdx %rsi %r10 %r14
%rbx %rdi %r11

ZF SF OF

Registers (RF: Register File)
Condition Codes (CC)
PC: Program Counter
Stat: Status Register
DMEM: Memory

Based just on the instructions we’ve talked about so far (MOV instructions and ALU operations), your task is to hypothesize how you might connect the pieces together to get the hardware to execute them.

Hint 1: The reason we call arithmetic and logical operations ALU operations is because most processors have a block of logic called an ALU.
Hint 2: Be as precise as you can about what information travels along the connections that you draw between boxes.
Hint 3: Where are the instructions before you execute them?
Hint 4: How do you know which instruction to execute next?
Hint 5: Use circles to identify places where you want to compute something (e.g., decide which ALU operation to perform)

CPSC 313.203 – 2019W2 Sequential CPU

2

Let’s Rearrange things

3
CPSC 313
%rax %rsp %r8 %r12
%rcx %rbp %r9 %r13
%rdx %rsi %r10 %r14
%rbx %rdi %r11

ZF SF OF

PC: Program Counter
DMEM: Memory

CPSC 313.203 – 2019W2 Sequential CPU
Y86 Implementation: Take 1

4
CPSC 313
%rax %rsp %r8 %r12
%rcx %rbp %r9 %r13
%rdx %rsi %r10 %r14
%rbx %rdi %r11

ZF SF OF

PC: Program Counter
DMEM: Memory
Compute next PC
ALU
Decode instruction
addr of next instruction
instruction
Identify registers to read/write
Register values
operation

write register value
update cond codes
data
read from memory
write to memory

CPSC 313.203 – 2019W2 Sequential CPU
Y86 Implementation: Take 1

5
CPSC 313
%rax %rsp %r8 %r12
%rcx %rbp %r9 %r13
%rdx %rsi %r10 %r14
%rbx %rdi %r11

ZF SF OF

PC: Program Counter
DMEM: Memory
Compute next PC
ALU
Decode instruction
addr of next instruction
instruction
Identify registers to read/write
Register values
operation

write register value
update cond codes
data
read from memory
write to memory

FETCH

DECODE

EXECUTE

CPSC 313.203 – 2019W2 Sequential CPU
CPSC 313: Computer Hardware and Operating Systems
Unit 1: The y86 (as a sequential processor)
A Deeper look at Execution
6

2019 Winter Term 2
Section 203
Donald Acton Acknowledgment – Many of the slides are courtesy of Margo

6

Administrivia
Quiz 1 – out this afternoon, due Monday 23:59
My office hours will be
12:00 – 13:00 on Monday
4:00 – 5:00 on Fridays
The ssl certificate expired on bitbucket.students.cs.ubc.ca so you would have had problems:
Creating teams and repos
Doing Push or pulls
Logging in to bitbucket

7

CPSC 313.203 – 2019W2 Sequential CPU

7

When Last we Left:
8
Memory
(DRAM)
PC: Program Counter
Increment PC
address
icode
ifun
rA
rB
valC
valP
Register File
valE
CC
srcA
srcB
Val B
Val A
0
address
(valM: value read from memory
value written to memory
Mem control
ALU

CPSC 313.203 – 2019W2 Sequential CPU

8

Warm Up
For each class of instructions: what functionality do we need to add to our design?
CMOV*
PUSHQ/POPQ
J*
CALL/RET

9

CPSC 313.203 – 2019W2 Sequential CPU

9

Commonalities
We frequently need to use the ALU before doing something with memory.
Selecting the next PC can be complicated.
How shall we address these two challenges?
10

CPSC 313.203 – 2019W2 Sequential CPU

10

Commonalities
We frequently need to use the ALU before doing something with memory.
Selecting the next PC can be complicated.
How shall we address these two challenges?
11
Execute
Execute
Memory
PC Update

CPSC 313.203 – 2019W2 Sequential CPU

11

12
Memory
(DRAM)
PC: Program Counter
Increment PC
address
icode
ifun
rA
rB
valC
valP
Register File
valE
CC
srcA
srcB
Val B
Val A
0
address
valM: value read from memory
value written to memory
Mem control
ALU

Execute

CPSC 313.203 – 2019W2 Sequential CPU

12

13
Memory
(DRAM)
PC: Program Counter
Increment PC
address
icode
ifun
rA
rB
valC
valP
Register File
valE
CC
srcA
srcB
Val B
Val A
0
ALU

Execute
Memory
address
value written to memory
valM: value read from memory
Mem control

CPSC 313.203 – 2019W2 Sequential CPU

13

14
Memory
(DRAM)
PC: Program Counter
Increment PC
address
icode
ifun
rA
rB
valC
valP
Register File
valE
CC
srcA
srcB
Val B
Val A
0
ALU

Execute
Memory
address
value written to memory
valM: value read from memory
Mem control
Cond
Conditional Move

CPSC 313.203 – 2019W2 Sequential CPU

14

15
Memory
(DRAM)
PC: Program Counter
Increment PC
address
icode
ifun
rA
rB
valC
valP
Register File
valE
CC
srcA
srcB
Val B
Val A
0
ALU

Execute
Memory
address
value written to memory
valM: value read from memory
Mem control
Cond
PUSHQ/POPQ
Addr
rsp
rsp

8

CPSC 313.203 – 2019W2 Sequential CPU

15

16
Memory
(DRAM)
PC: Program Counter
Increment PC
address
icode
ifun
rA
rB
valC
valP
Register File
valE
CC
srcA
srcB
Val B
Val A
0
ALU

Execute
Memory
address
value written to memory
valM: value read from memory
Mem control
Cond
PUSHQ/POPQ
Addr
rsp
rsp

8

CPSC 313.203 – 2019W2 Sequential CPU

16

17
Memory
(DRAM)
PC: Program Counter
Increment PC
address
icode
ifun
rA
rB
valC
valP
Register File
valE
CC
srcA
srcB
Val B
Val A
0
ALU

Execute
Memory
address
value written to memory
valM: value read from memory
Mem control
Cond
PUSHQ/POPQ
Addr
rsp
rsp

8
Data

CPSC 313.203 – 2019W2 Sequential CPU

17

CPSC 313: Computer Hardware and Operating Systems
Unit 1: The y86 (as a sequential processor)
A Deeper look at Execution
18

© 2020 Donald Acton et all

CPSC 313.203 – 2019W2 Sequential CPU

18

Administrivia
Quiz 1 – due today 23:59
My office hours will be: Mon 12:00 – 13:00; Fri 4:00 – 5:00

19

CPSC 313.203 – 2019W2 Sequential CPU

19

pushq & popq

20

CPSC 313.203 – 2019W2 Sequential CPU
pushq and popq
pushq %r11
R[%rsp] = R[%rsp] – 8
M[R[%rsp]] = R[%r11]
popq %r11
R[%r11] = M[R[%rsp]]
R[%rsp] = R[%rsp] + 8

21
0x1060 0xFFFFFFFFFFFFFFFF
42
1
0XCAFE
0xFACE

0x1000

B
0
ra
F
A
0
ra
F

CPSC 313.203 – 2019W2 Sequential CPU
CPSC 313
22
Memory
(DRAM)
PC: Program Counter
Increment PC
address
icode
ifun
rA
rB
valC
valP
Register File
valE
CC
srcA
srcB
Val B
Val A
0
ALU

Execute
Memory
address
valM: value read from memory
Mem control
Cond
PUSHQ/POPQ
Addr
rsp

8
value written to memory
Data
New elements connections in red

CPSC 313.203 – 2019W2 Sequential CPU

22

CPSC 313
23
Memory
(DRAM)
PC: Program Counter
Increment PC
address
icode
ifun
rA
rB
valC
valP
Register File
valE
CC
srcA
srcB
Val B
Val A
0
ALU

Execute
Memory
address
valM: value read from memory
Mem control
Cond
PUSHQ/POPQ
Addr
rsp

8
value written to memory
Data
New elements connections in red

CPSC 313.203 – 2019W2 Sequential CPU

23

CPSC 313
24
Memory
(DRAM)
PC: Program Counter
Increment PC
address
icode
ifun
rA
rB
valC
valP
CC
srcA
srcB
Val B
Val A
0
ALU

Execute
Memory
address
valM: value read from memory
Mem control
Cond
PUSHQ/POPQ
8
value written to memory
Data
rsp

ALU: R[%rsp] – 8 => ADDRESS
R[rA] => Data to Memory
Result of ALU written back to register file
Addr
valE
Register File

CPSC 313.203 – 2019W2 Sequential CPU

24

CPSC 313
25
Memory
(DRAM)
PC: Program Counter
Increment PC
address
icode
ifun
rA
rB
valC
valP
valE
CC
srcA
srcB
Val A
0
ALU

Execute
Memory
address
valM: value read from memory
Mem control
Cond
PUSHQ/POPQ
Addr
rsp

8
value written to memory
Data
ALU: R[%rsp] + 8 [written back to reg file]
R[rA] = Data from Memory
Original value of R[%rsp] => ADDRESS
Val B
Register File

CPSC 313.203 – 2019W2 Sequential CPU

25

J* Instructions (and CALL/RET)

26
Determine next PC
What signals (wires/register contents) might be used to determine the next PC?

CPSC 313.203 – 2019W2 Sequential CPU

26

J* Instructions
CPSC 313
27
Determine next PC
valP
This is the computed next PC
valC
This is the field from the instruction
PC
Halt instruction
valM
This is a value read from memory
icode

CPSC 313.203 – 2019W2 Sequential CPU

27

CPSC 313
28
Memory
(DRAM)
PC: Program Counter
Increment PC
address
icode
ifun
rA
rB
valC
valP
Register File
valE
CC
srcA
srcB
Val B
Val A
0
ALU

Execute
Memory
address
valM: value read from memory
Mem control
Cond
Addr
rsp

8
value written to memory
Data
Update PC

CPSC 313.203 – 2019W2 Sequential CPU

28

29

Memory
(DRAM)
PC: Program Counter
Increment PC
address
icode
ifun
rA
rB
valC
valP
Register File
valE
CC
srcA
srcB
Val B
Val A
0
ALU

Execute
Memory
address
valM: value read from memory
Mem control
Cond
Addr
rsp

8
value written to memory
Data
Update PC

CPSC 313.203 – 2019W2 Sequential CPU

29

30

CPSC 313.203 – 2019W2 Sequential CPU

30

Problem: How to express what is happening
5 stages
Fetch, Decode, Execute, Memory, Writeback
Writeback is where the Memory & or Registers are updated to reflect the new values resulting from this computation
What we will do is for each stage we will describe what the new values of the hidden registers are
31

CPSC 313.203 – 2019W2 Sequential CPU
Module 1.3: Y86-64 Implementation
Fetch:
icode: the opcode for the current instruction (0 to F).
ifun: the arithmetic logical operation, or the branch/move condition.
rA, rB: register numbers contained in the instruction.
valC: constant, displacement, or target of a jXX or call instruction, etc.
valP: the address of the instruction after the current one.
32

CPSC 313.203 – 2019W2 Sequential CPU
32

Module 1.3: Y86-64 Implementation
Decode:
srcA: first register to read from (often but not always the same as rA).
srcB: second register to read from (often but not always the same as rB).
valA: the value read from register srcA.
valB: the value read from regsiter srcB.
Execute:
valE: value computed by the ALU.
cnd: whether or not the branch condition was satisfied.
33

CPSC 313.203 – 2019W2 Sequential CPU
33

Module 1.3: Y86-64
Implementation
Memory:
valM: value read from memory.
Write back:
dstE: register to which value valE should be written.
dstM: register to which value valM should be written.
PC update:
newPC: the address of the next instruction (taking jXX, call, ret into account).
34

CPSC 313.203 – 2019W2 Sequential CPU
34

Fetch Stage
The “variables” are the names of signals
icode:iFun <= M1[PC] rA:rB <= M1[PC+1] Eventually we will also get valA and valB, valC <= M8[PC + ?] valP <= Current PC + ? Only the green “variables” are guaranteed to be computed for each fetch – others depend on the operation 35 Always computed CPSC 313.203 – 2019W2 Sequential CPU 35 313 - Overview We are officially wrapping up Module 1. By the end, you should be able to: Read and write simple y86 programs Write y86 programs that implement simple C statements Translate y86 assembly to/from its binary representation Explain the behavior of y86 instructions in terms of how they might be implemented in hardware Break apart y86 instruction execution into different phases Use and explain the y86 calling conventions Note: This is a subset of the learning objectives from Canvas 36 CPSC 313.203 – 2019W2 Sequential CPU Administrivia Assignment 1: Due Friday 23:59 Midterm 1 is Feb 10th at 5:30 Read the canvas announcement on this and follow the instructions. If you have a conflict report it NOW! Feb 10th lecture will be replaced by a Review Question/Answer sessions 37 CPSC 313.203 – 2019W2 Sequential CPU 37 Fetch Stage The “variables” are the names of signals icode:iFun <= M1[PC] rA:rB <= M1[PC+1] Eventually we will also get valA and valB, valC <= M8[PC + ?] valP <= Current PC + ? Only the green “variables” are guaranteed to be computed for each fetch – others depend on the operation 38 Always computed CPSC 313.203 – 2019W2 Sequential CPU 38 Decode Stage Read up to 2 operands from the register file based on the following: srcA, srcB – from rA, rB, or %rsp valA – from R[srcA] (valA = R[rA]) valB – from R[srcB] (valB = R[rb]) Also setup signals for writing back to registers – but ignore for now dstM – from rA, or %rsp dstE – from rB, or %rsp 39 CPSC 313.203 – 2019W2 Sequential CPU 39 Execute Depending upon the instruction, produces: valE – the value (result) of the computation performed as a result of the execute stage. This could be: Result of operation (+, -, /, * etc) specified by ifun Effective address for a memory reference Increment or decrement of the stack pointer Condition Codes (CC) (i.e. ZF, OF, SF) could be set if it is an arithmetic operation 40 CPSC 313.203 – 2019W2 Sequential CPU 40 Memory, Write back, PC Update Memory valM, set only if something is read from memory Write back Writes results to registers, value written contained in valM and/or valE PC update PC – set to the next instruction to execute and will come from one of valM, valC, valP 41 CPSC 313.203 – 2019W2 Sequential CPU 41 Allowed in specifications: Fetch: icode, ifun, rA, rB, valC, valP, Memory Decode: valA, valB Execute: valC, valE, CC/Cnd, Cond, constants: 0, 8, -8 CC are the condition codes Cond is logic that combines the condition codes and the ifun to produce a 0/1 Cnd signal that is used to enable/disable other operations. Memory: valA, valE, valM, valP, Memory Writeback: rA, rB, valE, valM PC Update: PC, Cnd, valC, valM, valP 42 Anywhere you use rA/rB, you might also use %rsp explicitly. CPSC 313.203 – 2019W2 Sequential CPU Understanding Execution We began by understanding each instruction in its logical form – what it did. Then, we looked at how each instruction was realized in hardware, using wiring diagrams. Next we examined execution as a staged process using internal hardware registers. Today, we’ll look at execution formally as a set of specification statements 43 CPSC 313.203 – 2019W2 Sequential CPU Let’s see how we can express the behaviour of the ISA in 3 ways 44 CPSC 313.203 – 2019W2 Sequential CPU rrmovq three ways From ISA description (and in Margo’s videos) R[%rB] <- R[%rA] 45 From implementation PC: Program Counter Inc PC icode ifun rA rB valC valP Register File valE srcA srcB Val B ValA 0 ALU CPSC 313.203 – 2019W2 Sequential CPU 45 rrmovq three ways From ISA description (and in Margo’s videos) R[%rB] <- R[%rA] 46 From implementation PC: Program Counter Inc PC icode ifun rA rB valC valP Register File valE srcA srcB Val B ValA 0 ALU By Specification icode:ifun = M1[PC] rA:rB = M1[PC+1] valP = PC + 2 valA = R[rA] valE = valA + 0 R[rB] = valE PC = valP FETCH DECODE EXECUTE MEMORY WRITEBACK PC UPDATE CPSC 313.203 – 2019W2 Sequential CPU 46 From rrmovq to cmovq 47 RRMOVQ icode:ifun = M1[PC] rA:rB = M1[PC+1] valP = PC + 2 valA = R[rA] valE = valA + 0 R[rB] = valE PC = valP FETCH DECODE EXECUTE MEMORY WRITEBACK PC UPDATE CPSC 313.203 – 2019W2 Sequential CPU 47 From rrmovq to cmovq 48 RRMOVQ icode:ifun = M1[PC] rA:rB = M1[PC+1] valP = PC + 2 valA = R[rA] valE = valA + 0 R[rB] = valE PC = valP FETCH DECODE EXECUTE MEMORY WRITEBACK PC UPDATE WRITEBACK EXECUTE CMOV* icode:ifun = M1[PC] rA:rB = M1[PC+1] valP = PC + 2 valA = R[rA] valE = valA + 0 Cnd = Cond(CC, ifun) R[rB] = valE PC = valP FETCH DECODE MEMORY PC UPDATE CPSC 313.203 – 2019W2 Sequential CPU 48 From rrmovq to cmovq CPSC 313 49 RRMOVQ icode:ifun = M1[PC] rA:rB = M1[PC+1] valP = PC + 2 valA = R[rA] valE = valA + 0 R[rB] = valE PC = valP FETCH DECODE EXECUTE MEMORY WRITEBACK PC UPDATE WRITEBACK EXECUTE CMOV* icode:ifun = M1[PC] rA:rB = M1[PC+1] valP = PC + 2 valA = R[rA] valE = valA + 0 Cnd = Cond(CC, ifun) R[rB] = Cnd ? valE :

PC = valP
FETCH
DECODE
MEMORY
PC UPDATE

CPSC 313.203 – 2019W2 Sequential CPU

49

TODO: irmovq
CPSC 313
50
EXECUTE
DECODE
FETCH
IRMOVQ

MEMORY
WRITEBACK
PC UPDATE
Left as an exercise

CPSC 313.203 – 2019W2 Sequential CPU

50

Solution: irmovq

51
EXECUTE
DECODE
FETCH
IRMOVQ
icode:ifun = M1[PC]
rA:rB = M1[PC+1]
valC = M8[PC+2]
valP = PC + 10

valE = valC + 0

R[rB] = valE

PC = valP
MEMORY
WRITEBACK
PC UPDATE
Not shown in class

CPSC 313.203 – 2019W2 Sequential CPU

51

TODO: mrmovq, rmmovq

52
FETCH
DECODE
EXECUTE
MEMORY
WRITEBACK
PC UPDATE
MRMOVQ
WRITEBACK
EXECUTE
FETCH
DECODE
MEMORY
PC UPDATE
RMMOVQ

CPSC 313.203 – 2019W2 Sequential CPU

52

Solution: mrmovq, rmmovq
CPSC 313
53
FETCH
DECODE
EXECUTE
MEMORY
WRITEBACK
PC UPDATE
MRMOVQ
icode:ifun = M1[PC]
rA:rB = M1[PC+1]
valC = M8[PC+2]
valP = PC + 10
valB = R[rB]

valE = valB + valC

valM = M8[valE]

R[rA] = valM

PC = valP
WRITEBACK
EXECUTE
FETCH
DECODE
MEMORY
PC UPDATE
RMMOVQ
icode:ifun = M1[PC]
rA:rB = M1[PC+1]
valC = M8[PC+2]
valP = PC + 10
valA = R[rA]
valB = R[rB]
valE = valB + valC

M8[valE] = valA

PC = valP

CPSC 313.203 – 2019W2 Sequential CPU

53

TODO: OPq (addq, subq, xorq, andq)
CPSC 313
54
FETCH
EXECUTE
OPq

DECODE
MEMORY
WRITEBACK
PC UPDATE
Left as an exercise

CPSC 313.203 – 2019W2 Sequential CPU

54

Solution: OPq (addq, subq, xorq, andq)

55
EXECUTE
OPq
icode:ifun = M1[PC]
rA:rB = M1[PC+1]
valP = PC + 2

valA = R[rA]
valB = R[rB]
valE = valA op valB
Set CC

R[rB] = valE

PC = valP
FETCH
DECODE
MEMORY
WRITEBACK
PC UPDATE
Not shown in class

CPSC 313.203 – 2019W2 Sequential CPU

55

TODO: pushq, call

56
FETCH
DECODE
EXECUTE
MEMORY
WRITEBACK
PC UPDATE
PUSHQ
FETCH
DECODE
EXECUTE
MEMORY
WRITEBACK
PC UPDATE
CALL

CPSC 313.203 – 2019W2 Sequential CPU

56

Solution: pushq, call
CPSC 313
57
FETCH
DECODE
EXECUTE
MEMORY
WRITEBACK
PC UPDATE
PUSHQ
icode:ifun = M1[PC]
rA:rB = M1[PC+1]
valP = PC + 2

valA = R[rA]
valB = R[%rsp]
valE = valB + (-8)

M8[valE] = valA

R[%rsp] = valE

PC = valP
FETCH
DECODE
EXECUTE
MEMORY
WRITEBACK
PC UPDATE
CALL
icode:ifun = M1[PC]
valC = M8[PC+2]
valP = PC + 10

valB = R[%rsp]

valE = valB + (-8)

M8[valE] = valP

R[%rsp] = valE

PC = valC

CPSC 313.203 – 2019W2 Sequential CPU

57

TODO: popq, ret

58
FETCH
DECODE
EXECUTE
MEMORY
WRITEBACK
PC UPDATE
RET
WRITEBACK
EXECUTE
FETCH
DECODE
MEMORY
PC UPDATE
POPQ

Left as an exercise

CPSC 313.203 – 2019W2 Sequential CPU

58

Solution: popq, ret
CPSC 313
59
FETCH
DECODE
EXECUTE
MEMORY
WRITEBACK
PC UPDATE
RET
icode:ifun = M1[PC]
valP = PC + 1

valA = R[%rsp]
valB = R[%rsp]
valE = valB + 8

valM = M8[valA]

R[%rsp] = valE

PC = valM
WRITEBACK
EXECUTE
FETCH
DECODE
MEMORY
PC UPDATE
POPQ
icode:ifun = M1[PC]
rA:rB = M1[PC + 1]
valP =PC + 2

valA = R[%rsp]
valB = R[%rsp]
valE = valB + 8

valM = M8[valA]

R[%rsp] = valE
R[%rA] = valM
PC = valP
Not shown in class

CPSC 313.203 – 2019W2 Sequential CPU

59

TODO: jmp, J* (je, jne, jle, jlt, jge, jgt)

60
FETCH
DECODE
EXECUTE
MEMORY
WRITEBACK
PC UPDATE
J*

CPSC 313.203 – 2019W2 Sequential CPU

60

Solution: jmp, J* (je, jne, jle, jlt, jge, jgt)
CPSC 313
61
FETCH
DECODE
EXECUTE
MEMORY
WRITEBACK
PC UPDATE
J*
icode:ifun = M1[PC]
valC = M8[PC+1]
valP = PC + 9

Cnd = Cond(CC, ifun)

PC = Cnd ? valC : valP

CPSC 313.203 – 2019W2 Sequential CPU

61

Let’s put this altogether
irmovq 0x2000, %rsp
irmovq 4, %rbx
pushq %rbx
call isodd
irmovq result, %rbx
rmmovq %rax, 0(%rbx)å
halt

isodd:
mrmovq 8(%rsp), %rax
irmovq 2, %rsi
modq %rsi, %rax
je done
irmovq 1, %rax
done:
ret

.pos 0x1000
result: .quad 0xDEADBEEF

# The stack
.pos 0x1FE0
.quad 0xDEADBEEF
.quad 0xDEADBEEF
.quad 0xDEADBEEF
.quad 0xDEADBEEF
000000  30 F4 00 20 00 00 00 00
000008  00 00 30 F3 04 00 00 00
000010  00 00 00 00 A0 3F 80 34
000018  00 00 00 00 00 00 00 30
000020  F3 00 10 00 00 00 00 00
000028  00 40 03 00 00 00 00 00
000030  00 00 00 00 50 04 08 00
000038  00 00 00 00 00 00 30 F6
000040  02 00 00 00 00 00 00 00
000048  66 60 73 5D 00 00 00 00
000050  00 00 00 30 F0 01 00 00
000058  00 00 00 00 00 90 00 00
***
001000  EF BE AD DE 00 00 00 00
***
001FE0  EF BE AD DE 00 00 00 00
001FE8  EF BE AD DE 00 00 00 00
001FF0  EF BE AD DE 00 00 00 00
001FF8  EF BE AD DE 00 00 00 00

62

CPSC 313.203 – 2019W2 Sequential CPU

62

63
Icode Ifun rA rB valA valB valC valP ValE ValM nextPC

irmovq 0x2000, %rsp
irmovq 4, %rbx
pushq %rbx
call isodd
irmovq result, %rbx
rmmovq %rax, 0(%rbx)
halt

isodd:
mrmovq 8(%rsp), %rax
irmovq 2, %rsi
modq %rsi, %rax
je done
irmovq 1, %rax
done:
ret

.pos 0x1000
result: .quad 0xDEADBEEF

# The stack
.pos 0x1FE0
.quad 0xDEADBEEF
.quad 0xDEADBEEF
.quad 0xDEADBEEF
.quad 0xDEADBEEF

CPSC 313.203 – 2019W2 Sequential CPU
64
Icode Ifun rA rB valA valB valC valP ValE ValM nextPC
irmovq 0x2000, %rsp 3 0 F 4 0 0 2000 A 2000 0 A

irmovq 0x2000, %rsp
irmovq 4, %rbx
pushq %rbx
call isodd
irmovq result, %rbx
rmmovq %rax, 0(%rbx)
halt

isodd:
mrmovq 8(%rsp), %rax
irmovq 2, %rsi
modq %rsi, %rax
je done
irmovq 1, %rax
done:
ret

.pos 0x1000
result: .quad 0xDEADBEEF

# The stack
.pos 0x1FE0
.quad 0xDEADBEEF
.quad 0xDEADBEEF
.quad 0xDEADBEEF
.quad 0xDEADBEEF

CPSC 313.203 – 2019W2 Sequential CPU
65
irmovq 0x2000, %rsp
irmovq 4, %rbx
pushq %rbx
call isodd
irmovq result, %rbx
rmmovq %rax, 0(%rbx)
halt

isodd:
mrmovq 8(%rsp), %rax
irmovq 2, %rsi
modq %rsi, %rax
je done
irmovq 1, %rax
done:
ret

.pos 0x1000
result: .quad 0xDEADBEEF

# The stack
.pos 0x1FE0
.quad 0xDEADBEEF
.quad 0xDEADBEEF
.quad 0xDEADBEEF
.quad 0xDEADBEEF
Icode Ifun rA rB valA valB valC valP ValE ValM nextPC
irmovq 0x2000, %rsp 3 0 F 4 0 0 2000 A 2000 0 A
irmovq 4, %rbx 3 0 F 3 0 0 4 14 4 0 14
pushq %rbx
call isodd

CPSC 313.203 – 2019W2 Sequential CPU
66
irmovq 0x2000, %rsp
irmovq 4, %rbx
pushq %rbx
call isodd
irmovq result, %rbx
rmmovq %rax, 0(%rbx)
halt

isodd:
mrmovq 8(%rsp), %rax
irmovq 2, %rsi
modq %rsi, %rax
je done
irmovq 1, %rax
done:
ret

.pos 0x1000
result: .quad 0xDEADBEEF

# The stack
.pos 0x1FE0
.quad 0xDEADBEEF
.quad 0xDEADBEEF
.quad 0xDEADBEEF
.quad 0xDEADBEEF
Icode Ifun rA rB valA valB valC valP ValE ValM nextPC
irmovq 0x2000, %rsp 3 0 F 4 0 0 2000 A 2000 0 A
irmovq 4, %rbx 3 0 F 3 0 0 4 14 4 0 14
pushq %rbx A 0 3 F 4 2000 0 16 4 0 16
call isodd 8 0 0 0 0 1FF8 34 1F 1FF0 0 34
mrmovq 8(%rsp), %rax
irmovq 2, %rsi
modq %rsi, %rax
je done 7 3 0 0 53 0 5D 53 0 4 5D
ret
irmovq result, %rbx
rmmovq %rax,0(%rbx)
halt

CPSC 313.203 – 2019W2 Sequential CPU

66

67
Complete solution to previous slide – you can always check by running through the simulator

CPSC 313.203 – 2019W2 Sequential CPU
68
irmovq 0x2000, %rsp
irmovq 4, %rbx
pushq %rbx
call isodd
irmovq result, %rbx
rmmovq %rax, 0(%rbx)
halt

isodd:
mrmovq 8(%rsp), %rax
irmovq 2, %rsi
modq %rsi, %rax
je done
irmovq 1, %rax
done:
ret

.pos 0x1000
result: .quad 0xDEADBEEF

# The stack
.pos 0x1FE0
.quad 0xDEADBEEF
.quad 0xDEADBEEF
.quad 0xDEADBEEF
.quad 0xDEADBEEF
Icode Ifun rA rB valA valB valC valP ValE ValM nextPC
irmovq 0x2000, %rsp 3 0 F 4 0 0 2000 A 2000 0 A
irmovq 4, %rbx 3 0 F 3 0 0 4 14 4 0 14
pushq %rbx A 0 3 F 4 2000 0 16 4 0 16
call isodd 8 0 0 0 0 1FF8 34 1F 1FF0 0 34
mrmovq 8(%rsp), %rax
irmovq 2, %rsi
modq %rsi, %rax
je done
ret
irmovq result, %rbx
rmmovq %rax,0(%rbx)
halt

CPSC 313.203 – 2019W2 Sequential CPU

68

69
irmovq 0x2000, %rsp
irmovq 4, %rbx
pushq %rbx
call isodd
irmovq result, %rbx
rmmovq %rax, 0(%rbx)
halt

isodd:
mrmovq 8(%rsp), %rax
irmovq 2, %rsi
modq %rsi, %rax
je done
irmovq 1, %rax
done:
ret

.pos 0x1000
result: .quad 0xDEADBEEF

# The stack
.pos 0x1FE0
.quad 0xDEADBEEF
.quad 0xDEADBEEF
.quad 0xDEADBEEF
.quad 0xDEADBEEF
Icode Ifun rA rB valA valB valC valP ValE ValM nextPC
irmovq 0x2000, %rsp 3 0 F 4 0 0 2000 A 2000 0 A
irmovq 4, %rbx 3 0 F 3 0 0 4 14 4 0 14
pushq %rbx A 0 3 F 4 2000 0 16 4 0 16
call isodd 8 0 0 0 0 1FF8 34 1F 1FF0 0 34
mrmovq 8(%rsp), %rax 5 0 0 4 0 1FF0 8 3E 1FF8 4 3E
irmovq 2, %rsi 3 0 F 6 0 0 2 48 2 4 48
modq %rsi, %rax 6 6 6 0 2 4 9 4A 9 4 4A
je done 7 3 0 0 53 0 5D 53 0 4 5D
ret 9 0 0 0 1FF0 1FF0 0 5E 1FF8 1F 1F
irmovq result, %rbx 3 0 F 3 0 0 1000 29 1000 0 29
rmmovq %rax,0(%rbx) 4 0 0 3 0 1000 0 33 1000 0 33
halt 0 0 0 0 0 0 0 34 0 0 33

This illustrates and interesting problem: What is in a register/signal when that signal isn’t used. It might be
Better to put in a “?” to indicate that we don’t know, but in this case we are just repeating the last set value
which may or may not be what is really there.

CPSC 313.203 – 2019W2 Sequential CPU