Impress
CMPSC-F353
Architecture of Comp Systems
Digital Components
Digital Components
Decoder
A combinational circuit that converts binary information from the n coded inputs to a maximum of 2n unique outputs
n-to-m line decoder = n x m decoder
n inputs, m outputs
If the n-bit coded information has unused bit combinations, the decoder may have less than 2n outputs
m 2n
3-to-8 Decoder
3-to-8 Decoder
Logic Diagram :
Truth Table :
Commercial decoders
include Enable Input(E)
A2
A1
A0
D0
D1
D2
D3
D4
D5
D6
D7
Enable(E)
3 X 8 Decoder constructed with two 2 X 4 Decoder
Enable inputs are a convenient way to interconnect circuits
A0
A1
A2
D0
D1
D2
D3
D4
D5
D6
D7
A 3-to-8 Decoder constructed with two with 2-to-4 Decoder
Decoder Expansion
Encoder
Inverse operation of a decoder
2n inputs, n outputs
3 OR Gates Implementation
A0 = D1 + D3 + D5 + D7
A1 = D2 + D3 + D6 + D7
A2 = D4 + D5 + D6 + D7
Encoder
Multiplexers
Multiplexer(Mux)
A combinational circuit that receives binary information from one of 2n input data lines and directs it to a single output line
A 2n to 1 multiplexer has 2n input data lines and
n input selection lines (Data Selector)
Example:
4-to-1 multiplexer:
I0
I1
I2
I3
S0
S1
Y
Multiplexers
Sometimes 2 or more multiplexers are enclosed in a package. Enable and Select inputs are shared among all.
Example: Quadruple 2-to-1 Multiplexer
Quadruple
2 x 1
Mux
A0
A1
A2
A3
B0
B1
B2
B3
Y0
Y1
Y2
Y3
Enable
Select
Multiplexer Expansion
Make a 8×1 multiplexer using 4×1 multiplexers with and without enable inputs.
Registers
Register
A group of flip-flops with each flip-flop capable of storing one bit of information
An n-bit register has a group of n flip-flops and is capable of storing any binary information of n bits
The simplest register consists only of flip-flops, with no external gate
A clock input C will load all four inputs in parallel
The clock must be inhibited if the content of the register must be left unchanged
I0
I1
I2
I3
Clock
Clear
A0
A1
A2
A3
4-bit register
Register with Parallel Load
Register with Parallel Load
A 4-bit register with a load control input
The clock inputs receive clock pulses at all times
The buffer gate in the clock input reduces power requirement
Load Input
1 : Four input transfer
0 : Input inhibited, Feedback from output to input(no change)
M..Morris Mano. 1993. Computer System Architecture (3rd ed.). Pearson, Page 52
Shift Registers
Shift Register
A register capable of shifting its binary information in one or both directions
The logical configuration of a shift register consists of a chain of flip-flops in cascade
The simplest possible shift register uses only flip-flops
The serial input determines what goes into the leftmost position during the shift
The serial output is taken from the output of the rightmost flip-flop
M..Morris Mano. 1993. Computer System Architecture (3rd ed.). Pearson, Page 53
Bidirectional Shift Register with Parallel Load
A register capable of shifting in one direction only is called a unidirectional shift register
A register that can shift in both directions is called a bidirectional shift register
The most general shift register has all the capabilities listed below:
An input clock pulse to synchronize all operations
A shift-right /left (serial output/input)
A parallel load, n parallel output lines
The register can remain unchanged even though clock pulses are applied continuously
Bidirectional Shift Register with Parallel Load
Bidirectional Shift Register with Parallel Load
M..Morris Mano. 1993. Computer System Architecture (3rd ed.). Pearson, Page 55
Binary Counter
Counter
A register goes through a predetermined sequence of states (Upon the application of input pulses)
Used for counting the number of occurrences of an event and useful for generating timing signals to control the sequence of operations in digital computers
An n-bit binary counter is a register of n flip-flop (count from 0 to 2n -1)
How to design a counter?
We did a 2-bit counter sequential circuit.
Suppose we want to design a 4-bit counter, Is there an easier way?
4-bit Synchronous Binary Counter
Going through the sequence 0000, 0001, 0010, 0011,… we see that:
LSB is complemented after every count
A bit is complemented after a count if and only if all its lower-order bits are 1.
A counter circuit will usually employ F/F with complementing capabilities(T and J-K F/F)
M..Morris Mano. 1993. Computer System Architecture (3rd ed.). Pearson, Page 57
What’s next?
HW2 is due Monday 9/23
Reading:
Chapter 2:
Section 2.2 to 2.7
Sheet1
Enable Inputs Outputs
E A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
0 x x x 0 0 0 0 0 0 0 0
1 0 0 0 0 0 0 0 0 0 0 1
1 0 0 1 0 0 0 0 0 0 1 0
1 0 1 0 0 0 0 0 0 1 0 0
1 0 1 1 0 0 0 0 1 0 0 0
1 1 0 0 0 0 0 1 0 0 0 0
1 1 0 1 0 0 1 0 0 0 0 0
1 1 1 0 0 1 0 0 0 0 0 0
1 1 1 1 1 0 0 0 0 0 0 0
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2 X 4
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2�
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2 X 4
Decoder�
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0�
2�
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Sheet1
Inputs Outputs
D7 D6 D5 D4 D3 D2 D1 D0 A2 A1 A0
0 0 0 0 0 0 0 1 0 0 0
0 0 0 0 0 0 1 0 0 0 1
0 0 0 0 0 1 0 0 0 1 0
0 0 0 0 1 0 0 0 0 1 1
0 0 0 1 0 0 0 0 1 0 0
0 0 1 0 0 0 0 0 1 0 1
0 1 0 0 0 0 0 0 1 1 0
1 0 0 0 0 0 0 0 1 1 1
Sheet1
Select Output
S1 S0 Y
0 0 I0
0 1 I1
1 0 I2
1 1 I3
SelectOutput
E S Y
0 xAll 0’s
1 0A
1 1B
Sheet1
Select Output
E S Y
0 x All 0’s
1 0 A
1 1 B
1 1 I3
Sheet1
Mode Operation
S1 S0
0 0 No chage
0 1 Shift right(down)
1 0 shift left(up)
1 1 Parallel load