程序代写代做代考 compiler CSCE-312 Day 1 Introduction

CSCE-312 Day 1 Introduction

L18 – HACK CPU

Hack computer
Computer System
data out
data
memory
instruction
memory

instruction

ALU

CPU
input
output

address
data in
of next instruction
D register
A register
PC
credit: nand2tetris.org
2

Hack CPU
Computer System
data out
data
memory
instruction
memory

instruction

ALU

CPU
input
output

address
data in
of next instruction
D register
A register
PC
Hack CPU: A 16-bit processor, designed to:
Execute the current instruction: dataOut = instruction(dataIn)
Figure out which instruction to execute next.

credit: nand2tetris.org
3

Hack CPU Interface

to data memory

to instruction memory

from
data
memory

from instruction memory

from
the user

credit: nand2tetris.org
4

Hack CPU Interface

to data memory

to instruction memory

data in

from
the user

credit: nand2tetris.org
5

Hack CPU Interface

to data memory

to instruction memory

data in

from
the user

credit: nand2tetris.org
6

Hack CPU Interface

data out

to instruction memory

data in

from
the user

credit: nand2tetris.org
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Hack CPU Interface

data out

address of next instruction

data in

restarting signal

pc
credit: nand2tetris.org
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Hack CPU Interface

data out

address of next instruction

data in

restarting signal

pc
credit: nand2tetris.org
9

Hack CPU Implementation

pc
10
credit: nand2tetris.org

It’s a very lean ALU, consisting of 2 registers, named D and A, a program counter, an ALU, and few more trivial gates.
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Hack CPU Implementation

(each “C” symbol represents a control bit)
pc
11
credit: nand2tetris.org

It’s a very lean ALU, consisting of 2 registers, named D and A, a program counter, an ALU, and few more trivial gates.
11

Hack CPU Implementation

(each “C” symbol represents a control bit)
pc
Disclaimer:
In what follows we don’t explain all the details of the CPU implementation, intentionally
We give enough information to let you figure out the implementation on your own, when you will actually build the CPU in project 5.
12
credit: nand2tetris.org

It’s a very lean ALU, consisting of 2 registers, named D and A, a program counter, an ALU, and few more trivial gates.
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CPU operation

pc
13
credit: nand2tetris.org

CPU operation: instruction handling

pc
14
credit: nand2tetris.org

CPU operation: instruction handling
0000000000000101
A-instruction
@5
15
credit: nand2tetris.org

Colors meaningless
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CPU operation: handling A-instructions
CPU handling of an A-instruction:
0000000000000101
A-instruction
@5
16
credit: nand2tetris.org

Colors meaningless
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CPU operation: handling A-instructions
CPU handling of an A-instruction:
Decodes the instruction into:
op-code
15-bit value
Stores the value in the A-register
Outputs the value (not shown in this diagram).
0000000000000101
A-instruction
@5
17
credit: nand2tetris.org

Colors meaningless
17

CPU operation: instruction handling
D=D+1;JMP
1110011111010111
C-instruction
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credit: nand2tetris.org

Colors meaningless
Cannot have two instructions at the same time!
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CPU operation: handling C-instructions
CPU handling of a C-instruction:

D=D+1;JMP
C-instruction
1110011111010111
19
credit: nand2tetris.org

Colors meaningless
Cannot have two instructions at the same time!
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CPU operation: handling C-instructions
D=D+1;JMP
C-instruction
CPU handling of a C-instruction:
Decodes the instruction bits into:
Op-code
ALU control bits
Destination load bits
Jump bits
Routes these bits to their chip-part destinations
The chip-parts (most notably, the ALU) execute the instruction.

1110011111010111
20
credit: nand2tetris.org

Colors meaningless
Cannot have two instructions at the same time!
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CPU operation: handling C-instructions
1110011111010111
ALU control inputs:
control bits
(from the instruction)
011111
writeM
ALU data inputs:
Input 1: from the D-register
Input 2: from either:
A-register, or
data memory
11…01
10…10

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credit: nand2tetris.org

CPU operation: handling C-instructions
1110011111010111

writeM
11…01
10…10
ALU data output:
Result of ALU calculation
Fed simultaneously to: D-register, A-register, data memory
01 … 11

0
1
0
Which destination actually commits to the ALU output is determined by the instruction’s destination bits.
011111
22
credit: nand2tetris.org

CPU operation: handling C-instructions
ALU control outputs:
is the output negative?
is the output zero?
01 … 11
1110011111010111
writeM

11…01
10…10
011111
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credit: nand2tetris.org

CPU operation: control

pc
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credit: nand2tetris.org

Which instruction should be executed next?
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CPU operation: control
The computer is loaded with some program;
Pushing reset causes the program to start running.

computer exterior (well, kind of)
reset
reset
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credit: nand2tetris.org

CPU operation: control

pc
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credit: nand2tetris.org

Which instruction should be executed next?
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CPU operation: control
PC operation (abstraction)
Emits the address of the next instruction:
restart: PC = 0
no jump: PC++
goto: PC=A
conditional goto: if (condition) PC = A else PC++

load
16
1
16
address of next instruction
pc
27
credit: nand2tetris.org

The botom line of this whole aparatus is the address of the next instruction
Assumption: if the j-bits code a goto directive, then we assume that the A register was previously set to the goto address
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CPU operation: control
PC operation (implementation)
if (reset==1) PC = 0
else
// in the course of handling the current instruction:
load = f (jump bits, ALU control outputs)
if (load == 1) PC = A // jump
else PC++ // next instruction

load
16
1
16
111 a c c c c c c d d d j j j
address of next instruction
pc
28
credit: nand2tetris.org

The botom line of this whole aparatus is the address of the next instruction
Assumption: if the j-bits code a goto directive, then we assume that the A register was previously set to the goto address
28

Hack CPU Implementation

That’s It!
pc
29
credit: nand2tetris.org

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30
Project – P5
credit: nand2tetris.org

Hardware organization: a hierarchy of chip parts
computer
memory
CPU
RAM units
ALU
PC
elementary logic gates
registers
adder
credit: nand2tetris.org
31

Hardware projects
computer
memory
CPU
RAM chips
ALU
registers
PC
elementary logic gates
adder
p1
p2
p2
p5
p5
p5
p3
p3
p3
credit: nand2tetris.org
32

Project 5: building the Hack Computer
computer
memory
CPU
RAM chips
ALU
registers
PC
elementary logic gates
adder
p5
p5
p5
credit: nand2tetris.org
33

Abstraction

Hack Computer

Hello, world

credit: nand2tetris.org
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Implementation

Hello, world

credit: nand2tetris.org
35

CPU Abstraction

Hack CPU
36
credit: nand2tetris.org

Use built-in chip parts
It’s a very lean ALU, consisting of 2 registers, named D and A, a program counter, an ALU, and few more trivial gates.
36

CPU Implementation

Implementation tips:
Chip-parts: Mux16, ARegister, DRegister, PC, ALU, …
Control: use HDL subscripting to parse and route the instruction bits to the
control bits of the relevant chip-parts.

111 a cccccc ddd jjj

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credit: nand2tetris.org

Use built-in chip parts
It’s a very lean ALU, consisting of 2 registers, named D and A, a program counter, an ALU, and few more trivial gates.
37

CPU Implementation
/**
* The Central Processing unit (CPU).
* Consists of an ALU and a set of registers,
* designed to fetch and execute instructions
* written in the Hack machine language.
*/
CHIP CPU {

IN
inM[16], // value of M = RAM[A]
instruction[16], // Instruction for execution
reset; // Signals whether to re-start the current program
// (reset == 1) or continue executing the current
// program (reset == 0).

OUT
outM[16] // value to write into M = RAM[A]
writeM, // Write into M?
addressM[15], // RAM address (of M)
pc[15]; // ROM address (of next instruction)

PARTS:
// Put you code here:
}
CPU.hdl

credit: nand2tetris.org
38

Hack Computer implementation

Hello, world

credit: nand2tetris.org
39

Memory implementation

Memory
credit: nand2tetris.org
40

/** Memory of 16K 16-bit registers */
CHIP RAM16K {
IN
address[14],
in[16],
load;
OUT
out[16];

BUILTIN RAM16K;
CLOCKED in, load;
}
Memory implementation
Implementation tips:
Use the three chip-parts:
RAM16K, Screen, and Keyboard
Route the address input to the correct address input of the relevant chip-part.
/** Memory of 8K 16-bit registers
* with a display unit side effect. */
CHIP Screen {
IN
address[13],
in[16],
load;
OUT
out[16];

BUILTIN Screen;
CLOCKED in, load;
}
/** 16-bit register with a
* keyboard input side effect */
CHIP Keyboard {
OUT
out[16];

BUILTIN Keyboard;
}
built-in chips
built-in chips
built in project 3
credit: nand2tetris.org
41

Hack Computer implementation
Implementation tip:
Use the built-in ROM32K chip.

Hello, world

credit: nand2tetris.org
42

Hack Computer implementation

Hello, world




credit: nand2tetris.org
43

Hack Computer implementation
/**
* The HACK computer, including CPU, ROM and RAM.
* When reset is 0, the program stored in the computer’s ROM executes.
* When reset is 1, the execution of the program restarts.
*/

CHIP Computer {

IN reset;

PARTS:
// Put your code here.
}
Computer.hdl

credit: nand2tetris.org
44

Best practice advice
Try to implement the chips in the given order
Strive to use as few chip-parts as possible
You will have to use chips that you’ve implemented in previous projects
The best practice is to use their built-in versions.
45
credit: nand2tetris.org

Perspective: from here to a “Traditional” computer
Caching
Pipelining/Super-Scalar
More I/O units
Special-purpose processors (I/O, graphics, communications, …)
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Perspective: from here to a “Traditional” computer
Multi-core / parallelism/
Efficiency
Energy consumption considerations
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Perspective: some issues we haven’t discussed (among many)
Hardware diversity: desktop, laptop, hand-held, game machines, …
General-purpose vs. embedded computers
Silicon compilers
And more …
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