程序代写代做代考 computer architecture assembly mips Introduction

Introduction
Lab #4: MIPS Single-Cycle Processor
In this lab you will build a simplified MIPS single-cycle processor using Verilog. You can use your ALU from Lab 1. The hardware implementation for a single cycle processor can be found in chapter 7.3 of the textbook, while the guideline for coding can be found in chapter 7.6. Then you will load a test program and confirm that the system works. You can find a sample test program on page 437 of the textbook. Next, you will implement two new instructions, and then write a new test program that confirms the new instructions work as well. By the end of this lab, you should thoroughly understand the internal operation of the MIPS single-cycle processor.
Before starting this lab, you should be very familiar with the single-cycle implementation of the MIPS processor described in Section 7.3 of your text, Digital Design and Computer Architecture. The single-cycle processor schematic from the text is repeated at the end of this lab assignment for your convenience. Please make sure to follow this design. This version of the MIPS single-cycle processor can execute the following instructions: add, sub, and, or, slt, lw, sw, beq, addi, and j.
Our model of the single-cycle MIPS processor divides the machine into two major units: the control and the datapath. Each unit is constructed from various functional blocks. For example, as shown in the figure on the last page of this lab, the datapath contains the 32-bit ALU that you designed in Lab 1, the register file, the sign extension logic, and five multiplexers to choose appropriate operands.
1. MIPS Single-Cycle Processor
The Verilog single-cycle MIPS module is given in Section 7.6 of the text. The code is given for the top module. The highest-level module, top, instantiates a data memory, instruction memory, and the MIPS processor. Each of the memories should be a 64-word ¡Á 32-bit array. The code for the instruction memory is given, which initializes the memory with a test program in ¡°memfile.dat¡±, which is the machine language code for the program given in Figure 7.60 of the textbook. Study the program until you understand what it does. The skeleton code for the MIPS processor and the data memory is also provided. Look in mips.v at the mips module, which instantiates two sub-modules, controller and datapath which should be implemented. Correlate signal names in the Verilog code with the wires on the schematic.
2. Testing the single-cycle MIPS processor
You need to write a test-bench module that instantiates the ¡°top¡± module to test your design. Name the module for that testbench tb. In a complex system, if you don¡¯t know what to expect the answer should be, you are unlikely to get the right answer. Begin by predicting what should happen on each cycle when running the program. Complete the chart in Table 1 at the end of the lab with your predictions. What address will the final sw instruction write to and what value will it write?
Simulate your processor with ModelSim. Be sure to add all of the .v files, including the one containing your ALU. Add all of the signals from Table 1 to your ¡°waves¡± window. (Note that
1

many are not at the top level; you¡¯ll have to drill down into the appropriate part of the hierarchy to find them.)
Run the simulation. Look at the waveforms and check that they match your predictions in Table 1. If you need to debug, you¡¯ll likely want to view more internal signals. However, on the final waveform that you turn in, show ONLY the following signals in this order: clk, reset, pc, instr, aluout, writedata, memwrite, and readdata. All the values need to be output in hexadecimal and must be readable to get full credit. After you have fixed any bugs, print out your final waveform containing these signals.
3. Modifying the MIPS single-cycle processor
Now, you need to modify the MIPS single-cycle processor by adding the ori and bne instructions. First, modify the MIPS processor schematic at the end of this lab to show what changes are necessary. You can draw your changes directly onto the schematic. Show your changes in the tables at the end of the lab. Finally, modify the Verilog code as needed to include your modifications.
4. Testing your modified MIPS single-cycle processor
Next, you¡¯ll need a test program to verify that your modified processor work. The program should check that your new instructions work properly and that the old ones didn¡¯t break. Use test2.asm below.
# test2.asm
#Assembly Code
main:
here: there:
ori $t0, $0, 0x8000
addi $t1, $0, -32768
ori $t2, $t0, 0x8001
beq $t0, $t1, there
slt $t3, $t1, $t0
bne $t3, $0, here
j there
sub $t2, $t2, $t0
ori $t0, $t0, 0xFF
add $t3, $t3, $t2
sub $t0, $t2, $t0
sw $t0, 82($t3)
Figure 1. MIPS assembly program: test2.asm
Convert the program to machine language (in hex) and put it in a file named memfile2.dat. Modify imem to load this file. Run the program and check your results. Debug if necessary. When you are done, print out the waveforms as before and indicate the address and data value written by the sw instruction.
What to Turn In
1. report in a single pdf file, containing each of the following items, clearly labeled and in the following order:
a. Please indicate how many hours you spent on this lab. This will not affect your grade (unless omitted), but will be helpful for calibrating the workload for next semester¡¯s labs.
b. A completed version of Table 1. 2

c. An image of the simulation waveforms showing correct operation of the processor. Does it write the correct value to address 84?
The simulation waveforms should give the signal values in hexadecimal format and should be in the following order: clk, reset, pc, instr, aluout, writedata, memwrite, and readdata. Do not display any other signals in the waveform. Check that the waveforms are zoomed in enough that the grader can read your bus values. Unreadable waveforms will receive no credit. Use several pages and multiple images if necessary.
d. Marked up versions of the datapath schematic and decoder tables that add the ori and bne instructions.
e. Your Verilog code for your modified MIPS processor (including ori and bne functionality) with the changes highlighted and commented.
f. Completed version of Tables 2 and 3 for the modified MIPS processor.
g. The contents of your memfile2.dat containing your test2 machine language code.
h. An image of the simulation waveforms showing correct operation of your modified processor on the new program. What address and data value are written by the sw instruction?
2. The final version of your codes (after adding ori and bne instructions). Codes should be heavily commented. Do not change the inputs and outputs of the given modules. Compress all your files to a single compressed file.
Make sure you name your test-bench module, tb. Email the report (single pdf file) and your Verilog files (single .rar or .zip file) to: ucsb.ece.154a@gmail.com. Follow the following naming convention to name the files:
Pdf: firstname_lastname_lab4.pdf
V files: firstname_lastname_lab4.zip or firstname_lastname_lab4.rar Email¡¯s Subject: ¡°firstname_lastname_Lab4¡±.
3

Cycle
reset
pc
Instr
branch
srca
srcb
aluresult
zero
pcsrc
Writedata
memwrite
read data
1
1
00
addi $2,$0,5
20020005
0
0
5
5
0
0
0
0
x
2
0
04
addi $3,$0,12
2003000c
0
0
c
c
0
0
0
0
x
3
0
08
addi $7,$3,-9
20067fff7
0
C
-9
3
0
0
0
0
x
4
0
0C
4
Table 1. First sixteen cycles of executing the test code of Fig. 7.60 in the textbook

Jump
Control MemWrite
Unit
MemtoReg Branch
31:26 Op
ALUSrc Funct RegDst
RegWrite
CLK
ALUControl2:0
PCSrc
5:0
0 0 1 1
CLK
PC’
PC
Instr
25:21
20:16 15:11
15:0
25:0
SrcA Zero ALUResult
ReadData 0 Result 1
CLK
A RD
Instruction Memory
20:16
A1 WE3 RD1
A2 RD2 A3
WD3 Register File
WE
A RD
Data Memory
WD
PCJump
0
1
0 SrcB 1
<<2 WriteData PCBranch PCPlus4 WriteReg 4:0 4 ImmExt 27:0 31:28 Sign Extend <<2 5 Single-cycle MIPS processor + ALU + Table 2. Extended functionality for the main decoder: Instruction Op5:0 RegWrite RegDst AluSrc Branch MemWrite MemtoReg ALUOp1:0 Jump R-type 000000 1 1 0 0 0 0 10 0 lw 100011 1 0 1 0 0 1 00 0 sw 101011 0 X 1 0 1 X 00 0 beq 000100 0 X 0 1 0 X 01 0 addi 001000 1 0 1 0 0 0 00 0 j 000010 0 X X X 0 X XX 1 ori 001101 bne 000101 Table 3. Extended functionality for the ALU decoder: ALUOp1:0 Meaning 00 Add 01 Subtract 10 Look at funct field 11 6