程序代写代做代考 Impress

Impress

CMPSC-F353
Architecture of Comp Systems

Basic Computer
Organization and Design

Control Unit

Flowchart for Instruction Cycle
D7

Register Ref. Instruction
r = D7I’T3 :
IR(i) = Bi IR(0 -11)
B0 – B11 : 12 bits Register Ref. Instruction

Address
Register Reference Instructions
M..Morris Mano. 1993. Computer System Architecture (3rd ed.). Pearson, Page 144

Memory Ref. Instruction
D7 : Register or I/O = 1
D6 – D0 : 7 bits Memory Ref. Instruction
Execution of a memory-reference instruction starts at T4
AND to AC

ADD to AC

LDA : memory read

IR(12,13,14)
= 111

3 X 8 Decoder

Memory-Reference Instructions

STA : memory write

BUN : branch unconditionally

BSA : branch and save return address

Example of BSA:

Memory-Reference Instructions
M..Morris Mano. 1993. Computer System Architecture (3rd ed.). Pearson, Page 148

ISZ : increment and skip if zero

Control Flowchart :
Flowchart for the 7 memory reference instruction
The longest instruction : ISZ(T6)

Memory-Reference Instructions

M..Morris Mano. 1993. Computer System Architecture (3rd ed.). Pearson, Page 150

Input-Output Configuration :
Input Register(INPR), Output Register(OUTR)
These two registers communicate with a communication interface serially and with the AC in parallel
Each quantity of information has 8 bits of an alphanumeric code
Input Flag(FGI), Output Flag(FGO)
FGI : set when INPR is ready clear when INPR is empty
FGO : set when operation is completed clear when output device is in the process of printing

1 : Ready
0 : Not ready
Input-Output and Interrupt

M..Morris Mano. 1993. Computer System Architecture (3rd ed.). Pearson, Page 151

Input-Output Instructions :
p = D7IT3 :
IR(i) = Bi IR(6 -11)
B6 – B11 : 6 bit I/O Instruction

Address

Input-Output Instructions
M..Morris Mano. 1993. Computer System Architecture (3rd ed.). Pearson, Page 152

Interrupt Cycle :
During execution, IEN is checked by the control
IEN = 0 : the programmer does not want to use the interrupt, so control continues with the next instruction cycle
IEN = 1 : the control circuit checks the flag bit, If either flag set to 1, R F/F is set to 1
At the end of the execute phase, control checks the value of R
R = 0 : instruction cycle
R = 1 : interrupt cycle
Interrupts

Demonstration of the interrupt cycle :
The memory location at address 0 as the place for storing the return address
Interrupt Branch to memory location 1

The condition for R = 1

Modified Fetch Phase
Modified Fetch and Decode Phase
Save Return
Address(PC) at 0

Jump to 1(PC=1)

Interrupts

M..Morris Mano. 1993. Computer System Architecture (3rd ed.). Pearson, Page 155

Complete Computer Description

M..Morris Mano. 1993. Computer System Architecture (3rd ed.). Pearson, Page 158

The basic computer consists of the following hardware components:
A memory unit with 4096 words of 16bits
Nine registers : AR, PC, DR, AC, IR, TR, OUTR, INPR, and SC
Seven F/Fs : I, S, E, R, IEN, FGI, and FGO
Two decoders in control unit : 3 x 8 operation decoder, 4 x 16 timing decoder
A 16-bit common bus
Control Logic Gates : Control Output
Adder and Logic circuit connected to the AC input
Control Logic Gates
Signals to control the inputs of the nine registers
Signals to control the read and write inputs of memory
Signals to set, clear, or complement the F/Fs
Signals for S2 S1 S0 to select a register for the bus
Signals to control the AC adder and logic circuit

Design of Basic Computer

Register Control : AR
Control inputs of AR : LD, INR, CLR
Find all the statements that change the AR
in Tab. 5-6
Control functions

Control of Registers and Memory

Memory Control : READ
Control inputs of Memory : READ, WRITE
Find all the statements that specify a read operation in Tab. 5-6
Control function

F/F Control : IEN
Control functions

Control of Registers and Memory

Encoder for Bus Selection : Tab. 5-7
S0 = x1 + x3 + x5 + x7
S1 = x2 + x3 + x6 + x7
S2 = x4 + x5 + x6 + x7
x1 = 1 :

Control Function :
x2 = 1 :

x7 = 1 :
Same as Memory Read
Control Function :

Encoder
Multiplexer
Bus Select
Input

x1
x2
x3
x4
x5
x6
x7

S0
S1
S2

Bus Control

Circuits associated with AC :

Fig. 5-21
Fig. 5-20
Fig. 2-11
Design of Accumulator Logic

Find the statement that change the AC :

LD
INR
CLR
Control of AC

Adder and Logic Circuit

Mano Machine
Fig. 5-4 : Common Bus(p.130)
Fig. 2-11 : Register(p. 59)
Fig. 5-6 : Control Unit(p. 137)
Fig. 5-16, 17,18 : Control Logic Gate(p.161- 163)
Fig. 5-20 : AC control(p.165)
Fig. 5-21 : Adder and Logic(p.166)

Integration !

What’s next?

HW#5 is due on Tuesday 22nd

Reading:
Chapter 5:
Section 5.4 to 5.10

Control
logic
gates�
I�
15 14 1 0
4��16
decoder�
4-bit
sequence
counter
(SC)�
3��8
decoder
7 6 5 4 3 2 1 0�
15 14 13 12 11 – 0 �
D�
0�
Instruction register (IR)�
Increment(INR)�
Clear(CLR)�
Other inputs�
Control
outputs�
Clock�
T�
0�
T�
15�
D�
7�
.
.
.


.
.
.


.
.
.


.
.
.

Start
SC 0�
Execute
memory-reference
instruction
SC 0�
Decode operation code in IR(12-14)
AR IR(0-11), I I(15)�
Nothing�
Execute
input-output
instruction
SC 0�
AR M[AR]�
Execute
register-reference
instruction
SC 0�
IR M[AR], PC PC+1�
AR PC�
I�
I�
I�
T�
0�
T�
3�
T�
3�
T�
3�
T�
3�
T�
2�
T�
1�
(Register or I/O) = 1�
0 = (Memory-reference�
0 = (register)�
(I/O) = 1�
(indirect) = 1�
0 = (direct)�

0,:
][:
50
40


SCDRACACTD
ARMDRTD

0,,:
][:
51
41


SCCEDRACACTD
ARMDRTD
out

0,:
][:
52
42


SCDRACTD
ARMDRTD

0,][:
43
 SCACARMTD

0,:
44
 SCARPCTD

0,:
1,][:
55
45


SCARPCTD
ARARPCARMTD

0),(136)(136:
1135)(136),(21]135[:
55
45


SCARPCTD
ARPCMTD

0),1()0(,][:
1:
][:
66
56
46



SCPCPCthenDRifDRARMTD
DRDRTD
ARMDRTD

Execute
instruction�
Branch to location 1
PC 1�
R�
Store return address
in location 0
M[0] PC�
Fetch and decode
instruction�
IEN 0
R 0�
FGI�
FGO�
IEN�
R 1 �
=0�
=1�
=0�
=0�
=0�
=1�
=1�
=1�
Instruction cycle�
Interrupt cycle�

0,0,0,1:
0,][:
,0:
2
1
0



SCRIENPCPCRT
PCTRARMRT
PCTRARRT

1:))((

2

1

0
 RFGOFGIIENTTT

?AR

AR�
LD�
T�
2�
T�
3�
D’�
7�
Clock�
CLR�
INR�
To Bus�
From Bus�
12�
12�
I�
R�
T�
4�
D�
5�
T�
0�

][? ARM

?][ARM

?IEN

0:
0:
1:
2
6
7



IENRT
IENpB
IENpB

T�
3�
D’�
7�
B�
6�
I�
B�
7�
R�
T�
2�
Clock�
IEN�
p�

ARFindARBus  ?

ARPCTD
ARPCTD


:
:
55
44

55441
TDTDx 

PCFindPCBus  ?

][? ARMFindMemoryBus 

Adder and
logic
circuit�
Accumulator
register
(AC)�
Control
gates�
INR�
LD�
CLR�
Clock�
From DR�
To Bus�
From INPR�
16�
16�
16�
16�
8�

?AC

1:
0:
)0(,:
)15(,:
:
)70(:
:
:
:
5
11
6
7
9
11
52
51
50









ACACrB
ACrB
EACACshrACrB
EACACshrACrB
ACACrB
INPRACpB
DRACTD
DRACACTD
DRACACTD

AC�
LD�
T�
5�
D�
0�
Clock�
CLR�
INR�
To Bus�
From adder
and logic�
16�
16�
p�
B�
11�
D�
1�
T�
5�
D�
2�
r�
B�
9�
B�
5�
B�
6�
B�
7�
B�
11�
AND�
COM�
INPR�
DR�
ADD�
INC�
SHL�
SHR�
CLR�

AND�
COM�
INPR�
DR�
ADD�
SHL�
SHR�
FA�
J�
Q�
K�
LD�
(Output of OR gate in Fig. 5-20)�
(Fig.2-11)�
I

i�
AC(i)�
Clock�
AC(i-1)�
AC(i+1)�
From
INPR
bit(i)�
C�
i+1�
C�
i�
DR(i)�
AC(i)�

Sheet1
J K Q(t+1)
0 1 0
1 0 1