Impress
CMPSC-F353
Architecture of Comp Systems
Basic Computer
Organization and Design
Control Unit
Flowchart for Instruction Cycle
D7
Register Ref. Instruction
r = D7I’T3 :
IR(i) = Bi IR(0 -11)
B0 – B11 : 12 bits Register Ref. Instruction
Address
Register Reference Instructions
M..Morris Mano. 1993. Computer System Architecture (3rd ed.). Pearson, Page 144
Memory Ref. Instruction
D7 : Register or I/O = 1
D6 – D0 : 7 bits Memory Ref. Instruction
Execution of a memory-reference instruction starts at T4
AND to AC
ADD to AC
LDA : memory read
IR(12,13,14)
= 111
3 X 8 Decoder
Memory-Reference Instructions
STA : memory write
BUN : branch unconditionally
BSA : branch and save return address
Example of BSA:
Memory-Reference Instructions
M..Morris Mano. 1993. Computer System Architecture (3rd ed.). Pearson, Page 148
ISZ : increment and skip if zero
Control Flowchart :
Flowchart for the 7 memory reference instruction
The longest instruction : ISZ(T6)
Memory-Reference Instructions
M..Morris Mano. 1993. Computer System Architecture (3rd ed.). Pearson, Page 150
Input-Output Configuration :
Input Register(INPR), Output Register(OUTR)
These two registers communicate with a communication interface serially and with the AC in parallel
Each quantity of information has 8 bits of an alphanumeric code
Input Flag(FGI), Output Flag(FGO)
FGI : set when INPR is ready clear when INPR is empty
FGO : set when operation is completed clear when output device is in the process of printing
1 : Ready
0 : Not ready
Input-Output and Interrupt
M..Morris Mano. 1993. Computer System Architecture (3rd ed.). Pearson, Page 151
Input-Output Instructions :
p = D7IT3 :
IR(i) = Bi IR(6 -11)
B6 – B11 : 6 bit I/O Instruction
Address
Input-Output Instructions
M..Morris Mano. 1993. Computer System Architecture (3rd ed.). Pearson, Page 152
Interrupt Cycle :
During execution, IEN is checked by the control
IEN = 0 : the programmer does not want to use the interrupt, so control continues with the next instruction cycle
IEN = 1 : the control circuit checks the flag bit, If either flag set to 1, R F/F is set to 1
At the end of the execute phase, control checks the value of R
R = 0 : instruction cycle
R = 1 : interrupt cycle
Interrupts
Demonstration of the interrupt cycle :
The memory location at address 0 as the place for storing the return address
Interrupt Branch to memory location 1
The condition for R = 1
Modified Fetch Phase
Modified Fetch and Decode Phase
Save Return
Address(PC) at 0
Jump to 1(PC=1)
Interrupts
M..Morris Mano. 1993. Computer System Architecture (3rd ed.). Pearson, Page 155
Complete Computer Description
M..Morris Mano. 1993. Computer System Architecture (3rd ed.). Pearson, Page 158
The basic computer consists of the following hardware components:
A memory unit with 4096 words of 16bits
Nine registers : AR, PC, DR, AC, IR, TR, OUTR, INPR, and SC
Seven F/Fs : I, S, E, R, IEN, FGI, and FGO
Two decoders in control unit : 3 x 8 operation decoder, 4 x 16 timing decoder
A 16-bit common bus
Control Logic Gates : Control Output
Adder and Logic circuit connected to the AC input
Control Logic Gates
Signals to control the inputs of the nine registers
Signals to control the read and write inputs of memory
Signals to set, clear, or complement the F/Fs
Signals for S2 S1 S0 to select a register for the bus
Signals to control the AC adder and logic circuit
Design of Basic Computer
Register Control : AR
Control inputs of AR : LD, INR, CLR
Find all the statements that change the AR
in Tab. 5-6
Control functions
Control of Registers and Memory
Memory Control : READ
Control inputs of Memory : READ, WRITE
Find all the statements that specify a read operation in Tab. 5-6
Control function
F/F Control : IEN
Control functions
Control of Registers and Memory
Encoder for Bus Selection : Tab. 5-7
S0 = x1 + x3 + x5 + x7
S1 = x2 + x3 + x6 + x7
S2 = x4 + x5 + x6 + x7
x1 = 1 :
Control Function :
x2 = 1 :
x7 = 1 :
Same as Memory Read
Control Function :
Encoder
Multiplexer
Bus Select
Input
x1
x2
x3
x4
x5
x6
x7
S0
S1
S2
Bus Control
Circuits associated with AC :
Fig. 5-21
Fig. 5-20
Fig. 2-11
Design of Accumulator Logic
Find the statement that change the AC :
LD
INR
CLR
Control of AC
Adder and Logic Circuit
Mano Machine
Fig. 5-4 : Common Bus(p.130)
Fig. 2-11 : Register(p. 59)
Fig. 5-6 : Control Unit(p. 137)
Fig. 5-16, 17,18 : Control Logic Gate(p.161- 163)
Fig. 5-20 : AC control(p.165)
Fig. 5-21 : Adder and Logic(p.166)
Integration !
What’s next?
HW#5 is due on Tuesday 22nd
Reading:
Chapter 5:
Section 5.4 to 5.10
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