程序代写代做代考 mips Introduction

Introduction
Lab #5: MIPS Multi-Cycle Processor
In this lab you will design and build your own multicycle MIPS processor. You may reuse any of your hardware (Verilog modules) from previous labs.
Your multicycle processor should match the design from the text, which is reprinted in Figure 1 for your convenience. It should handle the following instructions: add, sub, and, or, slt, lw, sw, beq, addi, and j. The multicycle processor is divided into three units: the controller, datapath, and mem (memory) units. Note that the mem unit contains the shared memory used to hold both data and instructions. Also note that the controller unit comprises both the Main Decoder that takes OP5:0 as inputs and the ALU Decoder that takes as inputs ALUOp1:0 and the Funct5:0 code from the 6 least significant bits of the instruction. The controller unit also includes the gates needed to produce the write enable signal, PCEn, for the PC register.
Generating Control Signals
Before you begin developing the hardware for your MIPS multicycle processor, you’ll need to determine the correct control signals for each state in the multicycle processor’s state transition diagram. This state transition diagram is shown in Figure 7.42 in the book (also reprinted here as Figure 2). Complete the output table of the Main Decoder in Table 4. Give the FSM control word in hexadecimal for each state. The first two rows are filled in as examples. Be careful with this step. It takes much longer to debug an erroneous circuit than to design it correctly the first time.
Overall Design
Now you will begin the hardware implementation of your multicycle processor. Start with the mipsmulti.v file that is given to you. The mips module instantiates both the datapath and control unit (called the controller module). The controller module should in turn instantiate the main decoder module (maindec) and the ALU decoder module (aludec). In this lab you have to design both the cotroller and the datapath. The memory is essentially identical to the data memory from Lab 4 and is provided for you.
1

control
CLK
PCWrite
IorD Control Unit
Op Funct
Branch
PCSrc1:0
PCEn
MemWrite
ALUControl2:0
IRWrite
ALUSrcB1:0
31:26
ALUSrcA
5:0
RegWrite
CLK PC
CLK
Adr
CLK
Instr
CLK
CLK
A
31:28
0
1
00
SrcA
Zero
CLK
00 ALUOut 01
10
WE
RD
A
Instr / Data Memory
WD
25:21
A1 WE3 RD1 A2 RD2
A3 WD3
PC’
0
1
EN
EN
20:16
B
mem
CLK
Data
20:16 0 15:11 1
0
1
Register File
4
01 SrcB 10
11
ALUResult PCJump
<<2 <<2 27:0 15:0 25:0 (jump) Sign Extend ImmExt datapath Figure 1. Multicycle Processor 2 MemtoReg RegDst ALU Unit Overview The three units have the following inputs and outputs. [5:0] [5:0] CLK Reset Op Funct Zero Input Input Input Input Input IorD MemWrite IRWrite RegDst MemtoReg RegWrite ALUSrcA ALUSrcB ALUControl PCSrc PCEn Output Output Output Output Output Output Output Output Output Output Output CLK Reset PCEn IorD IRWrite Input Input Input Input Input RegDst MemtoReg RegWrite ALUSrcA ALUSrcB ALUControl PCSrc ReadData Op Funct Zero Adr WriteData Input Input Input Input Input Input Input Input Output Output Output Output Output Table 1. Controller [5:0] [31:0] Table 2. Datapath [1:0] [31:0] [2:0] [5:0] [1:0] [5:0] [1:0] [2:0] [1:0] Note that PCWrite and Branch are internal signals (wires) within the controller. [5:0] [31:0] [31:0] 3. Memory 3 CLK Reset MemWrite Adr WriteData ReadData Table (mem) Input Input Input Input Input Output Control Unit Design The control unit consists of two modules, the Main Decoder and the ALU Decoder. The Main Decoder, maindec, should take the Opcode input and produce the outputs described in Table 4. On reset, the control unit should start at State 0. The control unit should support the instructions from Figure 7.42 in the text. The state transition diagram is also given at the end of this handout. Design your controller using an FSM for the Main Decoder and combinational logic for the ALU Decoder. Also include any additional logic needed to compute PCEn from the internal signals PCWrite, Branch, and Zero. The controller header is given showing its inputs and outputs. It would be a good idea to have a controllertest testbench for the controller module. Such testbench should test each of the instructions that the processor should support (add, sub, and, or, slt, lw, sw, beq, addi, and j), and both taken and non- taken branches. Visually inspect the states and outputs to verify that they match your expectations from Table 4. Also verify that PCEn performs correctly. If you find any errors, debug your circuit and correct the errors. Datapath Design Refer to Figure 1 for the hardware modules you need to set up your datapath. Design the datapath unit in Verilog. Remember that you may reuse hardware from earlier labs (such as the ALU, multiplexers, registers, sign-extension hardware modules, register file, etc.) wherever possible. All of your registers should take a Reset input to reset the initial value to a known state (0). The Instruction Register and PC also require enable inputs. Pay careful attention to bus connections; they are an easy place to make mistakes. Simulate your processor using the testbench from Lab 4. The Reset signal is set high at first. Display, at a minimum, the PC, Instr, FSM state (from within your controller module), SrcA and SrcB (from within your datapath), ALUResult, and Zero, and the control word. You will likely want to add other signals to help debug. Check that your results match the expectations from Table 5. If there are any mismatches, debug your design and fix the errors. Hints for Debugging  Be sure you thoroughly understand how the MIPS multicycle processor is supposed to work. This system is too complex to debug by trial and error. You should be able to predict what value every signal should be at every point in time while debugging.  In general, trace problems by finding the first point in a simulation where a signal has an incorrect value. Don’t worry about later problems because they could have been caused by the first error. Identify which circuit element is producing the bad output and add all its inputs to the simulation. Repeat until you have isolated the problem. 4 Test Program  Use the same test program and memfile.dat from Lab 4 (given in Figure 7.60 of the text).  As in Lab 4, it is very helpful to first predict the results of a test program before running the program so that you know what to expect and can discover and track down discrepancies. Table 5, which is partially completed, lists the expected instruction trace while running the test program. Complete the remainder of the table. Do this before you run simulations so you have a set of expectations to check your results against; otherwise, it is easy to fool yourself into believing that erroneous simulations are correct.  Notice that the instruction (instr) is fetched during state 0 and therefore not updated until state 1 of each instruction. What to Turn In Report in a single pdf file, containing each of the following items, clearly labeled and in the following order. Poorly organized submissions will lose points. 1. Number of hours you spent on this lab. 2. A completed Main Decoder output table (Table 4). 3. A completed copy of Table 5 indicating the expected outcome of running the test program. 4. All your Verilog codes (datapath, controller, maindec, and aludec modules). Your codes should be heavily commented. Do not change the inputs and outputs of the given modules. Compress all your files to a single compressed file. 5. Simulation waveforms of the controller module showing (in the given order): CLK, Reset, OP, Funct, Zero, the state (this is an internal registered signal), PC, instr, ALUResult, adr, writedata, and readdata of the memory unit, ALUControl, PCEn, and the entire control word (i.e. the 4-nibble word in Table 4, in the exact order shown there) demonstrating each instruction (including taken and non-taken branches). Unreadable waveforms will receive no credit. Display all signals in hexadecimal and make sure they are readable. Does it match your expectations? 5 FSM Control Word ALUOp[1:0] PCRsc[1:0] ALUSrcB[1:0] RegDst MemtoReg IorD Branch ALUSrcA RegWrite IRWrite MemWrite PCWrite State (Name) 0 (Fetch) 1 (Decode) 2 (MemAdr) 3 (MemRd) 4 (MemWB) 5 (MemWr) 6 (RtypeEx) 7 (RtypeWB) 8 (BeqEx) 9 (AddiEx) 10 (AddiWB) 11 (JEx) 1 0 1 0 0 0 0 0 0 01 00 00 0x5010 0 0 0 0 0 0 0 0 0 11 00 00 0x0030 Reset S2: MemAdr IorD = 0 AluSrcA = 0 ALUSrcB = 01 ALUOp = 00 PCSrc = 00 IRWrite PCWrite Op = LW or Op = SW S11: Jump ALUSrcA = 1 ALUSrcB = 10 ALUOp = 00 Op = LW S3: MemRead IorD = 1 ALUSrcA = 1 ALUSrcB = 00 ALUOp = 01 PCSrc = 01 Branch ALUSrcA = 1 ALUSrcB = 10 ALUOp = 00 S10: ADDI Writeback RegDst = 0 MemtoReg = 0 RegWrite S4: Mem Writeback RegDst = 0 MemtoReg = 1 RegWrite Figure 2. Controller’s FSM 6 S0: Fetch S1: Decode Table 4. Main Decoder Control output Op = SW S5: MemWrite IorD = 1 MemWrite ALUSrcA = 0 ALUSrcB = 11 ALUOp = 00 Op = R-type S6: Execute ALUSrcA = 1 ALUSrcB = 00 ALUOp = 10 S7: ALU Writeback RegDst = 1 MemtoReg = 0 RegWrite Op = J Op = ADDI PCSrc = 10 PCWrite Op = BEQ S8: Branch S9: ADDI Execute Cycle Reset PC Instr 0 addi 20020005 addi 20020005 addi 20020005 addi 20020005 addi 2003000c addi 2003000c addi 2003000c or 00e22025 or 00e22025 or 00e22025 or 00e22025 and 00642824 and 00642824 and 00642824 and 00642824 add 00a42820 add 00a42820 add 00a42820 add 00a42820 (FSM) SrcA SrcB ALUResult Zero Control state Word 0 00 04 04 0 5010 1 04 x x 0 0030 9 00 05 05 0 0420 10 x x x 0 0800 0 04 04 08 0 5010 1 08 x x 0 0030 9 00 0c 0c 0 0420 10 x x x 0 0800 1 10 x x 0 0030 6 03 05 07 0 0402 7 x x x 0 0840 0 10 04 14 0 5010 1 14 x x 0 0030 6 0c 07 04 0 0402 7 x x x 0 0840 0 14 04 18 0 5010 1 18 x x 0 0030 6 04 07 0b 0 0402 7 x x x 0 0840 0 18 04 1c 0 5010 1 1 00 2 0 04 3 0 04 4 0 04 5 0 04 6 0 08 7 0 08 8 0 08 90 10 0 11 0 12 0 13 0 14 0 10 15 0 10 16 0 10 17 0 10 18 0 14 19 0 14 20 0 14 21 0 14 22 0 18 23 0 18 24 0 18 25 0 18 26 0 27 0 28 0 29 0 30 0 31 0 32 0 33 0 34 0 35 0 36 0 37 0 38 0 39 0 40 0 30 41 0 30 42 0 30 43 0 30 44 0 34 45 0 34 46 0 34 47 0 34 48 0 38 49 0 38 50 0 38 51 0 38 52 0 3c 53 0 3c 54 0 3c 55 0 3c 56 0 3c 57 0 58 0 59 0 60 0 61 0 62 0 add 00853820 add 00853820 add 00853820 add 00853820 sub 00e23822 sub 00e23822 sub 00e23822 sub 00e23822 sw ac670044 sw ac670044 sw ac670044 sw ac670044 lw 8c020050 lw 8c020050 lw 8c020050 lw 8c020050 lw 8c020050 1 30 x x 0 0030 6 01 0b 0c 0 0402 7 x x x 0 0840 0 30 04 34 0 5010 1 34 x x 0 0030 6 0c 05 07 0 0402 7 x x x 0 0840 0 34 04 38 0 5010 1 38 x x 0 0030 2 0c 44 50 0 0420 5 x x x 0 2100 0 38 04 3c 0 5010 1 3c x x 0 0030 2 00 50 50 0 0420 3 x x x 0 0100 4 x x x 0 0880 0 3c 04 40 0 5010 Table 5. Expected Instruction Trace 7