Memory Allocation III CSE 351 Autumn 2016
RISC-V CPU Datapath, Control Intro
CMPT 295
L27: Datapath
Podcast link: https://gimletmedia.com/tags/6dug/super-tech-support
1
Design Principles
Five steps to design a processor:
Analyze instruction set →
datapath requirements
Select set of datapath
components & establish
clock methodology
Assemble datapath meeting
the requirements
Analyze implementation of each instruction to determine setting of control points that effects the register transfer
Assemble the control logic
Formulate Logic Equations
Design Circuits
2
Control
Datapath
Memory
Processor
Input
Output
CMPT 295
L27: Datapath
Summary !
Universal datapath
Capable of executing all RISC-V instructions in one cycle each
Not all units (hardware) used by all instructions
5 Phases of execution
IF (Instruction Fetch), ID (Instruction Decode), EX (Execute), MEM (Memory), WB (Write Back)
Not all instructions are active in all phases (except for loads!)
Controller specifies how to execute instructions
Worth thinking about: what new instructions can be added with just most control?
3
CMPT 295
L27: Datapath
Your CPU in two parts
Central Processing Unit (CPU):
Datapath: contains the hardware necessary to perform operations required by the processor
Reacts to what the controller tells it! (ie. “I was told to do an add, so I”ll feed these arguments through an adder)
Control: decides what each piece of the datapath should do
What operation am I performing? Do I need to get info from memory? Should I write to a register? Which register?
Has to make decisions based on the input instruction only!
4
CMPT 295
L27: Datapath
Design Principles
Determining control signals
Any time a datapath element has an input that changes behavior, it requires a control signal
(e.g. ALU operation, read/write)
Any time you need to pass a different input based on the instruction, add a MUX with a control signal as the selector
(e.g. next PC, ALU input, register to write to)
Your control signals will change based on your exact datapath
Your datapath will change based on your ISA
5
CMPT 295
L27: Datapath
5
Storage Element: Register File
Register File consists of 31 registers:
Output ports portA and portB
Input port portW
Register selection
Place data of register RA (number) onto portA
Place data of register RB (number) onto portB
Store data on portW into register RW (number) when Write Enable is 1
Clock input (CLK)
CLK is passed to all internal registers so they can be written to if they match RW and Write Enable is 1
6
Clk
portW
Write Enable
32
32
portA
32
portB
5
5
5
RW
RA
RB
32 x 32-bit
Registers
CMPT 295
L27: Datapath
Implementing R-Types
7
IMEM
+4
ALU
pc
inst[11:7]
inst[19:15]
inst[24:20]
Control
(4) Perform operation
New hardware: ALU (Arithmetic Logic Unit)
Abstraction for adders, multipliers, dividers, etc.
How do we know what operation to execute?
Our first control bit! ALUSel(ect)
Reg[]
AddrA
AddrB
DataA
AddrD
DataB
R[rs1]
R[rs2]
ALUSel
inst[31:0]
CMPT 295
L27: Datapath
7
Control Logic
Adding addi to datapath
8
+4
pc
pc+4
inst[11:7]
inst[19:15]
inst[24:20]
IMEM
inst[31:0]
Reg[]
AddrA
AddrB
DataA
AddrD
DataB
DataD
Reg[rs1]
Reg[rs2]
alu
ALU
ALUSel=Add
Imm.
Gen
0
1
RegWEn=1
inst[31:20]
imm[31:0]
ImmSel=I
BSel=1
Also works for all other I-format arithmetic instruction (slti,sltiu,andi,ori,xori,slli,srli,srai) just by changing ALUSel
CMPT 295
L27: Datapath
8
Adding lw to datapath
9
IMEM
ALU
Imm.
Gen
+4
DMEM
Reg[]
AddrA
AddrB
DataA
AddrD
DataB
DataD
Addr
DataR
0
1
pc
0
1
inst[11:7]
inst[19:15]
inst[24:20]
inst[31:20]
alu
mem
wb
pc+4
Reg[rs1]
imm[31:0]
Reg[rs2]
inst[31:0]
ImmSel=I
RegWEn=1
Bsel=1
ALUSel=Add
MemRW=Read
WBSel=0
wb
CMPT 295
L27: Datapath
9
Storage Element: Idealized Memory
Memory (idealized)
One input port: Data In
One output port: Data Out
Memory access:
Read: Write Enable = 0, data at Address is placed on Data Out
Write: Write Enable = 1, Data In written to Address
Clock input (CLK)
CLK input is a factor ONLY during write operation
During read, behaves as a combinational logic block: Address valid → Data Out valid after “access time”
10
CLK
Data In
Write Enable
32
32
DataOut
Address
CMPT 295
L27: Datapath
Current Datapath
11
IMEM
ALU
Imm.
Gen
+4
DMEM
Reg[]
AddrA
AddrB
DataA
AddrD
DataB
DataD
Addr
DataR
0
1
pc
0
1
inst[11:7]
inst[19:15]
inst[24:20]
inst[31:20]
ALU
mem
wb
Reg[rs1]
imm[31:0]
Reg[rs2]
inst[31:0]
ImmSel
BSel
ALUSel
MemRW
WBSel
wb
pc+4
CMPT 295
L27: Datapath
11
Adding sw to datapath
12
IMEM
ALU
Imm.
Gen
+4
DMEM
Reg[]
AddrA
AddrB
DataA
AddrD
DataB
DataD
Addr
DataW
DataR
0
1
pc
0
1
inst[11:7]
inst[19:15]
inst[24:20]
inst[31:7]
alu
mem
wb
pc+4
Reg[rs1]
imm[31:0]
Reg[rs2]
inst[31:0]
ImmSel=S
RegWEn=0
Bsel=1
ALUSel=Add
MemRW=Write
WBSel=*
wb
*= “Don’t Care”
CMPT 295
L27: Datapath
12
Adding branches to datapath
13
IMEM
ALU
Imm.
Gen
+4
DMEM
Branch Comp.
Reg[]
AddrA
AddrB
DataA
AddrD
DataB
DataD
Addr
DataW
DataR
1
0
0
1
1
0
pc
0
1
inst[11:7]
inst[19:15]
inst[24:20]
inst[31:7]
alu
mem
wb
alu
pc+4
Reg[rs1]
pc
imm[31:0]
Reg[rs2]
inst[31:0]
ImmSel=B
RegWEn=0
BrUn
BrEq
BrLT
ASel=1
Bsel=1
ALUSel=Add
MemRW=Read
WBSel=*
PCSel=taken/not-taken
wb
CMPT 295
L27: Datapath
13
Adding jalr to datapath
14
IMEM
ALU
Imm.
Gen
+4
DMEM
Branch Comp.
Reg[]
AddrA
AddrB
DataA
AddrD
DataB
DataD
Addr
DataW
DataR
1
0
0
1
2
1
0
pc
0
1
inst[11:7]
inst[19:15]
inst[24:20]
inst[31:7]
pc+4
alu
mem
wb
alu
pc+4
Reg[rs1]
pc
imm[31:0]
Reg[rs2]
inst[31:0]
ImmSel=B
RegWEn=1
BrUn=*
BrEq=*
BrLT=*
Asel=0
Bsel=1
ALUSel=Add
MemRW=Read
WBSel=2
PCSel
wb
CMPT 295
L27: Datapath
14
Adding jal to datapath
15
IMEM
ALU
Imm.
Gen
+4
DMEM
Branch Comp.
Reg[]
AddrA
AddrB
DataA
AddrD
DataB
DataD
Addr
DataW
DataR
1
0
0
1
2
1
0
pc
0
1
inst[11:7]
inst[19:15]
inst[24:20]
inst[31:7]
pc+4
alu
mem
wb
alu
pc+4
Reg[rs1]
pc
imm[31:0]
Reg[rs2]
inst[31:0]
ImmSel=J
RegWEn=1
BrUn=*
BrEq=*
BrLT=*
Asel=1
Bsel=1
ALUSel=Add
MemRW=Read
WBSel=2
PCSel
wb
CMPT 295
L27: Datapath
15
Implementing lui
16
IMEM
ALU
Imm.
Gen
+4
DMEM
Branch Comp.
Reg[]
AddrA
AddrB
DataA
AddrD
DataB
DataD
Addr
DataW
DataR
1
0
0
1
2
1
0
0
1
inst[11:7]
inst[19:15]
inst[24:20]
inst[31:7]
pc+4
alu
mem
wb
alu
pc+4
Reg[rs1]
pc
imm[31:0]
Reg[rs2]
inst[31:0]
ImmSel=U
RegWEn=1
BrUn=*
BrE=*
BrLT=*
Asel=*
Bsel=1
ALUSel=B
MemRW=Read
WBSel=1
PCSel=pc+4
wb
pc
CMPT 295
L27: Datapath
16
Implementing auipc
17
IMEM
ALU
Imm.
Gen
+4
DMEM
Branch Comp.
Reg[]
AddrA
AddrB
DataA
AddrD
DataB
DataD
Addr
DataW
DataR
1
0
0
1
2
1
0
0
1
inst[11:7]
inst[19:15]
inst[24:20]
inst[31:7]
pc+4
alu
mem
wb
alu
pc+4
Reg[rs1]
pc
imm[31:0]
Reg[rs2]
inst[31:0]
ImmSel=U
RegWEn=1
BrUn=*
BrE=*
BrLT=*
Asel=1
Bsel=1
ALUSel=Add
MemRW=0
WBSel=1
PCSel=pc+4
wb
pc
CMPT 295
L27: Datapath
17