程序代写代做代考 Transistors and Logic Gates

Transistors and Logic Gates

Chapter 3
Digital Logic
Structures

ECE 206 – Fall 2000 – G. Byrd

Transistor: Building Block of Computers
Microprocessors contain millions of transistors
Intel Pentium 4 (2000): 48 million
IBM PowerPC 750FX (2002): 38 million
IBM/Apple PowerPC G5 (2003): 58 million

Logically, each transistor acts as a switch
Combined to implement logic functions
AND, OR, NOT

Combined to build higher-level structures
Adder, multiplexer, decoder, register, …

Combined to build processor
LC-3

ECE 206 – Fall 2000 – G. Byrd
Intel and Pentium are trademarks of Intel Corporation. IBM and PowerPC are trademarks of International Business Machines Corporation. Apple is a trademark of Apple Computer, Inc.

Simple Switch Circuit
Switch open:
No current through circuit
Light is off
Vout is +2.9V

Switch closed:
Short circuit across switch
Current flows
Light is on
Vout is 0V

Switch-based circuits can easily represent two states:
on/off, open/closed, voltage/no voltage.

ECE 206 – Fall 2000 – G. Byrd

n-type MOS Transistor
MOS = Metal Oxide Semiconductor
two types: n-type and p-type

n-type
when Gate has positive voltage,
short circuit between #1 and #2
(switch closed)
when Gate has zero voltage,
open circuit between #1 and #2
(switch open)

Gate = 1
Gate = 0
Terminal #2 must be
connected to GND (0V).

ECE 206 – Fall 2000 – G. Byrd

p-type MOS Transistor
p-type is complementary to n-type
when Gate has positive voltage,
open circuit between #1 and #2
(switch open)
when Gate has zero voltage,
short circuit between #1 and #2
(switch closed)

Gate = 1
Gate = 0
Terminal #1 must be
connected to +2.9V.

ECE 206 – Fall 2000 – G. Byrd

Logic Gates
Use switch behavior of MOS transistors
to implement logical functions: AND, OR, NOT.

Digital symbols:
recall that we assign a range of analog voltages to each
digital (logic) symbol

assignment of voltage ranges depends on
electrical properties of transistors being used

typical values for “1”: +5V, +3.3V, +2.9V
from now on we’ll use +2.9V

ECE 206 – Fall 2000 – G. Byrd

CMOS Circuit
Complementary MOS
Uses both n-type and p-type MOS transistors
p-type

Attached to + voltage
Pulls output voltage UP when input is zero
n-type

Attached to GND
Pulls output voltage DOWN when input is one

For all inputs, make sure that output is either connected to GND or to +,
but not both!

ECE 206 – Fall 2000 – G. Byrd

Inverter (NOT Gate)
Truth table
In Out
0 V 2.9 V
2.9 V 0 V

In Out
0 1
1 0

ECE 206 – Fall 2000 – G. Byrd

NOR Gate
Note: Serial structure on top, parallel on bottom.
A B C
0 0 1
0 1 0
1 0 0
1 1 0

ECE 206 – Fall 2000 – G. Byrd

OR Gate
Add inverter to NOR.
A B C
0 0 0
0 1 1
1 0 1
1 1 1

ECE 206 – Fall 2000 – G. Byrd

NAND Gate (AND-NOT)
Note: Parallel structure on top, serial on bottom.
A B C
0 0 1
0 1 1
1 0 1
1 1 0

ECE 206 – Fall 2000 – G. Byrd

AND Gate
Add inverter to NAND.
A B C
0 0 0
0 1 0
1 0 0
1 1 1

ECE 206 – Fall 2000 – G. Byrd

Basic Logic Gates

ECE 206 – Fall 2000 – G. Byrd

DeMorgan’s Law
Converting AND to OR (with some help from NOT)
Consider the following gate:
Same as A+B!
To convert AND to OR
(or vice versa),
invert inputs and output.
A B
0 0 1 1 1 0
0 1 1 0 0 1
1 0 0 1 0 1
1 1 0 0 0 1

ECE 206 – Fall 2000 – G. Byrd
If there’s time, perhaps discuss how all gates can be implemented with NAND (or NOR).
Therefore, you can implement any truth table using only NAND (or NOR) gates.

More than 2 Inputs?
AND/OR can take any number of inputs.
AND = 1 if all inputs are 1.
OR = 1 if any input is 1.
Similar for NAND/NOR.

Can implement with multiple two-input gates,
or with single CMOS circuit.

ECE 206 – Fall 2000 – G. Byrd
NAND and NOR are not associative.

Jim Conrad’s example:
NAND(NAND(0,0), 1) = NAND(1, 1) = 0
NAND(0, NAND(0,1)) = NAND(0, 0) = 1

Summary
MOS transistors are used as switches to implement
logic functions.
n-type: connect to GND, turn on (with 1) to pull down to 0
p-type: connect to +2.9V, turn on (with 0) to pull up to 1

Basic gates: NOT, NOR, NAND
Logic functions are usually expressed with AND, OR, and NOT

DeMorgan’s Law
Convert AND to OR (and vice versa)
by inverting inputs and output

ECE 206 – Fall 2000 – G. Byrd

Building Functions from Logic Gates
Combinational Logic Circuit
output depends only on the current inputs
stateless

Sequential Logic Circuit
output depends on the sequence of inputs (past and present)
stores information (state) from past inputs

We’ll first look at some useful combinational circuits,
then show how to use sequential circuits to store information.

ECE 206 – Fall 2000 – G. Byrd

Decoder
n inputs, 2n outputs
exactly one output is 1 for each possible input pattern

2-bit
decoder

ECE 206 – Fall 2000 – G. Byrd
Uses of decoder:
convert memory/register address to a control line that selects that location
convert an opcode to one of n control lines

Multiplexer (MUX)
n-bit selector and 2n inputs, one output
output equals one of the inputs, depending on selector

4-to-1 MUX

ECE 206 – Fall 2000 – G. Byrd
Another view: decode S, and AND each output with one of the MUX inputs.
Also explain multi-bit inputs.
Uses of multiplexer:
select which input to use for function
select which computed value to pass to next stage (or to place on bus)

Full Adder
Add two bits and carry-in,
produce one-bit sum and carry-out.
A B Cin S Cout
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

ECE 206 – Fall 2000 – G. Byrd
A half-adder is one that doesn’t take a carry-in.
Sum is one when 1 or 3 inputs are one. Carry-out is one when 2 or 3 inputs are one.

Four-bit Adder

ECE 206 – Fall 2000 – G. Byrd
This is called a “ripple-carry” adder. The sum becomes valid as the carry ripples its way from the low bit to the high bit. How many gate delays until the output is settled?

Logical Completeness
Can implement ANY truth table with AND, OR, NOT.
1. AND combinations
that yield a “1” in the
truth table.
2. OR the results
of the AND gates.
A B C D
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 0
1 0 0 0
1 0 1 1
1 1 0 0
1 1 1 0

ECE 206 – Fall 2000 – G. Byrd
Note the use of the bubbles (NOT) in the input.

Combinational vs. Sequential
Combinational Circuit
always gives the same output for a given set of inputs

ex: adder always generates sum and carry,
regardless of previous inputs
Sequential Circuit
stores information
output depends on stored information (state) plus input

so a given input might produce different outputs,
depending on the stored information
example: ticket counter

advances when you push the button
output depends on previous state
useful for building “memory” elements and “state machines”

ECE 206 – Fall 2000 – G. Byrd

R-S Latch: Simple Storage Element
R is used to “reset” or “clear” the element – set it to zero.
S is used to “set” the element – set it to one.

If both R and S are one, out could be either zero or one.
“quiescent” state — holds its previous value
note: if a is 1, b is 0, and vice versa

1
0
1
1
1
1
0
0
1
1
0
0
1
1

ECE 206 – Fall 2000 – G. Byrd

Clearing the R-S latch
Suppose we start with output = 1, then change R to zero.
Output changes to zero.
Then set R=1 to “store” value in quiescent state.
1
0
1
1
1
1
0
0
1
0
1
0
0
0
1
1

ECE 206 – Fall 2000 – G. Byrd
Setting R to zero forces b (and B) to 1, which forces a (and A) to zero.
This is a stable state, because R=0 and A=0 means b=1.
Bring R back to one then keeps the output at zero.
What is the result if we start with a=0?

Setting the R-S Latch
Suppose we start with output = 0, then change S to zero.
Output changes to one.
Then set S=1 to “store” value in quiescent state.
1
1
0
0
1
1
0
1
1
1
0
0

ECE 206 – Fall 2000 – G. Byrd
Setting S to zero forces a (and A) to 1, which forces b (and B) to zero.
This is a stable state, because S=0 and B=0 means a=1.
Bring S back to one then keeps the output at one.
What is the result if we start with a=1?

R-S Latch Summary
R = S = 1
hold current value in latch

S = 0, R=1
set value to 1

R = 0, S = 1
set value to 0

R = S = 0
both outputs equal one
final state determined by electrical properties of gates
Don’t do it!

ECE 206 – Fall 2000 – G. Byrd

Gated D-Latch
Two inputs: D (data) and WE (write enable)
when WE = 1, latch is set to value of D

S = NOT(D), R = D
when WE = 0, latch holds previous value

S = R = 1

ECE 206 – Fall 2000 – G. Byrd
The D-latch is used to store a single data bit. The latch is set to the value of D whenever WE=1; when WE=0, the current value is stored, no matter what D becomes.
Using D and not(D) to control S and R makes it easier to ensure that S and R are never zero at the same time.
WE allows us to control when a new value is written to the latch.

Register
A register stores a multi-bit value.
We use a collection of D-latches, all controlled by a common WE.
When WE=1, n-bit value D is written to register.

ECE 206 – Fall 2000 – G. Byrd

Representing Multi-bit Values
Number bits from right (0) to left (n-1)
just a convention — could be left to right, but must be consistent

Use brackets to denote range:
D[l:r] denotes bit l to bit r, from left to right

May also see A<14:9>,
especially in hardware block diagrams.
A = 0101001101010101
A[2:0] = 101
A[14:9] = 101001
0
15

ECE 206 – Fall 2000 – G. Byrd

Memory
Now that we know how to store bits,
we can build a memory – a logical k × m array of
stored bits.
k = 2n
locations
m bits
Address Space:
number of locations
(usually a power of 2)
Addressability:
number of bits per location
(e.g., byte-addressable)

•
•
•

ECE 206 – Fall 2000 – G. Byrd

22 x 3 Memory
address
decoder
word select
word WE
address
write
enable
input bits
output bits

ECE 206 – Fall 2000 – G. Byrd
Decoder asserts one of the word select lines, based on address.
Word select activates one of the output AND gates, which drives the selected data to the output OR gate. (For a read, this is basically a MUX — decoder ANDed with signals, results ORed together.)
When writing, the only WE bits for the proper word are asserted (based on decoder again).

More Memory Details
This is a not the way actual memory is implemented.
fewer transistors, much more dense,
relies on electrical properties

But the logical structure is very similar.
address decoder
word select line
word write enable

Two basic kinds of RAM (Random Access Memory)
Static RAM (SRAM)
fast, maintains data as long as power applied

Dynamic RAM (DRAM)
slower but denser, bit storage decays – must be periodically refreshed

Also, non-volatile memories: ROM, PROM, flash, …

ECE 206 – Fall 2000 – G. Byrd

State Machine
Another type of sequential circuit
Combines combinational logic with storage
“Remembers” state, and changes output (and state)
based on inputs and current state

State Machine
Combinational
Logic Circuit
Storage
Elements
Inputs
Outputs

ECE 206 – Fall 2000 – G. Byrd

Combinational vs. Sequential
Two types of “combination” locks
Combinational
Success depends only on
the values, not the order in
which they are set.
Sequential
Success depends on
the sequence of values
(e.g, R-13, L-22, R-3).

4
1
8
4

30
15
5
10
20
25

ECE 206 – Fall 2000 – G. Byrd

State
The state of a system is a snapshot of
all the relevant elements of the system
at the moment the snapshot is taken.

Examples:
The state of a basketball game can be represented by
the scoreboard.

Number of points, time remaining, possession, etc.
The state of a tic-tac-toe game can be represented by
the placement of X’s and O’s on the board.

ECE 206 – Fall 2000 – G. Byrd

State of Sequential Lock
Our lock example has four different states,
labelled A-D:
A: The lock is not open,
and no relevant operations have been performed.
B: The lock is not open,
and the user has completed the R-13 operation.
C: The lock is not open,
and the user has completed R-13, followed by L-22.
D: The lock is open.

ECE 206 – Fall 2000 – G. Byrd

State Diagram
Shows states and
actions that cause a transition between states.

ECE 206 – Fall 2000 – G. Byrd

Finite State Machine
A description of a system with the following components:

A finite number of states
A finite number of external inputs
A finite number of external outputs
An explicit specification of all state transitions
An explicit specification of what determines each
external output value

Often described by a state diagram.
Inputs trigger state transitions.
Outputs are associated with each state (or with each transition).

ECE 206 – Fall 2000 – G. Byrd

The Clock
Frequently, a clock circuit triggers transition from
one state to the next.

At the beginning of each clock cycle,
state machine makes a transition,
based on the current state and the external inputs.
Not always required. In lock example, the input itself triggers a transition.

“1”
“0”
time
One
Cycle

ECE 206 – Fall 2000 – G. Byrd

Implementing a Finite State Machine
Combinational logic
Determine outputs and next state.

Storage elements
Maintain state representation.

State Machine
Combinational
Logic Circuit
Storage
Elements
Inputs
Outputs
Clock

ECE 206 – Fall 2000 – G. Byrd

Storage: Master-Slave Flipflop
A pair of gated D-latches,
to isolate next state from current state.
During 1st phase (clock=1),
previously-computed state
becomes current state and is
sent to the logic circuit.
During 2nd phase (clock=0),
next state, computed by
logic circuit, is stored in
Latch A.

ECE 206 – Fall 2000 – G. Byrd

Storage
Each master-slave flipflop stores one state bit.

The number of storage elements (flipflops) needed
is determined by the number of states
(and the representation of each state).

Examples:
Sequential lock

Four states – two bits
Basketball scoreboard

7 bits for each score, 5 bits for minutes, 6 bits for seconds,
1 bit for possession arrow, 1 bit for half, …

ECE 206 – Fall 2000 – G. Byrd

Complete Example
A blinking traffic sign
No lights on
1 & 2 on
1, 2, 3, & 4 on
1, 2, 3, 4, & 5 on
(repeat as long as switch
is turned on)

DANGER
MOVE
RIGHT
1
2
3
4
5

ECE 206 – Fall 2000 – G. Byrd

Traffic Sign State Diagram

State bit S1
State bit S0
Switch on
Switch off
Outputs
Transition on each clock cycle.

ECE 206 – Fall 2000 – G. Byrd

Traffic Sign Truth Tables

Outputs
(depend only on state: S1S0)
Lights 1 and 2
Lights 3 and 4
Light 5
Next State: S1’S0’
(depend on state and input)
Switch
Whenever In=0, next state is 00.
S1 S0 Z Y X
0 0 0 0 0
0 1 1 0 0
1 0 1 1 0
1 1 1 1 1

In S1 S0 S1’ S0’
0 X X 0 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 1
1 1 1 0 0

ECE 206 – Fall 2000 – G. Byrd

Traffic Sign Logic

Master-slave
flipflop

ECE 206 – Fall 2000 – G. Byrd

From Logic to Data Path
The data path of a computer is all the logic used to
process information.
See the data path of the LC-3 on next slide.

Combinational Logic
Decoders — convert instructions into control signals
Multiplexers — select inputs and outputs
ALU (Arithmetic and Logic Unit) — operations on data

Sequential Logic
State machine — coordinate control signals and data movement
Registers and latches — storage elements

ECE 206 – Fall 2000 – G. Byrd

LC-3 Data Path
Combinational
Logic
State Machine
Storage

ECE 206 – Fall 2000 – G. Byrd

B
A
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