程序代写代做代考 algorithm cache data structure Introduction to Computer Systems 15-213/18-243, spring 2009

Introduction to Computer Systems 15-213/18-243, spring 2009

Virtual Memory: Concepts

CMPE 120
Instructors:
Hungwen Li

Carnegie Mellon
‹#›
Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition

1

Address spaces
VM as a tool for caching
VM as a tool for memory management
VM as a tool for memory protection
Address translation

Carnegie Mellon
‹#›
Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition
A System Using Physical Addressing
Used in “simple” systems like embedded microcontrollers in devices like cars, elevators, and digital picture frames

0:
1:
M-1:
Main memory
CPU
2:
3:

4:
5:

6:
7:

Physical address
(PA)

Data word

8:

4

Carnegie Mellon
‹#›
Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition

A System Using Virtual Addressing
Used in all modern servers, laptops, and smart phones
One of the great ideas in computer science

0:
1:
M-1:
Main memory
MMU
2:
3:

4:
5:

6:
7:

Physical address
(PA)

Data word

8:

CPU
Virtual address
(VA)
CPU Chip
4
4100

Carnegie Mellon
‹#›
Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition

Address Spaces
Linear address space: Ordered set of contiguous non-negative integer addresses:
{0, 1, 2, 3 … }

Virtual address space: Set of N = 2n virtual addresses
{0, 1, 2, 3, …, N-1}

Physical address space: Set of M = 2m physical addresses
{0, 1, 2, 3, …, M-1}

Carnegie Mellon
‹#›
Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition

5

Why Virtual Memory (VM)?
Uses main memory efficiently
Use DRAM as a cache for parts of a virtual address space

Simplifies memory management
Each process gets the same uniform linear address space

Isolates address spaces
One process can’t interfere with another’s memory
User program cannot access privileged kernel information and code

Carnegie Mellon
‹#›
Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition

Address spaces
VM as a tool for caching
VM as a tool for memory management
VM as a tool for memory protection
Address translation

Carnegie Mellon
‹#›
Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition
VM as a Tool for Caching
Conceptually, virtual memory is an array of N contiguous bytes stored on disk.
The contents of the array on disk are cached in physical memory (DRAM cache)
These cache blocks are called pages (size is P = 2p bytes)

PP 2m-p-1
Physical memory
Empty

Empty
Uncached
VP 0
VP 1
VP 2n-p-1
Virtual memory
Unallocated
Cached
Uncached
Unallocated
Cached
Uncached
PP 0
PP 1

Empty

Cached

0
N-1
M-1
0
Virtual pages (VPs)
stored on disk
Physical pages (PPs)
cached in DRAM

Carnegie Mellon
‹#›
Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition

DRAM Cache Organization
DRAM cache organization driven by the enormous miss penalty
DRAM is about 10x slower than SRAM
Disk is about 10,000x slower than DRAM

Consequences
Large page (block) size: typically 4 KB, sometimes 4 MB
Fully associative
Any VP can be placed in any PP
Requires a “large” mapping function – different from cache memories
Highly sophisticated, expensive replacement algorithms
Too complicated and open-ended to be implemented in hardware
Write-back rather than write-through

Carnegie Mellon
‹#›
Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition

Enabling Data Structure: Page Table
A page table is an array of page table entries (PTEs) that maps virtual pages to physical pages.
Per-process kernel data structure in DRAM

null
null

Memory resident
page table
(DRAM)
Physical memory
(DRAM)
VP 7
VP 4

Virtual memory
(disk)

Valid
0
1
0
1
0
1
0
1
Physical page
number or
disk address
PTE 0
PTE 7
PP 0
VP 2
VP 1

PP 3
VP 1
VP 2
VP 4
VP 6
VP 7

VP 3

Carnegie Mellon
‹#›
Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition

Page Hit
Page hit: reference to VM word that is in physical memory (DRAM cache hit)

null
null

Memory resident
page table
(DRAM)
Physical memory
(DRAM)
VP 7
VP 4

Virtual memory
(disk)

Valid
0
1
0
1
0
1
0
1
Physical page
number or
disk address
PTE 0
PTE 7
PP 0
VP 2
VP 1

PP 3
VP 1
VP 2
VP 4
VP 6
VP 7

VP 3
Virtual address

Carnegie Mellon
‹#›
Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition

Page Fault
Page fault: reference to VM word that is not in physical memory (DRAM cache miss)

null
null

Memory resident
page table
(DRAM)
Physical memory
(DRAM)
VP 7
VP 4

Virtual memory
(disk)

Valid
0
1
0
1
0
1
0
1
Physical page
number or
disk address
PTE 0
PTE 7
PP 0
VP 2
VP 1

PP 3
VP 1
VP 2
VP 4
VP 6
VP 7

VP 3
Virtual address

Carnegie Mellon
‹#›
Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition

Handling Page Fault
Page miss causes page fault (an exception)

null
null

Memory resident
page table
(DRAM)
Physical memory
(DRAM)
VP 7
VP 4

Virtual memory
(disk)

Valid
0
1
0
1
0
1
0
1
Physical page
number or
disk address
PTE 0
PTE 7
PP 0
VP 2
VP 1

PP 3
VP 1
VP 2
VP 4
VP 6
VP 7

VP 3
Virtual address

Carnegie Mellon
‹#›
Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition

Handling Page Fault
Page miss causes page fault (an exception)
Page fault handler selects a victim to be evicted (here VP 4)

null
null

Memory resident
page table
(DRAM)
Physical memory
(DRAM)
VP 7
VP 4

Virtual memory
(disk)

Valid
0
1
0
1
0
1
0
1
Physical page
number or
disk address
PTE 0
PTE 7
PP 0
VP 2
VP 1

PP 3
VP 1
VP 2
VP 4
VP 6
VP 7

VP 3
Virtual address

Carnegie Mellon
‹#›
Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition

Handling Page Fault
Page miss causes page fault (an exception)
Page fault handler selects a victim to be evicted (here VP 4)

null
null

Memory resident
page table
(DRAM)
Physical memory
(DRAM)
VP 7
VP 3

Virtual memory
(disk)

Valid
0
1
1
0
0
1
0
1
Physical page
number or
disk address
PTE 0
PTE 7
PP 0
VP 2
VP 1

PP 3
VP 1
VP 2
VP 4
VP 6
VP 7

VP 3
Virtual address

Carnegie Mellon
‹#›
Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition

Handling Page Fault
Page miss causes page fault (an exception)
Page fault handler selects a victim to be evicted (here VP 4)
Offending instruction is restarted: page hit!

null
null

Memory resident
page table
(DRAM)
Physical memory
(DRAM)
VP 7
VP 3

Virtual memory
(disk)

Valid
0
1
1
0
0
1
0
1
Physical page
number or
disk address
PTE 0
PTE 7
PP 0
VP 2
VP 1

PP 3
VP 1
VP 2
VP 4
VP 6
VP 7

VP 3
Virtual address
Key point: Waiting until the miss to copy the page to DRAM is known as demand paging

Carnegie Mellon
‹#›
Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition

Allocating Pages
Allocating a new page (VP 5) of virtual memory.

null

Memory resident
page table
(DRAM)
Physical memory
(DRAM)
VP 7
VP 3

Virtual memory
(disk)

Valid
0
1
1
0
0
1
0
1
Physical page
number or
disk address
PTE 0
PTE 7
PP 0
VP 2
VP 1

PP 3
VP 1
VP 2
VP 4
VP 6
VP 7

VP 3
VP 5

Carnegie Mellon
‹#›
Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition
Locality to the Rescue Again!
Virtual memory seems terribly inefficient, but it works because of locality.

At any point in time, programs tend to access a set of active virtual pages called the working set
Programs with better temporal locality will have smaller working sets

If (working set size < main memory size) Good performance for one process after compulsory misses If ( SUM(working set sizes) > main memory size )
Thrashing: Performance meltdown where pages are swapped (copied) in and out continuously

Carnegie Mellon
‹#›
Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition

Address spaces
VM as a tool for caching
VM as a tool for memory management
VM as a tool for memory protection
Address translation

Carnegie Mellon
‹#›
Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition
VM as a Tool for Memory Management
Key idea: each process has its own virtual address space
It can view memory as a simple linear array
Mapping function scatters addresses through physical memory
Well-chosen mappings can improve locality
Virtual Address Space for Process 1:
Physical
Address
Space (DRAM)
0
N-1
(e.g., read-only
library code)
Virtual Address Space for Process 2:

VP 1
VP 2


0
N-1

VP 1
VP 2

PP 2

PP 6

PP 8


0
M-1
Address
translation

Carnegie Mellon
‹#›
Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition

VM as a Tool for Memory Management
Simplifying memory allocation
Each virtual page can be mapped to any physical page
A virtual page can be stored in different physical pages at different times
Sharing code and data among processes
Map virtual pages to the same physical page (here: PP 6)
Virtual Address Space for Process 1:
Physical
Address
Space (DRAM)
0
N-1
(e.g., read-only
library code)
Virtual Address Space for Process 2:

VP 1
VP 2


0
N-1

VP 1
VP 2

PP 2

PP 6

PP 8


0
M-1
Address
translation

Carnegie Mellon
‹#›
Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition

Simplifying Linking and Loading
Linking
Each program has similar virtual address space
Code, data, and heap always start at the same addresses.

Loading
execve allocates virtual pages for .text and .data sections & creates PTEs marked as invalid
The .text and .data sections are copied, page by page, on demand by the virtual memory system

Kernel virtual memory
Memory-mapped region for
shared libraries

Run-time heap
(created by malloc)

User stack
(created at runtime)

Unused
0
%rsp
(stack
pointer)

Memory
invisible to
user code

brk

0x400000
Read/write segment
(.data, .bss)
Read-only segment
(.init, .text, .rodata)

Loaded
from
the
executable
file

Carnegie Mellon
‹#›
Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition

Address spaces
VM as a tool for caching
VM as a tool for memory management
VM as a tool for memory protection
Address translation

Carnegie Mellon
‹#›
Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition
VM as a Tool for Memory Protection
Extend PTEs with permission bits
MMU checks these bits on each access
Process i:
Address
READ
WRITE
PP 6
Yes
No
PP 4
Yes
Yes
PP 2
Yes
VP 0:
VP 1:
VP 2:



Process j:
Yes
SUP
No
No
Yes
Address
READ
WRITE
PP 9
Yes
No
PP 6
Yes
Yes
PP 11
Yes
Yes
SUP
No
Yes
No
VP 0:
VP 1:
VP 2:
Physical
Address Space

PP 2

PP 4

PP 6

PP 8
PP 9

PP 11
EXEC
Yes
EXEC
Yes
Yes
Yes
Yes
No

Carnegie Mellon
‹#›
Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition

Address spaces
VM as a tool for caching
VM as a tool for memory management
VM as a tool for memory protection
Address translation

Carnegie Mellon
‹#›
Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition
VM Address Translation
Virtual Address Space
V = {0, 1, …, N–1}
Physical Address Space
P = {0, 1, …, M–1}
Address Translation
MAP: V  P U {}
For virtual address a:
MAP(a) = a’ if data at virtual address a is at physical address a’ in P
MAP(a) =  if data at virtual address a is not in physical memory
Either invalid or stored on disk

Carnegie Mellon
‹#›
Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition

Summary of Address Translation Symbols
Basic Parameters
N = 2n : Number of addresses in virtual address space
M = 2m : Number of addresses in physical address space
P = 2p : Page size (bytes)
Components of the virtual address (VA)
TLBI: TLB index
TLBT: TLB tag
VPO: Virtual page offset
VPN: Virtual page number
Components of the physical address (PA)
PPO: Physical page offset (same as VPO)
PPN: Physical page number

Carnegie Mellon
‹#›
Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition

Address Translation With a Page Table
Virtual page number (VPN)
Virtual page offset (VPO)

Physical page number (PPN)
Physical page offset (PPO)
Virtual address
Physical address
Valid
Physical page number (PPN)
Page table
base register
(PTBR)
Page table
Physical page table
address for the current
process
Valid bit = 0:
Page not in memory
(page fault)
0
p-1
p
n-1
0
p-1
p
m-1
Valid bit = 1

Carnegie Mellon
‹#›
Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition

28

Address Translation: Page Hit
1) Processor sends virtual address to MMU
2-3) MMU fetches PTE from page table in memory
4) MMU sends physical address to cache/memory
5) Cache/memory sends data word to processor
MMU
Cache/
Memory
PA
Data
CPU
VA
CPU Chip
PTEA
PTE
1
2
3
4
5

Carnegie Mellon
‹#›
Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition

Address Translation: Page Fault
1) Processor sends virtual address to MMU
2-3) MMU fetches PTE from page table in memory
4) Valid bit is zero, so MMU triggers page fault exception
5) Handler identifies victim (and, if dirty, pages it out to disk)
6) Handler pages in new page and updates PTE in memory
7) Handler returns to original process, restarting faulting instruction
MMU
Cache/
Memory
CPU
VA
CPU Chip
PTEA
PTE
1
2
3
4
5
Disk
Page fault handler

Victim page
New page
Exception
6
7

Carnegie Mellon
‹#›
Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition

Integrating VM and Cache
VA
CPU
MMU

PTEA
PTE

PA

Data

Memory

PA
PA
miss
PTEA
PTEA
miss

PTEA
hit

PA
hit

Data

PTE
L1
cache
CPU Chip
VA: virtual address, PA: physical address, PTE: page table entry, PTEA = PTE address

Carnegie Mellon
‹#›
Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition

Speeding up Translation with a TLB
Page table entries (PTEs) are cached in L1 like any other memory word
PTEs may be evicted by other data references
PTE hit still requires a small L1 delay
Solution: Translation Lookaside Buffer (TLB)
Small set-associative hardware cache in MMU
Maps virtual page numbers to physical page numbers
Contains complete page table entries for small number of pages

Carnegie Mellon
‹#›
Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition

Accessing the TLB
MMU uses the VPN portion of the virtual address to access the TLB:
TLB tag (TLBT)
TLB index (TLBI)
0
p-1
p
n-1
VPO

VPN
p+t-1
p+t

PTE
tag
v

PTE
tag
v
Set 0

PTE
tag
v

PTE
tag
v
Set 1

PTE
tag
v

PTE
tag
v
Set T-1
T = 2t sets
TLBI selects the set
TLBT matches tag of line within set

Carnegie Mellon
‹#›
Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition

TLB Hit
MMU
Cache/
Memory
CPU
CPU Chip
VA
1
PA
4
Data
5
A TLB hit eliminates a memory access
TLB
2
VPN
PTE
3

Carnegie Mellon
‹#›
Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition

TLB Miss
MMU
Cache/
Memory
PA
Data
CPU
VA
CPU Chip
PTE
1
2
5
6
TLB
VPN
4
PTEA
3
A TLB miss incurs an additional memory access (the PTE)
Fortunately, TLB misses are rare. Why?

Carnegie Mellon
‹#›
Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition

Multi-Level Page Tables
Suppose:
4KB (212) page size, 48-bit address space, 8-byte PTE

Problem:
Would need a 512 GB page table!
248 * 2-12 * 23 = 239 bytes

Common solution: Multi-level page table
Example: 2-level page table
Level 1 table: each PTE points to a page table (always memory resident)
Level 2 table: each PTE points to a page
(paged in and out like any other data)
Level 1
Table


Level 2
Tables

Carnegie Mellon
‹#›
Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition

A Two-Level Page Table Hierarchy
Level 1
page table

Level 2
page tables
VP 0

VP 1023
VP 1024

VP 2047

Gap
0
PTE 0

PTE 1023

PTE 0

PTE 1023

1023 null
PTEs
PTE 1023

1023
unallocated
pages
VP 9215

Virtual
memory

(1K – 9)
null PTEs
PTE 0
PTE 1
PTE 2 (null)
PTE 3 (null)
PTE 4 (null)
PTE 5 (null)
PTE 6 (null)
PTE 7 (null)
PTE 8

2K allocated VM pages
for code and data

6K unallocated VM pages

1023 unallocated pages

1 allocated VM page
for the stack
32 bit addresses, 4KB pages, 4-byte PTEs

Carnegie Mellon
‹#›
Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition

Translating with a k-level Page Table
Page table
base register
(PTBR)
VPN 1
0
p-1
n-1
VPO
VPN 2

VPN k

PPN
0
p-1
m-1
PPO
PPN

VIRTUAL ADDRESS
PHYSICAL ADDRESS



Level 1
page table
Level 2
page table
Level k
page table

Carnegie Mellon
‹#›
Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition

Summary
Programmer’s view of virtual memory
Each process has its own private linear address space
Cannot be corrupted by other processes

System view of virtual memory
Uses memory efficiently by caching virtual memory pages
Efficient only because of locality
Simplifies memory management and programming
Simplifies protection by providing a convenient interpositioning point to check permissions

Carnegie Mellon
‹#›
Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition

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