Chapter …
Chapter 4
The Processor
Morgan Kaufmann Publishers
Morgan Kaufmann Publishers
*
Chapter 4 — The Processor
*
Chapter 4 — The Processor
Chapter 4 — The Processor — *
Introduction
CPU performance factors
Instruction count
Determined by ISA and compiler
CPI and Cycle time
Determined by CPU hardware
We will examine two LEGv8 implementations
A simplified version
A more realistic pipelined version
Simple subset, shows most aspects
Memory reference: LDUR, STUR
Arithmetic/logical: add, sub, and, or
Control transfer: CBZ, BR(Branch to register)
§4.1 Introduction
Chapter 4 — The Processor — *
Morgan Kaufmann Publishers
Morgan Kaufmann Publishers
*
Chapter 4 — The Processor
*
Chapter 4 — The Processor
Chapter 4 — The Processor — *
Instruction Execution
PC instruction memory, fetch instruction
Register numbers register file, read registers
Depending on instruction class
Use ALU to calculate
Arithmetic result
Memory address for load/store
Branch target address
Access data memory for load/store
PC target address or PC + 4
Chapter 4 — The Processor — *
Morgan Kaufmann Publishers
Morgan Kaufmann Publishers
*
Chapter 4 — The Processor
*
Chapter 4 — The Processor
Chapter 4 — The Processor — *
CPU Overview
Chapter 4 — The Processor — *
Morgan Kaufmann Publishers
Morgan Kaufmann Publishers
*
Chapter 4 — The Processor
*
Chapter 4 — The Processor
Chapter 4 — The Processor — *
Multiplexers
Can’t just join wires together
Use multiplexers
Chapter 4 — The Processor — *
Morgan Kaufmann Publishers
Morgan Kaufmann Publishers
*
Chapter 4 — The Processor
*
Chapter 4 — The Processor
Chapter 4 — The Processor — *
Control
Chapter 4 — The Processor — *
Morgan Kaufmann Publishers
Morgan Kaufmann Publishers
*
Chapter 4 — The Processor
*
Chapter 4 — The Processor
Chapter 4 — The Processor — *
Building a Datapath
Datapath
Elements that process data and addresses
in the CPU
Registers, ALUs, mux’s, memories, …
We will build a LEGv8 datapath incrementally
Refining the overview design
§4.3 Building a Datapath
Chapter 4 — The Processor — *
Morgan Kaufmann Publishers
Morgan Kaufmann Publishers
*
Chapter 4 — The Processor
*
Chapter 4 — The Processor
Chapter 4 — The Processor — *
Instruction Fetch
32-bit register
Increment by 4 for next instruction
Chapter 4 — The Processor — *
Morgan Kaufmann Publishers
Morgan Kaufmann Publishers
*
Chapter 4 — The Processor
*
Chapter 4 — The Processor
Chapter 4 — The Processor — *
R-Format Instructions
Read two register operands
Perform arithmetic/logical operation
Write register result
Chapter 4 — The Processor — *
Morgan Kaufmann Publishers
Morgan Kaufmann Publishers
*
Chapter 4 — The Processor
*
Chapter 4 — The Processor
Chapter 4 — The Processor — *
Load/Store Instructions
Consider:
LDUR X1, [X2, offset_value]
STUR X1, [X2, offset_value]
Where offset_value is a 9-bit signed offset field, which needs to be added to X2 to find the 64-bit singed value. So it needs to be sign-extended to a 64-bit signed value.
Read register operands
Calculate address using 9-bit offset
Use ALU and the sign-extend offset to find the address
Load: Read memory and update register
Store: Write register value to memory
See Figure next slide.
Chapter 4 — The Processor — *
Morgan Kaufmann Publishers
Morgan Kaufmann Publishers
*
Chapter 4 — The Processor
*
Chapter 4 — The Processor
*
Load/Store Instructions
Chapter 4 — The Processor — *
Branch Instructions
Read register operands
Compare operands
Use ALU, subtract and check Zero output
Calculate target address
Sign-extend the 19-bit displacement to 64
Shift left 2 places (word displacement)
Add to PC + 4
Already calculated by instruction fetch
Chapter 4 — The Processor — *
Morgan Kaufmann Publishers
Morgan Kaufmann Publishers
*
Chapter 4 — The Processor
*
Chapter 4 — The Processor
Chapter 4 — The Processor — *
Branch Instructions
Sign-bit wire replicated
CBZ X1, 25
If (X1=0) go to PC +100
Chapter 4 — The Processor — *
Morgan Kaufmann Publishers
Morgan Kaufmann Publishers
*
Chapter 4 — The Processor
*
Chapter 4 — The Processor
Chapter 4 — The Processor — *
R-Type/Load/Store Datapath
Chapter 4 — The Processor — *
Morgan Kaufmann Publishers
Morgan Kaufmann Publishers
*
Chapter 4 — The Processor
*
Chapter 4 — The Processor
Chapter 4 — The Processor — *
Full Datapath
Chapter 4 — The Processor — *
Morgan Kaufmann Publishers
Morgan Kaufmann Publishers
*
Chapter 4 — The Processor
*
Chapter 4 — The Processor
Chapter 4 — The Processor — *
ALU Control
ALU used for
Load/Store: Function = add
Branch: Function = subtract
R-type: Function depends on opcode
§4.4 A Simple Implementation Scheme
ALU control Function
0000 AND
0001 OR
0010 add
0110 subtract
0111 pass input b (01) for CBZ
1100 NOR
Chapter 4 — The Processor — *
Morgan Kaufmann Publishers
Morgan Kaufmann Publishers
*
Chapter 4 — The Processor
*
Chapter 4 — The Processor
Chapter 4 — The Processor — *
ALU Control
Assume 2-bit ALUOp derived from opcode
Combinational logic derives ALU control
opcode ALUOp Operation Opcode field ALU function ALU control
LDUR 00 load register XXXXXXXXXXX add 0010
STUR 00 store register XXXXXXXXXXX add 0010
CBZ 01 compare and branch on zero XXXXXXXXXXX pass input b 0111
R-type 10 add 10001011000 add 0010
subtract 11001011000 subtract 0110
AND 10001010000 AND 0000
ORR 10101010000 OR 0001
Chapter 4 — The Processor — *
Morgan Kaufmann Publishers
Morgan Kaufmann Publishers
*
Chapter 4 — The Processor
*
Chapter 4 — The Processor
Chapter 4 — The Processor — *
The Main Control Unit
Control signals derived from instruction
Chapter 4 — The Processor — *
Morgan Kaufmann Publishers
Morgan Kaufmann Publishers
*
Chapter 4 — The Processor
*
Chapter 4 — The Processor
Chapter 4 — The Processor — *
Datapath With Control
Chapter 4 — The Processor — *
Morgan Kaufmann Publishers
Morgan Kaufmann Publishers
*
Chapter 4 — The Processor
*
Chapter 4 — The Processor
Chapter 4 — The Processor — *
R-Type Instruction
Chapter 4 — The Processor — *
Morgan Kaufmann Publishers
Morgan Kaufmann Publishers
*
Chapter 4 — The Processor
*
Chapter 4 — The Processor
Chapter 4 — The Processor — *
Load Instruction
Chapter 4 — The Processor — *
Morgan Kaufmann Publishers
Morgan Kaufmann Publishers
*
Chapter 4 — The Processor
*
Chapter 4 — The Processor
Chapter 4 — The Processor — *
CBZ Instruction
Chapter 4 — The Processor — *
Morgan Kaufmann Publishers
Morgan Kaufmann Publishers
*
Chapter 4 — The Processor
*
Chapter 4 — The Processor
Chapter 4 — The Processor — *
Implementing Uncnd’l Branch
Jump uses word address
Update PC with the sum of
The value of old PC, and
26-bit jump address (sign extended)
Like the Branch, the low-order two bits of a branch address are always 00
Need an extra control signal (OR Gate) decoded from opcode
Jump
2
address
31:26
25:0
Chapter 4 — The Processor — *
Morgan Kaufmann Publishers
Morgan Kaufmann Publishers
*
Chapter 4 — The Processor
*
Chapter 4 — The Processor
© 2016 Elsevier, Inc. All rights reserved.
*
Effect of the 7 Control Signals
© 2016 Elsevier, Inc. All rights reserved.
Chapter 4 — The Processor — *
Datapath With B Added (Fig 4.23)
Chapter 4 — The Processor — *
Morgan Kaufmann Publishers
Morgan Kaufmann Publishers
*
Chapter 4 — The Processor
*
Chapter 4 — The Processor
*
Final Control Truth Table
Chapter 4 — The Processor — *
Performance Issues
Longest delay determines clock period
Critical path: load instruction
Instruction memory register file ALU data memory register file
Not feasible to vary period for different instructions
Violates design principle
Making the common case fast
We will improve performance by pipelining
Chapter 4 — The Processor — *
Morgan Kaufmann Publishers
Morgan Kaufmann Publishers
*
Chapter 4 — The Processor
*
Chapter 4 — The Processor
Chapter 4 — The Processor — *
Pipelining Analogy
Pipelined laundry: overlapping execution
Parallelism improves performance
§4.5 An Overview of Pipelining
Four loads:
Sequentially, takes 8 hours
Pipelined, takes 3.5 hours
Speedup
= 8/3.5 = 2.3
But, ignoring start up and wind-down, speed up is 4 (the number of stages)
Chapter 4 — The Processor — *
Morgan Kaufmann Publishers
Morgan Kaufmann Publishers
*
Chapter 4 — The Processor
*
Chapter 4 — The Processor
Chapter 4 — The Processor — *
LEGv8 Pipeline
Five stages, one step per stage
IF: Instruction fetch from memory
ID: Instruction decode & register read
EX: Execute operation or calculate address
MEM: Access memory operand
WB: Write result back to register
Chapter 4 — The Processor — *
Morgan Kaufmann Publishers
Morgan Kaufmann Publishers
*
Chapter 4 — The Processor
*
Chapter 4 — The Processor
Five Pipeline Stages of a RISC
IF (or IM)
Fetch Instruction From Memory
Update PC
ID
Decode Instruction
Fetch Register Values
Detect if it is Branch or jump; compute the possible branch target address
EX
Do
ALU Operation, or
Compute memory Address, or
Test Branch Condition; change the PC to target if needed
MEM (or DM)
Read or Write memory Operand
WB
Write ALU result or Memory Load Operand into Destination Register
Chapter 4 — The Processor — *
Pipeline Performance
Assume time for stages is
100ps for register read or write
200ps for other stages
Compare pipelined datapath with single-cycle datapath
Instr Instr fetch Register read ALU op Memory access Register write Total time
LDUR 200ps 100 ps 200ps 200ps 100 ps 800ps
STUR 200ps 100 ps 200ps 200ps 700ps
R-format 200ps 100 ps 200ps 100 ps 600ps
CBZ 200ps 100 ps 200ps 500ps
Chapter 4 — The Processor — *
Morgan Kaufmann Publishers
Morgan Kaufmann Publishers
*
Chapter 4 — The Processor
*
Chapter 4 — The Processor
Chapter 4 — The Processor — *
Pipeline Performance
Single-cycle (Tc= 800ps)
Pipelined (Tc= 200ps)
Chapter 4 — The Processor — *
Morgan Kaufmann Publishers
Morgan Kaufmann Publishers
*
Chapter 4 — The Processor
*
Chapter 4 — The Processor
Chapter 4 — The Processor — *
Pipeline Speedup
If all stages are balanced
i.e., all take the same time
Time between instructionspipelined
= Time between instructionsnonpipelined
Number of stages
If not balanced, speedup is less
Speedup is due to increased throughput
Latency (time for each instruction) does not decrease.
Chapter 4 — The Processor — *
Morgan Kaufmann Publishers
Morgan Kaufmann Publishers
*
Chapter 4 — The Processor
*
Chapter 4 — The Processor
Chapter 4 — The Processor — *
Pipelining and ISA Design
LEGv8 ISA designed for pipelining
All instructions are 32-bits
Easier to fetch and decode in one cycle
c.f. x86: 1- to 17-byte instructions
Few and regular instruction formats
Can decode and read registers in one step
Load/store addressing
Can calculate address in 3rd stage, access memory in 4th stage
Alignment of memory operands
Memory access takes only one cycle
Chapter 4 — The Processor — *
Morgan Kaufmann Publishers
Morgan Kaufmann Publishers
*
Chapter 4 — The Processor
*
Chapter 4 — The Processor
Chapter 4 — The Processor — *
Hazards
Situations that prevent starting the next instruction in the next cycle
Structure hazards
A required resource is busy
Data hazard
Need to wait for previous instruction to complete its data read/write
Control hazard
Deciding on control action depends on previous instruction
Chapter 4 — The Processor — *
Morgan Kaufmann Publishers
Morgan Kaufmann Publishers
*
Chapter 4 — The Processor
*
Chapter 4 — The Processor
Chapter 4 — The Processor — *
Structure Hazards
Conflict for use of a resource
In LEGv8 pipeline with a single memory
Load/store requires data access
Instruction fetch would have to stall for that cycle
Would cause a pipeline “bubble”
Hence, pipelined datapaths require separate instruction/data memories
Or separate instruction/data caches
Chapter 4 — The Processor — *
Morgan Kaufmann Publishers
Morgan Kaufmann Publishers
*
Chapter 4 — The Processor
*
Chapter 4 — The Processor
Copyright © 2019, Elsevier Inc. All rights Reserved.
A processor with only one memory port will generate a conflict whenever a memory reference occurs. In this example the load instruction uses the memory for a data access at the same time instruction 3 wants to fetch an instruction from memory.
A Structural Hazard
Copyright © 2019, Elsevier Inc. All rights Reserved.
Morgan Kaufmann Publishers
*
Chapter 4 — The Processor
Chapter 4 — The Processor — *
Data Hazards
An instruction depends on completion of data access by a previous instruction
ADD X19, X0, X1
SUB X2, X19, X3
Chapter 4 — The Processor — *
Morgan Kaufmann Publishers
Morgan Kaufmann Publishers
*
Chapter 4 — The Processor
*
Chapter 4 — The Processor
Chapter 4 — The Processor — *
Forwarding (aka Bypassing)
Use result when it is computed
Don’t wait for it to be stored in a register
Requires extra connections in the datapath
Chapter 4 — The Processor — *
Morgan Kaufmann Publishers
Morgan Kaufmann Publishers
*
Chapter 4 — The Processor
*
Chapter 4 — The Processor
Chapter 4 — The Processor — *
Load-Use Data Hazard
Can’t always avoid stalls by forwarding
If value not computed when needed
Can’t forward backward in time!
Chapter 4 — The Processor — *
Morgan Kaufmann Publishers
Morgan Kaufmann Publishers
*
Chapter 4 — The Processor
*
Chapter 4 — The Processor
Chapter 4 — The Processor — *
Code Scheduling to Avoid Stalls
Example: Reorder code to avoid use of load result in the next instruction. Assume WB split Cycle.
C code for A = B + E; C = B + F;
LDUR X1, [X0,#0]
LDUR X2, [X0,#8]
ADD X3, X1, X2
STUR X3, [X0,#24]
LDUR X4, [X0,#16]
ADD X5, X1, X4
STUR X5, [X0,#32]
stall
stall
LDUR X1, [X0,#0]
LDUR X2, [X0,#8]
LDUR X4, [X0,#16]
ADD X3, X1, X2
STUR X3, [X0,#24]
ADD X5, X1, X4
STUR X5, [X0,#32]
Saves some cycles
Chapter 4 — The Processor — *
Morgan Kaufmann Publishers
Morgan Kaufmann Publishers
*
Chapter 4 — The Processor
*
Chapter 4 — The Processor
Time Diagram for the Example
Chapter 4 — The Processor — *
Instruction C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19
LDUR X1 IF ID EX ME WB
LDUR X2 IF ID EX ME WB
ADD X3, X1, X2 IF S S ID EX ME WB
STUR X3 IF S S ID EX ME WB
LDUR X4 IF ID EX ME WB
ADD X5, X1, X4 IF S S ID EX
ME WB
STUR X5 IF S S ID EX ME WB
Chapter 4 — The Processor — *
Time Diagram for the example with code re-arranging
Chapter 4 — The Processor — *
Instruction C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19
LDUR X1 IF ID EX ME WB
LDUR X2 IF ID EX ME WB
LDUR X4 IF ID EX ME WB
ADD X3, X1, X2 IF S ID EX ME WB
STUR X3 IF S S ID EX ME WB
ADD X5, X1, X4 IF ID EX ME WB
STUR X5 IF S S ID EX ME WB
Chapter 4 — The Processor — *
Time Diagram for the example with more code re-arranging
Chapter 4 — The Processor — *
Instruction C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19
LDUR X1 IF ID EX ME WB
LDUR X2 IF ID EX ME WB
LDUR X4 IF ID EX ME WB
ADD X3, X1, X2 IF S ID EX ME WB
ADD X5, x1, X4 IF ID EX ME WB
STUR X3 IF S ID EX ME WB
STUR X5 IF ID EX ME WB
Chapter 4 — The Processor — *
Chapter 4 — The Processor — *
Control Hazards
Branch determines flow of control
Fetching next instruction depends on branch outcome
Pipeline can’t always fetch correct instruction
Still working on ID stage of branch
In LEGv8 pipeline
Need to compare registers and compute target early in the pipeline
Add hardware to do it in ID stage
Chapter 4 — The Processor — *
Morgan Kaufmann Publishers
Morgan Kaufmann Publishers
*
Chapter 4 — The Processor
*
Chapter 4 — The Processor
Chapter 4 — The Processor — *
Stall on Branch
Wait until branch outcome determined before fetching next instruction
Chapter 4 — The Processor — *
Morgan Kaufmann Publishers
Morgan Kaufmann Publishers
*
Chapter 4 — The Processor
*
Chapter 4 — The Processor
Chapter 4 — The Processor — *
Branch Prediction
Longer pipelines can’t readily determine branch outcome early
Stall penalty becomes unacceptable
Predict outcome of branch
Only stall if prediction is wrong
In LEGv8 pipeline
Can predict branches not taken
Fetch instruction after branch, with no delay
Chapter 4 — The Processor — *
Morgan Kaufmann Publishers
Morgan Kaufmann Publishers
*
Chapter 4 — The Processor
*
Chapter 4 — The Processor
Chapter 4 — The Processor — *
More-Realistic Branch Prediction
Static branch prediction
Based on typical branch behavior
Example: loop and if-statement branches
Predict backward branches taken
Predict forward branches not taken
Dynamic branch prediction
Hardware measures actual branch behavior
e.g., record recent history of each branch
Assume future behavior will continue the trend
When wrong, stall while re-fetching, and update history
Chapter 4 — The Processor — *
Morgan Kaufmann Publishers
Morgan Kaufmann Publishers
*
Chapter 4 — The Processor
*
Chapter 4 — The Processor
Chapter 4 — The Processor — *
Pipeline Summary
Pipelining improves performance by increasing instruction throughput
Executes multiple instructions in parallel
Each instruction has the same latency
Pipelining does not intend to improve latency
Subject to hazards
Structure, data, control
Instruction set design affects complexity of pipeline implementation
The BIG Picture
Chapter 4 — The Processor — *
Morgan Kaufmann Publishers
Morgan Kaufmann Publishers
*
Chapter 4 — The Processor
*
Chapter 4 — The Processor
Chapter 4 — The Processor — *
LEGv8 Pipelined Datapath (Fig 4.32)
§4.6 Pipelined Datapath and Control
WB
MEM
Single-Cycle Datapath (similar to Fig 4.17)
Chapter 4 — The Processor — *
Morgan Kaufmann Publishers
Morgan Kaufmann Publishers
*
Chapter 4 — The Processor
*
Chapter 4 — The Processor
Chapter 4 — The Processor — *
Pipeline registers
Need registers between stages
To hold information produced in previous cycle
Chapter 4 — The Processor — *
Morgan Kaufmann Publishers
Morgan Kaufmann Publishers
*
Chapter 4 — The Processor
*
Chapter 4 — The Processor
Chapter 4 — The Processor — *
Pipeline Operation
Cycle-by-cycle flow of instructions through the pipelined datapath
“Single-clock-cycle” pipeline diagram
Shows pipeline usage in a single cycle
Highlight resources used
c.f. “multi-clock-cycle” diagram
Graph of operation over time
We’ll look at “single-clock-cycle” diagrams for load & store
Chapter 4 — The Processor — *
Morgan Kaufmann Publishers
Morgan Kaufmann Publishers
*
Chapter 4 — The Processor
*
Chapter 4 — The Processor
Chapter 4 — The Processor — *
IF for Load
Chapter 4 — The Processor — *
Morgan Kaufmann Publishers
Morgan Kaufmann Publishers
*
Chapter 4 — The Processor
*
Chapter 4 — The Processor
Chapter 4 — The Processor — *
ID for Load
Chapter 4 — The Processor — *
Morgan Kaufmann Publishers
Morgan Kaufmann Publishers
*
Chapter 4 — The Processor
*
Chapter 4 — The Processor
Chapter 4 — The Processor — *
EX for Load
Chapter 4 — The Processor — *
Morgan Kaufmann Publishers
Morgan Kaufmann Publishers
*
Chapter 4 — The Processor
*
Chapter 4 — The Processor
Chapter 4 — The Processor — *
MEM for Load
Chapter 4 — The Processor — *
Morgan Kaufmann Publishers
Morgan Kaufmann Publishers
*
Chapter 4 — The Processor
*
Chapter 4 — The Processor
Chapter 4 — The Processor — *
WB for Load
There is a bug in here which is corrected in next slide. Note the instruction in IF/ID supplies the write register number here; but this instruction is after the load instruction
Chapter 4 — The Processor — *
Morgan Kaufmann Publishers
Morgan Kaufmann Publishers
*
Chapter 4 — The Processor
*
Chapter 4 — The Processor
Chapter 4 — The Processor — *
Corrected Datapath for Load
There right register number now comes from MEM/WB pipeline register along with the data
Chapter 4 — The Processor — *
Morgan Kaufmann Publishers
Morgan Kaufmann Publishers
*
Chapter 4 — The Processor
*
Chapter 4 — The Processor
Chapter 4 — The Processor — *
EX for Store
Chapter 4 — The Processor — *
Morgan Kaufmann Publishers
Morgan Kaufmann Publishers
*
Chapter 4 — The Processor
*
Chapter 4 — The Processor
Chapter 4 — The Processor — *
MEM for Store
Chapter 4 — The Processor — *
Morgan Kaufmann Publishers
Morgan Kaufmann Publishers
*
Chapter 4 — The Processor
*
Chapter 4 — The Processor
Chapter 4 — The Processor — *
WB for Store
Chapter 4 — The Processor — *
Morgan Kaufmann Publishers
Morgan Kaufmann Publishers
*
Chapter 4 — The Processor
*
Chapter 4 — The Processor
© 2016 Elsevier, Inc. All rights reserved.
*
Pipeline Control
© 2016 Elsevier, Inc. All rights reserved.
© 2016 Elsevier, Inc. All rights reserved.
*
ALU Control Bits from Fig.4.12
© 2016 Elsevier, Inc. All rights reserved.
© 2016 Elsevier, Inc. All rights reserved.
*
Function of seven control Signal from 4.16
© 2016 Elsevier, Inc. All rights reserved.
© 2016 Elsevier, Inc. All rights reserved.
*
Value of Control lines from 4.18
© 2016 Elsevier, Inc. All rights reserved.
© 2016 Elsevier, Inc. All rights reserved.
*
Eight Control lines for last 3 Stages
© 2016 Elsevier, Inc. All rights reserved.
© 2016 Elsevier, Inc. All rights reserved.
*
The pipeline data path with control
© 2016 Elsevier, Inc. All rights reserved.
Chapter 4 — The Processor — *
Forwarding: Data Hazards in ALU Instructions
Consider this sequence:
SUB X2, X1,X3
AND X12,X2,X5
OR X13,X6,X2
ADD X14,X2,X2
STUR X15,[X2,#100]
We can resolve hazards with forwarding
How do we detect when to forward?
§4.7 Data Hazards: Forwarding vs. Stalling
Chapter 4 — The Processor — *
Morgan Kaufmann Publishers
Morgan Kaufmann Publishers
*
Chapter 4 — The Processor
*
Chapter 4 — The Processor
Chapter 4 — The Processor — *
Multi-Cycle Pipeline Diagram
Form showing resource usage
Chapter 4 — The Processor — *
Morgan Kaufmann Publishers
Morgan Kaufmann Publishers
*
Chapter 4 — The Processor
*
Chapter 4 — The Processor
© 2016 Elsevier, Inc. All rights reserved.
*
Dependencies
© 2016 Elsevier, Inc. All rights reserved.
Chapter 4 — The Processor — *
Dependencies & Forwarding
Chapter 4 — The Processor — *
Morgan Kaufmann Publishers
Morgan Kaufmann Publishers
*
Chapter 4 — The Processor
*
Chapter 4 — The Processor
© 2016 Elsevier, Inc. All rights reserved.
*
Forwarding with WB Split Cycle
© 2016 Elsevier, Inc. All rights reserved.
Chapter 4 — The Processor — *
Detecting the Need to Forward
Pass register numbers along pipeline
e.g., ID/EX.RegisterRs = register number for Rs sitting in ID/EX pipeline register
ALU operand register numbers in EX stage are given by
ID/EX.RegisterRn1, ID/EX.RegisterRm2
Data hazards when
1a. EX/MEM.RegisterRd = ID/EX.RegisterRn1
1b. EX/MEM.RegisterRd = ID/EX.RegisterRm2
2a. MEM/WB.RegisterRd = ID/EX.RegisterRn1
2b. MEM/WB.RegisterRd = ID/EX.RegisterRm2
Fwd from
EX/MEM
pipeline reg
Fwd from
MEM/WB
pipeline reg
Chapter 4 — The Processor — *
Morgan Kaufmann Publishers
Morgan Kaufmann Publishers
*
Chapter 4 — The Processor
*
Chapter 4 — The Processor
Chapter 4 — The Processor — *
Detecting the Need to Forward
But only if forwarding instruction will write to a register!
EX/MEM.RegWrite, MEM/WB.RegWrite
And only if Rd for that instruction is not XZR
EX/MEM.RegisterRd ≠ 31,
MEM/WB.RegisterRd ≠ 31
Chapter 4 — The Processor — *
Morgan Kaufmann Publishers
Morgan Kaufmann Publishers
*
Chapter 4 — The Processor
*
Chapter 4 — The Processor
Chapter 4 — The Processor — *
Forwarding Paths
Chapter 4 — The Processor — *
Morgan Kaufmann Publishers
Morgan Kaufmann Publishers
*
Chapter 4 — The Processor
*
Chapter 4 — The Processor
Chapter 4 — The Processor — *
Forwarding Conditions
Mux control Source Explanation
ForwardA = 00 ID/EX The first ALU operand comes from the register file.
ForwardA = 10 EX/MEM The first ALU operand is forwarded from the prior ALU result.
ForwardA = 01 MEM/WB The first ALU operand is forwarded from data memory or an earlier
ALU result.
ForwardB = 00 ID/EX The second ALU operand comes from the register file.
ForwardB = 10 EX/MEM The second ALU operand is forwarded from the prior ALU result.
ForwardB = 01 MEM/WB The second ALU operand is forwarded from data memory or an
earlier ALU result.
Chapter 4 — The Processor — *
Morgan Kaufmann Publishers
Morgan Kaufmann Publishers
*
Chapter 4 — The Processor
*
Chapter 4 — The Processor
Chapter 4 — The Processor — *
Double Data Hazard
Consider the sequence:
add X1,X1,X2
add X1,X1,X3
add X1,X1,X4
Both hazards occur
Want to use the most recent
Revise MEM hazard condition
Only fwd if EX hazard condition isn’t true
Chapter 4 — The Processor — *
Morgan Kaufmann Publishers
Morgan Kaufmann Publishers
*
Chapter 4 — The Processor
*
Chapter 4 — The Processor
Chapter 4 — The Processor — *
Revised Forwarding Condition
MEM hazard
if (MEM/WB.RegWrite
and (MEM/WB.RegisterRd ≠ 31)
and not(EX/MEM.RegWrite and (EX/MEM.RegisterRd ≠ 31)
and (EX/MEM.RegisterRd ≠ ID/EX.RegisterRn1))
and (MEM/WB.RegisterRd = ID/EX.RegisterRn1)) ForwardA = 01
if (MEM/WB.RegWrite
and (MEM/WB.RegisterRd ≠ 31)
and not(EX/MEM.RegWrite and (EX/MEM.RegisterRd ≠ 31)
and (EX/MEM.RegisterRd ≠ ID/EX.RegisterRm2))
and (MEM/WB.RegisterRd = ID/EX.RegisterRm2)) ForwardB = 01
Chapter 4 — The Processor — *
Morgan Kaufmann Publishers
Morgan Kaufmann Publishers
*
Chapter 4 — The Processor
*
Chapter 4 — The Processor
Chapter 4 — The Processor — *
Datapath with Forwarding
Chapter 4 — The Processor — *
Morgan Kaufmann Publishers
Morgan Kaufmann Publishers
*
Chapter 4 — The Processor
*
Chapter 4 — The Processor
Chapter 4 — The Processor — *
Load-Use Hazard Detection
Check when using instruction is decoded in ID stage
ALU operand register numbers in ID stage are given by
IF/ID.RegisterRn1, IF/ID.RegisterRm2
Load-use hazard when
ID/EX.MemRead and
((ID/EX.RegisterRd = IF/ID.RegisterRn1) or
(ID/EX.RegisterRd = IF/ID.RegisterRm1))
If detected, stall and insert bubble
Chapter 4 — The Processor — *
Morgan Kaufmann Publishers
Morgan Kaufmann Publishers
*
Chapter 4 — The Processor
*
Chapter 4 — The Processor
Chapter 4 — The Processor — *
How to Stall the Pipeline
Force control values in ID/EX register
to 0
EX, MEM and WB do nop (no-operation)
Prevent update of PC and IF/ID register
Using instruction is decoded again
Following instruction is fetched again
1-cycle stall allows MEM to read data for Load instruction.
Can subsequently forward to EX stage
Chapter 4 — The Processor — *
Morgan Kaufmann Publishers
Morgan Kaufmann Publishers
*
Chapter 4 — The Processor
*
Chapter 4 — The Processor
Chapter 4 — The Processor — *
Load-Use Data Hazard
Stall inserted here
Chapter 4 — The Processor — *
Morgan Kaufmann Publishers
Morgan Kaufmann Publishers
*
Chapter 4 — The Processor
*
Chapter 4 — The Processor
Chapter 4 — The Processor — *
Datapath with Hazard Detection
Chapter 4 — The Processor — *
Morgan Kaufmann Publishers
Morgan Kaufmann Publishers
*
Chapter 4 — The Processor
*
Chapter 4 — The Processor
Chapter 4 — The Processor — *
Stalls and Performance
Stalls reduce performance
But are required to get correct results
Compiler can arrange code to avoid hazards and stalls
Requires knowledge of the pipeline structure
The BIG Picture
Chapter 4 — The Processor — *
Morgan Kaufmann Publishers
Morgan Kaufmann Publishers
*
Chapter 4 — The Processor
*
Chapter 4 — The Processor
Chapter 4 — The Processor — *
Control Hazards
If branch outcome determined in MEM
§4.8 Control Hazards
PC
Flush these
instructions
(Set control
values to 0)
Chapter 4 — The Processor — *
Morgan Kaufmann Publishers
Morgan Kaufmann Publishers
*
Chapter 4 — The Processor
*
Chapter 4 — The Processor
Chapter 4 — The Processor — *
Reducing Branch Delay
Move hardware to determine outcome to ID stage
Target address adder
Register comparator
Example: branch taken
36: SUB X10, X4, X8
40: CBZ X1, 8
44: AND X12, X2, X5
48: ORR X13, X2, X6
52: ADD X14, X4, X2
56: SUB X15, X6, X7
…
72: LDUR X4, [X7,#50]
Chapter 4 — The Processor — *
Morgan Kaufmann Publishers
Morgan Kaufmann Publishers
*
Chapter 4 — The Processor
*
Chapter 4 — The Processor
Chapter 4 — The Processor — *
Example: Branch Taken
Chapter 4 — The Processor — *
Morgan Kaufmann Publishers
Morgan Kaufmann Publishers
*
Chapter 4 — The Processor
*
Chapter 4 — The Processor
Chapter 4 — The Processor — *
Example: Branch Taken
Chapter 4 — The Processor — *
Morgan Kaufmann Publishers
Morgan Kaufmann Publishers
*
Chapter 4 — The Processor
*
Chapter 4 — The Processor
Chapter 4 — The Processor — *
Dynamic Branch Prediction
In deeper and superscalar pipelines, branch penalty is more significant
Use dynamic prediction
Branch prediction buffer (aka Branch History Table)
Indexed by recent branch instruction addresses
Stores outcome (taken/not taken)
To execute a branch
Check table, expect the same outcome
Start fetching from fall-through or target
If wrong, flush pipeline and flip prediction
Chapter 4 — The Processor — *
Morgan Kaufmann Publishers
Morgan Kaufmann Publishers
*
Chapter 4 — The Processor
*
Chapter 4 — The Processor
Example
Suppose the following code is within a loop reading the values of x. Assume a Branch History Table of 1-bit predictor used. Fill out the table below as values 4, 5, 6, 8, 11 are read. Assume predictor buffers contain 0 initially.
If (x is odd) then Branch B1
print “O”
if (x is even) then Branch B2
print “E”
Overall prediction accuracy = 3/10 = 30%. What are the lessons?
BHT
4 5 6 8 11
B1 Buffer 0 0 1 0 0
B1 predicted Not taken Not taken Taken Not taken Not taken
B1 Predictor correct incorrect incorrect correct incorrect
B2 Buffer 0 1 0 1 1
B2 predicted Not taken Taken Not taken Taken Taken
B2 Predictor incorrect Incorrect incorrect correct incorrect
Branch B1 Address B1 predicted taken or untaken
Branch B2 Address B2 predicted taken or untaken
Morgan Kaufmann Publishers
*
Chapter 4 — The Processor
Chapter 4 — The Processor — *
2-Bit Predictor
Only change prediction on two successive mispredictions
Chapter 4 — The Processor — *
Morgan Kaufmann Publishers
Morgan Kaufmann Publishers
*
Chapter 4 — The Processor
*
Chapter 4 — The Processor
Example
Suppose the following code is within a loop reading the values of x. Assume a Branch History Table of 2-bit predictor used. Fill out the table below as values 4, 5, 6, 8, 11 are read. Assume predictor buffers contain 00 initially.
If (x is odd) then Branch B1
print “O”
if (x is even) then Branch B2
print “E”
Overall prediction accuracy = 4/10 = 40%. What are the lessons?
4 5 6 8 11
B1 Buffer 00 00 01 00 00
B1 predicted Not taken Not taken Not taken Not taken Not taken
B1 Predictor correct incorrect correct correct incorrect
B2 Buffer 00 01 00 01 11
B2 predicted Not taken Not taken Not taken Not taken Taken
B2 Predictor incorrect correct incorrect incorrect incorrect
Morgan Kaufmann Publishers
*
Chapter 4 — The Processor
Chapter 4 — The Processor — *
Calculating the Branch Target
Even with predictor, still need to calculate the target address
1-cycle penalty for a taken branch
Branch Target Buffer
Cache of target addresses
Indexed by PC when instruction fetched
If hit and instruction is branch predicted taken, can fetch target immediately
Chapter 4 — The Processor — *
Morgan Kaufmann Publishers
Morgan Kaufmann Publishers
*
Chapter 4 — The Processor
*
Chapter 4 — The Processor
Branch-Target Buffers
Next PC prediction buffer, indexed by current PC
Helps reduce branch penalty
Branch-Target Buffer
Morgan Kaufmann Publishers
The University of Adelaide, School of Computer Science
*
Chapter 2 — Instructions: Language of the Computer
*
Chapter 4 — The Processor
Time Diagram
Assume the following code segment, draw the time diagram, assuming WB split cycle, full forwarding, and branch resolution in EX with PC update in MEM. Assume X7 is not zero for CBZ instruction.
STUR X16, [X6, #12]
LDUR X16, [X6, #8]
SUB X7, X16, X4
CBZ X7, 2
ADD X5, X1, X4
SUBS X5, X15, X4
Chapter 4 — The Processor — *
Instruction C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14
STUR X16, [X6, #12] IF ID EX ME WB
LDUR X16, [X6, #8] IF ID EX ME WB
SUB X7, X16, X4 IF S ID EX ME WB
CBZ X7, 2 IF ID EX ME WB
ADD X5, X1, X4 IF ID EX ME WB
SUBS X5, X15, X4 IF ID EX ME WB
Chapter 4 — The Processor — *
Time Diagram
Assume the following code segment, draw the time diagram, assuming WB split cycle, full forwarding, and branch resolution in EX with PC update in MEM. Assume X7 is zero for CBZ instruction.
Chapter 4 — The Processor — *
Instruction C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14
STUR X16, [X6, #12 IF ID EX ME WB
LDUR X16, [X6, #8] IF ID EX ME WM
SUB X7, X16, X4 IF S ID EX ME WB
CBZ X7, 2 IF ID EX ME WB
ADD X5, X1, X4 IF ID Flush
SUB X5, X15, X4 IF ID EX ME WB
Chapter 4 — The Processor — *
Chapter 4 — The Processor — *
Exceptions and Interrupts
“Unexpected” events requiring change
in flow of control
Different ISAs use the terms differently
Exception
Arises within the CPU
e.g., undefined opcode, overflow, syscall, …
Interrupt
From an external I/O controller
Dealing with them without sacrificing performance is hard
§4.9 Exceptions
Chapter 4 — The Processor — *
Morgan Kaufmann Publishers
Morgan Kaufmann Publishers
*
Chapter 4 — The Processor
*
Chapter 4 — The Processor
Chapter 4 — The Processor — *
Handling Exceptions
Save PC of offending (or interrupted) instruction
In LEGv8: Exception Link Register (ELR)
Save indication of the problem
In LEGv8: Exception Syndrome Register (ESR)
We’ll assume 1-bit
0 for undefined opcode, 1 for overflow
Chapter 4 — The Processor — *
Morgan Kaufmann Publishers
Morgan Kaufmann Publishers
*
Chapter 4 — The Processor
*
Chapter 4 — The Processor
Chapter 4 — The Processor — *
Handler Actions
Read cause, and transfer to relevant handler
Determine action required
If restartable
Take corrective action
use EPC to return to program
Otherwise
Terminate program
Report error using EPC, cause, …
Chapter 4 — The Processor — *
Morgan Kaufmann Publishers
Morgan Kaufmann Publishers
*
Chapter 4 — The Processor
*
Chapter 4 — The Processor
Chapter 4 — The Processor — *
Exceptions in a Pipeline
Another form of control hazard
Consider overflow on add in EX stage
ADD X1, X2, X1
Prevent X1 from being clobbered
Complete previous instructions
Flush add and subsequent instructions
Set ESR and ELR register values
Transfer control to handler
Similar to mispredicted branch
Use much of the same hardware
Chapter 4 — The Processor — *
Morgan Kaufmann Publishers
Morgan Kaufmann Publishers
*
Chapter 4 — The Processor
*
Chapter 4 — The Processor
Chapter 4 — The Processor — *
Pipeline with Exceptions
Chapter 4 — The Processor — *
Morgan Kaufmann Publishers
Morgan Kaufmann Publishers
*
Chapter 4 — The Processor
*
Chapter 4 — The Processor
Chapter 4 — The Processor — *
Exception Properties
Restartable exceptions
Pipeline can flush the instruction
Handler executes, then returns to the instruction
Refetched and executed from scratch
PC saved in ELR register
Identifies causing instruction
Actually PC + 4 is saved
Handler must adjust
Chapter 4 — The Processor — *
Morgan Kaufmann Publishers
Morgan Kaufmann Publishers
*
Chapter 4 — The Processor
*
Chapter 4 — The Processor
Chapter 4 — The Processor — *
Exception Example
Exception on ADD in
40 SUB X11, X2, X4
44 AND X12, X2, X5
48 ORR X13, X2, X6
4C ADD X1, X2, X1
50 SUB X15, X6, X7
54 LDUR X16, [X7,#100]
…
Handler
80000180 STUR X26, [X0,#1000]
80000184 STUR X27, [X0,#1008]
…
Chapter 4 — The Processor — *
Morgan Kaufmann Publishers
Morgan Kaufmann Publishers
*
Chapter 4 — The Processor
*
Chapter 4 — The Processor
Chapter 4 — The Processor — *
Exception Example
Chapter 4 — The Processor — *
Morgan Kaufmann Publishers
Morgan Kaufmann Publishers
*
Chapter 4 — The Processor
*
Chapter 4 — The Processor
Chapter 4 — The Processor — *
Exception Example
Chapter 4 — The Processor — *
Morgan Kaufmann Publishers
Morgan Kaufmann Publishers
*
Chapter 4 — The Processor
*
Chapter 4 — The Processor
Chapter 4 — The Processor — *
Multiple Exceptions
Pipelining overlaps multiple instructions
Could have multiple exceptions at once
Simple approach: deal with exception from earliest instruction
Flush subsequent instructions
“Precise” exceptions
In complex pipelines
Multiple instructions issued per cycle
Out-of-order completion
Maintaining precise exceptions is difficult!
Chapter 4 — The Processor — *
Morgan Kaufmann Publishers
Morgan Kaufmann Publishers
*
Chapter 4 — The Processor
*
Chapter 4 — The Processor
Chapter 4 — The Processor — *
Imprecise Exceptions
Just stop pipeline and save state
Including exception cause(s)
Let the handler work out
Which instruction(s) had exceptions
Which to complete or flush
May require “manual” completion
Simplifies hardware, but more complex handler software
Not feasible for complex multiple-issue
out-of-order pipelines
Chapter 4 — The Processor — *
Morgan Kaufmann Publishers
Morgan Kaufmann Publishers
*
Chapter 4 — The Processor
*
Chapter 4 — The Processor
Chapter 4 — The Processor — *
Instruction-Level Parallelism (ILP)
Pipelining: executing multiple instructions in parallel
To increase ILP
Deeper pipeline
Less work per stage shorter clock cycle
Multiple issue
Replicate pipeline stages multiple pipelines
Start multiple instructions per clock cycle
CPI < 1, so use Instructions Per Cycle (IPC)
E.g., 4GHz 4-way multiple-issue
16 BIPS, peak CPI = 0.25, peak IPC = 4
But dependencies reduce this in practice
§4.10 Parallelism via Instructions
Chapter 4 — The Processor — *
Morgan Kaufmann Publishers
Morgan Kaufmann Publishers
*
Chapter 4 — The Processor
*
Chapter 4 — The Processor
Chapter 4 — The Processor — *
Multiple Issue
Static multiple issue
Compiler groups instructions to be issued together
Packages them into “issue slots”
Compiler detects and avoids hazards
Dynamic multiple issue
CPU examines instruction stream and chooses instructions to issue each cycle
Compiler can help by reordering instructions
CPU resolves hazards using advanced techniques at runtime
Chapter 4 — The Processor — *
Morgan Kaufmann Publishers
Morgan Kaufmann Publishers
*
Chapter 4 — The Processor
*
Chapter 4 — The Processor
Chapter 4 — The Processor — *
Speculation
“Guess” what to do with an instruction
Start operation as soon as possible
Check whether guess was right
If so, complete the operation
If not, roll-back and do the right thing
Common to static and dynamic multiple issue
Examples
Speculate on branch outcome
Roll back if path taken is different
Speculate on load
Roll back if location is updated
Chapter 4 — The Processor — *
Morgan Kaufmann Publishers
Morgan Kaufmann Publishers
*
Chapter 4 — The Processor
*
Chapter 4 — The Processor
Chapter 4 — The Processor — *
Compiler/Hardware Speculation
Compiler can reorder instructions
e.g., move load before branch
Can include “fix-up” instructions to recover from incorrect guess
Hardware can look ahead for instructions to execute
Buffer results until it determines they are actually needed
Flush buffers on incorrect speculation
Chapter 4 — The Processor — *
Morgan Kaufmann Publishers
Morgan Kaufmann Publishers
*
Chapter 4 — The Processor
*
Chapter 4 — The Processor
Chapter 4 — The Processor — *
Speculation and Exceptions
What if exception occurs on a speculatively executed instruction?
e.g., speculative load before null-pointer check
Static speculation
Can add ISA support for deferring exceptions
Dynamic speculation
Can buffer exceptions until instruction completion (which may not occur)
Chapter 4 — The Processor — *
Morgan Kaufmann Publishers
Morgan Kaufmann Publishers
*
Chapter 4 — The Processor
*
Chapter 4 — The Processor
Chapter 4 — The Processor — *
Static Multiple Issue
Compiler groups instructions into “issue packets”
Group of instructions that can be issued on a single cycle
Determined by pipeline resources required
Think of an issue packet as a very long instruction
Specifies multiple concurrent operations
Very Long Instruction Word (VLIW)
Chapter 4 — The Processor — *
Morgan Kaufmann Publishers
Morgan Kaufmann Publishers
*
Chapter 4 — The Processor
*
Chapter 4 — The Processor
Chapter 4 — The Processor — *
Scheduling Static Multiple Issue
Compiler must remove some/all hazards
Reorder instructions into issue packets
No dependencies with a packet
Possibly some dependencies between packets
Varies between ISAs; compiler must know!
Pad with nop if necessary
Chapter 4 — The Processor — *
Morgan Kaufmann Publishers
Morgan Kaufmann Publishers
*
Chapter 4 — The Processor
*
Chapter 4 — The Processor
Chapter 4 — The Processor — *
Dynamic Multiple Issue
“Superscalar” processors
CPU decides whether to issue 0, 1, 2, … each cycle
Avoiding structural and data hazards
Avoids the need for compiler scheduling
Though it may still help
Code semantics ensured by the CPU
Chapter 4 — The Processor — *
Morgan Kaufmann Publishers
Morgan Kaufmann Publishers
*
Chapter 4 — The Processor
*
Chapter 4 — The Processor
Chapter 4 — The Processor — *
Dynamic Pipeline Scheduling
Allow the CPU to execute instructions out of order to avoid stalls
But commit result to registers in order
Example
LDUR X0, [X21,#20]
ADD X1, X0, X2
SUB X23,X23,X3
ANDI X5, X23,#20
Can start sub while ADD is waiting for LDUI
Chapter 4 — The Processor — *
Morgan Kaufmann Publishers
Morgan Kaufmann Publishers
*
Chapter 4 — The Processor
*
Chapter 4 — The Processor
Chapter 4 — The Processor — *
Dynamically Scheduled CPU
Results also sent to any waiting reservation stations
Reorders buffer for register writes
Can supply operands for issued instructions
Preserves dependencies
Hold pending operands
Chapter 4 — The Processor — *
Morgan Kaufmann Publishers
Morgan Kaufmann Publishers
*
Chapter 4 — The Processor
*
Chapter 4 — The Processor
Chapter 4 — The Processor — *
Register Renaming
Reservation stations and reorder buffer effectively provide register renaming
On instruction issue to reservation station
If operand is available in register file or reorder buffer
Copied to reservation station
No longer required in the register; can be overwritten
If operand is not yet available
It will be provided to the reservation station by a function unit
Register update may not be required
Chapter 4 — The Processor — *
Morgan Kaufmann Publishers
Morgan Kaufmann Publishers
*
Chapter 4 — The Processor
*
Chapter 4 — The Processor
Chapter 4 — The Processor — *
Speculation
Predict branch and continue issuing
Don’t commit until branch outcome determined
Load speculation
Avoid load and cache miss delay
Predict the effective address
Predict loaded value
Load before completing outstanding stores
Bypass stored values to load unit
Don’t commit load until speculation cleared
Chapter 4 — The Processor — *
Morgan Kaufmann Publishers
Morgan Kaufmann Publishers
*
Chapter 4 — The Processor
*
Chapter 4 — The Processor
Chapter 4 — The Processor — *
Why Do Dynamic Scheduling?
Why not just let the compiler schedule code?
Not all stalls are predicable
e.g., cache misses
Can’t always schedule around branches
Branch outcome is dynamically determined
Different implementations of an ISA have different latencies and hazards
Chapter 4 — The Processor — *
Morgan Kaufmann Publishers
Morgan Kaufmann Publishers
*
Chapter 4 — The Processor
*
Chapter 4 — The Processor
Chapter 4 — The Processor — *
Does Multiple Issue Work?
Yes, but not as much as we’d like
Programs have real dependencies that limit ILP
Some dependencies are hard to eliminate
e.g., pointer aliasing
Some parallelism is hard to expose
Limited window size during instruction issue
Memory delays and limited bandwidth
Hard to keep pipelines full
Speculation can help if done well
The BIG Picture
Chapter 4 — The Processor — *
Morgan Kaufmann Publishers
Morgan Kaufmann Publishers
*
Chapter 4 — The Processor
*
Chapter 4 — The Processor
© 2016 Elsevier, Inc. All rights reserved.
*
Specs of ARM Cortex-A53 and Intel Core i7 920
© 2016 Elsevier, Inc. All rights reserved.
© 2016 Elsevier, Inc. All rights reserved.
*
The Cortex A-53 Pipeline
© 2016 Elsevier, Inc. All rights reserved.
© 2016 Elsevier, Inc. All rights reserved.
*
CPI of ARM Cortex A-53 for SPEC2006 Integer
© 2016 Elsevier, Inc. All rights reserved.
Core i7 Pipeline
Chapter 4 — The Processor — *
Chapter 4 — The Processor — *
© 2016 Elsevier, Inc. All rights reserved.
*
CPI of Intel Core i7 920 for SPEC2006 Integer
© 2016 Elsevier, Inc. All rights reserved.
Print
Print
Print
Print