程序代写代做代考 mips CO101

CO101
Principle of Computer

Organization

Lecture 12: Pipelined MIPS
Processor 2

Liang Yanyan

澳門科技大學
Macau of University of Science and Technology

MIPS Pipeline Datapath Additions

• State registers between each pipeline stage to isolate them.

2

Value Propagation

• Data propagation
• Any data required in later stages must be propagated through

the pipeline register.

• E.g. data from R[rs], R[rt] must be propagated to the ALU
through the ID/EX register.

• E.g. for SW instruction, data from R[rt] must be propagated to
the memory through the ID/EX and EX/MEM registers.

• Register address propagation
• Propagate register address

• ID stage decodes the address of R[rd], this address must be
propagated to WB stage for writing data.

3

Need to propagate register address: example

• Decoding instruction add $t0, $t1, $t2

4

add $t0, $t1,
$t2

destination is
$t0 when
decoding

Need to propagate register address: example

• Wrong address when store the result of $t0

5

add $t0, $t1,
$t2

sub $s0, $s1,
$s2

destination is
$s0 when
decoding

result of $t0

Propagate register address

6
result of $t0

Example: ID

7

add $t0, $t1, $t2

$t0

Example: EX

8

add $t0, $t1, $t2

$t0

result

Example: MEM

9

add $t0, $t1, $t2

$t0

result

Example: WB

10

add $t0, $t1, $t2

$t0

result

add $s0, $s1, $s2

$s0

Propagation of control signals

• The control signals are generated in the same way as in
the single-cycle processor.
• After an instruction is fetched, the processor decodes it and

produces the appropriate control values in ID stage.

• Some control signals will not be used until later stages.
• These signals must be propagated through the pipeline until they

reach the appropriate stage.

• We can just propagate them using the pipeline registers,
along with the data.

11

MIPS Pipeline Control Path

• All control signals can be determined during Decode
• and held in the state registers between pipeline stages

12

Propagate control signals

13

Propagate control signals

14

lw $t1, 4($t2)

control
signals for lw

Propagate control signals

15

lw $t1, 4($t2)add $s0, $s1, $s2

control
signals for
add

control
signals for lw

Propagate control signals: W, M, E
• Not necessary to propagate all control signals from ID stage to

WB stage. As a control signal is only used in one stage.

16

Control signal usage: EX

• ALUsrc, ALUFunc, RegDst are only required (used) in
EX stage.

17

0

1

4

ALU

+

ALUSrc

ALUFunc

ID/EX

EX/MEM

E

M

W

M

W

0

1

RegDst

Control
Inst[31-26]

Pipeline Control

• IF Stage: read Instr Memory (always asserted) and write
PC (on System Clock)

• ID Stage: no optional control signals to set

18

An example of pipeline execution

• Assumptions:
• Each register contains a value which is equal to its register

address plus 100. For instance, register $8 contains 108,
register $29 contains 129, and so forth.

• All data memory locations contain a constant value 99.

19

Clock cycle

1 2 3 4 5 6 7 8 9

1000: lw $8,4($29) IF ID EX
ME
M

WB

1004: sub $2,$4,$5 IF ID EX
ME
M

WB

1008: and $9,$10,$11 IF ID EX
ME
M

WB

1012: or $16,$17,$18 IF ID EX
ME
M

WB

1016: add $13,$14,$10 IF ID EX
ME
M

WB

Cycle 1 (filling)

20

Cycle 2

21

Cycle 3

22

Cycle 4

23

Cycle 5 (full)

24

Cycle 6 (flushing)

25

Cycle 7

26

Cycle 8

27

Cycle 9

28

Summary
• Utilize capabilities of the datapath by pipelined

instruction processing.
• Different stages use distinct functional units.
• Multiple instructions are processed simultaneously.
• Potential speedup is equal to the number of pipeline stages.
• Performance limited by length of longest stage (plus fill/flush).

• Single cycle processor
• CPI = 1, long cycle time.

• Multi-cycle processor
• Multiple cycles to execute one instruction, shorter cycle time
• Throughput is 1/CPI, which is less than 1.

• Pipelined processor
• Each instruction takes multiple cycles, but multiple instructions

can be processed simultaneously.
• Shorter cycle time.
• Increased throughput, potential throughput is 1 (one inst. per

cycle).

29