2stage.ppt
0
1
Addr
Instruction
memory
Instr
Address
Write
data
Data
memory
Read
data 1
0
Extend
ALUSrc
Result
ALU
Instr [15 – 0]
RegDst
Read
register 1
Read
register 2
Write
register
Write data
Read
data 2
Read
data 1
Registers
Rd
0
1
4
P
C
Add
1
0
PCSrc
Add
Shift
left 2
Rt
Rs
opcode
funct Decoder
MemToReg
control
signals
PCSrc AND
BEQ
Write enable
PC
next_PC
PC_plus4
PC_target
RegWrite
imm
rd1_data
rd2_data
ALUOp
alu_out_data
zero
negative
MemRead
MemWrite
load_data
wr_data
inst