HD44780U (LCD-II)
(Dot Matrix Liquid Crystal Display Controller/Driver)
ADE-207-272(Z) ‘99.9 Rev. 0.0
Description
The HD44780U dot-matrix liquid crystal display controller and driver LSI displays alphanumerics, Japanese kana characters, and symbols. It can be configured to drive a dot-matrix liquid crystal display under the control of a 4- or 8-bit microprocessor. Since all the functions such as display RAM, character generator, and liquid crystal driver, required for driving a dot-matrix liquid crystal display are internally provided on one chip, a minimal system can be interfaced with this controller/driver.
A single HD44780U can display up to one 8-character line or two 8-character lines.
The HD44780U has pin function compatibility with the HD44780S which allows the user to easily replace an LCD-II with an HD44780U. The HD44780U character generator ROM is extended to generate 208 5 × 8 dot character fonts and 32 5 × 10 dot character fonts for a total of 240 different character fonts.
The low power supply (2.7V to 5.5V) of the HD44780U is suitable for any portable battery-driven product requiring low power dissipation.
Features
• 5 × 8 and 5 × 10 dot matrix possible
• Low power operation support:
2.7 to 5.5V
• Wide range of liquid crystal display driver power
3.0 to 11V
• Liquid crystal drive waveform
A (One line frequency AC waveform)
• Correspond to high speed MPU bus interface
2 MHz (when VCC = 5V)
• 4-bit or 8-bit MPU interface enabled
• 80 × 8-bit display RAM (80 characters max.)
• 9,920-bit character generator ROM for a total of 240 character fonts
208 character fonts (5 × 8 dot) 32 character fonts (5 × 10 dot)
1
HD44780U
• 64 × 8-bit character generator RAM 8 character fonts (5 × 8 dot)
4 character fonts (5 × 10 dot)
• 16-common × 40-segment liquid crystal display driver
• Programmable duty cycles
1/8 for one line of 5 × 8 dots with cursor 1/11 for one line of 5 × 10 dots with cursor 1/16 for two lines of 5 × 8 dots with cursor
• Wide range of instruction functions:
Display clear, cursor home, display on/off, cursor on/off, display character blink, cursor shift,
display shift
• Pin function compatibility with HD44780S
• Automatic reset circuit that initializes the controller/driver after power on
• Internal oscillator with external resistors
• Low power consumption
Ordering Information
Type No.
Package CGROM
HD44780UA00FS FP-80B HCD44780UA00 Chip HD44780UA00TF TFP-80F
HD44780UA02FS FP-80B HCD44780UA02 Chip HD44780UA02TF TFP-80F
HD44780UBxxFS FP-80B HCD44780UBxx Chip HD44780UBxxTF TFP-80F
Note: xx: ROM code No.
Japanese standard font
European standard font
Custom font
2
HD44780U
HD44780U Block Diagram
OSC1 OSC2
CL1 CL2 M
D
COM1 to COM16
SEG1 to SEG40
Reset circuit ACL
7
MPU inter- face
Input/ output buffer
8
16-bit shift register
Common signal driver
RS R/W E
DB4 to DB7
DB0 to DB3
7
Timing generator
CPG
Instruction register (IR)
Instruction decoder
Display data RAM (DDRAM) 80 × 8 bits
Address counter
40-bit shift register
40-bit latch circuit
Segment signal driver
8
Data register (DR)
7
8
7 8
88
5
5
Cursor and blink controller
LCD drive voltage selector
Character generator RAM (CGRAM) 64 bytes
Character generator ROM (CGROM) 9,920 bits
Parallel/serial converter and
attribute circuit
40
Busy flag
GND
VCC
V1 V2 V3 V4 V5
3
HD44780U
HD44780U Pin Arrangement (FP-80B)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
SEG22 SEG39 SEG21 SEG40 SEG20 COM16 SEG19 COM15 SEG18 COM14 SEG17 COM13 SEG16 COM12 SEG15 COM11 SEG14 COM10 SEG13 COM9 SEG12 COM8 SEG11 FP-80B COM7 SEG10 (Top view) COM6 SEG9 COM5 SEG8 COM4 SEG7 COM3 SEG6 COM2 SEG5 COM1
SEG4 DB7 SEG3 DB6 SEG2 DB5 SEG1 DB4
GND DB3 OSC1 DB2
4
OSC2 25 V1 26 V2 27 V3 28 V4 29 V5 30 CL1 31 CL2 32 VCC 33 M34 D35 RS 36 R/W 37 E38 DB0 39 DB1 40
80 SEG23 79 SEG24 78 SEG25 77 SEG26 76 SEG27 75 SEG28 74 SEG29 73 SEG30 72 SEG31 71 SEG32 70 SEG33 69 SEG34 68 SEG35 67 SEG36 66 SEG37 65 SEG38
HD44780U
HD44780U Pin Arrangement (TFP-80F)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
SEG20 COM16 SEG19 COM15 SEG18 COM14 SEG17 COM13 SEG16 COM12 SEG15 COM11 SEG14 COM10 SEG13 COM9 SEG12 COM8 SEG11 TFP-80F COM7 SEG10 (Top view) COM6 SEG9 COM5 SEG8 COM4 SEG7 COM3 SEG6 COM2 SEG5 COM1
SEG4 DB7 SEG3 DB6 SEG2 DB5
SEG1
DB4
5
GND 21 OSC1 22 OSC2 23
80 SEG21 79 SEG22 78 SEG23 77 SEG24 76 SEG25 75 SEG26 74 SEG27 73 SEG28 72 SEG29 71 SEG30 70 SEG31 69 SEG32 68 SEG33 67 SEG34 66 SEG35 65 SEG36 64 SEG37 63 SEG38 62 SEG39 61 SEG40
V1 24 V2 25 V3 26 V4 27 V5 28
CL1 29 CL2 30 VCC 31
M32 D33
RS 34 R/W 35 E36 DB0 37 DB1 38 DB2 39 DB3 40
HD44780U
HD44780U Pad Arrangement
2 1 80
63
Chip size: Coordinate: Origin:
Pad size:
4.90 × 4.90 mm2 Pad center (μm) Chip center
114 × 114 μm2
Type code
HD44780U
Y
23
42
X
6
HCD44780U Pad Location Coordinates
Pad No.
1 2 3 4 5 6 7 8 9
Function X (um)
SEG22 –2100 SEG21 –2280 SEG20 –2313 SEG19 –2313 SEG18 –2313 SEG17 –2313 SEG16 –2313 SEG15 –2313 SEG14 –2313 SEG13 –2313 SEG12 –2313 SEG11 –2313 SEG10 –2313 SEG9 –2313 SEG8 –2313 SEG7 –2313 SEG6 –2313 SEG5 –2313 SEG4 –2313 SEG3 –2313 SEG2 –2313 SEG1 –2313 GND –2280 OSC1 –2080 OSC2 –1749 V1 –1550 V2 –1268 V3 –941 V4 –623 V5 –304
Y (um)
2313
2313
2089
1833
1617
1401
1186
970
755
539
323
108
–108
–323
–539
–755
–970
–1186
–1401
–1617
–1833
–2073
–2290
–2290
–2290
–2290
–2290
–2290
–2290
–2290
–2290
–2290
–2290
–2290
–2290
–2290
–2290
–2290
–2290
–2290
Pad No.
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
Function
DB2 DB3 DB4 DB5 DB6 DB7 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 SEG40 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23
X (um)
2070
2260
2290
2290
2290
2290
2313
2313
2313
2313
2313
2313
2313
2313
2313
2313
2313
2313
2313
2313
2313
2313
2296
2100
1617
1401
1186
970
755
539
323
108
–108
–323
–539
–755
–970
–1186
–1401
–1617
Y (um)
–2290
–2290
–2099
–1883
–1667
–1452
–1186
–970
–755
–539
–323
–108
108
323
539
755
970
1186
1401
1617
1833
2095
2313
2313
2313
2313
2313
2313
2313
2313
2313
2313
2313
2313
2313
2313
2313
2313
2313
2313
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 CL1 32 CL2 33 VCC 34 M 35 D 36 RS 37 R/W 38 E 39 DB0
–48
142
309
475
665
832
1022
1204
1454
1684
40 DB1
Coordinate
Coordinate
HD44780U
7
HD44780U
Pin Functions
Signal
RS
R/W
E
DB4 to DB7
DB0 to DB3
CL1
CL2
M
D
COM1 to COM16
SEG1 to SEG40
V1 to V5
VCC, GND
OSC1, OSC2
No. of
Lines I/O
1 I
1 I
1 I
4 I/O
4 I/O
1 O
1 O
1 O
1 O
16 O
40 O
5 —
2 —
2 —
Device Interfaced with
MPU
MPU
MPU
MPU
MPU
Extension driver
Extension driver
Extension driver
Extension driver
LCD
LCD
Power supply
Power supply
Oscillation resistor clock
Function
Selects registers.
0: Instruction register (for write) Busy flag:
address counter (for read)
1: Data register (for write and read)
Selects read or write. 0: Write
1: Read
Starts data read/write.
Four high order bidirectional tristate data bus pins. Used for data transfer and receive between the MPU and the HD44780U. DB7 can be used as a busy flag.
Four low order bidirectional tristate data bus pins. Used for data transfer and receive between the MPU and the HD44780U.
These pins are not used during 4-bit operation.
Clock to latch serial data D sent to the extension driver
Clock to shift serial data D
Switch signal for converting the liquid crystal drive waveform to AC
Character pattern data corresponding to each segment signal
Common signals that are not used are changed to non-selection waveforms. COM9 to COM16 are non-selection waveforms at 1/8 duty factor and COM12 to COM16 are non-selection waveforms at 1/11 duty factor.
Segment signals
Power supply for LCD drive VCC –V5 = 11 V (max)
VCC: 2.7V to 5.5V, GND: 0V
When crystal oscillation is performed, a resistor must be connected externally. When the pin input is an external clock, it must be input to OSC1.
8
Function Description Registers
The HD44780U has two 8-bit registers, an instruction register (IR) and a data register (DR).
The IR stores instruction codes, such as display clear and cursor shift, and address information for display data RAM (DDRAM) and character generator RAM (CGRAM). The IR can only be written from the MPU.
The DR temporarily stores data to be written into DDRAM or CGRAM and temporarily stores data to be read from DDRAM or CGRAM. Data written into the DR from the MPU is automatically written into DDRAM or CGRAM by an internal operation. The DR is also used for data storage when reading data from DDRAM or CGRAM. When address information is written into the IR, data is read and then stored into the DR from DDRAM or CGRAM by an internal operation. Data transfer between the MPU is then completed when the MPU reads the DR. After the read, data in DDRAM or CGRAM at the next address is sent to the DR for the next read from the MPU. By the register selector (RS) signal, these two registers can be selected (Table 1).
Busy Flag (BF)
When the busy flag is 1, the HD44780U is in the internal operation mode, and the next instruction will not be accepted. When RS = 0 and R/W = 1 (Table 1), the busy flag is output to DB7. The next instruction must be written after ensuring that the busy flag is 0.
Address Counter (AC)
The address counter (AC) assigns addresses to both DDRAM and CGRAM. When an address of an instruction is written into the IR, the address information is sent from the IR to the AC. Selection of either DDRAM or CGRAM is also determined concurrently by the instruction.
After writing into (reading from) DDRAM or CGRAM, the AC is automatically incremented by 1 (decremented by 1). The AC contents are then output to DB0 to DB6 when RS = 0 and R/W = 1 (Table 1).
Table 1
Register Selection
RS R/W 0 0
0 1
1 0
1 1
Operation
IR write as an internal operation (display clear, etc.)
Read busy flag (DB7) and address counter (DB0 to DB6)
DR write as an internal operation (DR to DDRAM or CGRAM) DR read as an internal operation (DDRAM or CGRAM to DR)
HD44780U
9
HD44780U
Display Data RAM (DDRAM)
Display data RAM (DDRAM) stores display data represented in 8-bit character codes. Its extended capacity is 80 × 8 bits, or 80 characters. The area in display data RAM (DDRAM) that is not used for display can be used as general data RAM. See Figure 1 for the relationships between DDRAM addresses and positions on the liquid crystal display.
The DDRAM address (ADD) is set in the address counter (AC) as hexadecimal. • 1-line display (N = 0) (Figure 2)
When there are fewer than 80 display characters, the display begins at the head position. For example, if using only the HD44780, 8 characters are displayed. See Figure 3.
When the display shift operation is performed, the DDRAM address shifts. See Figure 3.
Figure 1 DDRAM Address
Figure 2 1-Line Display
High order Low order
bits bits Example: DDRAM address 4E
1
0
0
1
1
1
0
AC6
AC5
AC4
AC3
AC2
AC1
AC0
AC (hexadecimal)
Display position (digit)
DDRAM address (hexadecimal)
1 2 3 4 5
79 80
00
01
02
03
04
. ……………..
4E
4F
Display
position 1 2 3 4 5 6 7 8
DDRAM address
For shift left
For
shift right
00
01
02
03
04
05
06
07
01
02
03
04
05
06
07
08
4F
00
01
02
03
04
05
06
Figure 3 1-Line by 8-Character Display Example
10
• 2-line display (N = 1) (Figure 4)
Case 1: When the number of display characters is less than 40 × 2 lines, the two lines are displayed
from the head. Note that the first line end address and the second line start address are not consecutive. For example, when just the HD44780 is used, 8 characters × 2 lines are displayed. See Figure 5.
When display shift operation is performed, the DDRAM address shifts. See Figure 5.
Figure 4 2-Line Display
Figure 5 2-Line by 8-Character Display Example
HD44780U
Display
position 1 2 3 4 5 39 40
DDRAM address (hexadecimal)
00
01
02
03
04
. ……………..
26
27
40
41
42
43
44
. ……………..
66
67
Display
position 1 2 3 4 5 6 7 8
DDRAM address
For shift left
For
shift right
00
01
02
03
04
05
06
07
40
41
42
43
44
45
46
47
01
02
03
04
05
06
07
08
41
42
43
44
45
46
47
48
27
00
01
02
03
04
05
06
67
40
41
42
43
44
45
46
11
HD44780U
Case 2: For a 16-character × 2-line display, the HD44780 can be extended using one 40-output extension driver. See Figure 6.
When display shift operation is performed, the DDRAM address shifts. See Figure 6.
Display
position 1 2 3 4 5 6 7 8 9 10111213141516
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
DDRAM address
For shift left
For
shift right
HD44780U display
Extension driver display
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
27
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
67
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
Figure 6 2-Line by 16-Character Display Example
12
HD44780U
Character Generator ROM (CGROM)
The character generator ROM generates 5 × 8 dot or 5 × 10 dot character patterns from 8-bit character codes (Table 4). It can generate 208 5 × 8 dot character patterns and 32 5 × 10 dot character patterns. User- defined character patterns are also available by mask-programmed ROM.
Character Generator RAM (CGRAM)
In the character generator RAM, the user can rewrite character patterns by program. For 5 × 8 dots, eight character patterns can be written, and for 5 × 10 dots, four character patterns can be written.
Write into DDRAM the character codes at the addresses shown as the left column of Table 4 to show the character patterns stored in CGRAM.
See Table 5 for the relationship between CGRAM addresses and data and display patterns. Areas that are not used for display can be used as general data RAM.
Modifying Character Patterns
• Character pattern development procedure
The following operations correspond to the numbers listed in Figure 7:
1. Determine the correspondence between character codes and character patterns.
2. Create a listing indicating the correspondence between EPROM addresses and data.
3. Program the character patterns into the EPROM.
4. Send the EPROM to Hitachi.
5. Computer processing on the EPROM is performed at Hitachi to create a character pattern listing, which
is sent to the user.
6. If there are no problems within the character pattern listing, a trial LSI is created at Hitachi and samples are sent to the user for evaluation. When it is confirmed by the user that the character patterns are correctly written, mass production of the LSI proceeds at Hitachi.
13
HD44780U
Hitachi User
Start
Computer processing
Determine character patterns
1
Create character pattern listing
Create EPROM address data listing
52
Write EPROM
EPROM → Hitachi
No
Evaluate character patterns
OK? Yes
M/T
3
4
Art work
Masking
Trial
Sample
Sample evaluation
OK?
Yes
Mass production
6
No
Note: For a description of the numbers used in this figure, refer to the preceding page.
Figure 7 Character Pattern Development Procedure
14
• Programming character patterns
This section explains the correspondence between addresses and data used to program character patterns
in EPROM. The HD44780U character generator ROM can generate 208 5 × 8 dot character patterns and 32 5 × 10 dot character patterns for a total of 240 different character patterns.
Character patterns
EPROM address data and character pattern data correspond with each other to form a 5 × 8 or 5 × 10 dot character pattern (Tables 2 and 3).
Table 2
Example of Correspondence between EPROM Address Data and Character Pattern (5 × 8 Dots)
HD44780U
EPROM Address
A11A10A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
0000 0001 0010 0011 0100 0101 0110 0111
1
1
1 11 1
1 1111
Data
LSB O4 O3 O2 O1 O0
0000 0000 00
11
01100010
1000 1001 1010 1011 1100 1101 1110 1111
00 000 000
00000
00000 00000 00000 00000 00000 00000 00000 00000
1 1 1
0
EPROM addresses A11 to A4 correspond to a character code.
Cursor position
Character code
Line position
Notes: 1.
2. EPROM addresses A3 to A0 specify a line position of the character pattern.
3. EPROM data O4 to O0 correspond to character pattern data.
4. EPROM data O5 to O7 must be specified as 0.
5. A lit display position (black) corresponds to a 1.
6. Line 9 and the following lines must be blanked with 0s for a 5 × 8 dot character fonts.
15
HD44780U
Handling unused character patterns
1. EPROM data outside the character pattern area: Always input 0s.
2. EPROM data in CGRAM area: Always input 0s. (Input 0s to EPROM addresses 00H to FFH.)
3. EPROM data used when the user does not use any HD44780U character pattern: According to the user
application, handled in one of the two ways listed as follows.
a. When unused character patterns are not programmed: If an unused character code is written into DDRAM, all its dots are lit. By not programing a character pattern, all of its bits become lit. (This is due to the EPROM being filled with 1s after it is erased.)
b. When unused character patterns are programmed as 0s: Nothing is displayed even if unused character codes are written into DDRAM. (This is equivalent to a space.)
Table 3
Example of Correspondence between EPROM Address Data and Character Pattern (5 × 10 Dots)
01010010
EPROM Address
A11A10A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
1010 1011 1100 1101 1110 1111
1 1 1
Data
LSB
O4 O3 O2 O1 O0
0000
0001 0010 0011 0100 0101
0110 0111 1000 1001
00000 00000 00
11
1 11 1 1 1111 1 1 1
00 000 000
0 0000 0000 0000
00000 00000 00000 00000 00000 00000
EPROM addresses A11 to A3 correspond to a character code.
Cursor position
Character code
Line position
Notes: 1.
2. EPROM addresses A3 to A0 specify a line position of the character pattern.
3. EPROM data O4 to O0 correspond to character pattern data.
4. EPROM data O5 to O7 must be specified as 0.
5. A lit display position (black) corresponds to a 1.
6. Line 11 and the following lines must be blanked with 0s for a 5 × 10 dot character fonts.
16
Table 4 Correspondence between Character Codes and Character Patterns (ROM Code: A00)
Upper 4
Lower Bits 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 4 Bits
CG RAM
xxxx0000 (1)
xxxx0001 (2)
xxxx0010 (3)
xxxx0011 (4)
xxxx0100 (5)
(6)
xxxx0110 (7)
(8)
xxxx1000 (1)
xxxx1001 (2)
(3)
xxxx1011 (4)
(5)
xxxx1101 (6)
xxxx1110 (7)
xxxx1111 (8)
Note: The user can specify any pattern for character-generator RAM.
xxxx0101
xxxx0111
xxxx1010
xxxx1100
HD44780U
17
HD44780U
Table 4 Correspondence between Character Codes and Character Patterns (ROM Code: A02)
Lower 4 Bits
Upper 4
Bits 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
CG
xxxx0000 RAM (1)
xxxx0001 (2)
xxxx0010 (3)
xxxx0011 (4)
xxxx0100 (5)
(6)
xxxx0110 (7)
(8)
xxxx1000 (1)
xxxx1001 (2)
(3)
xxxx1011 (4)
(5)
xxxx1101 (6)
xxxx1110 (7)
xxxx1111 (8)
xxxx0101
xxxx0111
xxxx1010
xxxx1100
18
HD44780U
Table 5 Relationship between CGRAM Addresses, Character Codes (DDRAM) and Character Patterns (CGRAM Data)
For 5 × 8 dot character patterns Character Codes
(DDRAM data)
76543210 High Low
0000*000
0000*001
0000*111 111
Character Patterns (CGRAM data)
CGRAM Address
543210 High Low
000 001 010 011 100 101 110 111
76543210 High Low
***
***
1111 1
1 1111 11
1 1
000
00
000 000
0
00 000
00000
0 00 0
0
1 1
001
000 001 010 011 100 101 110 111
***
***
1
1
1
000 0
1
0
00 00 00 00 00000
00
0
11 11111 1 11111 1
1
Character pattern (1)
Cursor position
Character pattern (2)
Cursor position
000 001
100 101 110 111
***
***
Notes: 1.
2. CGRAM address bits 0 to 2 designate the character pattern line position. The 8th line is the
cursor position and its display is formed by a logical OR with the cursor.
Maintain the 8th line data, corresponding to the cursor display position, at 0 as the cursor display. If the 8th line data is 1, 1 bits will light up the 8th line regardless of the cursor presence.
3. Character pattern row positions correspond to CGRAM data bits 0 to 4 (bit 4 being at the left).
4. As shown Table 5, CGRAM character patterns are selected when character code bits 4 to 7 are
all 0. However, since character code bit 3 has no effect, the R display example above can be
selected by either character code 00H or 08H.
5. 1 for CGRAM data corresponds to display selection and 0 to non-selection.
* Indicates no effect.
Character code bits 0 to 2 correspond to CGRAM address bits 3 to 5 (3 bits: 8 types).
19
HD44780U
Table 5 Relationship between CGRAM Addresses, Character Codes (DDRAM) and Character Patterns (CGRAM Data) (cont)
For 5 × 10 dot character patterns Character Codes
CGRAM Address
Character Patterns (CGRAM data)
76543210
(DDRAM data)
76543210 High Low
0000*00*
High
Low
543210 High Low
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010
***
00000 00000 00
00
1011 1100 1101 1110 1111
***
***
***
1
11
1
1 1111 1
1
1
11
00 000 000
1 1 1
0 0000 0000 0000 0 0 0 0 *****
*****
Character pattern
Cursor position
0
0000 *** 0001
0000*11* 111001
1010 ***
1011 ******** 1100
1101
1110
1111 ********
Notes:
1. Character code bits 1 and 2 correspond to CGRAM address bits 4 and 5 (2 bits: 4 types).
2. CGRAM address bits 0 to 3 designate the character pattern line position. The 11th line is the
cursor position and its display is formed by a logical OR with the cursor.
Maintain the 11th line data corresponding to the cursor display positon at 0 as the cursor display. If the 11th line data is “1”, “1” bits will light up the 11th line regardless of the cursor presence. Since lines 12 to 16 are not used for display, they can be used for general data RAM.
3. Character pattern row positions are the same as 5 × 8 dot character pattern positions. 4. CGRAM character patterns are selected when character code bits 4 to 7 are all 0.
However, since character code bits 0 and 3 have no effect, the P display example above can be selected by character codes 00H, 01H, 08H, and 09H.
5. 1 for CGRAM data corresponds to display selection and 0 to non-selection. * Indicates no effect.
20
Timing Generation Circuit
The timing generation circuit generates timing signals for the operation of internal circuits such as DDRAM, CGROM and CGRAM. RAM read timing for display and internal operation timing by MPU access are generated separately to avoid interfering with each other. Therefore, when writing data to DDRAM, for example, there will be no undesirable interferences, such as flickering, in areas other than the display area.
Liquid Crystal Display Driver Circuit
The liquid crystal display driver circuit consists of 16 common signal drivers and 40 segment signal drivers. When the character font and number of lines are selected by a program, the required common signal drivers automatically output drive waveforms, while the other common signal drivers continue to output non-selection waveforms.
Sending serial data always starts at the display data character pattern corresponding to the last address of the display data RAM (DDRAM).
Since serial data is latched when the display data character pattern corresponding to the starting address enters the internal shift register, the HD44780U drives from the head display.
Cursor/Blink Control Circuit
The cursor/blink control circuit generates the cursor or character blinking. The cursor or the blinking will appear with the digit located at the display data RAM (DDRAM) address set in the address counter (AC).
For example (Figure 8), when the address counter is 08H, the cursor position is displayed at DDRAM address 08H.
Figure 8 Cursor/Blink Display Example
HD44780U
For a 1-line display Display position
DDRAM address (hexadecimal)
For a 2-line display Display position
DDRAM address (hexadecimal)
1 2 3 4 5 6 7 8 9 10 11 00 01 02 03 04 05 06 07 08 09 0A
cursor position
1 2 3 4 5 6 7 8 9 10 11 00 01 02 03 04 05 06 07 08 09 0A 40 41 42 43 44 45 46 47 48 49 4A
cursor position
AC6 AC5 AC4 AC3 AC2 AC1 AC0
AC
0
0
0
1
0
0
0
Note:
The cursor or blinking appears when the address counter (AC) selects the character
generator RAM (CGRAM). However, the cursor and blinking become meaningless.
The cursor or blinking is displayed in the meaningless position when the AC is a CGRAM address.
21
HD44780U
Interfacing to the MPU
The HD44780U can send data in either two 4-bit operations or one 8-bit operation, thus allowing interfacing with 4- or 8-bit MPUs.
• For 4-bit interface data, only four bus lines (DB4 to DB7) are used for transfer. Bus lines DB0 to DB3 are disabled. The data transfer between the HD44780U and the MPU is completed after the 4-bit data has been transferred twice. As for the order of data transfer, the four high order bits (for 8-bit operation, DB4 to DB7) are transferred before the four low order bits (for 8-bit operation, DB0 to DB3).
The busy flag must be checked (one instruction) after the 4-bit data has been transferred twice. Two more 4-bit operations then transfer the busy flag and address counter data.
• For 8-bit interface data, all eight bus lines (DB0 to DB7) are used.
RS R/W E
DB7 DB6 DB5 DB4
IR7 IR3 IR6 IR2 IR5 IR1 IR4 IR0
Instruction register (IR) write
BF AC3
AC6 AC2
AC5 AC1
AC4 AC0
Busy flag (BF) and address counter (AC) read
DR7 DR3 DR6 DR2 DR5 DR1 DR4 DR0
Data register (DR) read
Figure 9 4-Bit Transfer Example
22
HD44780U
Reset Function
Initializing by Internal Reset Circuit
An internal reset circuit automatically initializes the HD44780U when the power is turned on. The following instructions are executed during the initialization. The busy flag (BF) is kept in the busy state until the initialization ends (BF = 1). The busy state lasts for 10 ms after VCC rises to 4.5 V.
1. Display clear
2. Function set:
DL = 1; 8-bit interface data
N = 0; 1-line display
F = 0; 5 × 8 dot character font
3. Display on/off control: D = 0; Display off
C = 0; Cursor off
B = 0; Blinking off
4. Entry mode set:
I/D = 1; Increment by 1 S = 0; No shift
Note: If the electrical characteristics conditions listed under the table Power Supply Conditions Using Internal Reset Circuit are not met, the internal reset circuit will not operate normally and will fail to initialize the HD44780U. For such a case, initial-ization must be performed by the MPU as explained in the section, Initializing by Instruction.
Instructions Outline
Only the instruction register (IR) and the data register (DR) of the HD44780U can be controlled by the MPU. Before starting the internal operation of the HD44780U, control information is temporarily stored into these registers to allow interfacing with various MPUs, which operate at different speeds, or various peripheral control devices. The internal operation of the HD44780U is determined by signals sent from the MPU. These signals, which include register selection signal (RS), read/
write signal (R/W), and the data bus (DB0 to DB7), make up the HD44780U instructions (Table 6). There are four categories of instructions that:
• Designate HD44780U functions, such as display format, data length, etc.
• Set internal RAM addresses
• Perform data transfer with internal RAM
• Perform miscellaneous functions
23
HD44780U
Normally, instructions that perform data transfer with internal RAM are used the most. However, auto- incrementation by 1 (or auto-decrementation by 1) of internal HD44780U RAM addresses after each data write can lighten the program load of the MPU. Since the display shift instruction (Table 11) can perform concurrently with display data write, the user can minimize system development time with maximum programming efficiency.
When an instruction is being executed for internal operation, no instruction other than the busy flag/address read instruction can be executed.
Because the busy flag is set to 1 while an instruction is being executed, check it to make sure it is 0 before sending another instruction from the MPU.
Note:
Table 6
Be sure the HD44780U is not in the busy state (BF = 0) before sending an instruction from the MPU to the HD44780U. If an instruction is sent without checking the busy flag, the time between the first instruction and next instruction will take much longer than the instruction time itself. Refer to Table 6 for the list of each instruc-tion execution time.
Instructions
Code
Instruction RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Description
Execution Time (max) (when fcp or
fOSC is 270 kHz)
1.52 ms
37 μs
37 μs
37 μs
37 μs
37 μs
37 μs
0 μs
Clear 0 0 display
Return 0 0 home
Entry 0 0 mode set
Display 0 0 on/off
control
Cursor or 0 0 display
shift
Function 0 0 set
Set 0 0 CGRAM
address
Set 0 0 DDRAM
address
Read busy 0 1 flag &
address
0 0
0 0
0 0
0 0
0 0
0 0
0 1
1 ADD
BF AC
0 0
0 0
0 0
0 0
0 1
0 0
0 0
0 1
1 D
S/C R/L
0 1
1 —
I/D S
C B
— —
— —
ACG ACG
ADD ADD
AC AC
Clears entire display and sets DDRAM address 0 in address counter.
Sets DDRAM address 0 in address counter. Also returns display from being shifted to original position. DDRAM contents remain unchanged.
Sets cursor move direction and specifies display shift. These operations are performed during data write and read.
Sets entire display (D) on/off, cursor on/off (C), and blinking of cursor position character (B).
Moves cursor and shifts display without changing DDRAM contents.
Sets interface data length (DL), number of display lines (N), and character font (F).
Sets CGRAM address. CGRAM data is sent and received after this setting.
Sets DDRAM address. DDRAM data is sent and received after this setting.
Reads busy flag (BF) indicating internal operation is being performed and reads address counter contents.
1 DLN F
ACG ACG ACG ACG
ADD ADD ADD ADD
AC AC
AC AC
24
HD44780U
Table 6 Instructions (cont)
Instruction RS
Code
R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Description
Execution Time (max) (when fcp or fOSC is 270 kHz)
37 μs
tADD = 4 μs*
37 μs
tADD = 4 μs*
Execution time changes when frequency changes Example:
When fcp or fOSC is 250 kHz,
37 μs × 270 = 40 μs 250
Write data to CG or DDRAM
Read data from CG or DDRAM
1 0
1 1
I/D = 1: I/D = 0: S =1: S/C = 1: S/C = 0: R/L = 1: R/L = 0: DL = 1: N =1: F =1: BF = 1: BF = 0:
Write data
Read data
Increment
Decrement
Accompanies display shift Display shift
Cursor move
Shift to the right
Shift to the left
8 bits, DL = 0:
2 lines, N = 0:
5 × 10 dots, F = 0: 5 × 8 dots Internally operating Instructions acceptable
Writes data into DDRAM or CGRAM.
Reads data from DDRAM or CGRAM.
DDRAM: Display data RAM CGRAM: Character generator
RAM
ACG: CGRAM address
ADD: DDRAM address (corresponds to cursor address)
AC: Address counter used for both DD and CGRAM addresses
4 bits 1 line
Note: — *
indicates no effect.
After execution of the CGRAM/DDRAM data write or read instruction, the RAM address counter is incremented or decremented by 1. The RAM address counter is updated after the busy flag turns off. In Figure 10, tADD is the time elapsed after the busy flag turns off until the address counter is updated.
Busy signal (DB7 pin)
Address counter (DB0 to DB6 pins)
Busy state
Note: t ADD depends on the operation frequency t ADD = 1.5/(f cp or f OSC ) seconds
A
A +1
tADD
Figure 10 Address Counter Update
25
HD44780U
Instruction Description Clear Display
Clear display writes space code 20H (character pattern for character code 20H must be a blank pattern) into all DDRAM addresses. It then sets DDRAM address 0 into the address counter, and returns the display to its original status if it was shifted. In other words, the display disappears and the cursor or blinking goes to the left edge of the display (in the first line if 2 lines are displayed). It also sets I/D to 1 (increment mode) in entry mode. S of entry mode does not change.
Return Home
Return home sets DDRAM address 0 into the address counter, and returns the display to its original status if it was shifted. The DDRAM contents do not change.
The cursor or blinking go to the left edge of the display (in the first line if 2 lines are displayed).
Entry Mode Set
I/D: Increments (I/D = 1) or decrements (I/D = 0) the DDRAM address by 1 when a character code is
written into or read from DDRAM.
The cursor or blinking moves to the right when incremented by 1 and to the left when decremented by 1. The same applies to writing and reading of CGRAM.
S: Shifts the entire display either to the right (I/D = 0) or to the left (I/D = 1) when S is 1. The display does not shift if S is 0.
If S is 1, it will seem as if the cursor does not move but the display does. The display does not shift when reading from DDRAM. Also, writing into or reading out from CGRAM does not shift the display.
Display On/Off Control
D: The display is on when D is 1 and off when D is 0. When off, the display data remains in DDRAM, but
can be displayed instantly by setting D to 1.
C: The cursor is displayed when C is 1 and not displayed when C is 0. Even if the cursor disappears, the function of I/D or other specifications will not change during display data write. The cursor is displayed using 5 dots in the 8th line for 5 × 8 dot character font selection and in the 11th line for the 5 × 10 dot character font selection (Figure 13).
B: The character indicated by the cursor blinks when B is 1 (Figure 13). The blinking is displayed as switching between all blank dots and displayed characters at a speed of 409.6-ms intervals when fcp or fOSC is 250 kHz. The cursor and blinking can be set to display simultaneously. (The blinking frequency changes according to fOSC or the reciprocal of fcp. For example, when fcp is 270 kHz, 409.6 × 250/270 = 379.2 ms.)
26
HD44780U
Cursor or Display Shift
Cursor or display shift shifts the cursor position or display to the right or left without writing or reading display data (Table 7). This function is used to correct or search the display. In a 2-line display, the cursor moves to the second line when it passes the 40th digit of the first line. Note that the first and second line displays will shift at the same time.
When the displayed data is shifted repeatedly each line moves only horizontally. The second line display does not shift into the first line position.
The address counter (AC) contents will not change if the only action performed is a display shift.
Function Set
DL: Sets the interface data length. Data is sent or received in 8-bit lengths (DB7 to DB0) when DL is 1, and in 4-bit lengths (DB7 to DB4) when DL is 0.When 4-bit length is selected, data must be sent or received twice.
N: Sets the number of display lines.
F: Sets the character font.
Note: Perform the function at the head of the program before executing any instructions (except for the read busy flag and address instruction). From this point, the function set instruction cannot be executed unless the interface data length is changed.
Set CGRAM Address
Set CGRAM address sets the CGRAM address binary AAAAAA into the address counter. Data is then written to or read from the MPU for CGRAM.
27
HD44780U
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
0
0
0
0
0
0
1
Clear display
Return home
Entry mode set
Display on/off control
Cursor or display shift
Code
Code
Code
Code
Code
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Higher Lower order bit order bit
Note: * Don’t care.
0
0
0
0
0
0
0
0
1
*
0
0
0
0
0
0
0
1
I/D
S
0
0
0
0
0
0
1
D
C
B
0
0
0
0
0
1
S/C
R/L
*
*
Function set Code
Note: * Don’t care.
0
0
0
0
1
DL
N
F
*
*
0
0
0
1
A
A
A
A
A
A
Set CGRAM address
Code
Figure 11 Instruction (1)
28
Set DDRAM Address
Set DDRAM address sets the DDRAM address binary AAAAAAA into the address counter. Data is then written to or read from the MPU for DDRAM.
However, when N is 0 (1-line display), AAAAAAA can be 00H to 4FH. When N is 1 (2-line display), AAAAAAA can be 00H to 27H for the first line, and 40H to 67H for the second line.
Read Busy Flag and Address
Read busy flag and address reads the busy flag (BF) indicating that the system is now internally operating on a previously received instruction. If BF is 1, the internal operation is in progress. The next instruction will not be accepted until BF is reset to 0. Check the BF status before the next write operation. At the same time, the value of the address counter in binary AAAAAAA is read out. This address counter is used by both CG and DDRAM addresses, and its value is determined by the previous instruction. The address contents are the same as for instructions set CGRAM address and set DDRAM address.
Table 7
S/C
0
0
1
1
Table 8
N F
0 0
0 1
1 *
Note:
Shift Function
R/L
HD44780U
0
1
0
1
Shifts the cursor position to the left. (AC is decremented by one.)
Shifts the cursor position to the right. (AC is incremented by one.)
Shifts the entire display to the left. The cursor follows the display shift.
Shifts the entire display to the right. The cursor follows the display shift.
Function Set
No. of
Display
Lines Character Font
Duty
Factor Remarks
1 5 × 8 dots 1/8
1 5 × 10 dots 1/11
2 5 × 8 dots Indicates don’t care.
1/16 Cannot display two lines for 5 × 10 dot character font
*
29
HD44780U
Cursor
5 × 8 dot 5 × 10 dot Alternating display character font character font
Cursor display example Blink display example
Figure 12 Cursor and Blinking
0
0
1
A
A
A
A
A
A
A
Set DDRAM address
Read busy flag and address
Code
Code
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Higher Lower order bit order bit
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Higher Lower order bit order bit
0
1
BF
A
A
A
A
A
A
A
Figure 13 Instruction (2)
30
Write Data to CG or DDRAM
Write data to CG or DDRAM writes 8-bit binary data DDDDDDDD to CG or DDRAM.
To write into CG or DDRAM is determined by the previous specification of the CGRAM or DDRAM address setting. After a write, the address is automatically incremented or decremented by 1 according to the entry mode. The entry mode also determines the display shift.
Read Data from CG or DDRAM
Read data from CG or DDRAM reads 8-bit binary data DDDDDDDD from CG or DDRAM.
The previous designation determines whether CG or DDRAM is to be read. Before entering this read instruction, either CGRAM or DDRAM address set instruction must be executed. If not executed, the first read data will be invalid. When serially executing read instructions, the next address data is normally read from the second read. The address set instructions need not be executed just before this read instruction when shifting the cursor by the cursor shift instruction (when reading out DDRAM). The operation of the cursor shift instruction is the same as the set DDRAM address instruction.
After a read, the entry mode automatically increases or decreases the address by 1. However, display shift is not executed regardless of the entry mode.
Note:
The address counter (AC) is automatically incremented or decremented by 1 after the write instructions to CGRAM or DDRAM are executed. The RAM data selected by the AC cannot be read out at this time even if read instructions are executed. Therefore, to correctly read data, execute either the address set instruction or cursor shift instruction (only with DDRAM), then just before reading the desired data, execute the read instruction from the second time the read instruction is sent.
Figure 14 Instruction (3)
HD44780U
1
0
D
D
D
D
D
D
D
D
Write data to CG or DDRAM
Read data from CG or DDRAM
Code
Code
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Higher Lower order bits order bits
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Higher Lower order bits order bits
1
1
D
D
D
D
D
D
D
D
31
HD44780U
Interfacing the HD44780U Interface to MPUs
• Interfacing to an 8-bit MPU
See Figure 16 for an example of using a I/O port (for a single-chip microcomputer) as an interface
device.
In this example, P30 to P37 are connected to the data bus DB0 to DB7, and P75 to P77 are connected to
E, R/W, and RS, respectively.
RS R/W
E
Internal operation
DB7 Data Instruction
write
Functioning
Busy
Busy flag check
Busy
Busy flag check
Not busy
Busy flag check
Data
Instruction write
Figure 15 Example of Busy Flag Check Timing Sequence
H8/325 HD44780U
8 16
40
LCD
P30 to P37
P77 P76 P75
DB0 to DB7
E RS R/W
COM1 to
COM16
SEG1 to SEG40
Figure 16 H8/325 Interface (Single-Chip Mode)
32
• Interfacing to a 4-bit MPU
The HD44780U can be connected to the I/O port of a 4-bit MPU. If the I/O port has enough bits, 8-bit
data can be transferred. Otherwise, one data transfer must be made in two operations for 4-bit data. In this case, the timing sequence becomes somewhat complex. (See Figure 17.)
See Figure 18 for an interface example to the HMCS4019R.
Note that two cycles are needed for the busy flag check as well as for the data transfer. The 4-bit operation is selected by the program.
Figure 18 Example of Interface to HMCS4019R
HD44780U
RS R/W E
Internal operation
DB7 IR7 IR3
Instruction write
Functioning
Busy AC3
Busy flag check
Not
busy AC3
Busy flag check
D7 D3
Instruction write
Note: IR7 , IR3 are the 7th and 3rd bits of the instruction. AC3 is the 3rd bit of the address counter.
Figure 17 Example of 4-Bit Data Transfer Timing Sequence
HMCS4019R HD44780
D15 D14 D13
R10 to R13
4
RS R/W E
DB4 to DB7
COM1 to COM16
SEG1 to SEG40
16
40
LCD
33
HD44780U
Interface to Liquid Crystal Display
Character Font and Number of Lines: The HD44780U can perform two types of displays, 5 × 8 dot and
5 × 10 dot character fonts, each with a cursor.
Up to two lines are displayed for 5 × 8 dots and one line for 5 × 10 dots. Therefore, a total of three types of common signals are available (Table 9).
The number of lines and font types can be selected by the program. (See Table 6, Instructions.) Connection to HD44780 and Liquid Crystal Display: See Figure 19 for the connection examples. Table 9 Common Signals
Number of Lines
1
1
2
Character Font
5 × 8 dots + cursor
5 × 10 dots + cursor
5 × 8 dots + cursor
Number of Common Signals
8
11
16
Duty Factor
1/8
1/11
1/16
HD44780
Example of a 5 × 8 dot, 8-character × 1-line display (1/4 bias, 1/8 duty cycle) HD44780
COM1
COM8 SEG1
SEG40
COM1
COM11
SEG1
SEG40
Example of a 5 × 10 dot, 8-character × 1-line display (1/4 bias, 1/11 duty cycle)
Figure 19 Liquid Crystal Display and HD44780 Connections
34
Since five segment signal lines can display one digit, one HD44780U can display up to 8 digits for a 1-line display and 16 digits for a 2-line display.
The examples in Figure 19 have unused common signal pins, which always output non-selection waveforms. When the liquid crystal display panel has unused extra scanning lines, connect the extra scanning lines to these common signal pins to avoid any undesirable effects due to crosstalk during the floating state.
HD44780U
HD44780
COM1
COM8 COM9
COM16
SEG1
SEG40
Example of a 5 × 8 dot, 8-character × 2-line display (1/5 bias, 1/16 duty cycle)
Figure 19 Liquid Crystal Display and HD44780 Connections (cont)
35
HD44780U
Connection of Changed Matrix Layout: In the preceding examples, the number of lines correspond to the scanning lines. However, the following display examples (Figure 20) are made possible by altering the matrix layout of the liquid crystal display panel. In either case, the only change is the layout. The display characteristics and the number of liquid crystal display characters depend on the number of common signals or on duty factor. Note that the display data RAM (DDRAM) addresses for 4 characters × 2 lines and for 16 characters × 1 line are the same as in Figure 19.
HD44780
COM1
COM8
SEG1
SEG40 COM9
COM16
5 × 8 dot, 16-character × 1-line display (1/5 bias, 1/16 duty cycle)
Figure 20 Changed Matrix Layout Displays
36
Various voltage levels must be applied to pins V1 to V5 of the HD44780U to obtain the liquid crystal display drive waveforms. The voltages must be changed according to the duty factor (Table 10).
VLCD is the peak value for the liquid crystal display drive waveforms, and resistance dividing provides voltages V1 to V5 (Figure 21).
Table 10 Duty Factor and Power Supply for Liquid Crystal Display Drive
HD44780U
Power Supply for Liquid Crystal Display Drive
Power Supply
V1
V2
V3
V4
V5
1/8, 1/11
1/4
VCC–1/4 VLCD
VCC–1/2 VLCD
VCC–1/2 VLCD
VCC–3/4 VLCD
VCC–VLCD
Duty Factor 1/16 Bias
1/5
VCC–1/5 VLCD
VCC–2/5 VLCD
VCC–3/5 VLCD
VCC–4/5 VLCD
VCC–VLCD
VCC (+5 V)
R R R R
VR –5 V
VLCD
VCC (+5 V)
R
R
R VLCD
R R
VR –5 V
VCC
V1 V2
V3 V4
V5
VCC V1
V2 V3 V4 V5
1/4 bias
(1/8, 1/11 duty cycle)
1/5 bias
(1/16, duty cycle)
Figure 21 Drive Voltage Supply Example
37
HD44780U
Relationship between Oscillation Frequency and Liquid Crystal Display Frame Frequency
The liquid crystal display frame frequencies of Figure 22 apply only when the oscillation frequency is 270 kHz (one clock pulse of 3.7 μs).
1/8 duty cycle
COM1
VCC
V1
V2 (V3) V4
V5
400 clocks
234 812
1
1 frame = 3.7 μs × 400 × 8 = 11850 μs = 11.9 ms
Frame frequency =
1/11 duty cycle
COM1
VCC
V1
V2 (V3) V4
V5
1 11.9 ms
= 84.3 Hz
1 frame
400 clocks
2 3 4
1 frame
11 1 2
1
1 frame = 3.7 μs × 400 × 11 = 16300 μs = 16.3 ms
Frame frequency =
1/16 duty cycle
COM1
VCC V1 V2 V3 V4 V5
1 16.3 ms
= 61.4 Hz
200 clocks
2 3 4
1 frame
16 1 2
1
1 frame = 3.7 μs × 200 × 16 = 11850 μs = 11.9 ms
Frame frequency =
1 11.9 ms
= 84.3 Hz
Figure 22 Frame Frequency
38
HD44780U
Instruction and Display Correspondence
• 8-bit operation, 8-digit × 1-line display with internal reset
Refer to Table 11 for an example of an 8-digit × 1-line display in 8-bit operation. The HD44780U
functions must be set by the function set instruction prior to the display. Since the display data RAM can store data for 80 characters, as explained before, the RAM can be used for displays such as for advertising when combined with the display shift operation.
Since the display shift operation changes only the display position with DDRAM contents unchanged, the first display data entered into DDRAM can be output when the return home operation is performed.
• 4-bit operation, 8-digit × 1-line display with internal reset
The program must set all functions prior to the 4-bit operation (Table 12). When the power is turned on,
8-bit operation is automatically selected and the first write is performed as an 8-bit operation. Since DB0 to DB3 are not connected, a rewrite is then required. However, since one operation is completed in two accesses for 4-bit operation, a rewrite is needed to set the functions (see Table 12). Thus, DB4 to DB7 of the function set instruction is written twice.
• 8-bit operation, 8-digit × 2-line display
For a 2-line display, the cursor automatically moves from the first to the second line after the 40th digit
of the first line has been written. Thus, if there are only 8 characters in the first line, the DDRAM address must be again set after the 8th character is completed. (See Table 13.) Note that the display shift operation is performed for the first and second lines. In the example of Table 13, the display shift is performed when the cursor is on the second line. However, if the shift operation is performed when the cursor is on the first line, both the first and second lines move together. If the shift is repeated, the display of the second line will not move to the first line. The same display will only shift within its own line for the number of times the shift is repeated.
Note: When using the internal reset, the electrical characteristics in the Power Supply Conditions Using Internal Reset Circuit table must be satisfied. If not, the HD44780U must be initialized by instructions. See the section, Initializing by Instruction.
39
HD44780U
Table 11 8-Bit Operation, 8-Digit × 1-Line Display Example with Internal Reset
Instruction
No. RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Display
1 Power supply on (the HD44780U is initialized by the internal reset circuit)
Step
2 Function set 00001 1
3 Display on/off control 00000 0
4 Entry mode set 00000 0
0 0 **
1 1 10
0 1 10
Operation
Initialized. No display.
Sets to 8-bit operation and selects 1-line display and 5 × 8 dot character font. (Number of display lines and character fonts cannot be changed after step #2.)
Turns on display and cursor. Entire display is in space mode because of initialization.
Sets mode to increment the address by one and to shift the cursor to the right at the time of write to the DD/CGRAM. Display is not shifted.
Writes H. DDRAM has already been selected by initialization when the power was turned on. The cursor is incremented by one and shifted to the right.
Writes I.
Writes I.
Sets mode to shift display at the time of write.
Writes a space.
_
_
5 Write data to CGRAM/DDRAM 100100 1
0 00
H_
6 Write data to CGRAM/DDRAM 1001001001
7·· ·· ·· ·· ··
8 Write data to CGRAM/DDRAM 1001001001
9 Entry mode set 0000000111
10 Write data to CGRAM/DDRAM 1000100000
HI_
HITACHI_
HITACHI_
ITACHI _
40
Step
HD44780U
Table 11 8-Bit Operation, 8-Digit × 1-Line Display Example with Internal Reset (cont)
Instruction
No. RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Display
11 Write data to CGRAM/DDRAM 1001001101
12 · · ·· ·· ·· ··
13 Write data to CGRAM/DDRAM 1001001111
14 Cursor or display shift 00000 1
15 Cursor or display shift 00000 1
16 Write data to CGRAM/DDRAM 10010 0
17 Cursor or display shift 00000 1
18 Cursor or display shift 00000 1
0 0 *
0 0 *
0 0 1
1 1 *
0 1 *
*
*
1
*
*
Operation
Writes M.
Writes O.
Shifts only the cursor position to the left.
Shifts only the cursor position to the left.
Writes C over K.
The display moves to the left.
Shifts the display and cursor position to the right.
Shifts the display and cursor position to the right.
Writes M.
Returns both display and cursor to the original position (address 0).
TACHI M_
MICROKO_
MICROKO_
MICROK_O
ICROCO_
MICROCO_
MICROCO_
19 Write data to CGRAM/DDRAM 1001001101
ICROCOM_
20
21 Return home 00000
· · ·· ·· ·· ··
00010
H_ITACHI
41
HD44780U
Table 12 4-Bit Operation, 8-Digit × 1-Line Display Example with Internal Reset
Instruction No. RS R/W DB7 DB6 DB5 DB4
Step
Display
Operation
Initialized. No display.
Sets to 4-bit operation.
In this case, operation is handled as 8 bits by initializa- tion, and only this instruction completes with one write.
Sets 4-bit operation and selects 1-line display and 5 × 8 dot character font. 4-bit operation starts from this step and resetting is necessary. (Number of display lines and character fonts cannot be changed after step #3.)
Turns on display and cursor. Entire display is in space mode because of initialization.
Sets mode to increment the address by one and to shift the cursor to the right at the time of write to the DD/CGRAM. Display is not shifted.
Writes H.
The cursor is incremented by one and shifts to the right.
1
2
3
4
5
6
Note:
Power supply on (the HD44780U is initialized by the internal reset circuit)
Function set 000 0
Function set 000 0 000 0
1
1 *
0
0 *
0 0
0 0
0 0
Display on/off 000 001
control
0 0
1 1
_
Entry mode set
0000 0
0001 1
Write data to CGRAM/DDRAM 10010 10100
_
H_
The control is the same as for 8-bit operation beyond step #6.
42
Step
HD44780U
Table 13 8-Bit Operation, 8-Digit × 2-Line Display Example with Internal Reset
Instruction
No. RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Display
1 Power supply on (the HD44780U is initialized by the internal reset circuit)
2 Function set 00001 1
3 Display on/off control 00000 0
4 Entry mode set 00000 0
1 0 *
1 1 1
0 1 1
*
0
0
0
Operation
Initialized. No display.
Sets to 8-bit operation and selects 2-line display and 5 × 8 dot character font.
Turns on display and cursor. All display is in space mode because of initialization.
Sets mode to increment the address by one and to shift the cursor to the right at the time of write to the DD/CGRAM. Display is not shifted.
Writes H. DDRAM has already been selected by initialization when the power was turned on. The cursor is incremented by one and shifted to the right.
Writes I.
Sets DDRAM address so that the cursor is positioned at the head of the second line.
_
_
5 Write data to CGRAM/DDRAM 100100 1
0 0
H_
6·· ·· ·· ·· ··
7 Write data to CGRAM/DDRAM 1001001001
8 Set DDRAM address 0011000000
HITACHI_
HITACHI
_
43
HD44780U
Table 13 8-Bit Operation, 8-Digit × 2-Line Display Example with Internal Reset (cont)
Instruction
No. RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Display
9 Write data to CGRAM/DDRAM 1001001101
10 · · ·· ·· ·· ··
11 Write data to CGRAM/DDRAM 1001001111
12 Entry mode set 0000000111
13 Write data to CGRAM/DDRAM 1001001101
14 · · ·· ·· ·· ··
15 Return home 0000000010
Step
Operation
Writes M.
Writes O.
Sets mode to shift display at the time of write.
Writes M. Display is shifted to the left. The first and second lines both shift at the same time.
Returns both display and cursor to the original position (address 0).
HITACHI
M_
HITACHI
MICROCO_
HITACHI
MICROCO_
ITACHI
ICROCOM_
H_ITACHI
MICROCOM
44
Initializing by Instruction
If the power supply conditions for correctly operating the internal reset circuit are not met, initialization by instructions becomes necessary.
Refer to Figures 23 and 24 for the procedures on 8-bit and 4-bit initializations, respectively.
Figure 23 8-Bit Interface
HD44780U
Power on
Wait for more than 15 ms after VCC rises to 4.5 V
RS R/WDB7DB6DB5DB4DB3DB2DB1DB0 000011****
Wait for more than 4.1 ms
RS R/WDB7DB6DB5DB4DB3DB2DB1DB0 000011****
Wait for more than 100 μs
RS R/WDB7DB6DB5DB4DB3DB2DB1DB0 000011****
Wait for more than 40 ms after VCC rises to 2.7 V
Function set (Interface is 8 bits long.)
Function set (Interface is 8 bits long.)
Function set (Interface is 8 bits long.)
Function set (Interface is 8 bits long. Specify the number of display lines and character font.)
The number of display lines and character font cannot be changed after this point.
Display off Display clear Entry mode set
BF cannot be checked before this instruction.
BF cannot be checked before this instruction.
BF cannot be checked before this instruction.
BF can be checked after the following instructions. When BF is not checked, the waiting time between instructions is longer than the execution instuction time. (See Table 6.)
RS R/WDB7DB6DB5DB4DB3DB2DB1DB0 000011NF**
0000001000
0000000001
0 0 0 0 0 0 0 1 I/D S
Initialization ends
45
HD44780U
Power on
Wait for more than 15 ms after VCC rises to 4.5 V
RS R/WDB7DB6DB5DB4 000011
Wait for more than 4.1 ms
RS R/WDB7DB6DB5DB4 000011
Wait for more than 100 μs
RS R/WDB7DB6DB5DB4 000011
Wait for more than 40 ms after VCC rises to 2.7 V
Function set (Interface is 8
Function set (Interface is 8
Function set (Interface is 8
Function set (Set interface Interface is 8 bits in length.
Function set (Interface is 4
number of display lines and character font.) The number of display lines and character font cannot be changed after this point.
Display off Display clear Entry mode set
BF cannot be checked before this instruction.
bits long.)
bits long.)
bits long.)
to be 4 bits long.)
BF cannot be checked before this instruction.
BF cannot be checked before this instruction.
RS R/WDB7DB6DB5DB4 000010
000010 00NF**
000000 001000
000000 000001
000000 0 0 0 1 I/D S
BF can be checked after the following instructions. When BF is not checked, the waiting time between instructions is longer than the execution instuction time. (See Table 6.)
bits long. Specify the
Initialization ends
Figure 24 4-Bit Interface
46
Item Symbol
Power supply voltage (1) VCC–GND
Power supply voltage (2) VCC–V5
Input voltage Vt
Operating temperature Topr
Storage temperature Tstg
Value Unit
–0.3 to +7.0 V
–0.3 to +13.0 V
–0.3 to VCC +0.3 V
–30 to +75 °C
–55 to +125 °C
Notes
1
1, 2
1
4
HD44780U
Absolute Maximum Ratings*
Note: * If the LSI is used above these absolute maximum ratings, it may become permanently damaged. Using the LSI within the following electrical characteristic limits is strongly recommended for normal operation. If these electrical characteristic conditions are also exceeded, the LSI will malfunction and cause poor reliability.
47
HD44780U
DC Characteristics (V = 2.7 to 4.5 V, T = –30 to +75°C*3) CC a
Item Symbol
Input high voltage (1) VIH1 (except OSC1)
Input low voltage (1) VIL1 (except OSC1)
Input high voltage (2) VIH2 (OSC1)
Input low voltage (2) VIL2 (OSC1)
Output high voltage (1) VOH1 (DB0–DB7)
Output low voltage (1) VOL1 (DB0–DB7)
Output high voltage (2) VOH2 (except DB0–DB7)
Output low voltage (2) VOL2 (except DB0–DB7)
Driver on resistance RCOM (COM)
Driver on resistance RSEG (SEG)
Input leakage current ILI
Pull-up MOS current –Ip (DB0–DB7, RS, R/W)
Power supply current ICC
LCD voltage VLCD1
Min Typ
0.7VCC —
–0.3 —
0.7VCC —
— —
0.75VCC —
— —
0.8VCC —
— —
— 2
— 2
–1 —
10 50
— 150
3.0 —
Max Unit
VCC V
0.55 V
VCC V
0.2VCC V
— V
0.2VCC V
— V
0.2VCC V
20 kΩ
30 kΩ
1 μA
120 μA
300 μA
11.0 V
Test Condition
Notes*
6
6
15
15
7
7
8
8
13
13
9
10, 14
16
16
–IOH = 0.1 mA
IOL = 0.1 mA
–IOH = 0.04 mA
IOL = 0.04 mA
±Id = 0.05 mA, VLCD = 4 V
±Id = 0.05 mA, VLCD = 4 V
VIN = 0 to VCC
VCC = 3 V
Rf oscillation, external clock VCC = 3 V,
fOSC = 270 kHz
VCC–V5, 1/5 bias
VLCD2 3.0 —
Note: * Refer to the Electrical Characteristics Notes section following these tables.
11.0 V
VCC–V5, 1/4 bias
48
AC Characteristics (V = 2.7 to 4.5 V, T = –30 to +75°C*3) CC a
Clock Characteristics
Item
External clock operation
Rf oscillation
Note: *
External clock frequency
External clock duty
External clock rise time
External clock fall time
Symbol Min
fcp 125
Duty 45
trcp —
tfcp —
Typ Max
250 350
Unit Test Condition Note*
kHz 11
HD44780U
50 55 %
— 0.2 μs
— 0.2 μs
fOSC 190
Refer to the Electrical Characteristics Notes section following these tables.
Clock oscillation frequency
270 350 kHz
Rf = 75 kΩ, 12 VCC = 3 V
Bus Timing Characteristics Write Operation
Item
Enable cycle time
Enable pulse width (high level)
Enable rise/fall time
Address set-up time (RS, R/W to E)
Address hold time
Data set-up time
Data hold time
Read Operation
Item
Enable cycle time
Enable pulse width (high level)
Enable rise/fall time
Address set-up time (RS, R/W to E)
Address hold time
Data delay time
Data hold time
Symbol Min Typ
tcycE 1000 —
Max Unit
— ns
Test Condition
Figure 25
PWEH 450 — —
tEr, tEf — — 25
tAS 60 — —
tAH 20 — —
tDSW 195 — —
tH 10 — —
Symbol Min Typ
tcycE 1000 —
Max Unit
— ns
Test Condition
Figure 26
PWEH 450 — —
tEr, tEf — — 25
tAS 60 — —
tAH 20 — —
tDDR — — 360
tDHR 5 — —
49
HD44780U
Interface Timing Characteristics with External Driver
Item
Clock pulse width
Clock set-up time
Data set-up time
Data hold time
M delay time
Clock rise/fall time
High level
Low level
Symbol Min
tCWH 800
tCWL 800
tCSU 500
tSU 300
tDH 300
tDM –1000
tct —
Typ Max Unit
— — ns
— —
— —
— —
— —
— 1000
— 200
Test Condition
Figure 27
Power Supply Conditions Using Internal Reset Circuit
Item
Power supply rise time
Power supply off time
Symbol Min
trCC 0.1
tOFF 1
Typ Max Unit
— 10 ms
— —
Test Condition
Figure 28
50
DC Characteristics (V = 4.5 to 5.5 V, T = –30 to +75°C*3) CC a
Item Symbol
Input high voltage (1) VIH1 (except OSC1)
Input low voltage (1) VIL1 (except OSC1)
Input high voltage (2) VIH2 (OSC1)
Input low voltage (2) VIL2 (OSC1)
Output high voltage (1) VOH1 (DB0–DB7)
Output low voltage (1) VOL1 (DB0–DB7)
Output high voltage (2) VOH2 (except DB0–DB7)
Output low voltage (2) VOL2 (except DB0–DB7)
Driver on resistance RCOM (COM)
Driver on resistance RSEG (SEG)
Input leakage current ILI
Pull-up MOS current –Ip (DB0–DB7, RS, R/W)
Power supply current ICC
LCD voltage VLCD1
Min Typ Max
Unit Test Condition Notes*
V 6
V 6
V 15
V 15
V –IOH = 0.205 mA 7
V IOL = 1.2 mA 7
V –IOH = 0.04 mA 8
V IOL = 0.04 mA 8
kΩ ±Id = 0.05 mA, 13 VLCD = 4 V
kΩ ±Id = 0.05 mA, 13 VLCD = 4 V
μA VIN = 0 to VCC 9
HD44780U
2.2 — VCC
–0.3 — 0.6
VCC–1.0 — VCC
— — 1.0
2.4 — —
— — 0.4
0.9 VCC — —
— — 0.1
— 2 20
— 2 30
–1 — 1
50 125 250
— 350 600
VCC
VLCD2 3.0 — 11.0
Note: * Refer to the Electrical Characteristics Notes section following these tables.
μA VCC = 5 V
μA Rf oscillation, external clock
VCC = 5 V,
fOSC = 270 kHz
10, 14
3.0 — 11.0
V VCC–V5, 1/5 bias 16
V VCC–V5, 1/4 bias 16
51
HD44780U
AC Characteristics (V = 4.5 to 5.5 V, T = –30 to +75°C*3) CC a
Clock Characteristics
Item
External clock operation
Rf oscillation
Note: *
Symbol Min
fcp 125
Duty 45
trcp —
tfcp —
fOSC 190
Refer to the Electrical Characteristics Notes section following these tables.
External clock frequency
External clock duty
External clock rise time
External clock fall time
Typ Max Unit
250 350 kHz
50 55 %
— 0.2 μs
— 0.2 μs
Test Condition Notes*
11
11
11
11
Clock oscillation frequency
270 350 kHz
Rf = 91 kΩ 12 VCC = 5.0 V
Bus Timing Characteristics Write Operation
Item
Enable cycle time
Enable pulse width (high level)
Enable rise/fall time
Address set-up time (RS, R/W to E)
Address hold time
Data set-up time
Data hold time
Read Operation
Item
Enable cycle time
Enable pulse width (high level)
Enable rise/fall time
Address set-up time (RS, R/W to E)
Address hold time
Data delay time
Data hold time
Symbol Min
tcycE 500
PWEH 230
tEr, tEf —
tAS 40
tAH 10
tDSW 80
tH 10
Symbol Min
tcycE 500
PWEH 230
tEr, tEf —
tAS 40
tAH 10
tDDR —
tDHR 5
Typ Max Unit
— — ns
— —
— 20
— —
— —
— —
— —
Typ Max Unit
— — ns
— —
— 20
— —
— —
— 160
— —
Test Condition
Figure 25
Test Condition
Figure 26
52
Item
Clock pulse width
Clock set-up time
Data set-up time
Data hold time
M delay time
Clock rise/fall time
High level
Low level
Symbol Min
tCWH 800
tCWL 800
tCSU 500
tSU 300
tDH 300
tDM –1000
tct —
Typ Max Unit
— — ns
— —
— —
— —
— —
— 1000
— 100
Test Condition
Figure 27
HD44780U
Interface Timing Characteristics with External Driver
Power Supply Conditions Using Internal Reset Circuit
Item
Power supply rise time
Power supply off time
Symbol Min
trCC 0.1
tOFF 1
Typ Max Unit
— 10 ms
— —
Test Condition
Figure 28
53
HD44780U
Electrical Characteristics Notes
1. All voltage values are referred to GND = 0 V.
VCC
V1
A
V5
B
Input pin
Pin: E (MOS without pull-up)
Pins: RS, R/W (MOS with pull-up) VCC VCC
Output pin
Pins: CL1, CL2, M, D
A = VCC –V5 B = VCC –V1 A ≥ 1.5 V
B ≤ 0.25 × A
The conditions of V1 and V5 voltages are for proper operation of the LSI and not for the LCD output level. The LCD drive voltage condition for the LCD output level is specified as LCD voltage VLCD.
2. VCC ≥ V1 ≥ V2 ≥ V3 ≥ V4 ≥ V5 must be maintained.
3. For die products, specified at 75°C.
4. For die products, specified by the die shipment specification.
5. The following four circuits are I/O pin configurations except for liquid crystal display output.
VCC
PMOS
NMOS
PMOS
PMOS
NMOS
PMOS
NMOS
I/O Pin
Pins: DB0 –DB7 (MOS with pull-up)
(pull up MOS)
VCC
VCC (pull-up MOS)
PMOS
(input circuit) PMOS
Input enable
NMOS
NMOS PMOS
Output enable Data
VCC
NMOS
(output circuit) (tristate)
54
6. Applies to input pins and I/O pins, excluding the OSC1 pin.
7. Applies to I/O pins.
8. Applies to output pins.
9. Current flowing through pull–up MOSs, excluding output drive MOSs.
10. Input/output current is excluded. When input is at an intermediate level with CMOS, the excessive
current flows through the input circuit to the power supply. To avoid this from happening, the input level must be fixed high or low.
11. Applies only to external clock operation.
Th
t rcp
Tl
HD44780U
Oscillator
OSC1
OSC2
Open
0.7 VCC 0.5 VCC 0.3 VCC
Duty =
12. Applies only to the internal oscillator operation using oscillation resistor Rf.
Th × 100% Th + Tl
t fcp
OSC1
OSC2
Rf : 75 kΩ ± 2% (when VCC = 3 V) Rf : 91 kΩ ± 2% (when VCC = 5 V)
Rf
500
400
300
(270)
200
100
50
Since the oscillation frequency varies depending on the OSC1 and
OSC2 pin capacitance, the wiring length to these pins should be minimized.
VCC
= 5 V
VCC = 3 V
max.
typ. min.
max.
typ.
min.
(91) 100
Rf (kΩ)
500
400
300 (270)
200
100
50
(75) 100 150 Rf (kΩ)
150
55
f
OSC
(kHz)
f
OSC
(kHz)
HD44780U
13. RCOM is the resistance between the power supply pins (VCC, V1, V4, V5) and each common signal pin (COM1 to COM16).
RSEG is the resistance between the power supply pins (VCC, V2, V3, V5) and each segment signal pin (SEG1 to SEG40).
14. The following graphs show the relationship between operation frequency and current consumption.
1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0
0
1.8 1.6 1.4 1.2
max. 1.0 0.8 typ. 0.6
0.4 0.2 0.0
max. typ.
VCC
= 5 V
VCC = 3 V
100 200 300 400 500 0 fOSC or fcp (kHz)
100 200 300 400 500 fOSC or fcp (kHz)
15. Applies to the OSC1 pin.
16. Each COM and SEG output voltage is within ±0.15 V when there is no load.
of the LCD voltage (VCC, V1, V2, V3, V4, V5)
56
ICC (mA)
ICC (mA)
HD44780U
Load Circuits Data Bus DB0 to DB7
For VCC = 4.5 to 5.5 V
Test Test
VCC = 5 V
3.9 kΩ
For VCC = 2.7 to 4.5 V point
point
90 pF 11 kΩ IS2074 H diodes
50 pF
External Driver Control Signals: CL1, CL2, D, M
Test point
30 pF
57
HD44780U
Timing Characteristics
RS
R/W
E
DB0 to DB7
VIH1 VIL1
tAS
VIH1 VIL1
VIL1
tAH
tAH tEf
tH
VIL1
VIH1 VIL1
PWEH
VIH1 VIL1
VIH1 VIL1
Valid data tcycE
VIL1
tEr
tDSW
VIH1 VIL1
Figure 25 Write Operation
RS
R/W
E
DB0 to DB7
VIH1 VIL1
tAS
VIH1
VIH1 VIL1
tAH
VIH1
VIH1 VIL1
tDDR
PWEH
VOH1 VOL1 *
VIH1 VIL1
tAH tEf
tDHR
VIL1
tEr
Valid data tcycE
VOH1 * VOL1
Note: * VOL1 is assumed to be 0.8 V at 2 MHz operation.
Figure 26 Read Operation
58
Figure 28 Internal Power Supply Reset
HD44780U
VOH2
VOH2
tct VOL2
CL1
CL2
D
M
tCWH
tCWH
tCSU VOL2
tCSU
VOH2
tCWL tct
tDH
VOH2 VOL2
tSU VOH2
tDM
Figure 27 Interface Timing with External Driver
VCC
2.7 V/4.5 V*2
0.2 V
trcc
0.1 ms ≤ trcc ≤10 ms
tOFF compensates for the power oscillation period caused by momentary power supply oscillations.
Specified at 4.5 V for 5-V operation, and at 2.7 V for 3-V operation.
For if 4.5 V is not reached during 5-V operation, the internal reset circuit will not operate normally.
In this case, the LSI must be initialized by software. (Refer to the Initializing by Instruction section.)
0.2 V 0.2 V
tOFF*1 tOFF ≥ 1 ms
Notes: 1.
2. 3.
59
HD44780U
Cautions
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the information contained in this document.
2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use.
3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However, contact Hitachi’s sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support.
4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail- safes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product.
5. This product is not designed to be radiation resistant.
6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Hitachi.
7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor products.
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