11/27/2018 CSCI2500: Computer Organization
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RPI Computer Science > Submitty > Computer Organization > Homework 5
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hw5.c (5.32kb)
submission timestamp: 11/27/2018 06:15:24 PM
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grading time: 9 seconds
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40 / 100 Total
Test 1 — Compilation /usr/bin/gcc -Wall -Werror -o a.out *.c -lm
Details
Visualize whitespace characters
Student STDOUT.txt
1 $s1
2 0
3 $s0
4 1
5
6 1
7
8 $s1
9 0
10 $s0
11 1
12
13 1
14 $t2
15 1
16
17 1
18 $s5
5 / 10 Test 2 ./a.out hw5-test02-stdin.txt
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11/27/2018 CSCI2500: Computer Organization
https://submitty.cs.rpi.edu/index.php?semester=f18&course=csci2500&component=student&gradeable_id=hw5 2/18
19 1
20
21 $s1
22 0
23 $s0
24 1
25
26 1
27 $t2
28 1
29
30 1
31 $s5
32 1
33 $t4
34 2
35
36 1
37
38 START OF SIMULATION
39
40 CPU Cycles ===> 1 2 3 4 5 6 7 8 9
41 add $s1,$s0,$s0 IF . . . . . . . .
42 add $t2,$s0,$s5 . . . . . . . . .
43 add $t4,$s3,70 . . . . . . . . .
44
45 CPU Cycles ===> 1 2 3 4 5 6 7 8 9
46 add $s1,$s0,$s0 IF ID . . . . . . .
47 add $t2,$s0,$s5 . IF . . . . . . .
48 add $t4,$s3,70 . . . . . . . . .
49
50 CPU Cycles ===> 1 2 3 4 5 6 7 8 9
51 add $s1,$s0,$s0 IF ID EX . . . . . .
52 add $t2,$s0,$s5 . IF ID . . . . . .
53 add $t4,$s3,70 . . IF . . . . . .
54
55 CPU Cycles ===> 1 2 3 4 5 6 7 8 9
56 add $s1,$s0,$s0 IF ID EX MEM . . . . .
57 add $t2,$s0,$s5 . IF ID EX . . . . .
58 add $t4,$s3,70 . . IF ID . . . . .
59
60 CPU Cycles ===> 1 2 3 4 5 6 7 8 9
61 add $s1,$s0,$s0 IF ID EX MEM WB . . . .
62 add $t2,$s0,$s5 . IF ID EX MEM . . . .
63 add $t4,$s3,70 . . IF ID EX . . . .
64
65 CPU Cycles ===> 1 2 3 4 5 6 7 8 9
66 add $s1,$s0,$s0 IF ID EX MEM WB . . . .
67 add $t2,$s0,$s5 . IF ID EX MEM WB . . .
68 add $t4,$s3,70 . . IF ID EX MEM . . .
69
70 CPU Cycles ===> 1 2 3 4 5 6 7 8 9
71 add $s1,$s0,$s0 IF ID EX MEM WB . . . .
72 add $t2,$s0,$s5 . IF ID EX MEM WB . . .
73 add $t4,$s3,70 . . IF ID EX MEM WB . .
74
75 END OF SIMULATION
76
Expected STDOUT.txt
11/27/2018 CSCI2500: Computer Organization
https://submitty.cs.rpi.edu/index.php?semester=f18&course=csci2500&component=student&gradeable_id=hw5 3/18
1 START OF SIMULATION
2
3 CPU Cycles ===> 1 2 3 4 5 6 7 8 9
4 add $s1,$s0,$s0 IF . . . . . . . .
5 add $t2,$s0,$s5 . . . . . . . . .
6 add $t4,$s3,70 . . . . . . . . .
7
8 CPU Cycles ===> 1 2 3 4 5 6 7 8 9
9 add $s1,$s0,$s0 IF ID . . . . . . .
10 add $t2,$s0,$s5 . IF . . . . . . .
11 add $t4,$s3,70 . . . . . . . . .
12
13 CPU Cycles ===> 1 2 3 4 5 6 7 8 9
14 add $s1,$s0,$s0 IF ID EX . . . . . .
15 add $t2,$s0,$s5 . IF ID . . . . . .
16 add $t4,$s3,70 . . IF . . . . . .
17
18 CPU Cycles ===> 1 2 3 4 5 6 7 8 9
19 add $s1,$s0,$s0 IF ID EX MEM . . . . .
20 add $t2,$s0,$s5 . IF ID EX . . . . .
21 add $t4,$s3,70 . . IF ID . . . . .
22
23 CPU Cycles ===> 1 2 3 4 5 6 7 8 9
24 add $s1,$s0,$s0 IF ID EX MEM WB . . . .
25 add $t2,$s0,$s5 . IF ID EX MEM . . . .
26 add $t4,$s3,70 . . IF ID EX . . . .
27
28 CPU Cycles ===> 1 2 3 4 5 6 7 8 9
29 add $s1,$s0,$s0 IF ID EX MEM WB . . . .
30 add $t2,$s0,$s5 . IF ID EX MEM WB . . .
31 add $t4,$s3,70 . . IF ID EX MEM . . .
32
33 CPU Cycles ===> 1 2 3 4 5 6 7 8 9
34 add $s1,$s0,$s0 IF ID EX MEM WB . . . .
35 add $t2,$s0,$s5 . IF ID EX MEM WB . . .
36 add $t4,$s3,70 . . IF ID EX MEM WB . .
37
38 END OF SIMULATION
39
Visualize whitespace characters
Student STDERR.txt
1
Details
Visualize whitespace characters
Student STDOUT.txt
1 $t13
2 0
3 $s0
4 1
5
4 / 10 Test 3 ./a.out hw5-test03-stdin.txt
11/27/2018 CSCI2500: Computer Organization
https://submitty.cs.rpi.edu/index.php?semester=f18&course=csci2500&component=student&gradeable_id=hw5 4/18
6 1
7
8 $t13
9 0
10 $s0
11 1
12
13 1
14 $t2
15 1
16
17 1
18
19 $t13
20 0
21 $s0
22 1
23
24 1
25 $t2
26 1
27
28 1
29 $t4
30 2
31 $t1
32 1
33
34 START OF SIMULATION
35
36 CPU Cycles ===> 1 2 3 4 5 6 7 8 9
37 add $t1,$s0,$s0 IF . . . . . . . .
38 add $t2,$s0,42 . . . . . . . . .
39 add $t4,$t1,70 . . . . . . . . .
40
41 CPU Cycles ===> 1 2 3 4 5 6 7 8 9
42 add $t1,$s0,$s0 IF ID . . . . . . .
43 add $t2,$s0,42 . IF . . . . . . .
44 add $t4,$t1,70 . . . . . . . . .
45
46 CPU Cycles ===> 1 2 3 4 5 6 7 8 9
47 add $t1,$s0,$s0 IF ID EX . . . . . .
48 add $t2,$s0,42 . IF ID . . . . . .
49 add $t4,$t1,70 . . IF . . . . . .
50
51 CPU Cycles ===> 1 2 3 4 5 6 7 8 9
52 add $t1,$s0,$s0 IF ID EX MEM . . . . .
53 add $t2,$s0,42 . IF ID EX . . . . .
54 add $t4,$t1,70 . . IF ID . . . . .
55
56 CPU Cycles ===> 1 2 3 4 5 6 7 8 9
57 add $t1,$s0,$s0 IF ID EX MEM WB . . . .
58 add $t2,$s0,42 . IF ID EX MEM . . . .
59 add $t4,$t1,70 . . IF ID EX . . . .
60
61 CPU Cycles ===> 1 2 3 4 5 6 7 8 9
62 add $t1,$s0,$s0 IF ID EX MEM WB . . . .
63 add $t2,$s0,42 . IF ID EX MEM WB . . .
64 add $t4,$t1,70 . . IF ID EX MEM . . .
65
66 CPU Cycles ===> 1 2 3 4 5 6 7 8 9
67 add $t1,$s0,$s0 IF ID EX MEM WB . . . .
68 add $t2,$s0,42 . IF ID EX MEM WB . . .
69 add $t4,$t1,70 . . IF ID EX MEM WB . .
70
11/27/2018 CSCI2500: Computer Organization
https://submitty.cs.rpi.edu/index.php?semester=f18&course=csci2500&component=student&gradeable_id=hw5 5/18
71 END OF SIMULATION
72
Expected STDOUT.txt
1 START OF SIMULATION
2
3 CPU Cycles ===> 1 2 3 4 5 6 7 8 9
4 add $t1,$s0,$s0 IF . . . . . . . .
5 add $t2,$s0,42 . . . . . . . . .
6 add $t4,$t1,70 . . . . . . . . .
7
8 CPU Cycles ===> 1 2 3 4 5 6 7 8 9
9 add $t1,$s0,$s0 IF ID . . . . . . .
10 add $t2,$s0,42 . IF . . . . . . .
11 add $t4,$t1,70 . . . . . . . . .
12
13 CPU Cycles ===> 1 2 3 4 5 6 7 8 9
14 add $t1,$s0,$s0 IF ID EX . . . . . .
15 add $t2,$s0,42 . IF ID . . . . . .
16 add $t4,$t1,70 . . IF . . . . . .
17
18 CPU Cycles ===> 1 2 3 4 5 6 7 8 9
19 add $t1,$s0,$s0 IF ID EX MEM . . . . .
20 add $t2,$s0,42 . IF ID EX . . . . .
21 add $t4,$t1,70 . . IF ID . . . . .
22
23 CPU Cycles ===> 1 2 3 4 5 6 7 8 9
24 add $t1,$s0,$s0 IF ID EX MEM WB . . . .
25 add $t2,$s0,42 . IF ID EX MEM . . . .
26 nop . . IF ID * . . . .
27 add $t4,$t1,70 . . IF ID ID . . . .
28
29 CPU Cycles ===> 1 2 3 4 5 6 7 8 9
30 add $t1,$s0,$s0 IF ID EX MEM WB . . . .
31 add $t2,$s0,42 . IF ID EX MEM WB . . .
32 nop . . IF ID * * . . .
33 add $t4,$t1,70 . . IF ID ID EX . . .
34
35 CPU Cycles ===> 1 2 3 4 5 6 7 8 9
36 add $t1,$s0,$s0 IF ID EX MEM WB . . . .
37 add $t2,$s0,42 . IF ID EX MEM WB . . .
38 nop . . IF ID * * * . .
39 add $t4,$t1,70 . . IF ID ID EX MEM . .
40
41 CPU Cycles ===> 1 2 3 4 5 6 7 8 9
42 add $t1,$s0,$s0 IF ID EX MEM WB . . . .
43 add $t2,$s0,42 . IF ID EX MEM WB . . .
11/27/2018 CSCI2500: Computer Organization
https://submitty.cs.rpi.edu/index.php?semester=f18&course=csci2500&component=student&gradeable_id=hw5 6/18
44 nop . . IF ID * * * . .
45 add $t4,$t1,70 . . IF ID ID EX MEM WB .
46
47 END OF SIMULATION
48
Visualize whitespace characters
Student STDERR.txt
1
Details
Visualize whitespace characters
Student STDOUT.txt
1
2 0
3 $a0
4 1
5
6
7 0
8 $a0
9 1
10
11 1
12 $t2
13 1
14
15 1
16
17
18 0
19 $a0
20 1
21
22 1
23 $t2
24 1
25
26 1
27 $t8
28 2
29 $t2
30 1
31
32 1
33
34 START OF SIMULATION
35
36 CPU Cycles ===> 1 2 3 4 5 6 7 8 9
37 lw $t2,20($a0) IF . . . . . . . .
38 and $t4,$t2,$t5 . . . . . . . . .
39 or $t8,$t2,$t6 . . . . . . . . .
40
41 CPU Cycles ===> 1 2 3 4 5 6 7 8 9
42 lw $t2,20($a0) IF ID . . . . . . .
43 and $t4,$t2,$t5 . IF . . . . . . .
44 or $t8,$t2,$t6 . . . . . . . . .
45
46 CPU Cycles ===> 1 2 3 4 5 6 7 8 9
47 lw $t2,20($a0) IF ID EX . . . . . .
48 and $t4,$t2,$t5 . IF ID . . . . . .
49 or $t8,$t2,$t6 . . IF . . . . . .
50
51 CPU Cycles ===> 1 2 3 4 5 6 7 8 9
52 lw $t2,20($a0) IF ID EX MEM . . . . .
53 and $t4,$t2,$t5 . IF ID EX . . . . .
54 or $t8,$t2,$t6 . . IF I D . . . . .
4 / 10 Test 4 ./a.out hw5-test04-stdin.txt
11/27/2018 CSCI2500: Computer Organization
https://submitty.cs.rpi.edu/index.php?semester=f18&course=csci2500&component=student&gradeable_id=hw5 7/18
55
56 CPU Cycles ===> 1 2 3 4 5 6 7 8 9
57 lw $t2,20($a0) IF ID EX MEM WB . . . .
58 and $t4,$t2,$t5 . IF ID EX MEM . . . .
59 or $t8,$t2,$t6 . . IF I D EX . . . .
60
61 CPU Cycles ===> 1 2 3 4 5 6 7 8 9
62 lw $t2,20($a0) IF ID EX MEM WB . . . .
63 and $t4,$t2,$t5 . IF ID EX MEM WB . . .
64 or $t8,$t2,$t6 . . IF I D EX MEM . . .
65
66 CPU Cycles ===> 1 2 3 4 5 6 7 8 9
67 lw $t2,20($a0) IF ID EX MEM WB . . . .
68 and $t4,$t2,$t5 . IF ID EX MEM WB . . .
69 or $t8,$t2,$t6 . . IF ID EX MEM WB . .
70
71 END OF SIMULATION
72
Expected STDOUT.txt
1 START OF SIMULATION
2
3 CPU Cycles ===> 1 2 3 4 5 6 7 8 9
4 lw $t2,20($a0) IF . . . . . . . .
5 and $t4,$t2,$t5 . . . . . . . . .
6 or $t8,$t2,$t6 . . . . . . . . .
7
8 CPU Cycles ===> 1 2 3 4 5 6 7 8 9
9 lw $t2,20($a0) IF ID . . . . . . .
10 and $t4,$t2,$t5 . IF . . . . . . .
11 or $t8,$t2,$t6 . . . . . . . . .
12
11/27/2018 CSCI2500: Computer Organization
https://submitty.cs.rpi.edu/index.php?semester=f18&course=csci2500&component=student&gradeable_id=hw5 8/18
13 CPU Cycles ===> 1 2 3 4 5 6 7 8 9
14 lw $t2,20($a0) IF ID EX . . . . . .
15 and $t4,$t2,$t5 . IF ID . . . . . .
16 or $t8,$t2,$t6 . . IF . . . . . .
17
18 CPU Cycles ===> 1 2 3 4 5 6 7 8 9
19 lw $t2,20($a0) IF ID EX MEM . . . . .
20 nop . IF ID * . . . . .
21 nop . IF ID * . . . . .
22 and $t4,$t2,$t5 . IF ID ID . . . . .
23 or $t8,$t2,$t6 . . IF I F . . . . .
24
25 CPU Cycles ===> 1 2 3 4 5 6 7 8 9
26 lw $t2,20($a0) IF ID EX MEM WB . . . .
27 nop . IF ID * * . . . .
28 nop . IF ID * * . . . .
29 and $t4,$t2,$t5 . IF ID ID ID . . . .
30 or $t8,$t2,$t6 . . IF I F IF . . . .
31
32 CPU Cycles ===> 1 2 3 4 5 6 7 8 9
33 lw $t2,20($a0) IF ID EX MEM WB . . . .
34 nop . IF ID * * * . . .
35 nop . IF ID * * * . . .
36 and $t4,$t2,$t5 . IF ID ID ID EX . . .
37 or $t8,$t2,$t6 . . IF I F IF ID . . .
38
39 CPU Cycles ===> 1 2 3 4 5 6 7 8 9
40 lw $t2,20($a0) IF ID EX MEM WB . . . .
41 nop . IF ID * * * . . .
42 nop . IF ID * * * . . .
43 and $t4,$t2,$t5 . IF ID ID ID EX MEM . .
44 or $t8,$t2,$t6 . . IF I F IF ID EX . .
45
46 CPU Cycles ===> 1 2 3 4 5 6 7 8 9
47 lw $t2,20($a0) IF ID EX MEM WB . . . .
48 nop . IF ID * * * . . .
49 nop . IF ID * * * . . .
50 and $t4,$t2,$t5 . IF ID ID ID EX MEM WB .
51 or $t8,$t2,$t6 . . IF IF IF ID EX MEM .
52
53 CPU Cycles ===> 1 2 3 4 5 6 7 8 9
54 lw $t2,20($a0) IF ID EX MEM WB . . . .
55 nop . IF ID * * * . . .
56 nop . IF ID * * * . . .
57 and $t4,$t2,$t5 . IF ID ID ID EX MEM WB .
58 or $t8,$t2,$t6 . . IF IF IF ID EX MEM WB
59
60 END OF SIMULATION
61
Visualize whitespace characters
Student STDERR.txt
1
Details
Visualize whitespace characters
Student STDOUT.txt
1 $s1[
2 0
3 $s0
4 1
5
6 1
7
8 $s1[
9 0
10 $s0
11 1
4 / 10 Test 5 ./a.out hw5-test05-stdin.txt
11/27/2018 CSCI2500: Computer Organization
https://submitty.cs.rpi.edu/index.php?semester=f18&course=csci2500&component=student&gradeable_id=hw5 9/18
12
13 1
14 $t2
15 1
16
17 1
18 $s5
19 1
20
21 $s1[
22 0
23 $s0
24 1
25
26 1
27 $t2
28 1
29
30 1
31 $s5
32 1
33 $t4
34 2
35
36 1
37
38 $s1[
39 0
40 $s0
41 1
42
43 1
44 $t2
45 1
46
47 1
48 $s5
49 1
50 $t4
51 2
52
53 1
54 $t4
55 3
56
57
58 1
59
60 START OF SIMULATION
61
62 CPU Cycles ===> 1 2 3 4 5 6 7 8 9
63 and $s1,$s0,$s0 IF . . . . . . . .
64 sub $t2,$s0,$s5 . . . . . . . . .
65 sub $t4,$s3,70 . . . . . . . . .
66 or $t4,$s1,73 . . . . . . . . .
67
68 CPU Cycles ===> 1 2 3 4 5 6 7 8 9
69 and $s1,$s0,$s0 IF ID . . . . . . .
70 sub $t2,$s0,$s5 . IF . . . . . . .
71 sub $t4,$s3,70 . . . . . . . . .
72 or $t4,$s1,73 . . . . . . . . .
73
74 CPU Cycles ===> 1 2 3 4 5 6 7 8 9
75 and $s1,$s0,$s0 IF ID EX . . . . . .
76 sub $t2,$s0,$s5 . IF ID . . . . . .
77 sub $t4,$s3,70 . . IF . . . . . .
78 or $t4,$s1,73 . . . . . . . . .
79
80 CPU Cycles ===> 1 2 3 4 5 6 7 8 9
81 and $s1,$s0,$s0 IF ID EX MEM . . . . .
82 sub $t2,$s0,$s5 . IF ID EX . . . . .
11/27/2018 CSCI2500: Computer Organization
https://submitty.cs.rpi.edu/index.php?semester=f18&course=csci2500&component=student&gradeable_id=hw5 10/18
83 sub $t4,$s3,70 . . IF ID . . . . .
84 or $t4,$s1,73 . . . IF . . . . .
85
86 CPU Cycles ===> 1 2 3 4 5 6 7 8 9
87 and $s1,$s0,$s0 IF ID EX MEM WB . . . .
88 sub $t2,$s0,$s5 . IF ID EX MEM . . . .
89 sub $t4,$s3,70 . . IF ID EX . . . .
90 or $t4,$s1,73 . . . IF ID . . . .
91
92 CPU Cycles ===> 1 2 3 4 5 6 7 8 9
93 and $s1,$s0,$s0 IF ID EX MEM WB . . . .
94 sub $t2,$s0,$s5 . IF ID EX MEM WB . . .
95 sub $t4,$s3,70 . . IF ID EX MEM . . .
96 or $t4,$s1,73 . . . IF ID EX . . .
97
98 CPU Cycles ===> 1 2 3 4 5 6 7 8 9
99 and $s1,$s0,$s0 IF ID EX MEM WB . . . .
100 sub $t2,$s0,$s5 . IF ID EX MEM WB . . .
101 sub $t4,$s3,70 . . IF ID EX MEM WB . .
102 or $t4,$s1,73 . . . IF ID EX MEM . .
103
104 CPU Cycles ===> 1 2 3 4 5 6 7 8 9
105 and $s1,$s0,$s0 IF ID EX MEM WB . . . .
106 sub $t2,$s0,$s5 . IF ID EX MEM WB . . .
107 sub $t4,$s3,70 . . IF ID EX MEM WB . .
108 or $t4,$s1,73 . . . IF ID EX MEM WB .
109
110 END OF SIMULATION
111
Expected STDOUT.txt
11/27/2018 CSCI2500: Computer Organization
https://submitty.cs.rpi.edu/index.php?semester=f18&course=csci2500&component=student&gradeable_id=hw5 11/18
1 START OF SIMULATION
2
3 CPU Cycles ===> 1 2 3 4 5 6 7 8 9
4 and $s1,$s0,$s0 IF . . . . . . . .
5 sub $t2,$s0,$s5 . . . . . . . . .
6 sub $t4,$s3,70 . . . . . . . . .
7 or $t4,$s1,73 . . . . . . . . .
8
9 CPU Cycles ===> 1 2 3 4 5 6 7 8 9
10 and $s1,$s0,$s0 IF ID . . . . . . .
11 sub $t2,$s0,$s5 . IF . . . . . . .
12 sub $t4,$s3,70 . . . . . . . . .
13 or $t4,$s1,73 . . . . . . . . .
14
15 CPU Cycles ===> 1 2 3 4 5 6 7 8 9
16 and $s1,$s0,$s0 IF ID EX . . . . . .
17 sub $t2,$s0,$s5 . IF ID . . . . . .
18 sub $t4,$s3,70 . . IF . . . . . .
19 or $t4,$s1,73 . . . . . . . . .
20
21 CPU Cycles ===> 1 2 3 4 5 6 7 8 9
22 and $s1,$s0,$s0 IF ID EX MEM . . . . .
23 sub $t2,$s0,$s5 . IF ID EX . . . . .
24 sub $t4,$s3,70 . . IF ID . . . . .
25 or $t4,$s1,73 . . . IF . . . . .
26
27 CPU Cycles ===> 1 2 3 4 5 6 7 8 9
28 and $s1,$s0,$s0 IF ID EX MEM WB . . . .
29 sub $t2,$s0,$s5 . IF ID EX MEM . . . .
30 sub $t4,$s3,70 . . IF ID EX . . . .
31 or $t4,$s1,73 . . . IF ID . . . .
32
33 CPU Cycles ===> 1 2 3 4 5 6 7 8 9
34 and $s1,$s0,$s0 IF ID EX MEM WB . . . .
35 sub $t2,$s0,$s5 . IF ID EX MEM WB . . .
36 sub $t4,$s3,70 . . IF ID EX MEM . . .
37 or $t4,$s1,73 . . . IF ID EX . . .
38
39 CPU Cycles ===> 1 2 3 4 5 6 7 8 9
40 and $s1,$s0,$s0 IF ID EX MEM WB . . . .
41 sub $t2,$s0,$s5 . IF ID EX MEM WB . . .
42 sub $t4,$s3,70 . . IF ID EX MEM WB . .
43 or $t4,$s1,73 . . . IF ID EX MEM . .
44
45 CPU Cycles ===> 1 2 3 4 5 6 7 8 9
46 and $s1,$s0,$s0 IF ID EX MEM WB . . . .
47 sub $t2,$s0,$s5 . IF ID EX MEM WB . . .
48 sub $t4,$s3,70 . . IF ID EX MEM WB . .
49 or $t4,$s1,73 . . . IF ID EX MEM WB .
50
51 END OF SIMULATION
52
Visualize whitespace characters
Student STDERR.txt
1
Details
Visualize whitespace characters
Student STDOUT.txt
1
2 0
3 $s0
4 1
5
4 / 10 Test 6 ./a.out hw5-test06-stdin.txt
11/27/2018 CSCI2500: Computer Organization
https://submitty.cs.rpi.edu/index.php?semester=f18&course=csci2500&component=student&gradeable_id=hw5 12/18
6 1
7
8
9 0
10 $s0
11 1
12
13 1
14 $t2
15 1
16
17 1
18 $s5
19 1
20
21
22 0
23 $s0
24 1
25
26 1
27 $t2
28 1
29
30 1
31 $s5
32 1
33 $t4
34 2
35
36 1
37
38
39 0
40 $s0
41 1
42
43 1
44 $t2
45 1
46
47 1
48 $s5
49 1
50 $t4
51 2
52
53 1
54 $t4
55 3
56
57 1
58
59
60 0
61 $s0
62 1
63
64 1
65 $t2
66 1
67
68 1
69 $s5
70 1
71 $t4
72 2
73
74 1
75 $t4
76 3
11/27/2018 CSCI2500: Computer Organization
https://submitty.cs.rpi.edu/index.php?semester=f18&course=csci2500&component=student&gradeable_id=hw5 13/18
77
78 1
79 $s1J
80 4
81
82 1
83
84 1
85
86 START OF SIMULATION
87
88 CPU Cycles ===> 1 2 3 4 5 6 7 8 9
89 and $s1,$s0,$s0 IF . . . . . . . .
90 sub $t2,$s0,$s5 . . . . . . . . .
91 sub $t4,$s3,70 . . . . . . . . .
92 or $t4,$s1,73 . . . . . . . . .
93 add $s1,$s1,$s4 . . . . . . . . .
94
95 CPU Cycles ===> 1 2 3 4 5 6 7 8 9
96 and $s1,$s0,$s0 IF ID . . . . . . .
97 sub $t2,$s0,$s5 . IF . . . . . . .
98 sub $t4,$s3,70 . . . . . . . . .
99 or $t4,$s1,73 . . . . . . . . .
100 add $s1,$s1,$s4 . . . . . . . . .
101
102 CPU Cycles ===> 1 2 3 4 5 6 7 8 9
103 and $s1,$s0,$s0 IF ID EX . . . . . .
104 sub $t2,$s0,$s5 . IF ID . . . . . .
105 sub $t4,$s3,70 . . IF . . . . . .
106 or $t4,$s1,73 . . . . . . . . .
107 add $s1,$s1,$s4 . . . . . . . . .
108
109 CPU Cycles ===> 1 2 3 4 5 6 7 8 9
110 and $s1,$s0,$s0 IF ID EX MEM . . . . .
111 sub $t2,$s0,$s5 . IF ID EX . . . . .
112 sub $t4,$s3,70 . . IF ID . . . . .
113 or $t4,$s1,73 . . . IF . . . . .
114 add $s1,$s1,$s4 . . . . . . . . .
115
116 CPU Cycles ===> 1 2 3 4 5 6 7 8 9
117 and $s1,$s0,$s0 IF ID EX MEM WB . . . .
118 sub $t2,$s0,$s5 . IF ID EX MEM . . . .
119 sub $t4,$s3,70 . . IF ID EX . . . .
120 or $t4,$s1,73 . . . IF ID . . . .
121 add $s1,$s1,$s4 . . . . IF . . . .
122
123 CPU Cycles ===> 1 2 3 4 5 6 7 8 9
124 and $s1,$s0,$s0 IF ID EX MEM WB . . . .
125 sub $t2,$s0,$s5 . IF ID EX MEM WB . . .
126 sub $t4,$s3,70 . . IF ID EX MEM . . .
127 or $t4,$s1,73 . . . IF ID EX . . .
128 add $s1,$s1,$s4 . . . . IF ID . . .
129
130 CPU Cycles ===> 1 2 3 4 5 6 7 8 9
131 and $s1,$s0,$s0 IF ID EX MEM WB . . . .
132 sub $t2,$s0,$s5 . IF ID EX MEM WB . . .
133 sub $t4,$s3,70 . . IF ID EX MEM WB . .
134 or $t4,$s1,73 . . . IF ID EX MEM . .
135 add $s1,$s1,$s4 . . . . IF ID EX . .
136
137 CPU Cycles ===> 1 2 3 4 5 6 7 8 9
138 and $s1,$s0,$s0 IF ID EX MEM WB . . . .
139 sub $t2,$s0,$s5 . IF ID EX MEM WB . . .
140 sub $t4,$s3,70 . . IF ID EX MEM WB . .
141 or $t4,$s1,73 . . . IF ID EX MEM WB .
142 add $s1,$s1,$s4 . . . . IF ID EX MEM .
143
144 CPU Cycles ===> 1 2 3 4 5 6 7 8 9
145 and $s1,$s0,$s0 IF ID EX MEM WB . . . .
146 sub $t2,$s0,$s5 . IF ID EX MEM WB . . .
147 sub $t4,$s3,70 . . IF ID EX MEM WB . .
11/27/2018 CSCI2500: Computer Organization
https://submitty.cs.rpi.edu/index.php?semester=f18&course=csci2500&component=student&gradeable_id=hw5 14/18
148 or $t4,$s1,73 . . . IF ID EX MEM WB .
149 add $s1,$s1,$s4 . . . . IF ID EX MEM WB
150
151 END OF SIMULATION
152
Expected STDOUT.txt
1 START OF SIMULATION
11/27/2018 CSCI2500: Computer Organization
https://submitty.cs.rpi.edu/index.php?semester=f18&course=csci2500&component=student&gradeable_id=hw5 15/18
2
3 CPU Cycles ===> 1 2 3 4 5 6 7 8 9
4 and $s1,$s0,$s0 IF . . . . . . . .
5 sub $t2,$s0,$s5 . . . . . . . . .
6 sub $t4,$s3,70 . . . . . . . . .
7 or $t4,$s1,73 . . . . . . . . .
8 add $s1,$s1,$s4 . . . . . . . . .
9
10 CPU Cycles ===> 1 2 3 4 5 6 7 8 9
11 and $s1,$s0,$s0 IF ID . . . . . . .
12 sub $t2,$s0,$s5 . IF . . . . . . .
13 sub $t4,$s3,70 . . . . . . . . .
14 or $t4,$s1,73 . . . . . . . . .
15 add $s1,$s1,$s4 . . . . . . . . .
16
17 CPU Cycles ===> 1 2 3 4 5 6 7 8 9
18 and $s1,$s0,$s0 IF ID EX . . . . . .
19 sub $t2,$s0,$s5 . IF ID . . . . . .
20 sub $t4,$s3,70 . . IF . . . . . .
21 or $t4,$s1,73 . . . . . . . . .
22 add $s1,$s1,$s4 . . . . . . . . .
23
24 CPU Cycles ===> 1 2 3 4 5 6 7 8 9
25 and $s1,$s0,$s0 IF ID EX MEM . . . . .
26 sub $t2,$s0,$s5 . IF ID EX . . . . .
27 sub $t4,$s3,70 . . IF ID . . . . .
28 or $t4,$s1,73 . . . IF . . . . .
29 add $s1,$s1,$s4 . . . . . . . . .
30
31 CPU Cycles ===> 1 2 3 4 5 6 7 8 9
32 and $s1,$s0,$s0 IF ID EX MEM WB . . . .
33 sub $t2,$s0,$s5 . IF ID EX MEM . . . .
34 sub $t4,$s3,70 . . IF ID EX . . . .
35 or $t4,$s1,73 . . . IF ID . . . .
36 add $s1,$s1,$s4 . . . . IF . . . .
37
38 CPU Cycles ===> 1 2 3 4 5 6 7 8 9
39 and $s1,$s0,$s0 IF ID EX MEM WB . . . .
40 sub $t2,$s0,$s5 . IF ID EX MEM WB . . .
41 sub $t4,$s3,70 . . IF ID EX MEM . . .
42 or $t4,$s1,73 . . . IF ID EX . . .
43 add $s1,$s1,$s4 . . . . IF ID . . .
44
45 CPU Cycles ===> 1 2 3 4 5 6 7 8 9
46 and $s1,$s0,$s0 IF ID EX MEM WB . . . .
47 sub $t2,$s0,$s5 . IF ID EX MEM WB . . .
48 sub $t4,$s3,70 . . IF ID EX MEM WB . .
49 or $t4,$s1,73 . . . IF ID EX MEM . .
50 add $s1,$s1,$s4 . . . . IF ID EX . .
51
52 CPU Cycles ===> 1 2 3 4 5 6 7 8 9
53 and $s1,$s0,$s0 IF ID EX MEM WB . . . .
54 sub $t2,$s0,$s5 . IF ID EX MEM WB . . .
55 sub $t4,$s3,70 . . IF ID EX MEM WB . .
56 or $t4,$s1,73 . . . IF ID EX MEM WB .
57 add $s1,$s1,$s4 . . . . IF ID EX MEM .
58
59 CPU Cycles ===> 1 2 3 4 5 6 7 8 9
60 and $s1,$s0,$s0 IF ID EX MEM WB . . . .
61 sub $t2,$s0,$s5 . IF ID EX MEM WB . . .
62 sub $t4,$s3,70 . . IF ID EX MEM WB . .
63 or $t4,$s1,73 . . . IF ID EX MEM WB .
64 add $s1,$s1,$s4 . . . . IF ID EX MEM WB
65
66 END OF SIMULATION
67
Visualize whitespace characters
Student STDERR.txt
11/27/2018 CSCI2500: Computer Organization
https://submitty.cs.rpi.edu/index.php?semester=f18&course=csci2500&component=student&gradeable_id=hw5 16/18
1
Details
Visualize whitespace characters
Student STDOUT.txt
1
2 0
3 $a0
4 1
5
6
7 0
8 $a0
9 1
10
11 1
12 $t8
13 1
14
15 1
16
17
18 0
19 $a0
20 1
21
22 1
23 $t8
24 1
25
26 1
27 $a0
28 2
29 $t4
30 1
31
32 START OF SIMULATION
33
34 CPU Cycles ===> 1 2 3 4 5 6 7 8 9
35 lw $t2,20($a0) IF . . . . . . . .
36 and $t4,$t8,$t5 . . . . . . . . .
37 sw $a0,48($t4) . . . . . . . . .
38
39 CPU Cycles ===> 1 2 3 4 5 6 7 8 9
40 lw $t2,20($a0) IF ID . . . . . . .
41 and $t4,$t8,$t5 . IF . . . . . . .
42 sw $a0,48($t4) . . . . . . . . .
43
44 CPU Cycles ===> 1 2 3 4 5 6 7 8 9
45 lw $t2,20($a0) IF ID EX . . . . . .
46 and $t4,$t8,$t5 . IF ID . . . . . .
47 sw $a0,48($t4) . . IF . . . . . .
48
49 CPU Cycles ===> 1 2 3 4 5 6 7 8 9
50 lw $t2,20($a0) IF ID EX MEM . . . . .
51 and $t4,$t8,$t5 . IF ID EX . . . . .
52 sw $a0,48($t4) . . IF ID . . . . .
53
54 CPU Cycles ===> 1 2 3 4 5 6 7 8 9
55 lw $t2,20($a0) IF ID EX MEM WB . . . .
56 and $t4,$t8,$t5 . IF ID EX MEM . . . .
57 sw $a0,48($t4) . . IF ID EX . . . .
58
59 CPU Cycles ===> 1 2 3 4 5 6 7 8 9
60 lw $t2,20($a0) IF ID EX MEM WB . . . .
61 and $t4,$t8,$t5 . IF ID EX MEM WB . . .
62 sw $a0,48($t4) . . IF ID EX MEM . . .
5 / 10 Test 7 ./a.out hw5-test07-stdin.txt
11/27/2018 CSCI2500: Computer Organization
https://submitty.cs.rpi.edu/index.php?semester=f18&course=csci2500&component=student&gradeable_id=hw5 17/18
63
64 CPU Cycles ===> 1 2 3 4 5 6 7 8 9
65 lw $t2,20($a0) IF ID EX MEM WB . . . .
66 and $t4,$t8,$t5 . IF ID EX MEM WB . . .
67 sw $a0,48($t4) . . IF ID EX MEM WB . .
68
69 END OF SIMULATION
70
Expected STDOUT.txt
1 START OF SIMULATION
2
3 CPU Cycles ===> 1 2 3 4 5 6 7 8 9
4 lw $t2,20($a0) IF . . . . . . . .
5 and $t4,$t8,$t5 . . . . . . . . .
6 sw $a0,48($t4) . . . . . . . . .
7
8 CPU Cycles ===> 1 2 3 4 5 6 7 8 9
9 lw $t2,20($a0) IF ID . . . . . . .
10 and $t4,$t8,$t5 . IF . . . . . . .
11 sw $a0,48($t4) . . . . . . . . .
12
13 CPU Cycles ===> 1 2 3 4 5 6 7 8 9
14 lw $t2,20($a0) IF ID EX . . . . . .
15 and $t4,$t8,$t5 . IF ID . . . . . .
16 sw $a0,48($t4) . . IF . . . . . .
17
18 CPU Cycles ===> 1 2 3 4 5 6 7 8 9
19 lw $t2,20($a0) IF ID EX MEM . . . . .
20 and $t4,$t8,$t5 . IF ID EX . . . . .
21 sw $a0,48($t4) . . IF ID . . . . .
22
23 CPU Cycles ===> 1 2 3 4 5 6 7 8 9
24 lw $t2,20($a0) IF ID EX MEM WB . . . .
25 and $t4,$t8,$t5 . IF ID EX MEM . . . .
26 nop . . IF ID * . . . .
11/27/2018 CSCI2500: Computer Organization
https://submitty.cs.rpi.edu/index.php?semester=f18&course=csci2500&component=student&gradeable_id=hw5 18/18
27 nop . . IF ID * . . . .
28 sw $a0,48($t4) . . IF ID ID . . . .
29
30 CPU Cycles ===> 1 2 3 4 5 6 7 8 9
31 lw $t2,20($a0) IF ID EX MEM WB . . . .
32 and $t4,$t8,$t5 . IF ID EX MEM WB . . .
33 nop . . IF ID * * . . .
34 nop . . IF ID * * . . .
35 sw $a0,48($t4) . . IF ID ID ID . . .
36
37 CPU Cycles ===> 1 2 3 4 5 6 7 8 9
38 lw $t2,20($a0) IF ID EX MEM WB . . . .
39 and $t4,$t8,$t5 . IF ID EX MEM WB . . .
40 nop . . IF ID * * * . .
41 nop . . IF ID * * * . .
42 sw $a0,48($t4) . . IF ID ID ID EX . .
43
44 CPU Cycles ===> 1 2 3 4 5 6 7 8 9
45 lw $t2,20($a0) IF ID EX MEM WB . . . .
46 and $t4,$t8,$t5 . IF ID EX MEM WB . . .
47 nop . . IF ID * * * . .
48 nop . . IF ID * * * . .
49 sw $a0,48($t4) . . IF ID ID ID EX MEM .
50
51 CPU Cycles ===> 1 2 3 4 5 6 7 8 9
52 lw $t2,20($a0) IF ID EX MEM WB . . . .
53 and $t4,$t8,$t5 . IF ID EX MEM WB . . .
54 nop . . IF ID * * * . .
55 nop . . IF ID * * * . .
56 sw $a0,48($t4) . . IF ID ID ID EX MEM WB
57
58 END OF SIMULATION
59
Visualize whitespace characters
Student STDERR.txt
1
3 / 10 Test 8 — Hidden Test Case 1 ./a.out hw5-test08-stdin.txt
3 / 10 Test 9 — Hidden Test Case 2 ./a.out hw5-test09-stdin.txt
4 / 10 Test 10 — Hidden Test Case 3 ./a.out hw5-test10-stdin.txt
4 / 10 Test 11 — Hidden Test Case 4 ./a.out hw5-test11-stdin.txt
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