Memory organisation
MAIN MEMORY
ORGANISATION
Bernhard Kainz (with thanks to A. Gopalan, N. Dulay and E.
Edwards)
b.kainz@imperial.ac.uk
mailto:b.kainz@imperial.ac.uk
Main Memory Organisation
• Addressing
• Byte Ordering
• Memory Modules and Chips
Main Memory (RAM)
• Each memory
location is W bits
long
• Normally a byte-
multiple, e.g. 16-
bits, 32-bits
• Memory Size
• R x W bits
• Access
• Can Read/Write
entire row or just
one byte at a time
R rows
W bits
101111101010101010111110
001010101011101010101011
011011010010100111011000
……..
101010101001001010111010
110110101000100010101010
010101011110001011111011
111011000000111110111111
Addressing
• Where in memory is the
16-bit value of 3?
• We need a scheme for uniquely
identifying every memory
location
• ADDRESSING
Identify memory locations with a
positive number called the
(memory) address
Main Memory
0110 1101 1010 1101
0000 0000 0000 0011
0000 0000 0000 0000
1111 1111 1111 1111
0000 0000 0000 0000
1001 1010 1010 0010
0000 0000 0000 0000
1111 1111 1111 1110
Word Addressing
Main Memory
0
1
2
3
4
5
6
7
Address
0110 1101 1010 1101
0000 0000 0000 0011
0000 0000 0000 0000
1111 1111 1111 1111
0000 0000 0000 0000
1001 1010 1010 0010
0000 0000 0000 0000
1111 1111 1111 1110
Addresses
entire row
Byte Addressing
Main Memory
0
2
4
6
8
10
12
14
Word Address
• With byte
addressing, every
byte in main
memory has an
address
• In this example
which is byte 0 and
which is byte 1?
0110 1101 1010 1101
0000 0000 0000 0011
0000 0000 0000 0000
1111 1111 1111 1111
0000 0000 0000 0000
1001 1010 1010 0010
0000 0000 0000 0000
1111 1111 1111 1110
Byte Addressing
• Two formats
• Big Endian
• Stores Most Significant Byte first
• Motorola 6800, IBM POWER, SPARC, System/360, ARM
• Little Endian
• Stores Least Significant Byte first
• x-86, ARM, DEC Alpha, VAX, PDP-11
Byte Addressing (Big Endian)
Main Memory
1
3
5
7
9
11
13
15
Byte Address
0
2
4
6
8
10
12
14
Byte Address
0110 1101 1010 1101
0000 0000 0000 0011
0000 0000 0000 0000
1111 1111 1111 1111
0000 0000 0000 0000
1001 1010 1010 0010
0000 0000 0000 0000
1111 1111 1111 1110
Byte Addressing (Little Endian)
Main Memory
0
2
4
6
8
10
12
14
Byte Address
1
3
5
7
9
11
13
15
Byte Address
0110 1101 1010 1101
0000 0000 0000 0011
0000 0000 0000 0000
1111 1111 1111 1111
0000 0000 0000 0000
1001 1010 1010 0010
0000 0000 0000 0000
1111 1111 1111 1110
Byte Ordering – Multibyte Data Items
Most Significant Byte (MSB) Least Significant Byte
(LSB)
VALUE
(8-byte)
+0 +1 +2 +3 +4 +5 +6 +7Byte Addresses
Least Significant Byte (LSB) Most Significant Byte (MSB)
VALUE
(8-byte)
+0 +1 +2 +3 +4 +5 +6 +7Byte Addresses
Big Endian
Little Endian
Example 1: 16-bit Integer (View 1)
• 16-bit integer ‘5’ stored at memory address 24
Big Endian
Little Endian
24Byte Addresses 25
0000 0000 0000 0101
24Byte Addresses 25
0000 0101 0000 0000
Example 1: 16-bit Integer (View 2)
• 16-bit integer ‘5’ stored at memory address 24
Big Endian
Little Endian
24Byte Addresses 25
0000 0000 0000 0101
25Byte Addresses 24
0000 0000 0000 0101
Word address 24
Word address 24
Example 2: 32-bit Value (View 1)
• 32-bit hex value 54 BC FE 30 stored at memory address 24
Big Endian
Little Endian
Byte Addresses 24 25
0101 0100 1011 1100 1111 1110 0011 0000
26 27
0011 0000 1111 1110 1011 1100 0101 0100
Byte Addresses 24 25 26 27
54 30FEBC
54BCFE30
Example 2: 32-bit Value (View 2)
• 32-bit hex value 54 BC FE 30 stored at memory address 24
Big Endian
Little Endian
Byte Addresses 24 25
0101 0100 1011 1100 1111 1110 0011 0000
26 27
0101 0100 1011 1100 1111 1110 0011 0000
Byte Addresses 27 26 25 24
54 30FEBC
30FE54 BC
Example 3: ASCII String (View 1)
• String “JIM BLOGGS” stored at memory address 24
• Treat a string as an array of (ASCII) bytes
• Each byte is considered individually so no difference – only when
multi-byte (such as Unicode where a character is 2-bytes)
Big Endian
J
24
I
25
M
26 27
B
28
L
29
O
30
G
31Byte Addresses
G
32
S
33
Little Endian
S G G O L B M
24 25 26 27 28 29 30 31Byte Addresses
I J
32 33
Example 3: ASCII String (View 2)
• String “JIM BLOGGS” stored at memory address 24
• Treat a string as an array of (ASCII) bytes
• Each byte is considered individually so no difference – only when
multi-byte (such as Unicode where a character is 2-bytes)
Big Endian
J
24
I
25
M
26 27
B
28
L
29
O
30
G
31Byte Addresses
G
32
S
33
Little Endian
J I M B L O G
2425262728293031Byte Addresses
G S
3233
Potential Problems
• How do we transfer a multi-byte value (e.g. a 32-bit
integer) from a Big-Endian memory to a Little-Endian
memory and vice-versa?
• How do we transfer an ASCII string value (e.g. “JIM
BLOGGS”) from a Big-Endian memory to a Little-Endian
memory and vice-versa?
• How do we transfer an object which holds both types of
values above and vice-versa?
• Why is it necessary?
Question
• What is the maximum amount of memory we can have in
a 32-bit machine with byte addressing?
• Each address pertains to one byte
• Number of available addresses = 232
• Recall: Kilo = 210 (103), Mega = 220 (106) and Giga = 230 (109)
• Hence, we have 232 = 22 x 230 = 4 * 230 bytes = 4 Gigabytes = 4GB
• How much memory for 64-bit addressing?
Memory Modules and Chips
1GB (256M x 32-bit) Memory
256M
rows
32 bits
1GB (256M x 32-bit) Memory
• Two 512MB memory modules
• Each module has two 128M x 16-bit RAM Chips
16 16
128M
Module 0
512MB
128M
Module 1
512MB
1GB (256M x 32-bit) Memory
• Two 512MB memory modules
• Each module has four 128M x 8-bit RAM Chips
8 8
128M
Module 0
512MB
8 8
128M
Module 1
512MB
1GB (256M x 32-bit) Memory
• Four 256MB memory modules
• Each module has two 64M x 16-bit RAM Chips
16 16
Module 0
256MB
64M
Module 1
256MB
Module 2
256MB
Module 3
256MB
64M
64M
64M
1GB (256M x 32-bit) Memory
• Four 256MB memory modules
• Each module has four 64M x 8-bit RAM Chips
8
Module 0
256MB
Module 1
256MB
Module 2
256MB
Module 3
256MB
64M
8 8 8
64M
64M
64M
Memory Interleaving
• Example:
• Memory = 4M words, each word = 32-bits
• Built with 4 x 1M x 32-bit memory modules
• For 4M words we need 22 bits for an address
• 22 bits = 2 bits (to select Modules) + 20 bits (to select row within
Module)
Row within Module
220
Low-Order Interleave
High-Order Interleave
Module
Row within Module
2 20
Module
High-Order Interleave
Address
Decimal
0 00 0000 0000 0000 0000 0000 Module=0 Row=0
1 00 0000 0000 0000 0000 0001 Module=0 Row=1
2 00 0000 0000 0000 0000 0010 Module=0 Row=2
3 00 0000 0000 0000 0000 0011 Module=0 Row=3
4 00 0000 0000 0000 0000 0100 Module=0 Row=4
5 00 0000 0000 0000 0000 0101 Module=0 Row=5
…
220-1 00 1111 1111 1111 1111 1111 Module=0 Row=220-1
220 01 0000 0000 0000 0000 0000 Module=1 Row=0
220+1 01 0000 0000 0000 0000 0001 Module=1 Row=1
Address
Binary
High-Order Interleave
• Good if Modules can be accessed independently by
different units, e.g. by the CPU and a Hard Disk (or a
second CPU) AND the units use different Modules
• Parallel operation Higher Performance
Hard Disk
Module 0 Module 1 Module 2 Module 3
CPU1 CPU2
Low-Order Interleave
Address
Decimal
0 00 0000 0000 0000 0000 0000 Module=0 Row=0
1 00 0000 0000 0000 0000 0001 Module=1 Row=0
2 00 0000 0000 0000 0000 0010 Module=2 Row=0
3 00 0000 0000 0000 0000 0011 Module=3 Row=0
4 00 0000 0000 0000 0000 0100 Module=0 Row=1
5 00 0000 0000 0000 0000 0101 Module=1 Row=1
…
220-1 00 1111 1111 1111 1111 1111 Module=3 Row=218-1
220 01 0000 0000 0000 0000 0000 Module=0 Row=218
220+1 01 0000 0000 0000 0000 0001 Module=1 Row=218
…
Address
Binary
Low-Order Interleave
• Good if the CPU (or other unit) can request multiple adjacent memory
locations
• Since adjacent memory locations lie in different Modules an
“advanced” memory system can perform the accesses in parallel
• Such adjacent accesses often occur in practice, e.g.
i. Elements in an array, e.g.. Array[N], Array[N+1], Array[N+2], ….
ii. Instructions in a Programs, InstructionN, InstructionN+1,…
• In the above situations, an “advanced” CPU can pre-fetch the
adjacent memory locations higher performance
Module 0 Module 1 Module 2 Module 3
CPU