程序代写代做代考 arm assembly mips cache compiler Chapter …

Chapter …

COMPUTER ORGANIZATION AND DESIGN
The Hardware/Software Interface

5th

Edition

Chapter 4

The Processor

Chapter 4 — The Processor — 2

Introduction

 CPU performance factors
 Instruction count

 Determined by ISA and compiler

 CPI and Cycle time
 Determined by CPU hardware

 We will examine two MIPS implementations
 A simplified version

 A more realistic pipelined version

 Simple subset, shows most aspects
 Memory reference: lw, sw

 Arithmetic/logical: add, sub, and, or, slt

 Control transfer: beq, j

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Chapter 4 — The Processor — 3

Instruction Execution

 PC  instruction memory, fetch instruction

 Register numbers  register file, read registers

 Depending on instruction class

 Use ALU to calculate

 Arithmetic result

 Memory address for load/store

 Branch target address

 Access data memory for load/store

 PC  target address or PC + 4

Chapter 4 — The Processor — 4

CPU Overview
(Need __________)

(Need ________ input)

Chapter 4 — The Processor — 5

Multiplexers

 Can’t just join

wires together

 Use multiplexers

Chapter 4 — The Processor — 6

Control

Chapter 4 — The Processor — 7

Logic Design Basics
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 Information encoded in binary

 Low voltage = 0, High voltage = 1

 One wire per bit

 Multi-bit data encoded on multi-wire buses

 Combinational element

 Operate on data

 Output is a function of input

 State (sequential) elements

 Store information

(Given the same input, always produces the same ______)

(ex) memory, register

(Has at least two inputs (____ and _____) and one output (data stored in the previous _____))

Chapter 4 — The Processor — 8

Combinational Elements

 AND-gate

 Y = A & B

A

B
Y

I0

I1
Y

M

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S

 Multiplexer

 Y = S ? I1 : I0

A

B

Y +

A

B

Y ALU

F

 Adder

 Y = A + B

 Arithmetic/Logic Unit

 Y = F(A, B)

Chapter 4 — The Processor — 9

Sequential Elements

 Register: stores data in a circuit

 Uses a clock signal to determine when to

update the stored value

 Edge-triggered: update when Clk changes

from 0 to 1

D

Clk

Q

Clk

D

Q

(positive(rising) edge or negative(falling) edge; _____-triggered)

Chapter 4 — The Processor — 10

Sequential Elements

 Register with write control

 Only updates on clock edge when write

control input is 1

 Used when stored value is required later

D

Clk

Q

Write

Write

D

Q

Clk

Chapter 4 — The Processor — 11

Clocking Methodology

 Combinational logic transforms data during
clock cycles

 Between clock edges

 Input from state elements, output to state
element

 Longest delay determines clock period

Chapter 4 — The Processor — 12

Building a Datapath

 Datapath

 Elements that process data and addresses

in the CPU

 Registers, ALUs, mux’s, memories, …

 We will build a MIPS datapath

incrementally

 Refining the overview design

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Chapter 4 — The Processor — 13

Instruction Fetch

32-bit

register

Increment by

4 for next

instruction

(Only add operation)

Chapter 4 — The Processor — 14

R-Format Instructions

 Read two register operands

 Perform arithmetic/logical operation

 Write register result (Read and Write can occur in one cycle. How?)

Chapter 4 — The Processor — 15

Load/Store Instructions

 Read register operands

 Calculate address using 16-bit offset
 Use ALU, but sign-extend offset

 Load: Read memory and update register

 Store: Write register value to memory

(Does sign-extension change the value?)

Chapter 4 — The Processor — 16

Branch Instructions

 Read register operands

 Compare operands

 Use ALU, subtract and check Zero output

 Calculate target address

 Sign-extend displacement

 Shift left 2 places (word displacement)

 Add to PC + 4

 Already calculated by instruction fetch

Chapter 4 — The Processor — 17

Branch Instructions

Just

re-routes

wires

Sign-bit wire

replicated

(Actually what operation?)

(What does this mean?)

Chapter 4 — The Processor — 18

Composing the Elements

 First-cut data path does an instruction in

one clock cycle

 Each datapath element can only do one

function at a time

 Hence, we need separate instruction and data

memories

 Use multiplexers where alternate data

sources are used for different instructions

Chapter 4 — The Processor — 19

R-Type/Load/Store Datapath
(ex) add $s0, $s1, $s2

(__)

(__)

(__)
( _ )

( _ )

(ex) ld $t0, 20($s3)

(__)

( _ )

( _ )

( _ )

( _ )

Chapter 4 — The Processor — 20

Full Datapath
(ex) beq $t1, $t2, loop; ($t1 = 1; $t2 = 2)

( _ )

(__)

( _ )

(___) ( _ )

( _ )

( _ )

Chapter 4 — The Processor — 21

ALU Control

 ALU used for

 Load/Store: F = add

 Branch: F = subtract

 R-type: F depends on funct field

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ALU control Function

0000 AND

0001 OR

0010 add

0110 subtract

0111 set-on-less-than

1100 NOR

Chapter 4 — The Processor — 22

ALU Control

 Assume 2-bit ALUOp derived from opcode

 Combinational logic derives ALU control

opcode ALUOp Operation funct ALU function ALU control

lw 00 load word XXXXXX add 0010

sw 00 store word XXXXXX add 0010

beq 01 branch equal XXXXXX subtract 0110

R-type 10 add 100000 add 0010

subtract 100010 subtract 0110

AND 100100 AND 0000

OR 100101 OR 0001

set-on-less-than 101010 set-on-less-than 0111

(Multiple level control: Instruction  ALUOp  ___________ )

(Adv: reduction of the size of CU; ______)

Chapter 4 — The Processor — 23

The Main Control Unit

 Control signals derived from instruction

0 rs rt rd shamt funct

31:26 5:0 25:21 20:16 15:11 10:6

35 or 43 rs rt address

31:26 25:21 20:16 15:0

4 rs rt address

31:26 25:21 20:16 15:0

R-type

Load/

Store

Branch

opcode always

read

read,

except

for load

write for

R-type

and load

sign-extend

and add

Chapter 4 — The Processor — 24

Datapath With Control

Chapter 4 — The Processor — 25

R-Type Instruction
(ex) add $s2, $s4, $s5

Chapter 4 — The Processor — 26

Load Instruction
(ex) ld $t0, 20($s3)

Chapter 4 — The Processor — 27

Branch-on-Equal Instruction
(ex) beq $t1, $t2, loop; ($t1 = 1; $t2 = 2)

Chapter 4 — The Processor — 28

Implementing Jumps

 Jump uses word address

 Update PC with concatenation of

 Top 4 bits of old PC

 26-bit jump address

 00

 Need an extra control signal decoded from

opcode

2 address

31:26 25:0

Jump

Chapter 4 — The Processor — 29

Datapath With Jumps Added

Chapter 4 — The Processor — 30

Performance Issues

 Longest delay determines clock period

 Critical path: load instruction

 Instruction memory  register file  ALU 

data memory  register file

 Not feasible to vary period for different

instructions

 Violates design principle

 Making the common case fast

 We will improve performance by pipelining

Chapter 4 — The Processor — 31

Pipelining Analogy

 Pipelined laundry: overlapping execution

 Parallelism improves performance

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 Four loads:

 Speedup

= 8/3.5 = 2.3

 Non-stop:

 Speedup

= 2n/(0.5n+1.5) ≈ 4

= number of stages

Chapter 4 — The Processor — 32

MIPS Pipeline

 Five stages, one step per stage

1. IF: Instruction fetch from memory

2. ID: Instruction decode & register read

3. EX: Execute operation or calculate address

4. MEM: Access memory operand

5. WB: Write result back to register

Chapter 4 — The Processor — 33

Pipeline Performance

 Assume time for stages is

 100ps for register read or write

 200ps for other stages

 Compare pipelined datapath with single-cycle

datapath

Instr Instr fetch Register

read

ALU op Memory

access

Register

write

Total time

lw 200ps 100 ps 200ps 200ps 100 ps 800ps

sw 200ps 100 ps 200ps 200ps 700ps

R-format 200ps 100 ps 200ps 100 ps 600ps

beq 200ps 100 ps 200ps 500ps

Chapter 4 — The Processor — 34

Pipeline Performance

Single-cycle (Tc= 800ps)

Pipelined (Tc= 200ps)

(Time between 1st and 4th inst: _____________)

(Time between 1st and 4th inst: ____________)

Chapter 4 — The Processor — 35

Pipeline Speedup

 If all stages are balanced

 i.e., all take the same time

 Time between instructionspipelined

= Time between instructionsnonpipelined

Number of stages

 If not balanced, speedup is less

 Speedup due to increased throughput

 Latency (time for each instruction) does not

decrease

Chapter 4 — The Processor — 36

Pipelining and ISA Design

 MIPS ISA designed for pipelining

 All instructions are 32-bits
 Easier to fetch and decode in one cycle

 c.f. x86: 1- to 17-byte instructions

 Few and regular instruction formats
 Can decode and read registers in one step

 Load/store addressing
 Can calculate address in 3rd stage, access memory

in 4th stage

 Alignment of memory operands
 Memory access takes only one cycle

Chapter 4 — The Processor — 37

Hazards

 Situations that prevent starting the next
instruction in the next cycle

 Structure hazards

 A required resource is busy

 Data hazard

 Need to wait for previous instruction to
complete its data read/write

 Control hazard

 Deciding on control action depends on
previous instruction

Chapter 4 — The Processor — 38

Structure Hazards

 Conflict for use of a resource

 In MIPS pipeline with a single memory

 Load/store requires data access

 Instruction fetch would have to stall for that

cycle

 Would cause a pipeline “bubble”

 Hence, pipelined datapaths require

separate instruction/data memories

 Or separate instruction/data caches

Chapter 4 — The Processor — 39

Data Hazards

 An instruction depends on completion of

data access by a previous instruction

 add $s0, $t0, $t1
sub $t2, $s0, $t3

Chapter 4 — The Processor — 40

Forwarding (aka Bypassing)

 Use result when it is computed

 Don’t wait for it to be stored in a register

 Requires extra connections in the datapath

Chapter 4 — The Processor — 41

Load-Use Data Hazard

 Can’t always avoid stalls by forwarding

 If value not computed when needed

 Can’t forward backward in time!

Chapter 4 — The Processor — 42

Code Scheduling to Avoid Stalls

 Reorder code to avoid use of load result in

the next instruction

 C code for A = B + E; C = B + F;

lw $t1, 0($t0)

lw $t2, 4($t0)

add $t3, $t1, $t2

sw $t3, 12($t0)

lw $t4, 8($t0)

add $t5, $t1, $t4

sw $t5, 16($t0)

stall

stall

lw $t1, 0($t0)

lw $t2, 4($t0)

lw $t4, 8($t0)

add $t3, $t1, $t2

sw $t3, 12($t0)

add $t5, $t1, $t4

sw $t5, 16($t0)

11 cycles 13 cycles

(________ ______)

Chapter 4 — The Processor — 43

Control Hazards

 Branch determines flow of control

 Fetching next instruction depends on branch
outcome

 Pipeline can’t always fetch correct instruction
 Still working on ID stage of branch

 In MIPS pipeline

 Need to compare registers and compute
target early in the pipeline

 Add hardware to do it in ID stage

Chapter 4 — The Processor — 44

Stall on Branch

 Wait until branch outcome determined

before fetching next instruction

(Need an assumption that extra HW is used to _______ the branch, calculate branch

________, and update ____ in the 2nd stage)

(If Branch is 17%, what is CPI? _________________)

Chapter 4 — The Processor — 45

Branch Prediction

 Longer pipelines can’t readily determine

branch outcome early

 Stall penalty becomes unacceptable

 Predict outcome of branch

 Only stall if prediction is wrong

 In MIPS pipeline

 Can predict branches not taken

 Fetch instruction after branch, with no delay

Chapter 4 — The Processor — 46

MIPS with Predict Not Taken

Prediction

correct

Prediction

incorrect

Chapter 4 — The Processor — 47

More-Realistic Branch Prediction

 Static branch prediction

 Based on typical branch behavior

 Example: loop and if-statement branches

 Predict backward branches taken

 Predict forward branches not taken

 Dynamic branch prediction

 Hardware measures actual branch behavior

 e.g., record recent history of each branch

 Assume future behavior will continue the trend

 When wrong, stall while re-fetching, and update history
(Need to make sure ________ guessed branch have no effect)

(Branch _________ buffer)

(More than ___% accuracy)

(The deeper the pipeline, the ______ the branch penalty)

(________ branch)

Chapter 4 — The Processor — 48

Pipeline Summary

 Pipelining improves performance by

increasing instruction throughput

 Executes multiple instructions in parallel

 Each instruction has the same latency

 Subject to hazards

 Structure, data, control

 Instruction set design affects complexity of

pipeline implementation

The BIG Picture

(Mostly with __ unit) (Mostly with ________ unit) (_____)

Chapter 4 — The Processor — 49

MIPS Pipelined Datapath
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WB

MEM

Right-to-left

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hazards

Chapter 4 — The Processor — 50

Pipeline registers

 Need registers between stages

 To hold information produced in previous cycle
(No ________ after WB stage since all instructions update register file, memory, or PC)

(__-bit wide) (___-bit) (__-bit) (__-bit)

Chapter 4 — The Processor — 51

Pipeline Operation

 Cycle-by-cycle flow of instructions through

the pipelined datapath

 “Single-clock-cycle” pipeline diagram

 Shows pipeline usage in a single cycle

 Highlight resources used

 c.f. “multi-clock-cycle” diagram

 Graph of operation over time

 We’ll look at “single-clock-cycle” diagrams

for load & store

Chapter 4 — The Processor — 52

IF for Load, Store, …

Chapter 4 — The Processor — 53

ID for Load, Store, …

Chapter 4 — The Processor — 54

EX for Load

Chapter 4 — The Processor — 55

MEM for Load

Chapter 4 — The Processor — 56

WB for Load

Wrong

register

number

(Why?)

Chapter 4 — The Processor — 57

Corrected Datapath for Load

Chapter 4 — The Processor — 58

EX for Store

(Why thicker

line?)

Chapter 4 — The Processor — 59

MEM for Store

Chapter 4 — The Processor — 60

WB for Store

(Any operation?)

Chapter 4 — The Processor — 61

Multi-Cycle Pipeline Diagram

 Form showing resource usage

Chapter 4 — The Processor — 62

Multi-Cycle Pipeline Diagram

 Traditional form

Chapter 4 — The Processor — 63

Single-Cycle Pipeline Diagram

 State of pipeline in a given cycle (Which cycle?)

Chapter 4 — The Processor — 64

Pipelined Control (Simplified)

(No write

control. Why?)

Chapter 4 — The Processor — 65

Pipelined Control

 Control signals derived from instruction

 As in single-cycle implementation

Chapter 4 — The Processor — 66

Pipelined Control

Chapter 4 — The Processor — 67

Data Hazards in ALU Instructions

 Consider this sequence:

sub $2, $1,$3
and $12,$2,$5
or $13,$6,$2
add $14,$2,$2
sw $15,100($2)

 We can resolve hazards with forwarding

 How do we detect when to forward?

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Chapter 4 — The Processor — 68

Dependencies & Forwarding

(____ hazard when go backward)

Chapter 4 — The Processor — 69

Detecting the Need to Forward

 Pass register numbers along pipeline
 e.g., ID/EX.RegisterRs = register number for Rs

sitting in ID/EX pipeline register

 ALU operand register numbers in EX stage
are given by
 ID/EX.RegisterRs, ID/EX.RegisterRt

 Data hazards when
1a. EX/MEM.RegisterRd = ID/EX.RegisterRs

1b. EX/MEM.RegisterRd = ID/EX.RegisterRt

2a. MEM/WB.RegisterRd = ID/EX.RegisterRs

2b. MEM/WB.RegisterRd = ID/EX.RegisterRt

Fwd from

EX/MEM

pipeline reg

Fwd from

MEM/WB

pipeline reg
sub $2, $1,$3
and $12,$2,$5
or $13,$6,$2
add $14,$2,$2

sw $15,100($2)

(Type __)

(Type __)

Chapter 4 — The Processor — 70

Detecting the Need to Forward

 But only if forwarding instruction will write

to a register!

 EX/MEM.RegWrite, MEM/WB.RegWrite

 And only if Rd for that instruction is not

$zero

 EX/MEM.RegisterRd ≠ 0,

MEM/WB.RegisterRd ≠ 0

Chapter 4 — The Processor — 71

Forwarding Paths

Chapter 4 — The Processor — 72

Forwarding Conditions

 EX hazard

 if (EX/MEM.RegWrite and (EX/MEM.RegisterRd ≠ 0)

and (EX/MEM.RegisterRd = ID/EX.RegisterRs))

ForwardA = 10

 if (EX/MEM.RegWrite and (EX/MEM.RegisterRd ≠ 0)

and (EX/MEM.RegisterRd = ID/EX.RegisterRt))

ForwardB = 10

 MEM hazard

 if (MEM/WB.RegWrite and (MEM/WB.RegisterRd ≠ 0)

and (MEM/WB.RegisterRd = ID/EX.RegisterRs))

ForwardA = 01

 if (MEM/WB.RegWrite and (MEM/WB.RegisterRd ≠ 0)

and (MEM/WB.RegisterRd = ID/EX.RegisterRt))

ForwardB = 01

Chapter 4 — The Processor — 73

Double Data Hazard

 Consider the sequence:

add $1,$1,$2
add $1,$1,$3
add $1,$1,$4

 Both hazards occur

 Want to use the most recent

 Revise MEM hazard condition

 Only fwd if EX hazard condition isn’t true
(Since the data of EX stage is more _______ and it must be _________)

Chapter 4 — The Processor — 74

Revised Forwarding Condition

 MEM hazard

 if (MEM/WB.RegWrite and (MEM/WB.RegisterRd ≠ 0)

and not (EX/MEM.RegWrite and (EX/MEM.RegisterRd ≠ 0)

and (EX/MEM.RegisterRd = ID/EX.RegisterRs))

and (MEM/WB.RegisterRd = ID/EX.RegisterRs))

ForwardA = 01

 if (MEM/WB.RegWrite and (MEM/WB.RegisterRd ≠ 0)

and not (EX/MEM.RegWrite and (EX/MEM.RegisterRd ≠ 0)

and (EX/MEM.RegisterRd = ID/EX.RegisterRt))

and (MEM/WB.RegisterRd = ID/EX.RegisterRt))

ForwardB = 01
lw $15,100($2)
sw $15,104($2)

or $13,$6,$2
add $14,$2,$2

sw $15,100($2)

Chapter 4 — The Processor — 75

Datapath with Forwarding

Chapter 4 — The Processor — 76

Load-Use Data Hazard

Need to stall

for one cycle

Chapter 4 — The Processor — 77

Load-Use Hazard Detection

 Check when using instruction is decoded
in ID stage

 ALU operand register numbers in ID stage
are given by

 IF/ID.RegisterRs, IF/ID.RegisterRt

 Load-use hazard when

 ID/EX.MemRead and
((ID/EX.RegisterRt = IF/ID.RegisterRs) or
(ID/EX.RegisterRt = IF/ID.RegisterRt))

 If detected, stall and insert bubble

(Check if the instruction is ____)

Chapter 4 — The Processor — 78

How to Stall the Pipeline

 Force control values in ID/EX register

to 0

 EX, MEM and WB do nop (no-operation)

 Prevent update of PC and IF/ID register

 Using instruction is decoded again

 Following instruction is fetched again

 1-cycle stall allows MEM to read data for lw

 Can subsequently forward to EX stage

Chapter 4 — The Processor — 79

Stall/Bubble in the Pipeline

Stall inserted

here

Chapter 4 — The Processor — 80

Stall/Bubble in the Pipeline

Or, more

accurately…

Chapter 4 — The Processor — 81

Datapath with Hazard Detection

Chapter 4 — The Processor — 82

Stalls and Performance

 Stalls reduce performance

 But are required to get correct results

 Compiler can arrange code to avoid

hazards and stalls

 Requires knowledge of the pipeline structure

The BIG Picture

Chapter 4 — The Processor — 83

Branch Hazards

 If branch outcome determined in MEM

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(Set control

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Chapter 4 — The Processor — 84

Reducing Branch Delay

 Move hardware to determine outcome to ID

stage

 Target address adder

 Register comparator

 Example: branch taken
36: sub $10, $4, $8
40: beq $1, $3, 7
44: and $12, $2, $5
48: or $13, $2, $6
52: add $14, $4, $2
56: slt $15, $6, $7

72: lw $4, 50($7)

(Branch address: ______________)

Chapter 4 — The Processor — 85

Example: Branch Taken

(________ IF/ID register) 36: sub $10, $4, $8
40: beq $1, $3, 7
44: and $12, $2, $5
48: or $13, $2, $6
52: add $14, $4, $2
56: slt $15, $6, $7

72: lw $4, 50($7)

Chapter 4 — The Processor — 86

Example: Branch Taken

Chapter 4 — The Processor — 87

Data Hazards for Branches

 If a comparison register is a destination of

2nd or 3rd preceding ALU instruction

IF ID EX MEM WB

IF ID EX MEM WB

IF ID EX MEM WB

IF ID EX MEM WB

add $4, $5, $6

add $1, $2, $3

beq $1, $4, target

 Can resolve using forwarding

Chapter 4 — The Processor — 88

Data Hazards for Branches

 If a comparison register is a destination of

preceding ALU instruction or 2nd preceding

load instruction

 Need 1 stall cycle

beq stalled

IF ID EX MEM WB

IF ID EX MEM WB

IF ID

ID EX MEM WB

add $4, $5, $6

lw $1, addr

beq $1, $4, target

Chapter 4 — The Processor — 89

Data Hazards for Branches

 If a comparison register is a destination of

immediately preceding load instruction

 Need 2 stall cycles

beq stalled

IF ID EX MEM WB

IF ID

ID

ID EX MEM WB

beq stalled

lw $1, addr

beq $1, $0, target

Chapter 4 — The Processor — 90

Dynamic Branch Prediction

 In deeper and superscalar pipelines, branch

penalty is more significant

 Use dynamic prediction

 Branch prediction buffer (aka branch history table)

 Indexed by recent branch instruction addresses

 Stores outcome (taken/not taken)

 To execute a branch

 Check table, expect the same outcome

 Start fetching from fall-through or target

 If wrong, flush pipeline and flip prediction

(______ portion of the address)

Chapter 4 — The Processor — 91

1-Bit Predictor: Shortcoming

 Inner loop branches mispredicted twice!

outer: …

inner: …

beq …, …, inner

beq …, …, outer

 Mispredict as taken on last iteration of

inner loop

 Then mispredict as not taken on first

iteration of inner loop next time around

(ex) 9 taken, and then not taken. Then, repeat.

(1 2 3 4 5 6 7 8 9 10 11 12 …)

( _ _ _ T T T T T _ __ _ _ … )

(PT __ __ __ __ PT PT PT __ __ ___ ___ …)

( _ _ o o o o o o o _ _ o … )

(__% accuracy)

Chapter 4 — The Processor — 92

2-Bit Predictor

 Only change prediction on two successive

mispredictions

(Accuracy is __%)

(1 2 3 4 5 6 7 8 9 10 11 12 …)

(PT PT PT PT PT PT PT PT __ __ __ __ …)

(T T T T T T T T __ __ __ __… )

(o o o o o o o o _ _ _ _ … )

Chapter 4 — The Processor — 93

Branch Delay Slot

 Delayed branch by compiler

(Best choice if available) (Preferred when branch

____ is highly likely;

need to make sure OK

when _________)

(Preferred when branch

_________ is highly

likely; need to make sure

OK when ____)

Chapter 4 — The Processor — 94

Calculating the Branch Target

 Even with predictor, still need to calculate

the target address

 1-cycle penalty for a taken branch

 Branch target buffer

 Cache of target addresses

 Indexed by PC when instruction fetched

 If hit and instruction is branch predicted taken, can

fetch target immediately

(Not prediction)

(Correlating predictor: decision based on ____ behavior and global behavior of ______ branches)

(Tournament branch predictor: ________ between the predictor with local behavior and global behavior)

Chapter 4 — The Processor — 95

Exceptions and Interrupts

 “Unexpected” events requiring change

in flow of control

 Different ISAs use the terms differently

 Exception

 Arises within the CPU

 e.g., undefined opcode, overflow, syscall, …

 Interrupt

 From an external I/O controller

 Dealing with them without sacrificing

performance is hard

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Chapter 4 — The Processor — 96

Handling Exceptions

 In MIPS, exceptions managed by a System
Control Coprocessor (CP0)

 Save PC of offending (or interrupted) instruction
 In MIPS: Exception Program Counter (EPC)

 Save indication of the problem
 In MIPS: Cause register

 We’ll assume 1-bit
 0 for undefined opcode, 1 for overflow

 Jump to handler at 8000 0180

Chapter 4 — The Processor — 97

An Alternate Mechanism

 Vectored Interrupts

 Handler address determined by the cause

 Example:

 Undefined opcode: C000 0000

 Overflow: C000 0020

 …: C000 0040

 Instructions either

 Deal with the interrupt, or

 Jump to real handler

Chapter 4 — The Processor — 98

Handler Actions

 Read cause, and transfer to relevant
handler

 Determine action required

 If restartable

 Take corrective action

 use EPC to return to program

 Otherwise

 Terminate program

 Report error using EPC, cause, …

Chapter 4 — The Processor — 99

Exceptions in a Pipeline

 Another form of control hazard

 Consider overflow on add in EX stage
add $1, $2, $1

 Prevent $1 from being clobbered

 Complete previous instructions

 Flush add and subsequent instructions

 Set Cause and EPC register values

 Transfer control to handler

 Similar to mispredicted branch

 Use much of the same hardware

Chapter 4 — The Processor — 100

Pipeline with Exceptions

(ALU _______ signal

is an input to the CU)

Chapter 4 — The Processor — 101

Exception Properties

 Restartable exceptions

 Pipeline can flush the instruction

 Handler executes, then returns to the

instruction

 Refetched and executed from scratch

 PC saved in EPC register

 Identifies causing instruction

 Actually PC + 4 is saved

 Handler must adjust

Chapter 4 — The Processor — 102

Exception Example

 Exception on add in
40 sub $11, $2, $4
44 and $12, $2, $5
48 or $13, $2, $6
4C add $1, $2, $1
50 slt $15, $6, $7
54 lw $16, 50($7)

 Handler
80000180 sw $25, 1000($0)
80000184 sw $26, 1004($0)

Chapter 4 — The Processor — 103

Exception Example

Chapter 4 — The Processor — 104

Exception Example

Chapter 4 — The Processor — 105

Multiple Exceptions

 Pipelining overlaps multiple instructions

 Could have multiple exceptions at once

 Simple approach: deal with exception from

earliest instruction

 Flush subsequent instructions

 “Precise” exceptions

 In complex pipelines

 Multiple instructions issued per cycle

 Out-of-order completion

 Maintaining precise exceptions is difficult!

Chapter 4 — The Processor — 106

Imprecise Exceptions

 Just stop pipeline and save state

 Including exception cause(s)

 Let the handler work out

 Which instruction(s) had exceptions

 Which to complete or flush

 May require “manual” completion

 Simplifies hardware, but more complex handler

software

 Not feasible for complex multiple-issue

out-of-order pipelines

Chapter 4 — The Processor — 107

Instruction-Level Parallelism (ILP)

 Pipelining: executing multiple instructions in
parallel

 To increase ILP
 Deeper pipeline

 Less work per stage  shorter clock cycle

 Multiple issue
 Replicate pipeline stages  multiple pipelines

 Start multiple instructions per clock cycle

 CPI < 1, so use Instructions Per Cycle (IPC)  E.g., 4GHz 4-way multiple-issue  16 BIPS, peak CPI = 0.25, peak IPC = 4  But dependencies reduce this in practice § 4 .1 0 P a ra lle lis m v ia In s tru c tio n s (Typically ______) Chapter 4 — The Processor — 108 Multiple Issue  Static multiple issue  Compiler groups instructions to be issued together  Packages them into “issue slots”  Compiler detects and avoids hazards  Dynamic multiple issue  CPU examines instruction stream and chooses instructions to issue each cycle  Compiler can help by reordering instructions  CPU resolves hazards using advanced techniques at runtime Chapter 4 — The Processor — 109 Speculation  “Guess” what to do with an instruction  Start operation as soon as possible  Check whether guess was right  If so, complete the operation  If not, roll-back and do the right thing  Common to static and dynamic multiple issue  Examples  Speculate on branch outcome  Roll back if path taken is different  Speculate on load  Roll back if location is updated (sw $1, 20($2) lw $3, 20($2)) Chapter 4 — The Processor — 110 Compiler/Hardware Speculation  Compiler can reorder instructions  e.g., move load before branch  Can include “fix-up” instructions to recover from incorrect guess  Hardware can look ahead for instructions to execute  Buffer results until it determines they are actually needed  Flush buffers on incorrect speculation Chapter 4 — The Processor — 111 Speculation and Exceptions  What if exception occurs on a speculatively executed instruction?  e.g., speculative load before null-pointer check  Static speculation  Can add ISA support for deferring exceptions  Dynamic speculation  Can buffer exceptions until instruction completion (which may not occur) Chapter 4 — The Processor — 112 Static Multiple Issue  Compiler groups instructions into “issue packets”  Group of instructions that can be issued on a single cycle  Determined by pipeline resources required  Think of an issue packet as a very long instruction  Specifies multiple concurrent operations   Very Long Instruction Word (VLIW) Chapter 4 — The Processor — 113 Scheduling Static Multiple Issue  Compiler must remove some/all hazards  Reorder instructions into issue packets  No dependencies with a packet  Possibly some dependencies between packets  Varies between ISAs; compiler must know!  Pad with nop if necessary Chapter 4 — The Processor — 114 MIPS with Static Dual Issue  Two-issue packets  One ALU/branch instruction  One load/store instruction  64-bit aligned  ALU/branch, then load/store  Pad an unused instruction with nop Address Instruction type Pipeline Stages n ALU/branch IF ID EX MEM WB n + 4 Load/store IF ID EX MEM WB n + 8 ALU/branch IF ID EX MEM WB n + 12 Load/store IF ID EX MEM WB n + 16 ALU/branch IF ID EX MEM WB n + 20 Load/store IF ID EX MEM WB Chapter 4 — The Processor — 115 MIPS with Static Dual Issue (2 more ____ ports and 1 more _____ port; ________ adder) Chapter 4 — The Processor — 116 Hazards in the Dual-Issue MIPS  More instructions executing in parallel  EX data hazard  Forwarding avoided stalls with single-issue  Now can’t use ALU result in load/store in same packet  add $t0, $s0, $s1 load $s2, 0($t0)  Split into two packets, effectively a stall  Load-use hazard  Still one cycle use latency, but now two instructions  More aggressive scheduling required Chapter 4 — The Processor — 117 Scheduling Example  Schedule this for dual-issue MIPS Loop: lw $t0, 0($s1) # $t0=array element addu $t0, $t0, $s2 # add scalar in $s2 sw $t0, 0($s1) # store result addi $s1, $s1,–4 # decrement pointer bne $s1, $zero, Loop # branch $s1!=0 ALU/branch Load/store cycle Loop: nop lw $t0, 0($s1) 1 addi $s1, $s1,–4 nop 2 addu $t0, $t0, $s2 nop 3 bne $s1, $zero, Loop sw $t0, 4($s1) 4  IPC = 5/4 = 1.25 (c.f. peak IPC = 2) Chapter 4 — The Processor — 118 Loop Unrolling  Replicate loop body to expose more parallelism  Reduces loop-control overhead  Use different registers per replication  Called “register renaming”  Avoid loop-carried “anti-dependencies”  Store followed by a load of the same register  Aka “name dependence”  Reuse of a register name Chapter 4 — The Processor — 119 Loop Unrolling Example  IPC = 14/8 = 1.75  Closer to 2, but at cost of registers and code size ALU/branch Load/store cycle Loop: addi $s1, $s1,–16 lw $t0, 0($s1) 1 nop lw $t1, 12($s1) 2 addu $t0, $t0, $s2 lw $t2, 8($s1) 3 addu $t1, $t1, $s2 lw $t3, 4($s1) 4 addu $t2, $t2, $s2 sw $t0, 16($s1) 5 addu $t3, $t4, $s2 sw $t1, 12($s1) 6 nop sw $t2, 8($s1) 7 bne $s1, $zero, Loop sw $t3, 4($s1) 8 Chapter 4 — The Processor — 120 Dynamic Multiple Issue  “Superscalar” processors  CPU decides whether to issue 0, 1, 2, … each cycle  Avoiding structural and data hazards  Avoids the need for compiler scheduling  Though it may still help  Code semantics ensured by the CPU Chapter 4 — The Processor — 121 Dynamic Pipeline Scheduling  Allow the CPU to execute instructions out of order to avoid stalls  But commit result to registers in order  Example lw $t0, 20($s2) addu $t1, $t0, $t2 sub $s4, $s4, $t3 slti $t5, $s4, 20  Can start sub while addu is waiting for lw Chapter 4 — The Processor — 122 Dynamically Scheduled CPU Results also sent to any waiting reservation stations Reorders buffer for register writes Can supply operands for issued instructions Preserves dependencies Hold pending operands Chapter 4 — The Processor — 123 Register Renaming  Reservation stations and reorder buffer effectively provide register renaming  On instruction issue to reservation station  If operand is available in register file or reorder buffer  Copied to reservation station  No longer required in the register; can be overwritten  If operand is not yet available  It will be provided to the reservation station by a function unit  Register update may not be required Chapter 4 — The Processor — 124 Speculation  Predict branch and continue issuing  Don’t commit until branch outcome determined  Load speculation  Avoid load and cache miss delay  Predict the effective address  Predict loaded value  Load before completing outstanding stores  Bypass stored values to load unit  Don’t commit load until speculation cleared Chapter 4 — The Processor — 125 Why Do Dynamic Scheduling?  Why not just let the compiler schedule code?  Not all stalls are predicable  e.g., cache misses  Can’t always schedule around branches  Branch outcome is dynamically determined  Different implementations of an ISA have different latencies and hazards Chapter 4 — The Processor — 126 Does Multiple Issue Work?  Yes, but not as much as we’d like  Programs have real dependencies that limit ILP  Some dependencies are hard to eliminate  e.g., pointer aliasing  Some parallelism is hard to expose  Limited window size during instruction issue  Memory delays and limited bandwidth  Hard to keep pipelines full  Speculation can help if done well The BIG Picture Chapter 4 — The Processor — 127 Power Efficiency  Complexity of dynamic scheduling and speculations requires power  Multiple simpler cores may be better Microprocessor Year Clock Rate Pipeline Stages Issue width Out-of-order/ Speculation Cores Power i486 1989 25MHz 5 1 No 1 5W Pentium 1993 66MHz 5 2 No 1 10W Pentium Pro 1997 200MHz 10 3 Yes 1 29W P4 Willamette 2001 2000MHz 22 3 Yes 1 75W P4 Prescott 2004 3600MHz 31 3 Yes 1 103W Core 2006 2930MHz 14 4 Yes 2 75W UltraSparc III 2003 1950MHz 14 4 No 1 90W UltraSparc T1 2005 1200MHz 6 1 No 8 70W Cortex A8 and Intel i7 Processor ARM A8 Intel Core i7 920 Market Personal Mobile Device Server, cloud Thermal design power 2 Watts 130 Watts Clock rate 1 GHz 2.66 GHz Cores/Chip 1 4 Floating point? No Yes Multiple issue? Dynamic Dynamic Peak instructions/clock cycle 2 4 Pipeline stages 14 14 Pipeline schedule Static in-order Dynamic out-of-order with speculation Branch prediction 2-level 2-level 1st level caches/core 32 KiB I, 32 KiB D 32 KiB I, 32 KiB D 2nd level caches/core 128-1024 KiB 256 KiB 3rd level caches (shared) - 2- 8 MB Chapter 4 — The Processor — 128 § 4 .1 1 R e a l S tu ff: T h e A R M C o rte x -A 8 a n d In te l C o re i7 P ip e lin e s ARM Cortex-A8 Pipeline Chapter 4 — The Processor — 129 ARM Cortex-A8 Performance Chapter 4 — The Processor — 130 Core i7 Pipeline Chapter 4 — The Processor — 131 Core i7 Performance Chapter 4 — The Processor — 132 Matrix Multiply  Unrolled C code 1 #include

2 #define UNROLL (4)

3

4 void dgemm (int n, double* A, double* B, double* C)

5 {

6 for ( int i = 0; i < n; i+=UNROLL*4 ) 7 for ( int j = 0; j < n; j++ ) { 8 __m256d c[4]; 9 for ( int x = 0; x < UNROLL; x++ ) 10 c[x] = _mm256_load_pd(C+i+x*4+j*n); 11 12 for( int k = 0; k < n; k++ ) 13 { 14 __m256d b = _mm256_broadcast_sd(B+k+j*n); 15 for (int x = 0; x < UNROLL; x++) 16 c[x] = _mm256_add_pd(c[x], 17 _mm256_mul_pd(_mm256_load_pd(A+n*k+x*4+i), b)); 18 } 19 20 for ( int x = 0; x < UNROLL; x++ ) 21 _mm256_store_pd(C+i+x*4+j*n, c[x]); 22 } 23 } Chapter 4 — The Processor — 133 § 4 .1 2 In s tru c tio n -L e v e l P a ra lle lis m a n d M a trix M u ltip ly Matrix Multiply  Assembly code: 1 vmovapd (%r11),%ymm4 # Load 4 elements of C into %ymm4 2 mov %rbx,%rax # register %rax = %rbx 3 xor %ecx,%ecx # register %ecx = 0 4 vmovapd 0x20(%r11),%ymm3 # Load 4 elements of C into %ymm3 5 vmovapd 0x40(%r11),%ymm2 # Load 4 elements of C into %ymm2 6 vmovapd 0x60(%r11),%ymm1 # Load 4 elements of C into %ymm1 7 vbroadcastsd (%rcx,%r9,1),%ymm0 # Make 4 copies of B element 8 add $0x8,%rcx # register %rcx = %rcx + 8 9 vmulpd (%rax),%ymm0,%ymm5 # Parallel mul %ymm1,4 A elements 10 vaddpd %ymm5,%ymm4,%ymm4 # Parallel add %ymm5, %ymm4 11 vmulpd 0x20(%rax),%ymm0,%ymm5 # Parallel mul %ymm1,4 A elements 12 vaddpd %ymm5,%ymm3,%ymm3 # Parallel add %ymm5, %ymm3 13 vmulpd 0x40(%rax),%ymm0,%ymm5 # Parallel mul %ymm1,4 A elements 14 vmulpd 0x60(%rax),%ymm0,%ymm0 # Parallel mul %ymm1,4 A elements 15 add %r8,%rax # register %rax = %rax + %r8 16 cmp %r10,%rcx # compare %r8 to %rax 17 vaddpd %ymm5,%ymm2,%ymm2 # Parallel add %ymm5, %ymm2 18 vaddpd %ymm0,%ymm1,%ymm1 # Parallel add %ymm0, %ymm1 19 jne 68 # jump if not %r8 != %rax

20 add $0x1,%esi # register % esi = % esi + 1

21 vmovapd %ymm4,(%r11) # Store %ymm4 into 4 C elements

22 vmovapd %ymm3,0x20(%r11) # Store %ymm3 into 4 C elements

23 vmovapd %ymm2,0x40(%r11) # Store %ymm2 into 4 C elements

24 vmovapd %ymm1,0x60(%r11) # Store %ymm1 into 4 C elements

Chapter 4 — The Processor — 134

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Chapter 4 — The Processor — 135

Chapter 4 — The Processor — 136

Fallacies

 Pipelining is easy (!)

 The basic idea is easy

 The devil is in the details

 e.g., detecting data hazards

 Pipelining is independent of technology

 So why haven’t we always done pipelining?

 More transistors make more advanced techniques

feasible

 Pipeline-related ISA design needs to take account of

technology trends

 e.g., predicated instructions

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Chapter 4 — The Processor — 137

Pitfalls

 Poor ISA design can make pipelining

harder

 e.g., complex instruction sets (VAX, IA-32)

 Significant overhead to make pipelining work

 IA-32 micro-op approach

 e.g., complex addressing modes

 Register update side effects, memory indirection

 e.g., delayed branches

 Advanced pipelines have long delay slots

Chapter 4 — The Processor — 138

Concluding Remarks

 ISA influences design of datapath and control

 Datapath and control influence design of ISA

 Pipelining improves instruction throughput

using parallelism

 More instructions completed per second

 Latency for each instruction not reduced

 Hazards: structural, data, control

 Multiple issue and dynamic scheduling (ILP)

 Dependencies limit achievable parallelism

 Complexity leads to the power wall

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