1007ICT / 1807ICT / 7611ICT Computer Systems & Networks
3B. Digital Logic and Digital Circuits
Dr. Sven Venema Dr. Vallipuram Muthukkumarasamy
Last Lecture:
Topics Covered:
• Digital logic, Basic logic gates, Boolean algebra
• Combinatorial logic gates
Lecture Content
Learning objectives
Logic unit, Selection logic, Decoder logic Multiplexing and demultiplexing
Half and Full adders
© Ruben Gonzalez. Revised and updated by Sven Venema, Vallipuram Muthukkumarasamy, and Wee Lum Tan
Page 3
Learning Objectives
At the end of this lecture you will have gained an understanding of:
Selection logic
Decoder logic
Multiplexors
Demultiplexors
Half and Full adders
© Ruben Gonzalez. Revised and updated by Sven Venema, Vallipuram Muthukkumarasamy, and Wee Lum Tan
Page 4
Logic Unit
Lets try to create a “programmable” logic unit that permits us to apply a predefined logic function to a given set of inputs.
ab
Output Select
We need a function that lets us select what operation to perform
AND OR XOR
NOT
© Ruben Gonzalez. Revised and updated by Sven Venema, Vallipuram Muthukkumarasamy, and Wee Lum Tan
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Selection Logic
Saywehaveanumberofinputs‘A,B,C,D’andwe want to select one of them to use in a logic function.
Weneedaspecialfunctiontoswitchtheselected input into the output ‘X’ based on the selection.
WecanuseinputsS0toS3toselectbetweenA-D
A B C D
Selector
X
S0 S1 S2 S3
© Ruben Gonzalez. Revised and updated by Sven Venema, Vallipuram Muthukkumarasamy, and Wee Lum Tan
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Decoder Logic
Justsaywewanttoselectbetweenoneof100’s of possible inputs – we need 100’s of selection inputs as well which gets too complicated.
DecoderswithNinputsallowustoenableany one of 2N possible selection lines.
Basicallyadecodertakesabinarycodednumber and enables the output representing the number
Inputs
Outputs
s1
s2
x0
x1
x2
x3
0
0
1
0
0
0
0
1
0
1
0
0
1
0
0
0
1
0
1
1
0
0
0
1
2 to 4 Decoder
x0 = s1ANDs2 x1 = s1ANDs2 x2 = s1ANDs2 x3 = s1ANDs2
X0 X1
X2 X3
2N outputs
© Ruben Gonzalez. Revised and updated by Sven Venema, Vallipuram Muthukkumarasamy, and Wee Lum Tan
Page 7
S2 S1
N Inputs
Multiplexing
Combiningtheselectoranddecoderwecan
create what is called a
IngeneralifwehaveNinputswewanttoswitch between we need to have log2(N) selection lines.
Multiplexor
A B C D
X
s0
s1
X
0
0
A
0
1
B
1
0
C
1
1
D
Decoder
S0 S1 selection
© Ruben Gonzalez. Revised and updated by Sven Venema, Vallipuram Muthukkumarasamy, and Wee Lum Tan
Page 8
2N inputs
Demultiplexing
We can also switch in the opposite direction to send one input ‘A’ into one of many different outputs (eg X1..Xn)
Decoder
A
X1 X2
Input X1 A X2
outputs X4
X3 X3
X4
(s0,s1) Select
S0 S1 selection
© Ruben Gonzalez. Revised and updated by Sven Venema, Vallipuram Muthukkumarasamy, and Wee Lum Tan
Page 9
Half-Adders
In addition to logic functions we can also create maths functions.
The simplest math function is the half-adder which can add 2 digits (bits) to give a sum and a carry bit
0011A 0 1 0 1B+ 0 1 1 10
AB
A
B
Sum
C
0
0
0
0
0
1
1
0
1
0
1
0
1
1
0
1
Sum = A XOR B Carry = A AND B
© Ruben Gonzalez. Revised and updated by Sven Venema, Vallipuram Muthukkumarasamy, and Wee Lum Tan
Page 10
Full-Adders
Ifwewanttoaddmorethan1bitvaluestogether we need to deal with the carry.
Full-addersacceptthetwoinputstobeaddedplus the carry from a previous stage.
Thecircuitmustbeabletodealwithpropagation delays
00 00 01 01 00 10 11 11A 00 01 00 01 10 01 10 11B+ 00 01 01 10 10 11 101 110
A0 B0 A1 B1 A2 B2 A3 B3
Full Adder
Full Adder
Full Adder
Full Adder
Cin
Cout
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S0 S1 4 bit adder S2 S3 © Ruben Gonzalez. Revised and updated by Sven Venema, Vallipuram Muthukkumarasamy, and Wee Lum Tan
Full-Adders
The logic to perform add with carry combines two half adders together.
Sum =AXORBXORCin
Cout = (AANDB)OR(CinAND(AXORB))
Cin
A
B
Sum
Cout
0
0
0
0
0
0
0
1
1
0
0
1
0
1
0
0
1
1
0
1
1
0
0
1
0
1
0
1
0
1
1
1
0
0
1
1
1
1
1
1
Cin AB
Sum Cout
Sum Carry
Sum A+B
© Ruben Gonzalez. Revised and updated by Sven Venema, Vallipuram Muthukkumarasamy, and Wee Lum Tan
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Subtraction
A–BisthesameasA+(-B)
IfweconvertBtothenegativeequivalentofits value, we can use the basic adder as it is. We can use an XOR gate to do this.
However,convertingBto–Busingtwo’s complement also requires adding 1
A B0 Sign bit 0
+0 if positive +1 if negative
© Ruben Gonzalez. Revised and updated by Sven Venema, Vallipuram Muthukkumarasamy, and Wee Lum Tan
Page 13
Full Adder
S0
Summary
Have considered: Selection logic Decoder logic
Multiplexors
Demultiplexors
Half and Full adders
© Ruben Gonzalez. Revised and updated by Sven Venema, Vallipuram Muthukkumarasamy, and Wee Lum Tan
Page 14
Next….
Arithmetic logic unit
Binary multiplication and division
Shifting
Sequential Logic
Data latches, S-R Latch
Clocks and synchronisation
Registers, Buses, Computer memory Processors and Memory Organisation
© Ruben Gonzalez. Revised and updated by Sven Venema, Vallipuram Muthukkumarasamy, and Wee Lum Tan
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