Lecture 2a:
Instructions: Language of the Computer (1/3)
John Owens
Introduction to Computer Architecture UC Davis EEC 170, Winter 2021
Big picture for today
▪ Stored program computer: both programs and information are treated as data
– “Information”: text, pictures, videos, simulation data, etc. ▪ All data is stored in the “memory” of the machine
▪ We wish to manipulate this data:
– Some data is instructions; we will treat that data as instructions and execute/evaluate them (but also treat them as data! e.g., linking against other code)
– Some data is information; our instructions will operate on this information
▪ Today’s topic: What are these instructions?
UC Davis EEC 170, Winter 2021 / © John Owens
The instruction set is the most fundamental abstraction in this course.
It is the boundary between software and hardware.
UC Davis EEC 170, Winter 2021 / © John Owens
What factors do we want to consider when we are designing our instructions?
UC Davis EEC 170, Winter 2021 / © John Owens
Instruction Set
▪ ▪
▪
▪ ▪
The repertoire of instructions of a computer Different computers have different instruction sets
– But with many aspects in common
Early computers had very simple instruction sets
– Simplified implementation
Many modern computers also have simple instruction sets
Since the 1980s, the dominant philosophy has been toward simpler (“reduced”, “RISC”) instruction sets as opposed to complex (“CISC”)
– x86 is an exception, but x86 CPUs are RISC underneath
UC Davis EEC 170, Winter 2021 / © John Owens
§2.1 Introduction
The RISC-V Instruction Set
▪ ▪ ▪ ▪
▪
▪
Used as the example throughout the book Developed at UC Berkeley as open ISA
Now managed by the RISC-V Foundation (riscv.org) Typical of many modern ISAs
– See RISC-V Reference Data tear-out card Increasing market!
– It’s a good ISA
– It’s also ~free
Similar ISAs have a large share of embedded core market
– Applications in consumer electronics, network/storage equipment, cameras, printers, …
UC Davis EEC 170, Winter 2021 / © John Owens
–
Throughout this discussion: What decisions did the
architects make about the RISC-V instruction set? Why did they make these decisions?
–
UC Davis EEC 170, Winter 2021 / © John Owens
Arithmetic Operations
▪ Add and subtract, three operands
– Two sources and one destination
▪
–
▪ All arithmetic operations have this form
▪ Design Principle 1: Simplicity favors regularity
– Regularity makes implementation simpler
– Simplicity enables higher performance at lower cost
add a, b, c // a gets b + c
– What are a, b, and c?
addonly operates on integer data (what’s an integer?) – Note: RISC V instructions put the destination first
UC Davis EEC 170, Winter 2021 / © John Owens
§2.2 Operations of the Computer Hardware
Arithmetic Example ▪ C code:
f = (g + h) – (i + j);
▪ Compiled RISC-V code:
add t0, g, h
add t1, i, j
sub f, t0, t1
// temp t0 = g + h
// temp t1 = i + j
// f = t0 – t1
▪ We’re not done yet though—where are t0, g, etc.?
UC Davis EEC 170, Winter 2021 / © John Owens
Load Half Unsigned
I LHU
rd,rs1,imm
L{W|D}U
rd,rs1,imm
Atomic Read &
e
m r
a
a W u
)
UJ
CB
Stores Store Byte S SB rs1,rs2,imm Atomic Read Store Halfword S SH rs1,rs2,imm Change Lev
RISC-V Reference Card
StoreWord S SW rs1,rs2,imm S{D|Q} rs1,rs2,imm Environ Shifts Shift Left R SLL rd,rs1,rs2 SLL{W|D} rd,rs1,rs2 Envi
▪ Google it to find it
Shift Right Immediate I SRLI rd,rs1,shamt SRLI{W|D} rd,rs1,shamt Hypervisor Tr
Load Halfword I LH rd,rs1,imm Atomic Read & Set Bit CSRRS rd,csr,rs1 Load Word I LW rd,rs1,imm L{D|Q} rd,rs1,imm Atomic Read & Clear Bit CSRRC rd,csr,rs1
Shift Left Immediate I SLLI rd,rs1,shamt SLLI{W|D} rd,rs1,shamt Trap Redire
ift
Shift Right Arith Imm
S
c
h
R
ig
h
t
Ar
Free & Open Reference Card 1
Shift Right R SRL rd,rs1,rs2 SRL{W|D} rd,rs1,rs2 Redirect Tr
▪ It’l
Base Integer Instructions: RV32I, RV64I, and RV128I RV Privileged Instructions Category Name Fmt RV32I Base +RV{64,128} Category Name RV mnemonic Loads Load Byte I LB rd,rs1,imm CSR Access Atomic R/W CSRRW rd,csr,rs1
l
b
e
a
t
t
a
c
h
it
h
e
m
d
t
eti
Load Byte Unsigned I
Load Half Unsigned I LHU rd,rs1,imm L{W|D}U rd,rs1,imm Atomic Read & Set Bit Imm CSRRSI rd,csr,imm
o yRouSrRAexamrd,srs1,rs2 SRA{W|D} rd,rs1,rs2 Interrupt
LBU rd,rs1,imm
I SRAI rd,rs1,shamt SRAI{W|D} rd,rs1,shamt MMU S
Stores Store Byte S SB rs1,rs2,imm Atomic Read & Clear Bit Imm CSRRCI rd,csr,imm Change Level Env. Call ECALL
L{W|D} rd,rs1,rs2 Environment Return ERET
r
d
,
r
s X
C
.LW rd′
I
OR Immediate I ORI rd,rs1,imm
SP CI C.
XOR Im
te
OR R OR rd,rs1,rs2
me
dia
Loa
– ADD is an “R” type instruction (you don’t know this yet)
-mpare Set< R SL
(source 2). The “r” means “register”.
ReaD CYCLE upper Half I RDCYCLEH rd Set < Imm Unsigned I SLTAIUDDrd,rs1,imm ReaD TIME I RDTIME rd
SLLI rd,rd,imm
NSTR
Branches Branch = SB BEQ rs1,rs2,imm
Jump Register CR C.JR rd,rs1 JALR x0,rs1,0
Store Quad CS C.SQ rs1
1 ORI
,r rd,
▪ What this says:
OR Immediate I ORI rd,rs1,imm Load Double SP CI C.LDSP rd,
AND Immediate I ANDI rd,rs1,imm
SW rs1′,rs2′,imm*4
CL C.LD rd′
Compare Set < R SLT rd,rs1,rs2 OR R OR rd,rs1,rs2
LQ rd,sp,imm*16
s rs
2 1,imm
LI{W|D} rd,rs1,shamt Trap Redirect to SupervisorMRTS ADDI{W|D} rd,rs1,imm
L{W|D} rd,rs1,rs2 Redirect Trap to Hypervisor MRTH
LI{W|D} rd,rs1,shamt Hypervisor Trap to Supervisor HRTS
A{W|D} rd,rs1,rs2 Interrupt Wait for Interrupt WFI SUB{W|D} rd,rs1,rs2
AI{W|D} rd,rs1,shamt MMU Supervisor FENCE SFENCE.VM rs1
D{W|D} rd,rs1,rs2
DI{W|D} rd,rs1,imm
B{W|D} rd,rs1,rs2
dW
Load Double Load Double SP Load Quad Load Quad SP
Load Word SP CL C.LQ rd′,rs1′,imm CI C.LQSP rd,imm
CI C.LWSP rd,
LQ rd′,rs1′,imm*16
SW rs2,sp,imm*4 Set < Imm Unsigned I SLTIU rd,rs1,imm Store Double SP CSS C.SDSP rs2,imm SD rs2,sp,imm*8
AND R AND
AND Immediate I ANDI rd,rs1,imm Load Quad SP CI C.LQSP rd,
Branches Branch = SB BEQ rs1,rs2,imm Store Quad CS C.SQ rs1′,rs2′,imm SQ rs1′,rs2′,imm*16
Re
RETired I RDINSTRET rd
uad Branch < SB BLT rs1,rs2,imm Arithmetic ADD CR C.ADD rd,rs1
r
d
,
r
s
1
,r rs1
d
Q
.LQ rd′ *16
B
SB
2
s2,imm Store Quad SP CSS C.S
C
ran
Synch Instr & Data I
Load Upper Imm CI C.LUI rd,imm MoVe CR C.MV rd,rs1
LUI rd,imm
ADD rd,rs1,x0
ch
≠
B
NE
QS
P
r
s2,i
mm
SQ r
Branch ≥ Unsigned SB BGEU rs1,rs2,imm ADD Word Imm CI C.ADDIW rd,imm ADDIW rd,rd,imm ADD’s operands arerd(destination),rs1(source 1),rs2
Co
- SUB is ~the same as
r
s
o
C
S
,
Set < Immediate I SLTI rd,rs1,imm
.
Store Word SP CSS C.SWSP rs2
Set < Unsigned R SLTU
Counters ReaD CYCLE I RDCYCLE rd Shifts Shift Left Imm CI C.SLLI rd,imm
C
S
aD I
System
B
I
r
d
,
r
s
1
,
rs2
u
s1 C
REA
K
S
BRE
AK
C
.
SUB
rd
,r
s1
SUB
r
d,rd,r
J
rd,
im
m
*1
C.A
D
DI1
6
SP x
0,i
mm
ADDI
s
p,sp,i
mm*
16
s ,r
Branch ≥ SB BGE rs1,rs2,imm ADD Word CR C.ADDW rd,rs1 ADDW rd,rd,imm
Branch < Unsigned SB BLTU rs1,rs2,imm ADD Immediate CI C.ADDI rd,imm ADDI rd,rd,imm
T
Jump & Link Register UJ JALR rd,rs1,imm
rd
Synch Synch thread I FENCE
,r System System CALL I SCALL
s
C
SW rs1 .SD rs1
Ju
mp & Link
J&
UJ
6 CI
L
ADD
S
r
s FENCE.I
AL 1
rd
m 2
Jump
ReaD INSTR upper Half I RDINSTRETH rd Jump & Link J&L CJ C.JAL imm
ReaD TIME upper Half I RDTIMEH rd
Branch ≠ SB BNE rs1,rs2,imm
32-bit Instruction Formats 16-bit (RVC) Instruction Formats
Branch < SB BLT rs1,rs2,imm Arithm CR C.ADD R CI
I CSS
Branch ≥ SB BGE rs1,rs2,imm
S CIW
ADD Word CR C.ADDW
Branch < Unsigned SB BL
D Immediate CI C.ADDI
SB CL
U
UC Davis EEC 170, Winter 2021 / © John Owens
TU rs1,rs2,imm AD
S
t
e
o
L
o
a
Atomic R/W Imm CSRRWI rd,csr,imm
Arithmetic ADD ADD Immediate SUBtract
Load Upper Imm Add Upper Imm to PC
R I R
U U
SUB
r
d
,
RA 1
1,rs2 SR 2
Store Halfword S SH rs1,rs2,imm
Store Word S SW rs1,rs2,imm S{ ADD rd,rs1,rs2
Shifts Shift Left R
SLL rd,rs1,rs2 SL
Shift Left Immediate I SLLI rd,rs1,shamt SL ADDI rd,rs1,imm
Shift Right Shift Right Immediate
R SRL rd,rs1,rs2 SR I SRLI rd,rs1,shamt SR
s Arithmetic ADD R ADD
,r
s
Shift Right Ar
R
ith
met
Shift Right Arith Imm
ADD Immediate I ADDI
rd,rs1,rs2 AD rd,rs1,imm AD rd,rs1,rs2 SU
rd,imm
rd,imm C
ic
S
rd,
rs
r
I SRAI rd,rs1,shamt SR
LUI rd,imm SUBtract R SUB
Load Upper Imm U LUI AUIPC rd,imm
Add Upper Imm to PC U AUIPC
D|Q} rs1,rs2,imm Environment Breakpoint EBREAK ADD{W|D} rd,rs1,rs2
Optional Compressed (16-bit
Logical
ategory Name Fmt RVC
Loads Load Word CL C.LW rd′,rs1′,imm
RVI equivalent
XOR R XOR
XOR Immediate I XORI rd,rs1,imm
AND R AND rd,rs1,rs2
Lo
C
L
Logical
XOR R XOR rd,rs1,rs2
ord CL C.LD rd′,rs1′,imm
LW rd′,rs1′,imm*4
Optional Compressed (16-bit) Instruction Extension: RVC
Category Name Fmt R
a
d
s
L
ord
LW
CI C.LDSP rd,imm
Stores Store Word CS C.SW rs1′,rs2′,imm Load Double
Set < Immediate I SLTI rd,rs1,imm Store Word SP CSS C.SWSP rs2,imm
Set < Unsigned R SLTU rd,rs1,rs2 Store Double CS C.SD rs1′,rs2′,imm SD rs1′,rs2′,imm*8
o
SP
rd,i
mm
LW r
d,s
p,imm*
4
ad
W
e
ADD SP Imm * 4 CIW C.ADDI4SPN rd',imm ADDI rd',sp,imm*4
P Im
S
t
r
W
Load Immediate CI C.LI rd,imm ADDI rd,x0,imm
Jump & Link Register System Env. BREAK
CR C.JALR
CSS C.SQSP rs2
SUB CR S
S
C
I
C.
E
BREA
K
EBR
EA
K
CS
t
o
t
ble
o
r
e
Q
uad SP
re D
etic ADD CR
o
o
Branches Branch=0 CB C.BEQZ rs1′,imm BEQ rs1',x0,imm
Store Double SP CSS C.SDSP rs2
Branch≠0 CB C.BNEZ rs1′,imm BNE rs1',x0,imm Jump CJ C.J imm JAL x0,imm
rs1
LD rd′,rs1′,imm*8
LD rd,sp,imm*8
C
L
s2,
ADD rd,rd,rs1
JAL ra,imm
JALR ra,rs1,0
sp,imm
Register Operands
▪ ▪
▪
▪
RISC-V has a 32 × 64-bit register file
- Use for frequently accessed data
- 64-bit data (in RISC-V) is called a “doubleword”
- 32 × 64-bit general purpose registers x0 to x31
- x0 is hardwired to 0
- 32-bit data is called a “word”
Where is the data stored?
Arithmetic instructions use register operands
- Important! In RISC-V, all arithmetic instructions ONLY use register operands
Design Principle 2: Smaller is faster
- c.f. main memory: millions of locations
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§2.3 Operands of the Computer Hardware
RISC-V Registers
▪ x0: the constant value 0 ▪ x1: return address
▪ x2: stack pointer
▪ x3: global pointer
▪ x4: thread pointer
▪ x5 – x7, x28 – x31: temporaries
▪ x8: frame pointer
▪ x9, x18 – x27: saved registers
▪ x10 – x11: function arguments/results ▪ x12 – x17: function arguments
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Register Operand Example ▪ C code:
f = (g + h) - (i + j);
- f, ..., j in x19, x20, ..., x23 ▪ Compiled RISC-V code:
add x5, x20, x21
add x6, x22, x23
sub x19, x5, x6
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Memory Operands (architectural decisions)
▪ Main memory used for composite data - Arrays, structures, dynamic data
▪ To apply arithmetic operations:
- Load values from memory into registers
- Store result from register to memory
▪ Memory is byte addressed
- Each address identifies an 8-bit byte
- Support for byte [8b], halfword [16b], word [32b], doubleword [64b]
▪ RISC-V is Little Endian
- Least-significant byte at least address of a word [processors]
- c.f. Big Endian: most-significant byte at least address [network]
▪ RISC-V does not require words to be aligned in memory
- Unlike some other ISAs
https://en.wikipedia.org/wiki/Endianness
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Memory Operand Example ▪ C code:
A[12] = h + A[8];
- h in x21, base address of A in x22 ▪ Compiled RISC-V code:
- Index 8 requires offset of 64 - 8 bytes per doubleword
▪
▪
ld dest, imm(src):
▪ dest: destination register
▪ imm: immediate (integer)
▪ src: base memory address, in register
ld x9, 64(x22) // x9 <- Mem[x22 + 64]
add x9, x21, x9
sd x9, 96(x22) // Mem[x22 + 96] <- x9
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Registers vs. Memory
▪ Registers are (much) faster to access than memory ▪ Operating on memory data requires loads and stores
- More instructions to be executed
▪ Compiler must use registers for variables as much as possible
- Only spill to memory for less frequently used variables
- Register optimization is important!
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Immediate Operands
▪ ConstantdataspecifieFdrineaenin&struOctpioenn
Base Integer Instructions: RV32I, RV64I, and RV128I Category Name Fmt RV32I Base +RV{64,128}
addi x22, x22, 4 // add the number 4 to
Loads Load Byte I LB rd,rs1,imm
- Small constants are common
Load Halfword I LH rd,rs1,imm
// x22, store back in x22
Load Word Load Byte Unsigned Load Half Unsigned
I LW I LBU I LHU
rd,rs1,imm
rd,rs1,imm
rd,rs1,imm
rs1,rs2,imm
rs1,rs2,imm
rs1,rs2,imm
L{D|Q}
L{W|D}U
S{D|Q}
rd,rs1,imm
rd,rs1,imm
rs1,rs2,im
Stores Store Byte S SB ▪ Make the common case fast
Store Halfword S SH Store Word S SW
Shifts Shift Left R SLL
Shift Left Immediate I SLLI rd,rs1,shamt
rd,rs1,rs2
rd,rs1,sha
rd,rs1,rs2
rd,rs1,sha
rd,rs1,rs2
rd,rs1,sha
- Immediate operand avoids a load instruction
Shift Right R SRL rd,rs1,rs2 Shift Right Immediate I SRLI rd,rs1,shamt
Shift Right Arithmetic R SRA rd,rs1,rs2
Shift Right Arith Imm
I SRAI rd,rs1,shamt
rd,rs1,rs2
SLL{W|D}
SLLI{W|D}
SRL{W|D}
SRLI{W|D}
SRA{W|D}
SRAI{W|D}
ADD{W|D} rd,rs1,rs2
ADDI{W|D} rd,rs1,imm
SUB{W|D} rd,rs1,rs2
Arithmetic ADD ADD Immediate SUBtract
Load Upper Imm Add Upper Imm to PC
R I R
U U
ADD rd,rs1,rs2
ADDI rd,rs1,imm
SUB rd,rs1,rs2
LUI rd,imm
AUIPC rd,imm
Logical
XOR R XOR rd,rs1,rs2
Optional Compr
Category Name F
Loads Load Word C UC Davis EEC 170, Winter 2021 / © John Owens
XOR Immediate I XORI rd,rs1,imm
m
m m m
e
m
L Load Word SP CI
Unsigned Binary Integers ▪ Given an n-bit number
n−1 n−2 1 0 x=xn−12 +xn−22 +!+x12 +x02
Range: 0 to +2n – 1 ▪ Example
- 0000 0000 ... 0000 10112
= 0×231 + ... + 1×23 + 0×22 +1×21 +1×20 = 0 + ... + 8 + 0 + 2 + 1 = 1110
▪ Using 64 bits: 0 to +18,446,774,073,709,551,615
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§2.4 Signed and Unsigned Numbers
Numbers
▪ Bits are just bits (no inherent meaning)
- conventions define relationship between bits and numbers
▪ Binary numbers (base 2)
- 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001... - decimal: 0 .. 2n-1
▪ Of course it gets more complicated:
- numbers are finite (overflow)
- fractions and real numbers
- negative numbers
- RISC-V restrictions (e.g., no RISC-V subi instruction; addi can add a negative number)
▪ How do we represent negative numbers?
- i.e., which bit patterns will represent which numbers?
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Possible Representations
▪ Sign Magnitude 000 = +0
001 = +1 010 = +2 011 = +3 100 = -0 101 = -1 110 = -2 111 = -3
One's Complement 000 = +0
001 = +1
010 = +2
011 = +3 100 = -3 101 = -2 110 = -1 111 = -0
Two's Complement 000 = +0
001 = +1
010 = +2
011 = +3 100 = -4 101 = -3 110 = -2 111 = -1
▪ In all these, the most significant bit is the “sign bit” ▪ Issues: balance, number of zeros, ease of operations
UC Davis EEC 170, Winter 2021 / © John Owens
2s-Complement Signed Integers
▪
Given an n-bit number
n−1 n−2 1 0 x=−xn−12 +xn−22 +!+x12 +x02
▪
Range: –2n – 1 to +2n – 1 – 1 Example
- 1111 1111 ... 1111 11002
= –1×231 + 1×230 + ... + 1×22 +0×21 +0×20 = –2,147,483,648 + 2,147,483,644 = –410
▪
Using 64 bits: −9,223,372,036,854,775,808 to 9,223,372,036,854,775,807
UC Davis EEC 170, Winter 2021 / © John Owens
2s-Complement Signed Integers
▪
▪ ▪
▪
Bit 63 (the most significant bit, MSB) is sign bit
- 1 for negative numbers
- 0 for non-negative numbers
–(–2n – 1) can’t be represented
Non-negative numbers have the same unsigned and 2s- complement representation
Some specific numbers
- 0:
- –1:
- Most-negative:
- Most-positive:
0000 0000 ... 0000 1111 1111 ... 1111 1000 0000 ... 0000 0111 1111 ... 1111
UC Davis EEC 170, Winter 2021 / © John Owens
Signed Negation
▪
Complement and add 1
-
- Complement means “flip all the bits”
Complement means 1 → 0, 0 → 1
x+x=1111...111 =−1 2
x +1= −x
-
▪
Example: negate +2
- +2 = 0000 0000 ... 0010two
- –2 = 1111 1111 ... 1101two + 1 = 1111 1111 ... 1110two
UC Davis EEC 170, Winter 2021 / © John Owens
Sign Extension
▪ ▪
▪
Representing a number using more bits - Preserve the numeric value
Replicate the sign bit to the left
- c.f. unsigned values: extend with 0s
Examples: 8-bit to 16-bit
- +2: 0000 0010 => 0000 0000 0000 0010
– –2: 1111 1110 => 1111 1111 1111 1110
Base Integer Instructions: RV32I, RV64I, and RV128I
Category
Name Fmt
RV32I Base
rs1,rs2,imm
rs1,rs2,imm
rs1,rs2,imm
rd,rs1,rs2
rd,rs1,shamt
rd,rs1,rs2
rd,rs1,shamt
rd,rs1,rs2
rd,rs1,shamt
rd,rs1,rs2
+RV{64,128} Cate CSR
Free & Open
Loads Load Byte Load Halfword Load Word Load Byte Unsigned Load Half Unsigned
I I I I I
LB rd,rs1,imm
LH rd,rs1,imm
LW rd,rs1,imm
LBU rd,rs1,imm
LHU rd,rs1,imm
L{D|Q} rd,rs1,imm
L{W|D}U rd,rs1,imm
▪
– –
In RISC-V instruction set
Stores
Store Byte S SB Store Halfword S SH Store Word S SW
Ato Atom Chan
lb: sign-extend loaded byte Shifts
S{D|Q}
SLL{W|D}
SLLI{W|D}
SRL{W|D}
SRLI{W|D}
SRA{W|D}
SRAI{W|D}
ADD{W|D}
rs1,rs2,imm
rd,rs1,rs2
lbu: zero-extend loaded byte Shift Right R SRL Shift Right Immediate I SRLI
Shift Right Arithmetic R SRA
Shift Right Arith Imm I SRAI Arithmetic ADD R ADD
ADD Immediate I ADDI SUBtract R SUB
rd,rs1,imm ADDI{W|D} rd,rs1,imm
Shift Left R SLL Shift Left Immediate I SLLI
rd,rs1,shamt Trap rd,rs1,rs2 Re rd,rs1,shamt Hyper rd,rs1,rs2 Inter rd,rs1,shamt MMU rd,rs1,rs2
rd,rs1,rs2
SUB{W|D} rd,rs1,rs2
UC Davis EEC 170, Winter 2021 / © John Owens
R
g
A
A
m i
E d
Break
UC Davis EEC 170, Winter 2021 / © John Owens
Administrative stuff
▪ I’m going to aim for a W 8:30–9:30 office hour (Coffee House) ▪ HW1 is out. Questions? Issues? Post on Slack #hw1
▪ Looking at the RARS MIPS-V simulator.
– Do you want to run on personal computers or in lab?
– Can you run Java?
▪ Slides ran a bit slow this morning! ▪ Word vs. Doubleword (sorry)
UC Davis EEC 170, Winter 2021 / © John Owens
Representing Instructions
▪
Instructions are encoded in binary – Called “machine code”
–
RISC-V instructions
How do we get from add x5, x20, x21 to binary? ▪
– Encoded as 32-bit instruction words
– Big picture: We divide the 32-bit instruction word into “fields”, each of a few bits, and encode different pieces information from the instruction into each field
– Small number of formats encoding operation code (opcode), register numbers, …
– Regularity!
UC Davis EEC 170, Winter 2021 / © John Owens
§2.5 Representing Instructions in the Computer
Hexadecimal
▪ Base 16
– Compact representation of bit strings
– 4 bits (“nibble”) per hex digit
– 0x means “I’m hexadecimal”
0
0000
4
0100
8
1000
c
1100
1
0001
5
0101
9
1001
d
1101
2
0010
6
0110
a
1010
e
1110
3
0011
7
0111
b
1011
f
1111
▪ Example: 0x eca8 6420
– 1110 1100 1010 1000 0110 0100 0010 0000
UC Davis EEC 170, Winter 2021 / © John Owens
RISC-V R-format Instructions
▪ Instruction fields
– opcode: operation code
– rd: destination register number
– funct3: 3-bit function code (additional opcode)
– rs1: the first source register number
– rs2: the second source register number
– funct7: 7-bit function code (additional opcode)
7 bits 5 bits 5 bits 3 bits 5 bits 7 bits
funct7
rs2
rs1
funct3
rd
opcode
UC Davis EEC 170, Winter 2021 / © John Owens
R-format Example
add x9,x20,x21
7 bits 5 bits 5 bits 3 bits 5 bits 7 bits
funct7
rs2
rs1
funct3
rd
opcode
0
21
20
0
9
51
0000000
10101
10100
000
01001
0110011
0000 0001 0101 1010 0000 0100 1011 0011two = 015A04B316
UC Davis EEC 170, Winter 2021 / © John Owens
imm[11:0] imm[11:5] rs2
rs1 funct3 rd
rs1 funct3 imm[4:0] rs1 funct3 imm[4:1|11]
rd rd
opcode opcode opcode opcode opcode
I-type S-type B-type U-type J-type
LUI AUIPC JAL JALR BEQ BNE BLT BGE BLTU BGEU LB
LH LW LBU LHU SB
SH SW ADDI SLTI SLTIU XORI ORI ANDI SLLI SRLI SRAI
SUB
SLL
SLT
Opcode Map
imm[12|10:5] rs2
imm[31:12] imm[20|10:1|11|19:12]
RV32I Base Instruction Set
imm[31:12]
rd
0110111
imm[31:12]
rd
0010111
imm[20|10:1|11|19:12] imm[11:0]
rd
1101111
rs1
000
rd
1100111
imm[12|10:5] imm[12|10:5] imm[12|10:5] imm[12|10:5] imm[12|10:5] imm[12|10:5]
imm[11:0]
rs2
rs1
000
imm[4:1|11] imm[4:1|11] imm[4:1|11] imm[4:1|11] imm[4:1|11] imm[4:1|11] rd
1100011
rs2
rs1
001
1100011
rs2
rs1
100
1100011
rs2
rs1
101
1100011
rs2
rs1
110
1100011
rs2
rs1
111
1100011
rs1
000
0000011
imm[11:0]
rs1
001
rd
0000011
imm[11:0]
rs1
010
rd
0000011
imm[11:0]
rs1
100
rd
0000011
imm[11:0]
rs1
101
rd
0000011
imm[11:5]
rs2
rs1
000
imm[4:0]
0100011
imm[11:5]
rs2
rs1
001
imm[4:0]
0100011
imm[11:5]
rs2
rs1
010
imm[4:0]
0100011
imm[11:0]
rs1
000
rd
0010011
imm[11:0]
rs1
010
rd
0010011
imm[11:0]
rs1
011
rd
0010011
imm[11:0]
rs1
100
rd
0010011
imm[11:0]
rs1
110
rd
0010011
imm[11:0]
rs1
111
rd
0010011
0000000
0100000
shamt
rs1
001
rd
0010011
0000000
shamt
shamt
rs1
rs1
101
101
rd
rd
0010011
0010011
0000000 rs2 rs1 000 rd 0110011 ADD
0100000
rs2
rs1
000
rd
0110011
0000000 rs2 rs1 001
rd 0110011
0000000 rs2 0000000 rs2 0000000 rs2
rs1 010 rs1 011 rs1 100
rd rd rd
0110011
0110011
0110011
SLTU
UC Davis EEC 170, Winter 2021 / © John Owens
XOR
RISC-V I-format Instructions
▪ Immediate arithmetic and load instructions
– rs1: source or base address register number
– immediate: constant operand, or offset added to base address
– 2s-complement, sign extended
– How big can this immediate be?
– Why did they pick this size?
– Advantages/disadvantages of making it bigger/smaller?
12 bits 5 bits 3 bits 5 bits 7 bits
immediate
rs1
funct3
rd
opcode
UC Davis EEC 170, Winter 2021 / © John Owens
RISC-V I-format vs. R-format
▪ ▪
▪
I-format:
R-format:
7 bits
12 bits
5 bits
3 bits
5 bits
7 bits
immediate
rs1
funct3
rd
opcode
funct7
rs2
rs1
funct3
rd
opcode
5 bits
5 bits
3 bits
5 bits
7 bits
Design Principle 3: Good design demands good compromises
– Different formats complicate decoding, but allow 32-bit
instructions uniformly
– Keep formats as similar as possible
UC Davis EEC 170, Winter 2021 / © John Owens
RISC-V S-format Instructions
▪ Different immediate format for store instructions
– rs1: base address register number
– rs2: source operand register number
– immediate: offset added to base address
– Split so that rs1 and rs2 fields always in the same place
imm[11:5]
rs2
rs1
funct3
imm[4:0]
opcode
7 bits 5 bits 5 bits 3 bits 5 bits 7 bits
UC Davis EEC 170, Winter 2021 / © John Owens
RISC-V I-format vs. R-format vs. S-format ▪ I-format:
immediate
rs1
funct3
rd
opcode
▪ R-format: 7 bits
▪ S-format: 7 bits
5 bits
5 bits
3 bits
5 bits
7 bits
12 bits
5 bits
3 bits
5 bits
7 bits
funct7
rs2
rs1
funct3
rd
opcode
imm[11:5]
rs2
rs1
funct3
imm[4:0]
opcode
5 bits
5 bits
3 bits
5 bits
7 bits
UC Davis EEC 170, Winter 2021 / © John Owens