Introduction to Computer Architecture Interstage Registers
Consider the following set of assembly language instructions and data:
add $t0, $t1, $t2
lw $t1, 8 ($sp)
sw $ra, 4 ($sp)
addi $sp, $sp, 4
sub $t0, $t0, $t1
$t0 15
$t1 40
$t2 5
$sp 0xFFFF F000
$ra 0x0400 BA12
$sp+8 125
Assuming that the interstage registers are all zeroed at the beginning, show the state of all of the registers
for the nine cycles that it takes for all five instructions to move through the pipeline. You may leave the
values in sensible terms, you do not need to covert the data to binary.
Objectives:
1. To understand the data flow in a pipelined processor.