Module: Electronic Engineering Practice
Code
Title
Module Leader
EL2242
State Machine Development
Steve Sigurnjak
Assessment
Title
Weighting
State Machine Development
25%
Submit to:
Deadline
Post-box
Blackboard
Other
10/02/2017
Late submissions will incur a penalty according to University regulations
Additional submission details:
A presentation of the working system will take place in the Tuesday lab session, week beginning 13th February 2017
In this assessment, the student will demonstrate the ability to:
Design and synthesise a finite state machine
Specify the behaviour of a digital system using a hardware description language.
Design a digital system and its interface to external hardware
Assessment Elements
Weighting (%)
Development report including state machine diagrams, comparisons and advantages and disadvantages between the microcontroller and the Verilog HDL
50
Code (layout, naming convensions, efficiency, comments etc)
20
Presentation of the working system
30
Total
100
Feedback Arrangments
Feed back will be given within the University’s 15 working day policy for feedback. In addition general verbal feedback will be given after the presentation of the system.
Assessment Brief
You are required to develop as simple state machine using the C programming language and an 8051 microcontroller and Using Verilog HDL and a FPGA development board. The state machine will mimic the operation of a simple vending machine.
The vending machine will vend a product when the value of the coins is equal to or greater than £5. The machine will only accept £1 coins and reject all other coins.
Your system must be able to count the value and the number of coins inserted to keep a total value, when the total amount either equals or exceeds the vending value the product will automatically vend.
Define the state machine by using an appropriate diagram, ensuring that all states and transitions are documented.
Create the state machine using C and the 8051 microcontroller and simulate this and record the results to ensure that the state machine is operating correctly. In addition implement the state machine using Verilog HDL and deploy this on an appropriate development board, such as the Altera DE1 SoC using appropriate input methods to denote the coins and appropriate output method(s) to denote the vending of the product and other features. Also run a simulation of the system.
Compare and contrast the development process and overall performance of the state machines. Compile a table of the advantages and disadvantages of using a microcontroller and a HDL language and FPGA based off research and your experience developing this.
There are 2 parts to the assignment, the development report and a presentation of the systems, further details are outlined below;
Development Report
You are tasked with creating a technical report of the development of the system. Within the report explain the following:
· Description of state machines and their implementation
· Overview of the general functions of the system
· The state machine diagram of the system that you are implementing
· The design justification and development of the system
· Testing of the completed design(s) against set criteria
· A comparison between the development of the state machine using the microcontroller and the FPGA
· A table of advantages and disadvantages between the 2 development processes
Include appropriate images and references of the development
Presentation
You are required to present your final working design on the development board and show your simulation for the microcontroller. Give a brief overview of the code and its functions for both the C programme and the Verilog HDL, as well as a demonstration of the system. It is envisioned that this will take no more than 10 minutes including questions.
Deliverables
The report and a transcript (text file) of your Verilog code is to be submitted to blackboard as a single word document. The A presentation of the working system will take place in the Tuesday lab session week beginning 13th February 2017.
Assessment Criteria
Grade
Mark
Descriptor
100
Flawless work, publishable as a peer reviewed document
Exceptional 1st
96
Impressive treatment of all requirements, thorough analysis, accurate crystal clear diagrams, insightful comparisons with an exceptional report.
High 1st
89
Excellent treatment of all requirements, thorough analysis, accurate clear diagrams, critical comparisons with an outstanding quality report.
Mid 1st
81
Comprehensive treatment of all requirements, thorough analysis, clear diagrams, critical comparisons, a good range of properly referenced sources with an appropriately structured, grammatically correct, clear and concise report.
Low 1st
74
Very good treatment of all requirements, sound analysis, clear diagrams, sound comparisons, a good range of properly referenced sources, with an appropriately structured, grammatically correct, clear and concise report.
High 2.1
68
Good treatment of all requirements, sound analysis, clear diagrams, critical comparisons, a range of properly referenced sources, with an appropriately structured, grammatically correct and clear report.
Mid 2.1
65
Good treatment of most requirements, good analysis, clear diagrams, sound comparisons, with numerous properly referenced sources with an appropriately structured, mostly grammatically correct and clear report
Low 2.1
62
Generally a good treatment of most requirements, good analysis, clear diagrams, some comparisons, with referenced sources and structured, mostly grammatically correct and clear report.
High 2.2
58
Generally a good treatment of key requirements, some analysis, quite clear diagrams with referenced sources and structured, mostly grammatically correct and clear report.
Mid 2.2
55
Generally a good treatment of key requirements, some analysis, quite clear diagrams with a few referenced sources and a satisfactory report.
Low 2.2
52
Mostly a reasonable treatment of requirements, some analysis, quite clear diagrams with a few referenced sources and a satisfactory report.
High 3rd
48
Adequate treatment of requirements, basic analysis, some diagrams with a few referenced sources and content structured and quite clearly presented.
Mid 3rd
45
Patchy treatment of requirements, limited analysis, some diagrams with some attempt at referencing sources and a generally satisfactory report.
Low 3rd
42
Limited treatment of requirements, superficial analysis, poor diagrams with some attempt at referencing sources and some attempt to structure content as a report.
Marginal Fail
35
Superficial treatment of requirements, poor analysis, poor diagrams with limited attempt at referencing sources and structured content.
Mid Fail
30
Inadequate treatment of requirements, little if any analysis with poor attempt at referencing sources used.
Low Fail
25
Poor treatment of requirements with no referenced sources.
Fail
10
Limited and incoherent treatment of requirements.
Non submission
0
No work submitted by deadline.