Logisim Circuit
One way to build an edge-
triggered D flip-flop is to connect two D latches in series, such that the two D latches use opposite levels
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of the clock for gating the latch. This is called a master-slave flip-flop, see Fig. I
The output of the master-slave flip flop changes on a clock edge, unlike the latch, which changes according
to the level of the clock. For a positive edge-triggered flip-flop, the output changes when the clock edge
rises, i.e., when clock transitions from 0 to 1.
For this part of the lab, you must perform the following steps:
1. In Logisim, build this gated D latch from Fig. I and the master slave flip-flop from Fig. E, each in
its own module. The flip-flop should be implemented using the module you create for the D latch,
and the latch should make use of the logic gates available in the Gates component set. Some of
you have noticed that there is a special Clock signal in the Wiring set. You do not need to use
that for this part (you will in future labs). For now, just use the default input pin type for the Clk
input signal (the one that you’ve been using up to this point). (PRELAB)
2. Study the behaviour of the latch for different D and clock (Clk) settings by using Poke Ar ).
3. Try creating a test vector to test this circuit. In your prelab report, describe what happens when
you test various input combinations with a test vector. (PRELAB)
4. For the D latch and the flip flop, are there any input combinations of Clk and D that should
NOT be the first you test with the Poke( An) tool? Explain this in your prelab and list them if
applicable.
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