Embedded Systems with ARM Cortex-M Microcontrollers in Assembly Language and C (Dr. )
Chapter 14 General-Purpose Input/Output (GPIO)
ECE3375B: Microprocessors and Microcomputers Electrical and Computer Engineering Western University
Dr. Leod (Section 1, Dr. (Section 2,
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Interfacing Peripherals
Usually, each on-chip peripheral device has a few registers, such as control registers, status registers, data input registers, and data output registers.
In general, there are two approaches to exchange data between the processor core, and a peripheral device:
1. Port-mapped I/O
UsespecialCPUinstructions:Special_instructionReg,Port
2. Memory-mapped I/O
MostCPUsthesedaysdoI/OviamemorymappedI/O
A simpler and more convenient way to interface I/O devices
Each device registers is assigned to a memory address in the address space of the microprocessor
Usenativeload/storeinstructionstoinputoroutputdata:LDR/STRReg,[Reg,#imm]
0x48000024
0x4800001C
0x48000014
GPIO Data Output Register
0x48000020
Pin output
0x48000018
0x48000010
Memory Space
GPIO Output
ARM Cortex-M microprocessors use memory-mapped I/O.
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Memory Map of Cortex-M4
0xFFFFFFFF
0xE0000000
0xA0000000
0x60000000
0x40000000
0x20000000
0x00000000
NVIC, System Timer, SCB, vendor-specific memory
Such as SD card
Off-chip memory for data
AHB & APB, such as timers, GPIO
On-chip RAM, for stack, & code On-chip Flash, for code & data
External Device
External RAM
Peripheral
0.5 GB 0.5 GB 0.5 GB
One Byte (8 bits)
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Memory Map of STM32L4
External Device
External RAM
Peripheral
0.5 GB 0.5 GB 0.5 GB
0xFFFFFFFF
0xE0000000
0xA0000000
0x60000000
0x40000000
0x20000000
0x00000000
0x60000000
0x48001000
0x48000C00
0x48000800
0x48000400
0x48000000
0x40000000
Embedded Systems with ARM Cortex-M Microcontrollers (Dr. Y. Zhu): Chapter 14
GPIO D (1 KB)
GPIO C (1 KB)
GPIO B (1 KB)
GPIO A (1 KB) …
One Byte (8 bits)
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GPIO Memory Map
0x48000400
0x48000400
0x48000000
GPIO A (1 KB)
0x4800002C
0x48000028 0x48000024
0x48000020 0x4800001C
0x48000018
0x48000014
0x48000010
0x4800000C
0x48000008
0x48000004
0x48000000
Each register has 4 bytes.
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GPIO Memory Map
0x48000400
Set pin A.14 to high
0x48000400
0x48000000
GPIO A (1 KB)
0x4800002C
0x48000028 0x48000024
0x48000020
0x4800001C
0x48000018
0x48000014
0x48000010
0x4800000C
0x48000008
0x48000004
0x48000000
Set bit 14 of ODR to high
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Embedded Systems with ARM Cortex-M Microcontrollers (Dr. Y. Zhu): Chapter 14
Output Data Register (ODR)
0x48000017
0x48000014
0x48000017
0x48000016
0x48000015
0x48000014
1 word (i.e. 32 bits)
Little Endian
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Output Data Register (ODR)
0x48000017
0x48000014
0x48000017
0x48000016
0x48000015
0x48000014
1 word (i.e. 32 bits)
Little Endian
*((uint32_t *) 0x48000014) |= 1UL<<14;
Dereferencing a pointer Bitwise OR
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Dereferencing a Memory Address
0x4800002C
0x48000028 0x48000024
0x48000020 0x4800001C
0x48000018
0x48000014
0x48000010
0x4800000C
0x48000008
0x48000004
0x48000000
typedef struct {
volatile uint32_t MODER; volatile uint32_t OTYPER; volatile uint32_t OSPEEDR; volatile uint32_t PUPDR; volatile uint32_t IDR; volatile uint32_t ODR; volatile uint32_t BSRR; volatile uint32_t LCKR; volatile uint32_t AFR[2]; volatile uint32_t BRR; volatile uint32_t ASCR;
} GPIO_TypeDef;
// Mode register
// Output type register
// Output speed register
// Pull-up/pull-down register
// Input data register
// Output data register
// Bit set/reset register
// Configuration lock register
// Alternate function registers // Bit Reset register
// Analog switch control register
// Casting memory address to a pointer
#define GPIOA ((GPIO_TypeDef *) 0x48000000)
GPIOA->ODR |= 1UL<<14; or (*GPIOA).ODR |= 1UL<<14;
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Memory layout used in the DE10-Standard Computer
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Parallel Ports
There are several parallel ports implemented in the FPGA
Support input, output, and bidirectional transfers of data between the ARM A9 processor and I/O peripherals.
Each parallel port is assigned a Base address and contains up to four 32-bit registers. Ports that have output capability include a writable Data register
Ports with input capability have a readable Data register.
Bidirectional parallel ports also include a Direction register
Each bit in the Data register can be configured as
An input by setting the corresponding bit in the Direction register to 0, or An output by setting this bit position to 1.
We will talk about two other registers later on.
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Red LED Output Parallel Port
The port contains a 10-bit Data register,
It has the address 0xFF200000.
This register can be written or read by the processor using word accesses The upper bits not used in the registers are ignored.
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Slider Switch Input Parallel Port
The SW0-9 slider switches on the board are connected to an input parallel
This port contains a 10-bit read-only Data register
It is mapped to address 0xFF200040.
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Example 1: A simple Program
It continuously reads the state of the slider switches on the DE1-SoC board and displays their state on the red LEDs.
The .equ assembler directive tells the assembler to substitute a value for a symbol or label R1 contains the address of LEDs: R1= 0xFF200000
R2 contains the address of SWITCHES: R2=0xFF200040
Based on this particular switches: R3=0x00000317
We can read the state of the output port if needed: R4=0x00000317 as presented in the last
line of the code.
14 INTEL® FPGA MONITOR PROGRAM TUTORIAL FOR ARM* ECE 3375b (A. Reyhani)
Example 1: A simple Program (cont.)
The pseudo-instruction LDR R1, =LEDs is replaced by actual instruction of ldr r1, [pc, #16]
Since Load instructions cannot specify 32-bit immediate operand, the address 0xFF200000 is
placed in the literal pool after the last instruction.
ldr r1, [pc, #16] uses relative addressing mode (PC has the base address with offset of #16) to
access the desired address value of 0x18
15 INTEL® FPGA MONITOR PROGRAM TUTORIAL FOR ARM* ECE 3375b (A. Reyhani)
Example 1: A simple Program (cont.)
Three-state Pipelining allows hardware resources to be fully utilized
In our example, the updated PC contents will be 0x08 when the first LDR instruction is
being executed
PC(instruction i Execution) +16= PC(instruction i+2 Fetch)+16= PC(instruction i Fetch)+8+16=0+8+16=0x18
Pipeline of 32-bit instructions
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7-Segment Displays Parallel Port
There are two parallel ports connected to the 7-segment
Each of which comprises a 32-bit write-only Data register.
Data can be written into these two registers, and read back, by using word operations.
Writing d1001111d1001111d0000111d1101101 in the data register with address 0xFF200020 displays 3375 in digits 0-3, where d is don’t care
0b01001111010011110000011101101101=0x4F4F076D
Writing 0x0000F939 in address 0xFF200020 displays EC in digits 4-5
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Example 2: 7-Segment Displays
The code (Seven_Seg_EC3375.s) displays EC3375 in seven-segment displays
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Pushbutton Key Parallel Port
The parallel port connected to the KEY3-0 pushbutton switches on the DE10- Standard board comprises three 4-bit registers
These registers have the base address 0xFF200050 and can be accessed using word operations.
The read-only Data register provides the values of the switches KEY3-0.
The other two registers at addresses 0xFF200058 and 0xFF20005C will be
discussed later.
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Example 3: Using the Parallel Ports with Assembly Language
The code (rotate2.s) displays the values of the SW switches on the LED lights.
A rotating pattern is displayed on the LEDs
This pattern is rotated to the left by using
an ARM A9 rotate instruction
a delay loop is used to make the shifting slow enough to observe.
The pattern can be changed to the values of the SW switches by pressing a pushbutton KEY.
When a pushbutton key is pressed, the program waits in a loop until the key is released.
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Example 4: Using the Parallel Ports with C Code
It performs the same operation as the previous assembly code does
Declare volatile pointers to I/O registers
so that the compiler does not perform
optimization on the code
volatileint*LED_ptr=(int*)LED_BASE;//LEDaddress
volatile int * S W_switch_ptr = (int *)S W_B ASE; // S W slider
switch address
volatile int * KE Y_ptr = (int *)KE Y_B ASE; // pushbutton KE Y address
A for loop is used for delay only without
performing anything inside the loop
The loop int variable is declared as volatile int so that the C compiler does not remove the loop
volatile int delay_count;
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C programs
01001 10101 11100 01011
Binary executable
Performance, Performance, Performance!
Compiler can make aggressive optimization
Cache results in register to reduce memory accesses Reorder computations
Eliminate useless and redundant computations
22 Embedded Systems with ARM Cortex-M Microcontrollers (Dr. Y. Zhu)
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Volatile variables
Qualifier volatile tells the compiler that this value may change at any time Do not apply any optimizations to remove reads or writes to these variables
volatile int x;
y = x + x + x + x;
The computation cannot complete within a single clock cycle and x can change any time.
Compiler cannot optimize it as:
variable x
This value may change any time.
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y = 4 * x;
y = x << 2;
Volatile variables (cont.)
Volatile forces compiler to generate executable that performs actual memory reads and writes, instead of caching values in registers!
Read volatile variable X in C
Write to volatile variable X in C
24 Embedded Systems with ARM Cortex-M Microcontrollers (Dr. Y. Zhu) ECE 3375b (A. Reyhani)
LDR r0, =x
LDR r1, [r0]
LDR r0, =x STR r1, [r0]
General Purpose Input/Output (GPIO)
8 GPIO Ports:
A, B, C, D, E, F, G, H
Up to 16 pins in each port
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General Purpose Input/Output (GPIO)
ARM Cortex-M4 FPU
APB Bus Matrix
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AHB Bus Matrix
Basic Structure of an I/O Port Bit Input and Output
Schmitt trigger
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Basic Structure of an I/O Port Bit: Output
GPIO Pull-up/Pull-down R
00=Nopull-up,pull-down 01 10 = Pull-down 11
GPIO Output Type Register (OTYPER) 0 = Output push-pull (default)
1 = Output open-drain
egister (PUPDR)
= Reserved
Data Register
GPIO MODE Register
00 = Input, 01 = Output,
10 = AF, 11 = Analog (default)
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Enable Clock
AHB2 peripheral clock enable register (RCC_AHB2ENR)
#define RCC_AHB2ENR_GPIOBEN ((uint32_t)0x00000002U) RCC->AHB2ENR |= RCC_AHB2ENR_GPIOBEN;
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Clock for Port B
GPIO Mode Register (MODER) 32 bits (16 pins, 2 bits per pin)
Pin 2 Pin 1 Pin 0
GPIOB->MODER &= ~(3UL<<4); // Clear bits 4 and 5 for Pin 2 GPIOB->MODER |= 1UL<<4; // Set bit 4, set Pin 2 as output
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GPIO Output Type Register (OTYPE) 16 bits reserved, 16 data bits, 1 bit for each pin
GPIO S Output Bit
GPIO Output Pin
GPIOB->OTYPE &= ~(1UL<<2); // Clear bit 2
Controller
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GPIO Input: Pull Up and Pull Down
A digital input can have three states: High, Low, and High-Impedance (also called floating, tri-stated, HiZ)
If external input is HiZ, the input is read as a valid HIGH.
If external input is HiZ, the input is read as a valid LOW.
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GPIO Output: Push-Pull
GPIO Output Pin
GPIO Output Bit
GPIO Output Pin
GPIO Output Bit
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Controller
Controller
GPIO Output = 1
Source current to external circuit
GPIO Output: Push-Pull
GPIO S Output Bit
GPIO Output Pin
GPIO Output Bit
GPIO Output Pin
Drain current
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Controller
Controller
GPIO Output = 0
Drain current from external circuit
GPIO Output: Open-Drain
OPEN DRAIN
GPIO Output Bit
GPIO Output Pin
GPIO Output Bit
GPIO Output Pin
Controller
Controller
GPIO Output = 0
Drain current from external circuit
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GPIO Output: Open-Drain
OPEN DRAIN
GPIO Output Bit
GPIO Output Pin
GPIO Output Bit
GPIO Output Pin
Controller
Controller
Output = 1
GPIO Pin has high-impedance to external circuit
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GPIO Output Speed
Output Speed:
Speed of rising and falling
Four speeds: Low, Medium, Fast, High
Tradeoff
Speed of Rising
Low Medium
Higher GPIO speed increases EMI noise and power consumption
Configure based on peripheral speed Fast Low speed for toggling LEDs
High speed for SPI
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Maximum rate of change of the output voltage
A high slew rate allows the output to be toggled at a fast speed.
𝑆𝑙𝑒𝑤 𝑅𝑎𝑡𝑒 = 𝑚𝑎𝑥
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GPIO Output: Push-Pull vs Open-Drain
Output Bit
Open-Drain
Use push-pull output, instead of open-drain output!
39 Embedded Systems with ARM Cortex-M Microcontrollers (Dr. Y. Zhu): Chapter 14 ECE 3375b (A. Reyhani)
GPIO Output Data Register (ODR) 16 bits reserved, 16 data bits, 1 bit for each pin
GPIOB->ODR |= 1UL << 2; // Set bit 2
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Light up the Red LED (PB.2)
RCC->AHB2ENR |= RCC_AHB2ENR_GPIOBEN; // Enable clock of Port B GPIOB->MODER &= ~(3UL<<4); // Clear mode bits
GPIOB->MODER |= 1UL<<4; // Set mode to output GPIOB->OTYPE &= ~(1UL<<2); // Select push-pull output GPIOB->ODR |= 1UL << 2; // Output 1 to turn on red LED
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GPIO Initialization
Turn on the clock to the GPIO Port (e.g. Port B)
RCC->AHBENR |= RCC_AHBENR_GPIOBEN; Reset and Clock Control (RCC)
Configure GPIO mode, output type, speed, pull-up/pull-down
typedef struct
__IO uint32_t MODER;
__IO uint16_t OTYPER;
uint16_t RESERVED0;
__IO uint32_t OSPEEDR;
__IO uint32_t PUPDR;
__IO uint16_t IDR;
uint16_t RESERVED1;
__IO uint16_t ODR;
uint16_t RESERVED2;
__IO uint16_t BSRRL; /* BSRR register is split to 2 * 16-bit fields BSRRL */ __IO uint16_t BSRRH; /* BSRR register is split to 2 * 16-bit fields BSRRH */ __IO uint32_t LCKR;
__IO uint32_t AFR[2]; } GPIO_TypeDef;
#define PERIPH_BASE #define AHBPERIPH_BASE #define GPIOB_BASE
((uint32_t)0x40000000)
(PERIPH_BASE + 0x20000)
(AHBPERIPH_BASE + 0x0400)
#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
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STM32L4 Discovery Kit
Joystick with 4- direction control and selector
Embedded Systems with ARM Cortex-M Microcontrollers (Dr. Y. Zhu): Chapter 14
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Internal diagram of joystick
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Basic Structure of an I/O Port Bit Input and Output
Schmitt trigger
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Basic Structure of an I/O Port Bit:
GPIO Pull-up/Pull-down Register (PUPDR)
00 = No pull-up, pull-down 10 = Pull-down
01 = Pull-up 11 = Reserved
Data Register
GPIO Output Type Register (OTYPER) 0 = Output push-pull (default)
1 = Output open-drain
10 = AF, 11 = Analog (default)
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GPIO MODE Register
00 = Input, 01 = Output,
Basic Structure of an I/O Port Bit Input and Output
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Basic Structure of an I/O Port Bit:
Schmitt trigger
• Reduce noise
• Increase slew
Input Data Register (IDR)
Input is sampled into IDR every AHB clock cycle!
GPIO Pull-up/Pull-down Register (PUPDR) 00 = No pull-up, pull-down 01 = Pull-up
10 = Pull-down 11 = Reserved
Embedded Systems with ARM Cortex-M Microcontrollers (Dr. Y. Zhu): Chapter 14
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