程序代写 #include

#include
#include
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int main(int argc, char* argv[]) {
if (argc < 2) { std::cerr << "Usage: " << argv[0] << " logfile" << std::endl; std::ifstream infile(argv[1]); std::string line; char op, colon; typedef unsigned int Instruction; typedef unsigned int Address; unsigned int data; Instruction previous = 0xdeadbeef; // This is a stupid cache. It has one entry of one word. Address cache[1]; cache[0] = 0xcafebabe; unsigned int cache_hits = 0; unsigned int cache_misses = 0; while (std::getline(infile, line)) { std::istringstream iss(line); if (!(iss >> op >> colon >> std::hex >> data)) {
std::cerr << "Parse error: " << line << std::endl; std::cout << std::hex << std::setfill('0') << std::setw(8) << std::showbase; * Here's where your logic goes. switch(op) { std::cout << "I see an instruction: " << data << std::endl; std::cout << "The previous instruction I ran was: " << previous << std::endl; previous = data; // for next time std::cout << "I accessed an instruction at address: " << data << std::endl; std::cout << "I issued a load from memory address: " << data << std::endl; // let's see if it's a hit! // our cache stores a whole word, so any access within the word // should be a hit data &= 0xfffffffc; // this sets bottom two bits to zero if (data == cache[0]) { cache_hits++; std::cout << "That data access was a hit in cache!" << std::endl; cache_misses++; std::cout << "That data access was a miss in cache!" << std::endl << "What was actually in that cache slot was " << cache[0] << std::endl; // now update the cache cache[0] = data; std::cout << "I issued a store to memory address: " << data << std::endl; std::cerr << "Something went wrong: I see op " << op << std::endl; return -1; std::cout << std::dec << std::setw(0) << std::noshowbase; std::cout << std::dec << "I saw " << cache_hits << " cache hits and " << cache_misses << " cache misses" << std::endl; 程序代写 CS代考 加微信: powcoder QQ: 1823890830 Email: powcoder@163.com