All registers and memory locations are 32 bits, the concept of byte does not apply except in the few special string-processing instructions. When characters are stored to make a string, they are packed four per memory location, with the first character of the string being in the least-significant 8 bits.
Negative numbers are represented in the two’s complement format.
Floating point numbers are stored in the intel 32-bit floating format, whatever that is.
Bits are numbered from 0, the least significant, to 31 the most significant. In numeric representations, bit 31 is the sign bit.
There are 16 regular registers, numbered from 0 to 15.
R0 is a scratch register, with slightly limited functionality
R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12 are general purpose registers SP, the stack pointer, is encoded as register 13
FP, the frame pointer, is encoded as register 14
PC, the program counter, is encoded as register 15
The instruction format
I is the Indirect bit. Two’s complement, range -32768 to +32767
If bits 16-19 are all zero, i.e. “Index Register” indicates R0, then no index register is used when the instruction executes. Thus it is not possible to use R0 as an index register.
In the description of an instruction, the term reg refers to the register indicated by bits 20 to 23 (main register), and operand refers to the combination of indirect bit, index register, and numeric operand as illustrated on the next two pages.
If the term value appears in the description, it refers to the value of the operand, which is calculated as follows:
part1 = numeric operand; part2 = 0;
if (index register 0)
part2 = contents of indicated index register total = part1 + part2;
if (indirect bit 0)
value = contents of memory location [total];
else
value = total;
If the sequence “reg ← x” appears, it means that the content of the main register is replaced by x.
If the sequence “destination ← x” appears, then the operand my consist of just an index register, in which case the content of the register is replaced by x, otherwise the indirect bit must be set, and the content of memory location [total] is replaced by x.
Operation
I
Main Register
Index Register
Numeric Operand
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Assembly Examples:
RET
0100101 0 0000 0000 0000000000000000 4AOOOOOO
INC R6
0000100 0 0110 0000 0000000000000000 O86OOOOO
LOAD R2, 36
0000001 0 0010 0000 0000000000100100 O22OOO24
ADD R7, R3
0000110 0 0111 0011 0000000000000000 OC73OOOO
LOAD R7,R3+12
0000001 0 0111 0011 0000000000001100 O273OOOC
ADD R4, [R3]
0000110 1 0100 0011 0000000000000000 OD43OOOO
STORE R2, [1234]
0000011 1 0010 0000 0000010011010010 O72OO4D2
STORE R2, [R5 ‐ 375]
0000011 1 0010 0101 1111111010001001 O725FE89
Operation Indirect bit Main register Index register Numeric
Operation Indirect bit Main register Index register Numeric
Operation Indirect bit Main register Index register Numeric
Operation Indirect bit Main register Index register Numeric
Operation Indirect bit Main register Index register Numeric
Operation Indirect bit Main register Index register Numeric
Operation Indirect bit Main register Index register Numeric
Operation Indirect bit Main register Index register Numeric
= 37 =0 =0 =0 =0
=4 =0 =6 =0 =0
=1 =0 =2 =0 =36
=6 =0 =7 =3 =0
=1 =0 =7 =3 =12
=6 =1 =4 =3 =0
=3 =1 =2 =0
= 1234
=3 =1 =2 =5
= -375
Execution Examples, starting from these values already in memory:
location
contents
27100 592
27101 759
27102 43
27103 27105
27104 2
27105 682
27106 11
27107 22
27108 33
LOAD R2, 5
LOAD R3, R2+4
LOAD R4, 27102
LOAD R5, [27100]
LOAD R6, [R4]
ADD R6, R2
STORE R6, [27101]
INC R6
STORE R6, [R4 ‐ 2]
LOAD SP, 27108
PUSH R2
PUSH [R4]
POP R4
STORE R6, 27101
The value
The value
The value
The value
The value
The value
The content of memory location 27101 is changed from 759 to 48 The value stored in register 6 is now 49
stored in register 2 is now 5 stored in register 3 is now 9 stored in register 4 is now 27102 stored in register 5 is now 592 stored in register 6 is now 43 stored in register 6 is now 48
The content of memory location 27100 is changed from 592 to 49 The value stored in register 13 (stack pointer) is now 27108
The content of memory location 27107 is changed from 22 to 5 The value stored in register 13 (stack pointer) is now 27107
The content of memory location 27106 is changed from 11 to 43 The value stored in register 13 (stack pointer) is now 27106
The value stored in register 4 is now 43
The value stored in register 13 (stack pointer) is now 27107
Fails to execute, as the operand does not address memory.
opcode mnemonic
0 HALT
1 LOAD reg, operand
2 LOADH reg, operand
3 STORE reg, operand
action
the processor is halted, execution of instructions stops.
reg ← value
reg ← ( reg FFFF ) + ( value « 16 )
the most significant 16 bits of the register are replaced
destination ← reg
destination ← value + 1
destination ← value ‐ 1
reg ← reg + value
reg ← reg ‐ value
reg ← reg × value
reg ← reg ÷ value
reg ← reg modulo value
reg ← value ‐ reg
reg ← value ÷ reg
reg ← value modulo reg
reg ← reg value
reg ← reg value
reg ← reg value
reg ← ~ value
flagZ ← 1 if most sig. (value) bits of reg all 0, otherwise 0 reg ← reg « value, zeros being inserted at the right
flagZ ← 1 if least sig. (value) bits of reg all 0, otherwise 0 reg ← reg » value, zeros being inserted at the left
flagZ ← 1 if reg = value, otherwise 0 flagN ← 1 if reg < value, otherwise 0
flagZ ← 1 if value = 0, otherwise 0 flagN ← 1 if value < 0, otherwise 0
flagZ ← valueth bit of reg valueth bit of reg ← 1 valueth bit of reg ← 0
4 INC
5 DEC
6 ADD
7 SUB
8 MUL
9 DIV
operand
operand reg, operand reg, operand reg, operand reg, operand reg, operand
10 MOD
11 RSUB reg, operand
12 RDIV reg, operand
13 RMOD reg, operand
14 AND reg, operand
15 OR reg, operand
16 XOR reg, operand
17 NOT reg, operand
18 SHL reg, operand
19 SHR reg, operand
20 COMP reg, operand
21 COMPZ operand
22 TBIT reg, operand
23 SBIT reg, operand
24 CBIT reg, operand
25 26 27 28 29
0 1 2 3 4 5 6
30 31 32 33 34
JUMP operand JZER reg, operand JPOS reg, operand JNEG reg, operand JCOND
JCOND EQL, operand JCOND NEQ, operand JCOND LSS, operand JCOND LEQ, operand JCOND GTR, operand JCOND GEQ, operand JCOND ERR, operand
GETFL reg, operand SETFL reg, operand GETSR reg, operand SETSR reg, operand PUSH operand
PC ← value if(reg=0)PC←value if (reg0)PC←value if(reg<0)PC←value
Note that no main register is used with the JCOND instruction. Instead, its 4 bits are used to encode one of the seven condition tests shown here.
if(flagZ)PC←value
if (~flagZ ) PC ← value if(flagN)PC←value
if (flagZflagN) PC←value
if ( ~flagZ ~flagN ) PC ← value if(~flagN)PC←value if(flagE)PC←value
reg ← flag[value]
flag[value] ← reg
reg ← specialregister[value]
specialregister[value] ← reg
SP ← SP‐1 memory[SP] ← value
destination ← memory[SP] SP ← SP+1
SP ← SP‐1 memory[SP] ← PC PC ← value
PC ← memory[SP] SP ← SP+1
value is treated as a memory address. The regth 8-bit byte (character) starting from that address in memory is loaded into reg. i.e.,
reg ← byte (reg modulo 4) of memory[value + reg÷4]
value is treated as a memory address. The regth 8-bit
byte (character) starting from that address is replaced by the value of register 0 without modifying the other 24 bits of that word.
byte (reg modulo 4) of memory[value + reg÷4] ← R0 Control peripheral activity: see separate documentation all flags ← reg
35
36 CALL
37 RET 38 LDCH
39 STCH
40 PERI
reg, operand
reg, operand
42
FLAGSJ reg, operand
POP operand operand
43 WAIT
44 PAUSE
45 BREAK
46 IRET
PC ← value
CPU idles until interrupted
CPU idles for approximately 50mS, unless interrupted Enter CPU single-stepping mode
all flags ← memory[SP+1] PC ← memory[SP+5]
FP ← memory[SP+6]
SP ← memory[SP+7]
R12 ← memory[SP+8] R11 ← memory[SP+9] R10 ← memory[SP+10] R9 ← memory[SP+11] R8 ← memory[SP+12] R7 ← memory[SP+13] R6 ← memory[SP+14] R5 ← memory[SP+15] R4 ← memory[SP+16] R3 ← memory[SP+17] R2 ← memory[SP+18] R1 ← memory[SP+19] R0 ← memory[SP+20] SP ← SP+21
47 SYSCALL reg, code
memory[SP-1]
memory[SP-2]
memory[SP-3]
memory[SP-4]
memory[SP-5]
memory[SP-6]
memory[SP-7]
memory[SP-8]
memory[SP-9]
memory[SP-10] ← R9
memory[SP-11] ← R10
memory[SP-12] ← R11
memory[SP-13] ← R12
memory[SP-14] ← SP
memory[SP-15] ← FP
memory[SP-16] ← PC
memory[SP-17] ← reg
memory[SP-18] ← main register number memory[SP-19] ← code
memory[SP-20] ← all flags
memory[SP-21] ← 40
SP ← SP‐21
PC ← memory[specialregister[CGBR] + code] flagSys ← 1
← R0 ← R1 ← R2 ← R3 ← R4 ← R5 ← R6 ← R7 ← R8
48 ATAS reg, operand
49 PHLOAD reg, operand
50 PHSTORE reg, operand
51 VTRAN reg, operand
52 MOVE reg, reg2
53 FADD reg, operand
54 FSUB reg, operand
55 FMUL reg, operand
56 FDIV reg, operand
57 FCOMP reg, operand
58 FCOMPZ reg, operand
59 FIX reg, operand
60 FRND reg, operand
61 FLOAT reg, operand
62 FLOG reg, operand
63 FEXP reg, operand
64 FFO reg, operand
65 FLZ reg, operand
66 RAND reg
reg ← value ; destination ← 1
performed indivisibly, ignoring interrupts
reg ← physicalmemory[value] physicalmemory[value] ← reg
reg ← physical address for virtual address value
while R0 > 0 repeat
{ memory[reg2] ← memory[reg]
reg2 ← reg2 + 1 reg ← reg + 1 R0 ← R0 ‐ 1 }
floating point: reg ← reg + value floating point: reg ← reg ‐ value floating point: reg ← reg × value floating point: reg ← reg ÷ value
floating point:
flagZ ← 1 if reg = value, otherwise 0 flagN ← 1 if reg < value, otherwise 0
floating point:
flagZ ← 1 if reg = 0, otherwise 0 flagN ← 1 if reg < 0, otherwise 0
reg ← (int)value, value interpreted as floating point reg ← (float)(closest int to value), both floating point reg ← (float)value, value interpreted as an integer
floating point:
reg←naturallog(reg), if value=0 reg ← log base value(reg), otherwise
floating point:
reg←etopower(reg), if value=0 reg ←value to power(reg), otherwise
reg ← number of bits to right of first 1 in value if value = 0: reg ← ‐1, flagZ ← 1, flagN ← 1
reg ← number of bits to right of last 0 in value if value =‐1: reg ←‐1, flagZ ← 1, flagN ← 1
reg ← random positive number
67 TRACE reg, operand
68 TYPE operand
69 INCH operand
70 ANDN reg, operand
71 ORN reg, operand
72 NEG reg, operand
73 FNEG reg, operand
74 ROTL reg, operand
75 ROTR reg, operand
76 ASR reg, operand
77 EXBR reg, operand
78 EXBRV reg, operand
79 DPBR reg, operand
80 DPBRV reg, operand
81 ADJS reg, operand
82 UEXBR reg, operand
83 UEXBRV reg, operand
84 UCOMP reg, operand
85 UMUL reg, operand
86 UDIV reg, operand
87 UMOD reg, operand
88 CLRPP operand
89 FILL reg, operand
display PC, reg, and value on console
send single character value to controlling teletype
destination ← one character code from controlling keyboard or ‐1 if none available
reg←reg~value
reg←reg~value
reg ← ‐ value
reg ← ‐ value, value interpreted as floating point
reg is shifted value bits left, with the bits lost at the left being reinserted at the right.
reg is shifted value bits right, with the bits lost at the right being reinserted at the left.
flagZ ← 1 if least sig. (value) bits of reg all 0, otherwise 0 reg ← reg » value, the sign bit being duplicated at the left
R0 ← bit range described by reg from value,
with the most significant bit of the range giving the sign.
R0 ← bit range described by reg of value,
with the most significant bit of the range giving the sign.
bit range described by reg from value ← R0. bit range described by reg of value ← R0.
the bit range selector in reg is advanced by value positions, taking into account the range size and the requirement for ranges not to span two words. value may be negative.
R0 ← bit range described by reg from value, unsigned. R0 ← bit range described by reg of value, unsigned.
flagZ ← 1 if reg = value, otherwise 0
flagN ← 1 if reg < value, otherwise 0, an unsigned comparison
reg ← reg × value, unsigned
reg ← reg ÷ value, unsigned
reg ← reg modulo value, unsigned
page containing physical address value all set to zero
while R0 > 0 repeat
{ memory[reg2] ← value
reg ← reg + 1 R0 ← R0 ‐ 1 }