The Chinese University of Hong Kong Department of Electronic Engineering
ELEG3202 Homework 3
Submission Date: 22 March 2021, 2:00pm, via CUHK Blackboard No late submission will be accepted
You are asked to design TWO opamps: a folded cascode opamp and a two-stage Miller-compensated opamp. You need to submit a report for both opamps. In the report, you have to include circuit diagrams (accept hand drawn), netlists, hand calculations (accept hand written), tables to compare simulated and hand calculated results, as well as simulated plots. Details can be referred to “HW3_example.doc”.
Guidelines:
1. Your circuit should be implemented by transistors using the provided transistor models.
2. For each opamp, you can use two ideal voltage sources for VDD and VSS and one ideal current source to
provide the bias current. 3. ALL transistors must have
NMOS: VGSN – VTHN > 50mV and
PMOS:|VSGP|-|VTHP|>50mV.
4. Channel length: L ≥ 2μm (since the provided CMOS technology has minimum channel length of 2μm).
5. Violation of the rules of transistor sizing (even only one transistor in the circuit) will result in zero mark for that
part (i.e. Part I and II) of homework.
6. You have to submit a report for the homework. For the requirement of the report, you can refer to
“HW3_template.doc”. For more details, you can refer to the provided example “HW3_example.pdf”.
7. Mark all the simulation results (low-frequency voltage gain, UGF, phase margin, SR and output swing) using the
cursors (refer the provided example “HW3_example.pdf”).
Part I: Folded Cascode Opamp Design (Full mark = 5)
Design a differential-input single-ended folded cascode opamp using the provided transistor model (i.e. mosfet_model.txt).
Supply voltage
VDD = 2.5V (fixed) and VSS = -2.5V (fixed)
Output capacitance
CO = 100pF (fixed)
Low-frequency voltage gain (Spec.)
≥ 100dB
UGF (Spec.)
≥ 10MHz
SR (Spec.)
≥ 6V/μs (apply a step input from 0V to 1V and measure the slope between 0.2V and 0.8V)
Output Swing (Spec.)
-2.3V ≤ VO ≤ 2.3V
Phase Margin (Spec.)
≥ 60o
Current Consumption (Spec.)
≤ 500μA
p. 1
Grading for Part I
Violations of sizing & VGS – VTH ⇒ 0 Mark
No violation of spec. ⇒ 4 Marks
1 violation of spec. ⇒ 3 Marks
2 violations of spec. ⇒ 2 Marks
3 violations of spec. ⇒ 1 Mark
4 or more violations of spec. ⇒ 0 Mark
Hand calculations: 1 Mark
Part II: Two-stage Miller-Compensated Opamp Design (Full mark = 5)
Design a differential-input single-ended two-stage Miller-compensated opamp using the provided transistor model (i.e. mosfet_model.txt).
Supply voltage
VDD = 2.5V (fixed) and VSS = -2.5V (fixed)
Output capacitance
CO = 100pF (fixed)
Low-frequency voltage gain (Spec.)
≥ 100dB
UGF (Spec.)
≥ 5MHz
SR (Spec.)
≥ 4.5V/μs (apply a step input from 0V to 1V and measure the slope between 0.2V and 0.8V)
Output Swing (Spec.)
-2.3V ≤ VO ≤ 2.3V
Phase Margin (Spec.)
≥ 60o
Current Consumption (Spec.)
≤ 700μA
Grading for Part II
Hand calculations: 1 Mark
Violations of sizing & VGS – VTH ⇒ 0 Mark
No violation of spec. ⇒ 4 Marks
1 violation of spec. ⇒ 3 Marks
2 violations of spec. ⇒ 2 Marks
3 violations of spec. ⇒ 1 Mark
4 or more violations of spec. ⇒ 0 Mark
− END −
p. 2