Low on cache?
Caches, Part I
Slides from Patterson’s 61C, Fall 2001
• Memory Hierarchy
• Direct-Mapped Cache
• Types of Cache Misses
• A (long) detailed example
Outline
McGill COMP 273 2
Slides from Patterson’s 61C, Fall 2001
Memory Hierarchy (1/4)
• Processor
– executes programs
– runs on order of nanoseconds to picoseconds
– needs to access code and data for programs: where are these?
• Disk
– HUGE capacity (virtually limitless)
– VERY slow: runs on order of milliseconds – so how do we account for this gap?
McGill COMP 273 3
Slides from Patterson’s 61C, Fall 2001
Memory Hierarchy (2/4)
• Memory (DRAM)
– smaller than disk (not limitless capacity)
– contains subset of data on disk: basically portions of programs that are currently being run
– much faster than disk: memory accesses don’t slow down processor quite as much
– Problem: memory is still too slow (hundreds of nanoseconds)
– Solution: add more layers (caches)
McGill COMP 273 4
Slides from Patterson’s 61C, Fall 2001
Memory Hierarchy (3/4)
Processor
Level 1
Level 2
Level 3 . .. Level n
Higher
Levels in
memory hierarchy
Lower
Increasing Distance from Proc., Decreasing speed
Size of memory at each level
As we move to deeper levels the latency goes up and price per bit
goes down.
McGill COMP 273 5
Slides from Patterson’s 61C, Fall 2001
Memory Hierarchy (4/4)
• If level is closer to Processor, it must… – Be smaller
– Be faster
– Contain a subset (most recently used data) of lower levels beneath it
(i.e., levels farther from processor)
– Contain all the data in higher levels above it (i.e., levels closer to processor)
• Lowest Level (usually disk) contains all available data • Is there another level lower than disk?
McGill COMP 273 6
Slides from Patterson’s 61C, Fall 2001
Memory Hierarchy
Computer
Keyboard, Mouse
Disk, Network
Display, Printer
Processor
(active)
Control
(“brain”)
Datapath
(“brawn”)
Memory
(passive) (where programs, data live when running)
Devices Input
Output
• Purpose:
– Faster access to large memory from processor
McGill COMP 273 7
Slides from Patterson’s 61C, Fall 2001
Memory Hierarchy Analogy: Library (1/2)
• You (the processor) are writing a term paper at a table in Schulich
• Schulich Library is equivalent to disk – essentially limitless capacity
– very slow to retrieve a book
• Table is memory
– smaller capacity: means you must return book when table fills up
– easier and faster to find a book there once you’ve already retrieved it
McGill COMP 273 8
Slides from Patterson’s 61C, Fall 2001
Memory Hierarchy Analogy: Library (2/2) • Open books on table are cache
– smaller capacity: can have very few open books fit on table; again, when table fills up, you must close a book
– much, much faster to retrieve data
• Illusion created: whole library open on the tabletop
– Keep as many recently used books open on table as possible since likely to use again
– Also keep as many books on table as possible, since faster than going to library
McGill COMP 273 9
Slides from Patterson’s 61C, Fall 2001
Memory Hierarchy Basis
• Disk contains everything
• When Processor needs something, bring it into to all lower levels of memory
• Cache contains copies of data in memory that are being used
• Memory contains copies of data on disk that are being used
• Entire idea is based on Temporal Locality: if we use it now, we’ll want to use it again soon (a Big Idea)
McGill COMP 273 10
Slides from Patterson’s 61C, Fall 2001
McGill COMP 273 11
Slides from Patterson’s 61C, Fall 2001
Athlon XP-64 Core
• The greatest share of the surface (over 50 percent) is taken up by the 1 MB L2 cache.
McGill COMP 273 12
Slides from Patterson’s 61C, Fall 2001
Cache Design • How do we organize cache?
• Where does each memory address map to?
– Remember that cache is subset of memory, so multiple memory
addresses map to the same cache location.
• How do we know which elements are in cache? • How do we quickly locate them?
McGill COMP 273 13
Slides from Patterson’s 61C, Fall 2001
Direct-Mapped Cache (1/2)
• In a direct-mapped cache, each memory address is associated
with one possible block within the cache
– Therefore, we only need to look in a single location in the cache to
see if the data exists in the cache
– A block is the unit of transfer between cache and memory
McGill COMP 273 14
Slides from Patterson’s 61C, Fall 2001
Memory Address
0 1 2 3 4 5 6 7 8 9 A B C D E F
Direct-Mapped Cache (2/2)
Memory
Cache Index
0 1 2 3
4 Byte Direct Mapped Cache
• Cache Location 0 can be occupied by data from:
– Memory location 0, 4, 8, … – In general: any memory
location that is multiple of 4
McGill COMP 273 15
Slides from Patterson’s 61C, Fall 2001
1
2
•
Issues with Direct-Mapped
Since multiple memory addresses map to same cache index, how do we tell which one is in there?
What if we have a block size > 1 byte?
Solution: divide memory address into three fields
tttttttttttttttttt
iiiiiiiiii
oooo
tag
to check
if have correct block
index
to select block
offset
byte within block
McGill COMP 273
16
Slides from Patterson’s 61C, Fall 2001
Direct-Mapped Cache Terminology • All fields are read as unsigned integers.
• The Index: specifies the cache index (which “row” of the cache we should look in)
• The Offset: once we’ve found correct block, specifies which byte within the block we want
• The Tag: the remaining bits after offset and index are determined; these are used to distinguish between all the memory addresses that map to the same location
McGill COMP 273 17
Slides from Patterson’s 61C, Fall 2001
Direct-Mapped Cache Example
• Suppose we have a direct-mapped 16KB cache with 4 word
blocks.
• Determine the size of the tag, index and offset fields if we’re using a 32-bit architecture.
McGill COMP 273 18
Slides from Patterson’s 61C, Fall 2001
Direct-Mapped Cache Example
• Offset
– need to specify correct byte within a block
– block contains
4 words = 16 bytes = 24 bytes
– need 4 bits to specify correct byte
McGill COMP 273 19
Slides from Patterson’s 61C, Fall 2001
Direct-Mapped Cache Example
• Index
– need to specify correct row in cache
– cache contains 16 KB = 24 210 = 214 bytes block contains 24 bytes (4 words)
# rows/cache
= # blocks/cache (there’s one block/row) bytes/cache
=
bytes/row
214 bytes/cache
=
= 210 rows/cache
24 bytes/row
– need 10 bits to specify this many rows
McGill COMP 273 20
Slides from Patterson’s 61C, Fall 2001
• Tag
Direct-Mapped Cache Example – used remaining bits as tag
– tag length = memory address bits minus offset bits minus index bits = 32 – 4 – 10 bits
= 18 bits
– so the tag is leftmost 18 bits of memory address
McGill COMP 273 21
Slides from Patterson’s 61C, Fall 2001
Accessing data in a direct mapped cache
• Example: 16KB, direct- mapped, 4 word blocks
• Read 4 addresses
0x00000014 0x0000001C 0x00000034 0x00008014
• Memory values on right:
– Let us only consider cache and memory levels of hierarchy
Memory
Address (hex)
00000010
00000018
0000001C
…
00000030
00000038 0000003C
Value of Word
…
…
McGill COMP 273
22
00000014
a
b
c
d
…
00000034
e
f
g
…
h
00008010
00008018
0000801C
…
00008014
…
…
i
j
k
l
Slides from Patterson’s 61C, Fall 2001
Accessing data in a direct mapped cache
• 4 Addresses:
0x00000014, 0x0000001C, 0x00000034, 0x00008014
• 4 Addresses divided (for convenience) into Tag, Index, Byte Offset fields
000000000000000000 0000000001 0100
000000000000000000 0000000001 1100
000000000000000000 0000000011 0100
000000000000000010 0000000001 0100
Tag Index Offset
McGill COMP 273
23
Slides from Patterson’s 61C, Fall 2001
Accessing data in a direct mapped cache
• Lets go through accessing some data in this cache
– 16KB, direct-mapped, 4 word blocks
• Will see 3 types of events:
• cache miss: nothing in cache in appropriate block, so fetch from memory
• cache hit: cache block is valid and contains proper address, so read desired word
• cache miss, block replacement: wrong data is in cache at appropriate block, so discard it and fetch desired data from memory
McGill COMP 273 24
Slides from Patterson’s 61C, Fall 2001
16 KB Direct Mapped Cache, 16B blocks
Valid
0x0-3
Example Block
0x4-7 0x8-b 0xc-f
Index Tag
0 1 2 3 4 5 6 7
0
0
0
0
0
Valid bit: determines if anything
is stored in that row (when
computer initially turned on, all
0
0
0
entries are invalid)
…
…
1022 0 1023 0
McGill COMP 273 25
Slides from Patterson’s 61C, Fall 2001
Valid
Tag field
0x0-3
Index field Offset
0x4-7 0x8-b 0xc-f
Index Tag
0 1 2 3 4 5 6 7
Read 0x00000014
000000000000000000 0000000001 0100
0
0
0
0
0
0
0
0
…
1022 0 1023 0
…
McGill COMP 273 26
Slides from Patterson’s 61C, Fall 2001
So we read block 1 (0000000001)
000000000000000000 0000000001 0100
Valid
Index Tag
1
2 3 4 5 6 7
…
1022 0 1023 0
Tag field
0x0-3
Index field Offset
0x4-7 0x8-b 0xc-f
0
0
0
0
0
0
0
0
0
…
McGill COMP 273 27
Slides from Patterson’s 61C, Fall 2001
No valid data
000000000000000000 0000000001 0100
Valid
Index Tag 0
1
2 3 4 5 6 7
…
1022 0 1023 0
Tag field
0x0-3
Index field Offset
0x4-7 0x8-b 0xc-f
0
0
0
0
0
0
0
0
…
McGill COMP 273 28
Slides from Patterson’s 61C, Fall 2001
0 1 2 3 4 5 6 7
So load that data into cache, setting tag, valid
000000000000000000 0000000001 0100
Valid
Tag field
0x0-3
Index field Offset
0x4-7 0x8-b 0xc-f
Index Tag
0
1
0
a
b
c
d
0
0
0
0
0
0
…
1022 0 1023 0
…
McGill COMP 273 29
Slides from Patterson’s 61C, Fall 2001
Read from cache at offset, return word b 000000000000000000 0000000001 0100
Valid
Index Tag
1
2 3 4 5 6 7
…
10220 10230
Tag field
0x0-3
Index field Offset
0x4-7 0x8-b 0xc-f
0
0
1
0
a
b
c
d
0
0
0
0
0
0
…
McGill COMP 273 30
Slides from Patterson’s 61C, Fall 2001
Valid
Tag field
0x0-3
Index field Offset
0x4-7 0x8-b 0xc-f
Index Tag
0 1 2 3 4 5 6 7
Read 0x0000001C
000000000000000000 0000000001 1100
0
1
0
a
b
c
d
0
0
0
0
0
0
…
1022 0 1023 0
…
McGill COMP 273 31
Slides from Patterson’s 61C, Fall 2001
Data valid, tag OK, so read offset return word d 000000000000000000 0000000001 1100
Valid
Index Tag
1
2 3 4 5 6 7
…
1022 0 1023 0
Tag field
0x0-3
Index field Offset
0x4-7 0x8-b 0xc-f
0
1
0
a
b
c
d
0
0
0
0
0
0
0
…
McGill COMP 273 32
Slides from Patterson’s 61C, Fall 2001
Valid
Tag field
0x0-3
Index field Offset
0x4-7 0x8-b 0xc-f
Index Tag
0 1 2 3 4 5 6 7
Read 0x00000034
000000000000000000 0000000011 0100
0
1
0
a
b
c
d
0
0
0
0
0
0
…
1022 0 1023 0
…
McGill COMP 273 33
Slides from Patterson’s 61C, Fall 2001
0 1 2 3 4 5 6 7
Valid
Tag field
0x0-3
Index field Offset
0x4-7 0x8-b 0xc-f
So read block 3
000000000000000000 0000000011 0100
Index Tag
0
1
0
a
b
c
d
0
0
0
0
0
0
…
1022 0 1023 0
…
McGill COMP 273 34
Slides from Patterson’s 61C, Fall 2001
0 1 2 3 4 5 6 7
Valid
Tag field
0x0-3
Index field Offset
0x4-7 0x8-b 0xc-f
No valid data
000000000000000000 0000000011 0100
Index Tag
0
1
0
a
b
c
d
0
0
0
0
0
0
…
1022 0 1023 0
…
McGill COMP 273 35
Slides from Patterson’s 61C, Fall 2001
0 1 2 3 4 5 6 7
Load that cache block, return word f 000000000000000000 0000000011 0100
Valid
Tag field
0x0-3
Index field Offset
0x4-7 0x8-b 0xc-f
Index Tag
0
1
0
a
b
c
d
0
1
0
e
f
g
h
0
0
0
0
…
1022 0 1023 0
…
McGill COMP 273 36
Slides from Patterson’s 61C, Fall 2001
Valid
Tag field
0x0-3
Index field Offset
0x4-7 0x8-b 0xc-f
Index Tag
0 1 2 3 4 5 6 7
Read 0x00008014
000000000000000010 0000000001 0100
0
1
0
a
b
c
d
0
1
0
e
f
g
h
0
0
0
0
…
1022 0 1023 0
…
McGill COMP 273 37
Slides from Patterson’s 61C, Fall 2001
So we read block 1, Data is Valid
000000000000000010 0000000001 0100
Valid
Index Tag
1
2 3 4 5 6 7
…
1022 0 1023 0
Tag field
0x0-3
Index field Offset
0x4-7 0x8-b 0xc-f
0
0
1
0
a
b
c
d
0
1
0
e
f
g
h
0
0
0
0
…
McGill COMP 273 38
Slides from Patterson’s 61C, Fall 2001
Cache Block 1 Tag does not match (0 != 2)
000000000000000010 0000000001 0100
Valid
Index Tag
1
2 3 4 5 6 7
…
1022 0 1023 0
Tag field
0x0-3
Index field Offset
0x4-7 0x8-b 0xc-f
0
0
1
0
a
b
c
d
0
1
0
e
f
g
h
0
0
0
0
…
McGill COMP 273 39
Slides from Patterson’s 61C, Fall 2001
Miss, replace block 1 with new data & tag 000000000000000010 0000000001 0100
Valid
Tag field
0x0-3
Index field Offset
0x4-7 0x8-b 0xc-f
Index Tag
0 1 2 3 4 5 6 7
0
1
2
i
j
k
l
0
1
0
e
f
g
h
0
0
0
0
…
1022 0 1023 0
…
McGill COMP 273 40
Slides from Patterson’s 61C, Fall 2001
Valid
Tag field
0x0-3
Index field Offset
0x4-7 0x8-b 0xc-f
Index Tag
And return word j 000000000000000010 0000000001 0100
0
1
2
i
j
k
l
0
1
0
e
f
g
h
0
0
0
0
0 1 2 3 4 5 6 7
…
1022 0 1023 0
…
McGill COMP 273 41
Slides from Patterson’s 61C, Fall 2001
Do an example yourself. What happens?
• Cache: Hit, Miss, Miss with replace ? Values returned: a ,b, c, d, e, …, k, l ?
• Read address 0x00000030 ? 000000000000000000 0000000011 0000
• Read address 0x0000001c ? 000000000000000000 0000000001 1100
Cache
Valid Index Tag
0x0-3
0x4-7 0x8-b 0xc-f
0 1 2 3 4 5 6
0
1
0
1
2
0
i
e
j
f
k
g
l
h
0
0
0
0
7
…
…
McGill COMP 273 42
Slides from Patterson’s 61C, Fall 2001
Answers
• 0x00000030 a hit Index = 3, Tag matches,
Offset = 0, value = e • 0x0000001c a miss
Index = 1, Tag mismatch, so replace from memory, Offset = 0xc, value = d
• Therefore,returned values are:
– 0x00000030 = e – 0x0000001c = d
Memory
Address
…
00000010 00000014 00000018 0000001c
…
00000030
00000034
00000038
0000003c
Value of Word
…
a
b
c
d
…
e
f
g
McGill COMP 273
43
…
h
00008010 00008014 00008018
0000801c
…
…
…
i
j
k
l
Slides from Patterson’s 61C, Fall 2001
“And in Conclusion…”
• We would like to have the capacity of disk at the speed of the processor: unfortunately this is not feasible.
• So we create a memory hierarchy:
– each successively higher level contains “most used” data from next
lower level
– exploits temporal locality and spatial locality
– do the common case fast, worry less about the exceptions (design principle of MIPS)
• Locality of reference is a Big Idea
McGill COMP 273 44
Slides from Patterson’s 61C, Fall 2001
Review and More Information • Sections 5.1 – 5.3 of textbook
McGill COMP 273 45
Slides from Patterson’s 61C, Fall 2001