ModelSim® Tutorial
Software Version 10.1d
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Table of Contents
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Assumptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Before you Begin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Example Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Conceptual Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Basic Simulation Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Project Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Multiple Library Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Debugging Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Basic Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Create the Working Design Library. . . . . . . . . …………………………….. 13 Compile the Design Units . . . . . . . . . . . . . . . . …………………………….. 15 Load the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . 16 Run the Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . 19 Set Breakpoints and Step through the Source . …………………………….. 20
Projects. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Create a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Add Objects to the Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Changing Compile Order (VHDL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Compile the Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Load the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Organizing Projects with Folders. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Add Folders. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Moving Files to Folders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Simulation Configurations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Working With Multiple Libraries. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Creating the Resource Library . . Creating the Project . . . . . . . . . . Linking to the Resource Library
Verilog . . . . . . . . . . . . . . . . . . VHDL . . . . . . . . . . . . . . . . . . . Linking to a Resource Library
… ……………………………………. 37 ……………………………………. … 39 . ……………………………………… 40 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . 40 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . 41 … ……………………………………. 42
ModelSim Tutorial, v10.1d
Viewing And Initializing Memories
View a Memory and its Contents. . . Navigate Within the Memory . . . . Export Memory Data to a File . . . . . Initialize a Memory . . . . . . . . . . . . . Interactive Debugging Commands .
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. …………………………………… 54 . …………………………………… 58 . …………………………………… 60 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . 61 . …………………………………… 64
Automating Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Creating a Simple DO File. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Running in Command-Line Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Using Tcl with the Simulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
End-User License Agreement
Table of Contents
Permanently Mapping VHDL Resource Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Analyzing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Loading a Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Add Objects to the Wave Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Zooming the Waveform Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Using Cursors in the Wave Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Working with a Single Cursor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Working with Multiple Cursors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
4 ModelSim Tutorial, v10.1d
Figure 4-1. Create Project Dialog – Project Lab … .
Figure 4-2. Adding New Items to a Project . . . . … .
Figure 4-3. Add file to Project Dialog. . . . . . . . … .
Figure 4-4. Newly Added Project Files Display a ’?’
Figure 4-5. Compile Order Dialog. . . . . . . . . . . … .
Figure 4-6. Library Window with Expanded Library
Figure 4-7. Structure(sim) window for a Loaded Design
Figure 4-8. Adding New Folder to Project . . . . . . . . . . .
Figure 4-9. A Folder Within a Project . . . . . . . . . . . . . . .
Figure 4-10. Creating Subfolder . . . . . . . . . . . . . . . . . . .
Figure 4-11. A folder with a Sub-folder . . . . . . . . . . . . .
Figure 4-12. Changing File Location via the Project Compiler Settings Dialog. . . . . . . . . . 33
Figure 4-13. Simulation Configuration Dialog . . . . . . . . . . . . . . . . . . . Figure 4-14. A Simulation Configuration in the Project window . . . . . Figure 4-15. Transcript Shows Options for Simulation Configurations
. …………… 34 . …………… 35 . …………… 35 . …………… 38 . …………… 39 . …………… 41 . …………… 42 . …………… 43 . …………… 45 . …………… 48 . …………… 49
Figure 5-1. Creating New Resource Library . . . . . . . . . . . . . . . . . . . Figure 5-2. Compiling into the Resource Library . . . . . . . . . . . . . . . Figure 5-3. Verilog Simulation Error Reported in Transcript . . . . . . Figure 5-4. VHDL Simulation Warning Reported in Main Window Figure 5-5. Specifying a Search Library in the Simulate Dialog. . . . Figure 6-1. Panes of the Wave Window . . . . . . . . . . . . . . . . . . . . . . Figure 6-2. Zooming in with the Mouse Pointer . . . . . . . . . . . . . . . . Figure 6-3. Working with a Single Cursor in the Wave Window . . .
.. .. .. .. .. .. .. ..
. …………. . …………. . …………. for Status . . . . . .
. ………. . ………. . ………. . ………. . ………. . ………. . ……….
List of Figures
Figure 2-1. Basic Simulation Flow – Overview Lab . . . .
Figure 2-2. Project Flow . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 2-3. Multiple Library Flow. . . . . . . . . . . . . . . . . .
Figure 3-1. The Create a Dialog. . . . . . . . .
Figure 3-2. work Library Added to the Library Window
Figure 3-3. Compile Source Files Dialog . . . . . . . . . . . .
Figure 3-4. Verilog Modules Compiled into work Library
Figure 3-5. Loading Design with Start Simulation Dialog
Figure 3-6. The Design Hierarchy . . . . . . . . . . . . . . . . . . .
Figure 3-7. The Object Window and Processes Window .
Figure 3-8. Using the Popup Menu to Add Signals to Wave Window . Figure 3-9. Waves Drawn in Wave Window. . . . . . . . . . . . . . . . . . . . . Figure 3-10. Setting Breakpoint in Source Window . . . . . . . . . . . . . . . Figure 3-11. Setting Restart Functions . . . . . . . . . . . . . . . . . . . . . . . . . Figure 3-12. Blue Arrow Indicates Where Simulation Stopped.. . . . . . Figure 3-13. Values Shown in Objects Window . . . . . . . . . . . . . . . . . . Figure 3-14. Parameter Name and Value in Source Examine Window
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. …………… 9 . . . . . . . . . . . . . . .. 11 . …………… 12 . …………… 14 . …………… 15 . …………… 16 . …………… 16 . …………… 17 . …………… 18 . …………… 18 . …………… 19 . …………… 20 . …………… 21 . …………… 21 . …………… 22 . …………… 22 . …………… 23 . …………… 26 . …………… 27 . …………… 27 . …………… 28 . …………… 29 . …………… 30 . …………… 30 . …………… 31 . …………… 32 . …………… 32 . …………… 32
ModelSim Tutorial, v10.1d
Figure 6-6. A Locked Cursor in the Wave Window . .
Figure 7-1. The Memory List in the Memory window
Figure 7-2. Verilog Memory Data Window . . . . . . ..
Figure 7-3. VHDL Memory Data Window . . . . . . . ..
Figure 7-4. Verilog Data After Running Simulation ..
Figure 7-5. VHDL Data After Running Simulation ..
Figure 7-6. Changing the Address Radix. . . . . . . . . ..
Figure 7-7. Radix and Line Length (Verilog.
Figure 7-8. Radix and Line Length (VHDL)
Figure 7-9. Goto Dialog. . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 7-10. Editing the Address Directly. . . . . . . . . . . . . .
Figure 7-11. Searching for a Specific Data Value . . . . . . . .
Figure 7-12. Export Memory Dialog . . . . . . . . . . . . . . . . . .
Figure 7-13. Import Memory Dialog . . . . . . . . . . . . . . . . . .
Figure 7-14. Initialized Memory from File and Fill Pattern
Figure 7-15. Data Increments Starting at Address 251 . . . .
Figure 7-16. Original Memory Content. . . . . . . . . . . . . . . .
Figure 7-17. Changing Memory Content for a Range of Addresses**OK . . . . . . . . . . . . . . 65 Figure 7-18. Random Content Generated for a Range of Addresses. . . . . . . . . . . . . . . . . . . 66 Figure 7-19. Changing Memory Contents by Highlighting. . . . . . . . . . . . . . . . . . . . . . . . . . 66 Figure 7-20. Entering Data to Change**OK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Figure 7-21. Changed Memory Contents for the Specified Addresses . . . . . . . . . . . . . . . . . 67 Figure 8-1. Wave Window After Running the DO File. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Figure 8-2. The counter.wlf Dataset in the Main Window Workspace. . . . . . . . . . . . . . . . . 72
… . … . … . … . … . … . … .
List of Figures
Figure 6-4. Renaming a Cursor . . . . . . . . . . . . . . . . . . . . . . Figure 6-5. Interval Measurement Between Two Cursors. .
. …………………… 50 . …………………… 50 . …………………… 51 . …………………… 54 . …………………… 55 . …………………… 55 . …………………… 56 . …………………… 56 . …………………… 57 . …………………… 57 . …………………… 58 . . . . . . . . . . . . . . . . . . . . . . . .. 58 . …………………… 59 . …………………… 59 . …………………… 60 . …………………… 62 . …………………… 63 . …………………… 64 . …………………… 65
ModelSim Tutorial, v10.1d
Introduction
Assumptions
Using this tutorial for ModelSimTM is based on the following assumptions:
• You are familiar with how to use your operating system, along with its window management system and graphical interface: OpenWindows, OSF/Motif, CDE, KDE, GNOME, or Microsoft Windows XP.
• You have a working knowledge of the language in which your design and/or test bench is written (such as VHDL, Verilog). Although ModelSim is an excellent application to use while learning HDL concepts and practices, this tutorial is not intended to support that goal.
Before you Begin
Preparation for some of the lessons leaves certain details up to you. You will decide the best way to create directories, copy files, and execute programs within your operating system. (When you are operating the simulator within ModelSim’s GUI, the interface is consistent for all platforms.)
Examples show Windows path separators – use separators appropriate for your operating system when trying the examples.
Example Designs
ModelSim comes with Verilog and VHDL versions of the designs used in these lessons. This allows you to do the tutorial regardless of which license type you have. Though we have tried to minimize the differences between the Verilog and VHDL versions, we could not do so in all cases. In cases where the designs differ (e.g., line numbers or syntax), you will find language- specific instructions. Follow the instructions that are appropriate for the language you use.
ModelSim Tutorial, v10.1d 7
Introduction
Before you Begin
8 ModelSim Tutorial, v10.1d
Conceptual Overview
Introduction
ModelSim is a verification and simulation tool for VHDL, Verilog, SystemVerilog, and mixed- language designs.
This lesson provides a brief conceptual overview of the ModelSim simulation environment. It is divided into fourtopics, which you will learn more about in subsequent lessons.
• Basic simulation flow — Refer to Chapter 3, Basic Simulation.
• Project flow — Refer to Chapter 4, Projects.
• Multiple library flow — Refer to Chapter 5, Working With Multiple Libraries.
• Debugging tools — Refer to remaining lessons.
Basic Simulation Flow
The following diagram shows the basic steps for simulating a design in ModelSim.
Figure 2-1. Basic Simulation Flow – Overview Lab
Create a working library
Compile design files
Load and Run simulation
• Creating the Working Library
Debug results
ModelSim Tutorial, v10.1d
Conceptual Overview
Project Flow
In ModelSim, all designs are compiled into a library. You typically start a new simulation in ModelSim by creating a working library called “work,” which is the default library name used by the compiler as the default destination for compiled design units.
• Compiling Your Design
After creating the working library, you compile your design units into it. The ModelSim library format is compatible across all supported platforms. You can simulate your design on any platform without having to recompile your design.
• Loading the Simulator with Your Design and Running the Simulation
With the design compiled, you load the simulator with your design by invoking the simulator on a top-level module (Verilog) or a configuration or entity/architecture pair (VHDL).
Assuming the design loads successfully, the simulation time is set to zero, and you enter a run command to begin simulation.
• Debugging Your Results
If you don’t get the results you expect, you can use ModelSim’s robust debugging environment to track down the cause of the problem.
Project Flow
A project is a collection mechanism for an HDL design under specification or test. Even though you don’t have to use projects in ModelSim, they may ease interaction with the tool and are useful for organizing files and specifying simulation settings.
The following diagram shows the basic steps for simulating a design within a ModelSim project.
10 ModelSim Tutorial, v10.1d
Figure 2-2. Project Flow
Create a project
Add files to the project
Compile design files
Run simulation
Debug results
Conceptual Overview
Multiple Library Flow
As you can see, the flow is similar to the basic simulation f
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