4.1: Solution
(a) Open-circuit the capacitors to obtain the bias circuit shown in Figure 1, which indicates the given values.
From the voltage divider, we have VG = 15 5 = 5 V 10+5
From the circuit, we obtain VG = VGs + 0.5 × 7 = 1.5 + 3.5 = 5 V. Which is consistent with the value provided by the voltage divider.
Since the drain voltage (+7 V) is higher than the gate voltage (+5 V), the transistor is operating in saturation.
From the circuit:
VD =VDD −IDRD =15−0.5×16=+7
VGS = 1.5 V, thus VOV = 1.5 − Vt = 1.5 − 1 = 0.5 V
I =1k V2 =1×4×0.52 =0.5mA D 2nOV 2
(b)
gm = 2ID = 2 × 0.5 = 2 mA VOV 0.5 V
ro =VA =100=200kΩ ID 0.5
(c)
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(d)
Rin = 10 MΩ||5 MΩ = 3.33 MΩ
Vgs = Rin = 3.33 = 0.94 Vsig Rin + Rsig 3.33 + 0.2
Vo =−gm(200||16||16)=−2×7.69=−15.38 Vgs
Vo = Vgs × Vo =−0.94×15.38=−14.5 Vsig Vsig Vgs
4.2: Solution
(a) DC circuit is shown in Figure 2:
𝑉 =2×𝐼 =2×0.5=1 → V =2−1=1V 𝐺𝐷 GS
VOV =VGS −Vt =1−0.7=0.3V
VD = 2.5 V is higher than VG − Vt = 1.3 V by 1.2 V, so the circuit operating in saturation.
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I =1k V2 →0.5=1k ×0.32 →k =11.1mA/V2 D2nOV 2n n
(b)
The amplifier small-signal equivalent-circuit model is shown in figure 3:
Rin = RG1||RG2 = 300||200 = 120 kΩ
gm = 2ID = 2 × 0.5 = 3.33 mA VOV 0.3 V
ro = VA = 50 = 100 KΩ ID 0.5
GV = − Rin gm(ro||RD||RL) = − Rin + Rsig
(C)
To remain in saturation,
̂̂
VDS ≥ VGS − Vt
̂̂̂ 2.5-8.1Vgs ≥ 2 + Vgs − 0.7 if we have equality: Vgs =
̂ So, the corresponding value of Vgs is:
̂
VG=2V, VD=2.5V ̂̂
VGS= 2+Vgs, ̂̂
VDS = 2.5 − |AV|Vgs , |AV| = gm(ro||RD||RL) = 8.1
120 × 3.33 × (100||5||5) = −4.1 120 + 120
2.5−1.3
9.1 = 0.132 V
̂ ̂ 120+120 Vsig = Vgs ( 120
) = 2 × 0.132 = 0.264 V . The corresponding amplitude at the output will be: |GV|Vsig = 4.1 × 0.264 = 1.08 V
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4.3: Solution:
(a) DC bias: When all capacitors eliminated: Rin at gate =RG = 10 ΜΩ
V = 0, thus V = −V , where V can be obtained from: I G S GS GS
VOV=0.4V →VGS=Vt+0.4=0.8+0.4=1.2V VS = −1.2 V
RS =−1.2−(−5)=9.5kΩ 0.4
= 1 k V2 → 0.4 = 1 × 5 × V2 → D2nOV 2 OV
To remain in saturation, the minimum drain voltage must be limited to VG − Vt = 0 − 0.8 = −0.8 V. Now, to allow for 0.8 V negative signal swing, we must have:
VD = 0 V
RD =5−0=12.5kΩ
0.4
(b)
gm = 2ID = 2 × 0.4 = 2 mA VOV 0.4 V
ro = VA = 40 = 100 kΩ ID 0.4
(c)
If terminal Z connected to ground. The circuit becomes a CS amplifier,
GV = − Vy = RG × −gm(ro||RD||RL) = − 10 × 2 × (100||12.5||10) = −9.6 Vsig RG + Rsig 10 + 1
(d) If terminal Y is grounded, the circuit becomes a CD or source-follower amplifier:
VZ = (RS||ro) = (9.5||100) = 0.946
Vx (RS||ro)+ 1 (9.5||100)+1 gm 2
Looking into terminal Z, we see Ro = Rs||ro|| 1 = 9.5||100|| 1 = 473 Ω gm 2
(e) IF X is grounded, the circuit becomes a CG amplifier:
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The figure shows the circuit prepared for signal calculations:
𝑉 =𝑖 ×[𝑅 ||𝑅 || 1 ]=50×10−3[100||9.5||1]=0.024𝑉
𝑠𝑔 𝑠𝑖𝑔 𝑠𝑖𝑔 𝑆 𝑔𝑚
𝑉 =(𝑔 𝑅 )𝑉 =(2×12.5)×0.024=0.6𝑉 𝑦 𝑚𝐷𝑠𝑔
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