Ex: 9.1 Referring to Fig. 9.3, If RD is doubled to 5 k,
VD1 = VD2 = VDD − I RD 2
=1.5− 0.4mA (5k)=0.5V 2
VCMmax =Vt +VD =0.5+0.5=+1.0V Since the currents ID1, and ID2 are still 0.2 mA
each,
VGS =0.82V
So, VCMmin = VSS + VCS + VGS
= −1.5 V + 0.4 V + 0.82 V = −0.28 V So, the common-mode range is
−0.28 V to +1.0 V
Ex:9.2 (a) Thevalueofv thatcausesQ to id√ 1
VDD
Exercise 9–1
RD 5 k
Thus,
RD 5 k
ID
ID
I 0.8 mA VSS
VOV = W= 0.2mA/V2(100)
2ID
2(0.4mA)
k′n = 0.2 V
L
= 0.4mA×2 =4mA/V 0.2 V
conduct the entire current is
→√2×0.316=0.45V then,VD1 =VDD −I×RD = 1.5−0.4×2.5 = 0.5 V VD2 =VDD =+1.5V
2 VOV
gm = ID VOV /2
(b) For Q2 to conduct the entire current: vid =−√2VOV =−0.45V
then,
VD1 =VDD =+1.5V
VD2 = 1.5−0.4×2.5 = 0.5 V
(c) Thus the differential output range is VD2 −VD1:from1.5−0.5= +1V
to 0.5 − 1.5 = −1 V
Ex: 9.3 Refer to answer table for Exercise 9.3 where values were obtained in the following way:
VOV = I/knW/L ⇒ W = I LkV2
ro = VA = 20V =50k ID 0.4 mA
Ad =gm(RD ∥ro)
Ad =(4mA/V)(5k∥50k)=18.2V/V
Ex: 9.5 With I = 200 μA, for all transistors, ID = I = 200μA =100μA
22
L = 2(0.18 μm) = 0.36 μm
VA′L ro1 =ro2 =ro3 =ro4 = I
D
= (10 V/ μm)(0.36 μm) = 36 k
0.1 mA SinceI =I = μC
D1 D2 2 n ox W 2ID
V2 , L OV
W L=L=μCV2
1 W
n OV
2(100 μA)
400 μA/V2 (0.2 V)2 = 12.5
W = W = 2ID
L 3 L 4 μpCox|VOV|2
1 2 n ox OV
gm=2(I/2)= I VOV VOV
2(100 μA) 100μA/V2(0.2)2 =50
vid/22 V
=0.1→vid =2VOV
√
0.1
OV
ID
gm = VOV /2 =
(100 μA) (2) 0.2 V
= 1 mA/V,
Ex:9.4 ID = I = 0.8mA =0.4mA 22
1 W
ID = 2k′n L (VOV)2
so
Ad =gm1(ro1 ∥ro3)=1(mA/V)(36k∥36k)
=18V/V
Ex: 9.6 L = 2(0.18 μm) = 0.36 μm VA′ · L
Allro = ID
The drain current for all transistors is
ID = I = 200μA =100μA 22
ro = (10 V/ μm) (0.36 μm) = 36 k 0.1 mA
Ex: 9.8
VCC
2.5 V I IC2
2.5 V VEE
Exercise 9–2
RC
C1
RC 5 k
Refering to Fig. 9.13(a),
1 W
I 0.4 mA
SinceI = μC V2 forallNMOS D 2 n ox L OV
transistors,
W W W W ===
L1L2L3L4 2ID 2(100μA)
IC1 =IC2 ≃IE1 =IE2 = I = 0.4mA 2 2
=0.2mA
VCMmax ≃VC +0.4V
=VCC −ICRC +0.4V =2.5−0.2mA(5k)+0.4V=+1.9V
VCM min = −VEE + VCS + VBE
VCMmin =−2.5V+0.3V+0.7V=−1.5V Input common-mode range is −1.5 V to +1.9 V
Ex: 9.9 Substituting iE1 + iE2 = I in Eqn. (9.45) yields
=μC V2 =400μA/V2(0.2V)2 =12.5 n ox OV
W W W W L = L = L = L
2ID 2(100μA)
= μ C V2 = 100μA/V2(0.2V)2 =50
5678
p ox OV
For all transistors,
gm = |ID| = (0.1 mA)(2) = 1 mA/V
|VOV | /2 From Fig. 9.13(b),
(0.2 V)
Ron = (gm3ro3) ro1 = (1 × 36) × 36
= 1.296 M
R =(g r )r =(1×36)×36
i = E1
I 1+e(vB2−vB1)/VT
op m5 o5 o7
= 1.296 M
A =g R ∥R d m1 on op
=(1mA/V)(1.296M∥1.296M) = 648 V/V
I
0.99I = 1+e(vB2−vB1)/VT
1 vB1−vB2 =−VTln 0.99−1
= −25ln (1/99)
= 25ln (99) = 115 mV
Ex: 9.10 (a) The DC current in each transister is 0.5 mA. Thus VBE for each will be
0.5 VBE =0.7+0.025ln 1
= 0.683 V
⇒vE =5−0.683=+4.317V
(b)gm=IC = 0.5 =20mA VT 0.025 V
(c) iC1 = 0.5 + gm1vBE1
= 0.5 + 20 × 0.005 sin (2π × 1000t) = 0.5 + 0.1 sin(2π × 1000t), mA
Ex: 9.7
0.5 V Q1 vC1 5 V
1 k
5 V
1 k
5 0.7 1
4.3 mA vE 0.7 V
OFF
ON
Q2
0
vC2 5 4.3 1 0.7 V
4.3 mA (a 1)
1 k 5 V
iC2 = 0.5 − 0.1 sin(2π × 1000t), mA (d) vC1 =(VCC −ICRC)−0.1
×RC sin(2π × 1000t)
= (15 − 0.5 × 10) − 0.1 × 10 sin(2π × 1000t) = 10 − 1 sin(2π × 1000t) , V
vC2 =10+1sin(2π×1000t),V
(e) vC2 −vC1 =2·sin(2π×1000t),V
(f) Voltage gain ≡ vC2 − vC1 vB1 −vB2
Ex: 9.13 If the output of a MOS differential amplifier is taken single-endedly, then
|Ad|= 1gmRD 2
(that is, half the gain obtained with the output taken differentially), and from Fig. 9.25(d) we have
Exercise 9–3
|Acm|≃ RD 2RSS
Thus,
CMRR≡|A |=gmRSS
Ex: 9.14
VCC
VB3 Q3 Q4 VB4 vo1 vo2
=
2Vpeak 0.01 V peak
= 200 V/V
|Ad| cm
Q.E.D.
Ex: 9.11 The transconductance for each transistor is
gm = 2μnCox (W/L)ID
ID = I = 0.8mA =0.4mA
22
gm =√2×0.2×100×0.4=4mA/V The differential gain for matched
RD values is Ad = vO2 − vO1 = gmRD vid
If we ignore the 1% here, then we obtain
Ad =gmRD =(4mA/V)(5k)=20V/V
Thus,
vi1
Q1
Q2 vi2 I 200 A
Q5 5 VEE
R R | Acm| = D D
VB5
2RSS RD
= 2 × 25 (0.01) = 0.001 V/V
|Ad| 20 CMRR(dB)=20log|ACM|=20log 0.001
= 86 dB
Ex:9.12 FromExercise9.11,
W/L = 100, μnCox = 0.2 mA/V2, ID = I = 0.8mA =0.4mA
W gm = 2μnCox L ID
I=200μA Sinceβ≫1,
22
IC1 ≈IC2 ≈ I = 200μA =100μA 22
gm1 =gm2 =gm = IC = 100μA =4mA/V VT 25 mV
RC1 =RC2 =RC =ro = |VA| IC
= 10V =100k 100μA
ro1=ro2=VA =10=100k I/2 0.1
re1 =re2 =re = VT = 25mV =0.25k IE 0.1 mA
|Ad|= RC ∥ro = 100k∥100k
(100)(0.4 mA)
Using Eq. (9.88) and the fact that RSS = 25 k,
2(4 mA/V) (25 k) 0.01
= 2 0.2 mA/V2 gm =4mA/V
weobtain
CMRR= g =
re
0.25 k rπ = β = 100
(2 gm RSS ) m
=200V/V
Rid =2rπ,
Rid = 2(25 k) = 50 k
gm
=25k
= 20, 000
CMRR(dB) = 20log10 (20,000) = 86 dB
gm 4 mA/V
VA 10V REE=I=200μA=50k
If the total load resistance is assumed to be mismatched by 1%, then we have
| A | = RC RC cm 2REE RC
= 100 ×0.01=0.01V/V
2×50
Exercise 9–4
−32 = 3×2×10
= 3.46 mV
Ex: 9.16 From Eq. (9.120), we get
R2 I2 V=VC+S
CMRR(dB)=20log Ad =20log 200
= 25 (0.02)2 +(0.1)2 = 2.55 mV
10Acm Using Eq. (9.96), we obtain
100.01
OS T RC
IS
∼= 0.5 μA
= 86 dB
IB = 100 = 2(β + 1)
β IOS = IB β
100
2 × 101
1+ RC βro
1+RC +2REE ro
1+ 100 100×100
Ex: 9.15 From Exercise 9.4:
VOV =0.2V
Using Eq. (9.101) we obtain VOS due to RD/RD
Ricm = βREE ·
=100×50× R ≃1.68M
=0.5×0.1μA=50nA Ex:9.17 ID = 1I =0.4mA
1+100+2×50 100
2 I=1μC WV2
icm
D 2 n ox L OV n
as: V R VOS= OV · D
2 RD = 0.2 ×0.02=0.002V
i.e2mV
0.4 = 1 × 0.2 × 100 × V 2 2 OV
⇒VOV =0.2V
gm1,2 = 2ID = 2×0.4 =4mA/V
VOV 0.2 Gm=gm1,2=4mA/V
VAn 20
ro2=I =0.4=50k
D
|VAp| 20
ro4= I =0.4=50k
D
Ro =ro2 ∥ro4 =50∥50=25k
Ad =GmRo =4×25=100V/V
I/2 Ex:9.18 Gm =gm1,2 ≃ =
2
ToobtainVOS dueto W/L ,
useEq.(9.106),
(W/L)
VOS = ⇒VOS =
2
0.2 2
W/L ×0.02=0.002
0.4mA 0.025 V
V (W/L) OV
VT
ro2 =ro4 = VA = VA = 100 =250k
=16mA/V
⇒2mV
The offset voltage arising from Vt is obtained
from Eq. (9.109):
VOS =Vt =2mV
Finally, from Eq. (9.110) the total input offset is VOS =
IC I/2 0.4
Ro =ro2 ∥ro4 =250∥250=125k
Ad = GmRo = 16×125 = 2000 V/V
Rid =2rπ =2× β =2×160=20k
V R OV D
V (W/L)2 OV
1/2
gm1,2 Ex: 9.19 I/2
2 −32
+(Vt)2
−32
+
+ 2×10
Gm =gm1 =gm2 ≃ =
=20mA/V
16
0.5 mA VT 0.025V
= 100V =200k 0.5mA
2RD
= 2×10
2W/L −32
r o4
= VA I/2
+ 2×10
Ro4 ≃ β4ro4 = 50 × 200 = 10,000 k = 10 M Ro5 = 1β5ro5
Ex: 9.22 Refer to Fig. (9.40). (a) Using Eq. (9.170), we obtain
(W/L)6
I6 = (W/L) (I/2)
⇒100= 100 ×50 thus, (W/L)6 = 200
UsingEq.(9.171),weget I7 = (W/L)7I
2 where
ro5 = VA I/2
Thus,
= 200 k
4 (W/L)6
Exercise 9–5
Ro5 = 1 ×100×200=10M 2
Ro =Ro4 ∥Ro5 =10∥10=5M
Ad = GmRo
=20mA/V×5000k=105 V/Vor100dB
Ex: 9.20 From Exercise 9.17, we get
ID=0.4mA
V =0.2V g =4mA/V OV m1,2
Gm =4mA/V Ad =100V/V Now,
RSS =25k
W gm3=2μpCox LID
p
√
= 2×0.1×200×0.4 = 4 mA/V
(W/L)5 (W/L)7
⇒100= 200 ×100
thus, (W/L)7 = 200 (b) For Q1,
I1W
= μC V2
2 2 p ox L OV1 1
⇒VOV1 =1 2
×30×200
50
=0.129V
SimilarlyforQ2,VOV2 =0.129V For Q6,
|Acm|= 1 = 1 2gm3RSS 2 × 4 × 25
CMRR= |Ad| = 100 |Acm| 0.005
=0.005V/V
1 2 100 = 2 × 90 × 200VOV 6
⇒VOV6 =0.105V (c) g = 2ID
m
VOV
ID
50 μA
50 μA 100 μA
= 20,000 or 20 log 20,000 = 86 dB
Ex: 9.21 From Exercise 9.18, we get
I =0.8mA, IC ≃0.4mA, VA =100V gm1,2 = 16 mA/V, Gm = 16 mA/V
ro2 =ro4 =250k, Ad =2000V/V Now,
REE = 100V =125k 0.8 mA
Using Eq. (9.165),
ro4 250
|Acm|= β R = 160×125 =0.0125V/V
Q1 Q2 Q6
VOV
0.129 V 0.129 V 0.105 V
gm
0.775 mA/V 0.775 mA/V 1.90 mA/V
3 EE
CMRR= |Ad| = 2000 =160,000V/V
(d) ro2 =10/0.05=200k ro4 = 10/0.05 = 200 k
ro6 =10/0.1=100k
ro7 = 10/0.1 = 100 k
(e) Eq. (9.168):
A1 = −gm1 (ro2 ∥ ro4)
= −0.775 (200 ∥ 200) = −77.5 V V
Eq. (9.169):
A =−g (r ∥r ) 2 m6 o6 o7
= −95V/V
|Acm| 0.0125 20 log CMRR = 104 dB
Overall voltage gain is
A1 ×A2 =−77.5× −95=7363V/V
Ex: 9.23 Rid = 20.2 k
Avo = 8513 V/V
Ro =152
WithRS =10kandRL =1k,
G = 20.2 ×8513× 1
v 20.2 + 10 (1 + 0.152)
ib7= R3 = 3 =0.0126 ic5 R3 +Ri3 3+234.8
Exercise 9–6
ic5 =β5 =100 ib5
ib5 = R1 + R2
ic2 R1 +R2 +Ri2
ic2 =β2 =100 i1
= 40 40+5.05
= 0.888
= 4943 V/V
Ex:9.24 ie8 =β8 +1=101
Thus the overall current gain is
ie8 = 101×0.0492×100×0.0126×100
i1
× 0.888 × 100
= 55,599 A/A
and the overall voltage gain is
vo = R6 · ie8 vid Ri1 i1
ib8 ib8 = R5
ic7 R5 + Ri4
ic7 =β7 =100 ib7
=
15.7 15.7 + 303.5
=0.0492
= 3 20.2
×55599 = 8257 V/V
1W 9.1 Refer to Fig. 9.2. ID1,2 = k′p
I1W 2L
(a) = μC V2 2 2 n ox L OV
|VOV |2 2
Chapter 9–1
1,2 0.08= 1 ×0.4×10×V2
1
0.25= 2 ×4×|VOV|
2 OV ⇒VOV =0.2V
⇒|VOV|=0.35V
VSG =|Vtp|+|VOV|
= 0.8+0.35 = 1.15 V
VS =0+VSG =+1.15V
VD1 =VD2 =−VSS +IDRD
=−2.5+0.25×4
= −1.5 V
Since for each of Q1 and Q2,
VSD = 1.15 − (−1.5)
= 2.65 V
which is greater than |VOV |, Q1 and Q2 are operating in saturation as implicitly assumed.
(b) The highest value of VCM is limited by the need to keep a minimum of 0.4 V across the current source, thus
VCMmax =+2.5−0.4−VSG
= +2.5 − 0.4 − 1.15 = +0.95 V
ThelowestvalueofVCM islimitedbytheneedto keep Q1 and Q2 in saturation, thus
VGS = Vtn + VOV = 0.4 + 0.2 = 0.6 V (b) VCM = 0
VS =0−VGS =−0.6V
ID1 =ID2 = I =0.08mA 2
VD1 = VD2 = VDD − ID1,2RD
= 1 − 0.08 × 5 = +0.6 V
(c) VCM = +0.4 V
VS =0.4−VGS =0.4−0.6=−0.2V
ID1 =ID2 = I =0.08mA 2
VD1 = VD2 = VDD − ID1,2RD = 1 − 0.08 × 5 = +0.6 V
SinceVCM =0.4VandVD =0.6V,
VGD = −0.2 V, which is less than Vtn (0.4 V), indicating that our implicit assumption of saturation-mode operation is justified.
(d) VCM = −0.1 V
VS =−0.1−VGS =−0.1−0.6=−0.7V
ID1 =ID2 = I =0.08mA 2
VD1 = VD2 = VDD − ID1,2RD = 1 − 0.08 × 5 = +0.6 V
(e) The highest value of VCM for which Q1 and Q2 remain in saturation is
VCM max = VD1,2 + Vtn = 0.6+0.4 = 1.0 V
(f) To maintain the current-source operating properly, we need to keep a minimum voltage of 0.2 V across it, thus
VCMmin =VD1,2 −|Vtp|
= −1.5 − 0.8 = −2.3 V Thus,
−2.3 V ≤ VICM ≤ +0.95 V
9.3
RD
G1
RD
VDD 1 V
5 k vD1
iD2
5 k vD2
iD1
G2 Q2
VSmin =−VSS +VCS =−1+0.2=−0.8V V =V +V
Q1
vid vGS1 vGS2
v S
I 0.16 mA VSS 1 V
(a) For iD1 = iD2 = 0.08 mA, vG1 = vG2
CMmin Smin GS = −0.8 + 0.6
= −0.2 V
9.2 Refer to Fig. P9.2.
(a) ForvG1 =vG2 =0V,
ID1 = ID2 = 1 × 0.5 = 0.25 mA 2
Thus,
vid =0V
0.16 = 1 ×0.4×10 (vid +0.4−0.4)2 2
⇒vid =0.283V 1W √
whichis 2VOV,asderivedinthetext. vGS1 = 0.283 − (−0.4) = 0.683 V
vD1 =VDD −iD1RD
= 1 − 0.16 × 5 = +0.2 V
Note that since vG1 = vid = 0.283 V, Q1 is still operating in saturation, as implicitly assumed.
vD2 =VDD −iD2RD =1−0×5=1V
vD2 − vD1 = 1 − 0.2 = 0.8 V
(d) iD1 = 0.04 mA and iD2 = 0.12 mA. Since this split of the current I is the complement of that in case(b)above,thevalueofvid mustbethe negative of that found in (b). Thus,
vid =−0.104V
vGS1 = 0.541 V
vS = −0.645 V
vGS2 = 0.645 V
vD1 =VDD −iD1RD
= 1−0.04×5 = 0.8 V
vD2 = 1−0.12×5 = 0.4 V vD2 − vD1 = −0.4 V
(e) iD1 =0(Q1 justcutsoff)andiD2 =0.16mA. This case is the complement of that in (c) above, thus
vGS1 =Vtn =0.4V
vGS2 = 0.683 V
vS = −0.683 V
vid =−0.683+0.4=−0.283V √
which is − 2 VOV , as derived in the text. vD1 =VDD −iD1RD =1−0×5=1V
vD2 = VDD −iD2RD = 1−0.16×5 = 0.2 V vD2 − vD1 = −0.8 V
Summary
A summary of the results is shown in the following table on the next page.
i =i = 1
⇒VOV =0.2V
vGS1 =vGS2 =0.2+0.4=0.6V
vS =−0.6V
vD1 = vD2 = VDD − iD1,2RD
= 1−0.08×5 = 0.6 V
vD2 − vD1 = 0 V
(b) ForiD1 =0.12mAandiD2 =0.04mA,
1 W
iD2 = 2μnCox L (vGS2 − Vtn)2
0.04 = 1 ×0.4×10×(vGS2 −0.4)2 2
⇒vGS2 =0.541V Thus,
vS = −0.541 V
1 2
Chapter 9–2
μ C V2 D1 D2 2 n ox L OV
0.08= ×0.4×10×V2 2OV
1 W iD1 = 2μnCox L
(vGS1 − Vtn)2 ×0.4×10 (vid −vS −Vtn)2
0.12 =
= 1 ×0.4×10(vid +0.541−0.4)2
2
⇒vid =0.104V
vGS1 = 0.104 − (−0.541) = 0.645 V vD1 =VDD −iD1RD
= 1−0.12×5 = 0.4 V
vD2 =VDD −iD2RD
= 1−0.04×5 = 0.8 V
vD2 −vD1 =0.8−0.4=0.4V
(c) iD1 =0.16mAandiD2 =0withQ2 just cutting off, thus
vGS2 =Vtn =0.4V ⇒vS2 =−0.4V
iD1 = 1 × 0.4 × 10 (vGS1 − Vtn)2 2
Chapter 9–3
Case
iD1(mA)
iD2(mA)
vid (V)
vS (V)
vD1 (V)
vD2 (V)
vD2 − vD1(V)
a
0.08
0.08
0
−0.6
+0.6
+0.6
0
b
0.12
0.04
+0.104
−0.541
+0.4
+0.8
+0.4
c
0.16
0
+0.283
−0.4
+0.2
+1.0
+0.8
d
0.04
0.12
−0.104
−0.645
+0.8
+0.4
−0.4
e
0
0.16
−0.283
−0.683
+1.0
+0.2
−0.8
9.4 RefertoFig.P9.2. To determine VOV ,
0.25 = 1 × 4 × |VOV |2 2
⇒ |VOV | = 0.354 V
With vG2 = 0 and vG1 = vid , to steer the current
from one side of the differential pair to the other,
vid mustbetheendsoftherange √√
− 2 |VOV | ≤ vid ≤ 2 |VOV |
that is,
−0.5V≤vid ≤+0.5V
At vid = −0.5 V, Q2 just cuts off, thus vS =|Vtp|=0.8V
and
vSG1 =0.8−(−0.5)=1.3V At this value of vSG1,
iD1 = 1 ×4×(1.3−0.8)2 2
=0.5mA
which is the entire bias current.
vD1 =−2.5+0.5×4=−0.5V
vD2 =−2.5+0.5×4=−0.5V
which verifies that Q2 is operating in saturation,
as implicitly assumed.
9.5
vid
VDD 1 V
RD
RD
5 k vD1
iD2
5 k vD2
G1
iD1
G2 vGS1 vGS2
S
I 0.16 mA
Q2 v
Q1
VSS 1 V ForiD1 =0.09mAandiD2 =0.07mA,
1 W
iD2 = 2μnCox L (vGS2 − Vtn)2
Observe that since vG1 = vD1, Q1 is still
operating in saturation, as implicitly assumed. 2
At vid = +0.5 V, Q1 just cuts off, thus
1 W vS =+0.5+0.8=+1.3V iD1 = 2μnCox L
0.07 = 1 × 0.4 × 10(vGS2 − 0.4)2 ⇒vGS2 =0.587V
vD2 =−2.5V
and
vSG1 =|Vtp|=0.8Vand vS =−0.587V
and thus
vSG2 = 1.3 V which results in
iD1 = 1 ×4(1.3−0.8)2 2
= 0.5 mA
which is the entire bias current. Here,
(vGS1 −Vtn)2 0.09 = 2 ×0.4×10 (vGS1 −0.4)
⇒ vGS1 = 0.612 V
vid =vS +vGS1 =−0.587+0.612 = 0.025 V
vD2 =VDD −iD2RD
= 1−0.07×5 = 0.65 V
1
2
vD1 =1−0.09×5=0.55V
vD2 −vD1 = 0.65−0.55 = 0.10 V vD2 −vD1 0.10
TheupperlimitonVCM isdeterminedbytheneed to keep Q1 and Q2 in saturation, thus
VICM max = VD1,2 + Vtn
= 0.1+0.4 = 0.5 V Thus,
−0.2V≤VICM ≤+0.5V
9.7 From Exercise 9.3 and the accompanying table, we note that |vid |max is proportional to VOV :
|vid |max = 0.126 = 0.63 VOV 0.2
Thus, to obtain |vid |max = 220 mV = 0.22 V at the same level of linearity, we use
VOV=0.22=0.35V 0.63
For this value of VOV , the required (W/L) can be
= 0.025 = 4 V/V
To obtain the complementary split in current, that
Voltage gain = v
is,iD1 =0.07mAandiD2 =0.09mA,
For Q3,
0.4=1×0.4× W ×0.152 vid/2 √
Chapter 9–4
vid =−0.025V
9.6 Refer to the circuit in Fig. P9.6.
ForvG1 =vG2 =0V,
ID1 =ID2 = 0.4 =0.2mA
2 To obtain
VD1 =VD2 =+0.1V VDD − ID1,2 RD = 0.1 0.9−0.2 RD = 0.1 ⇒ RD =4k
found from
0.2=1×0.2× W ×0.352
id
For Q1 and Q2,
1 W
2L ⇒ L =16.3
The value of g is m
I=μCV2 D1,2 2 n ox L OV
W
1 W 0.2 = × 0.4
2 ID gm = V
2 × 0.2 = 0.35
⇒
= 44.4
OV
2 L1,2
W L 1,2
× 0.152
=1.14mA/V 9.8 Refer to Eq. (9.23). For
1,2
OV
vid/22 V≤k
2L3 ⇒V≤k(1) OV
⇒ W =88.8 L3
Since Q3 and Q4 form a current mirror with ID3 = 4ID4,
W 1W
= = 22.2
L4 4L3
VGS4 = VGS3 = Vtn +VOV = 0.4+0.15
= 0.55 V
R= 0.9−(−0.9)−0.55
0.1
The lower limit on VCM is determined by the need to keep Q3 operating in saturation. For this to happen, the minimum value of VDS3 is
VOV =0.15V.Thus,
VICMmin =−VSS +VOV3 +VGS1,2 = −0.9 + 0.15 + 0.4 + 0.15
= −0.2 V
v /2 v /22 id 1 − id
△I = I
△Imax = I √k√1 − k
VOV VOV
Thus,
△Imax = 2k(1 − k) Q.E.D. (2)
= 12.5 k
Eq.(2)as√
vidmax = 2 kVOV Q.E.D. (3) Equations (2) and (3) can be used to evaluate
△Imax and vidmax for various values of k: I/2 VOV
I/2
andthecorrespondingvalueofvid isfoundfrom
k
0.01
0.1
0.2
vidmax VOV
0.2
0.632
0.894
△Imax I/2
0.2
0.6
0.8
9.9 Switching occurs at v =√2V
(b) In Eqs. (9.23) and (9.24) let
I I iD1= 2 + 2 ×△
Chapter 9–5
id OV
Thus,
0.3=√2VOV ⇒VOV =0.212V
Now, to obtain full current switching at vid =0.5V,VOV mustbeincreasedto
VOV =0.212× 0.5 =0.353V 0.3
iD2 = I − I ×△ 22
where
v v/22
△=id 1−id VOV VOV
Ifvid issuchthat iD1
Since I is proportional to V 2 the current I and
D OV D =m
hence the bias current I must be increased by the ratio (0.353/0.212)2, then I must be
0.3532 0.212
iD2
then
m=1+△ 1−△
⇒△=m−1 m+1
Form=1,△=0andvid =0 For m = 2,
△=2−1=1 2+1 3
I =200×
=554.5μA
9.10 Refer to Fig. 9.5.
gm = 2(I/2) = VOV
1=I 0.25
⇒I =0.25mA
I=1μCWV2 2 2 n ox L OV
11W ×0.25 = ×0.4×
22L ⇒ W = 10
L
I VOV
2
vid 1−1vid =1 VOV 4 VOV 3
0.252
Squaring both sides, we obtain a quadratic
v 2
equation in obtain
id which can be solved to VOV
9.11 Equations (9.23) and (9.24):
I Iv v/22 iD1=+ id 1−id
2 2 VOV VOV
I Iv v/22 iD2 = − id 1− id
2 2 VOV VOV
vid = 0.338VOV For m = 1.1,
1.1−1 0.1
(9.23) △= =≃0.05
(9.24)
1.1 + 1 2.1 Thus,
v 1v2
id 1 − id VOV 4 VOV
⇒ vid ≃ 0.05VOV For m = 1.01
1.01 − 1
△= 1.01+1 ≃ 0.005
v 1v2
id 1− id VOV 4 VOV
vid ≃ 0.005VOV
(a) For 10% increase above the equilibrium value
= 0.05
= 0.005
I
of 2,
Iv v/22
id 1 − id
2 VOV VOV
1 − 1 vid 4 VOV
⇒ id ≃0.1 VOV
vid ≃ 0.1VOV
I
2
2
= 0.1 × = 0.1
vid
VOV
v
For m = 20,
△ = m − 1 = 19 = 0.905 V
Using this value, we obtain
VD = VDD − I RD 2
0.2 = 1−0.25×RD ⇒R=3.2k
=0.905
OVOV dmD
V 1−4 V ⇒vid =1.072VOV
A=gR 10=gm ×3.2
gm = 10 =3.125mA/V 3.2
Chapter 9–6
m+1 21 Thus,
2 vid 1 vid
D
1
9.12 0.1= ×0.2×32V2
⇒VOV =0.18V
2×(I/2) I gm = V = V
gm =
ro= A=
2OV But
2 × (0.2/2)
0.18 = 1.11 mA/V
OV
3.125= 0.5 VOV
OV
V
10 0.1
=100k Ad =gm(RD ∥ro)
ID
⇒VOV =0.16V
To obtain W/L, we use
= 1.11 × (10 ∥ 100) = 10.1 V/V 9.13 Forvid =0.1V
vid/22 VOV
vid/2 =0.2 VOV
0.1/2 = 0.2 VOV
⇒VOV =0.25V g = 2 × (I /2)
1 W I=μC V2
D 2 n ox L OV 1 W
= 0.04
0.25=2×0.4× L ×0.162 ⇒ W = 48.8 ≃ 50
m
VOV
L
9.15 Since the quiescent power dissipation is P = (VDD + VSS ) × I
then the maximum allowable I is
I = 1 mW = 0.5 mA 2V
Weshallutilizethisvalue.ThevalueofVOV can be found from
2=I 0.25
⇒ I = 0.5 mA Ad = 1V =10
0.1 V gmRD =10
⇒RD = 10 =5k 2
I=1μC WV2 2 2 n ox L OV
√
⇒VOV = √ =0.18V
2VOV =0.25V 0.25
1 W 0.25 = × 0.2 ×
2 × 0.25
2 Therealizedvalueofgm willbe
2×(I/2) gm= VOV
= 0.5 =2.8mA/V 0.18
ToobtainadifferentialgainAd of10V/V, Ad =gmRD
10 = 2.8×RD
⇒RD =3.6k
Finally, the required value of W/L can be determined from
I =I=1μC WV2 D 22noxLOV
2L ⇒ L =40
W
9.14 To limit the power dissipation to 1 mW, P = (VDD + VSS )I
Thus, the maximum value we can use for I is
I=1mW=0.5mA 2V
0.25= 1 ×0.4× W ×0.182 where 2L
⇒ W = 38.6 L
9.16 (a) Ad = gmRD 20=gm×47
⇒gm = 20 =0.426mA/V 47
(b)gm=2ID =2(I/2)= I
Chapter 9–7
g = 2μ C W I
m
Thus
2μnCox L I/2RD (2) Equating the gains from Eqs. (1) and (2), we get
I=2ID
That is, the differential pair must be biased at a current twice that of the CS amplifier. Since both circuits use equal power supplies, the power dissipation of the differential pair will be twice that of the CS amplifier.
9.18 Since both circuits use the same supply voltages and dissipate equal powers, then their currents must be equal, that is,
ID = I
where ID is the bias current of the CS amplifier andI isthebiascurrentofthedifferentialpair. The gain of the CS amplifier is
|A| = gmRD where
W
2μnCox L
n ox L 2 W
Ad =
VOV VOV 0.426 = I
0.2
⇒I =0.085mA=85μA
VOV
(c) Across each RD the dc voltage is I 0.085
2 RD = 2 × 47 = 2 V
(d) The peak sine-wave signal across each gate source is 5 mV, thus at each drain the peak sine wave is
Ad ×5=20×5=100mV=0.1V
(e) The minimum voltage at each drain will be
vDmin = VDD − RDID − Vpeak
=VDD −2−0.1
For the transistor to remain in saturation vDmin ≥vGmax −Vtn
where
vGmax =VCM +Vpeak(input)
= 0.5+0.005 = 0.505 V
Thus,
VDD − 2.1 ≥ 0.505 − 0.5 VDD≥2.105V Thus,thelowestvalueofVDD is2.21V.
9.17 For a CS amplifier biased at a current ID and utilizing a drain resistance RD, the voltage gain is
|A| = gmRD
where
W gm = 2μnCox L ID
Thus,
gm =
Thus,
ID
CS
|A|= 2μ C W I R (1)
n ox L D D
CS
The gain of the differential amplifier is
Ad =gmRD
where
Thus,
Ad = 2μnCox L diff 2 RD (2) Equating the gains in Eqs. (1) and (2) and
substituting ID = I gives
g = 2μ C W I
m
n ox L diff 2 W I
W |A|= 2μnCox L IDRD
W = W ×1 LCS Ldiff2
(1) For a differential pair biased with a current I and
⇒
W
= 2
W
L
utilizing drain resistances RD, the differential gain is
Ad =gmRD
If all transistors have the same channel length, each of the differential pair transistors must be twiceaswideasthetransistorintheCSamplifier.
L
diff
CS
Chapter 9–8
9.19
9.20
Q3
vid Q1 2
(vod / 2)
vid 2
RD
vod/2
Rs/2
(a) The figure shows the differential half-circuit.
Recalling that the incremental (small-signal)
resistance of a diode-connected transistor is given
From symmetry, a virtual ground appears at the mid point of Rs. Thus, the differential half circuit will be as shown in the figure, and
vod RD
1
∥ ro Q1 will be
by g m
, the equivalent load resistance of
RD= 1 ∥ro3 gm3
and the differential gain of the amplifier in Fig. P9.19 will be
v 1 Ad ≡ od =gm1 ∥ro3 ∥ro1
Since both sides of the amplifier are matched, this expression can be written in a more general way as
Ad≡ = vid
Ad = gm1,2 g ∥ ro3,4 ∥ ro1,2 m3,4
(b) Neglecting ro1,2 and ro3,4 (much larger that 1/gm3,4 ),
Ad ≃ gm1,2 gm3,4
= 2μnCox(W/L)1,2(I/2)
2μpCox(W/L)3,4(I/2)
Ad=2 W1,2 W3,4
ForAd =10,
9.21 Refer to Fig. P9.21. (a) WithvG1 =vG2 =0,
vGS1 =vGS2 =VOV1,2 +Vtn Thus
VS1 =VS2 =−(VOV1,2 +Vtn)
(b) For the situation in (a), VDS of Q3 is zero, thus zero current flows in Q3. Transistor Q3 will have an overdrive voltage of
VOV3 =VC −VS1,2 −Vtn
= VC + (VOV 1,2 + Vtn ) − Vtn
=V+V
C OV1,2
(c) With vG1 = vid /2 and vG2 = −vid /2 where vid isasmallsignal,asmallsignalwillappear between drain and source of Q3. Transistor Q3 will be operating in the triode region and its drain-source resistance rDS will be given by
rDS =
For Rs = 0, Ad = RD
1 + Rs gm 2
= gmRD,
vid gm3
Toreducethegaintohalfthisvalue,weuse Rs = 1
2 gm ⇒R = 2
1/gm asexpected.
1 sgm
μn(W/L)1,2 μp(W/L)3,4
=
(c) μn = 4μp and all channel lengths are equal,
10 = 2 ⇒W1,2=25
W
1 μC W V
W1,2 W3,4
3,4
n ox L OV3 3
Thus,
Since
gm1,2 =μnCox L VOV (2) 1,2
Rs = Now,
W μCV
1 W
Chapter 9–9
n ox L OV3 3
substituting from (2) into (1) gives 1 (W/L)1,2
gm1,2 = (μnCox) L W
gm3 =(μnCox) L W W 3
VOV1,2 VOV3
W
rDS 3,4 = gm1,2 (W/L)3,4 and since
For L = L , 3 1,2
W gm1,2
Rs = rDS3 + rDS4
then
Rs = 2 (W/L)1,2 (3)
1,2
μnCox
Thus,
R= s
=
gm1,2 (W/L)3,4
(b) Withv =v /2andv =−v /2where
L
gm1,2 VOV1,2
VOV 1,2
= 1 VOV1,2
G1 id G2 id vid is a small signal,
1
× VOV 3
Ad ≡ vod vid
gm1,2
VOV 3
=
2 RD
1 +Rs+ 1
(d)(i)Rs= 1 gm1,2
VOV3 =VOV1,2 But
VOV3 =VC +VOV1,2 ⇒VC =0
(ii) Rs = 0.5 gm1,2
⇒ VOV3 = 2 VOV1,2 But
VOV3 =VC +VOV1,2 ⇒V =V
gm1 gm2 Using (3), we obtain
Ad= RD
1 + 1 (W/L)1,2
gm1,2 gm1,2 (W/L)3,4 gm1,2 RD
= (W/L)1,2 1 + (W/L)3,4
9.23 Refer to Fig. P9.23.
The value of R is found as follows: VG6 − VG7
C OV1,2
R= IREF
= 0.8−(−0.8) = 8 k
9.22 Refer to Fig. P9.22.
(a) WithvG1 =vG2 =0V,
VS1 =VS2 =−VGS1,2 =−(Vt +VOV)
The current through Q3 and Q4 will be zero because the voltage across them (vDS3 + vDS4) is zero.
Because the voltages at their gates are zero and at
0.2
Since I = IREF, Q3 and Q6 are matched and are operating at
|VOV | = 1.5 − 0.8 − 0.5 = 0.2 V Thus,
theirsourcesare−(V +V ),eachofQ andQ
t OV 3 4 ⇒ = =100
1
0.2= ×0.1×
W
×0.22
2 L 6,3 W W
will be operating at an overdrive voltage equal to VOV . Thus each of Q3 and Q4 will have an rDS given by
rDS3,4 = 1 (1) μ C W V
L 3 L 6
Each of Q4 and Q5 is conducting a dc current of (I /2) while Q7 is conducting a dc current
IREF = I. Thus Q4 and Q5 are matched and their W/L ratios are equal while Q7 has twice the (W/L) ratio of Q4 and Q5. Thus,
n ox L OV
3,4
I1W =μCV2
9.24 Refer to Fig. P9.24.
(a) Since the dc voltages VGS1 and VGS2 are equal, Q1 and Q2 will be operating at the same value of VOV and their dc currents ID1 and ID2 will have the same ratio at their (W/L) ratios, that is,
22noxL OV4,5 4,5
Chapter 9–10
where
VOV4,5 =−0.8−(−1.5)−0.5=0.2V thus,
I =I/3 1W D1
0.1 = 2 × 0.25 × W W
L
× 0.04
ID2 =2I/3
(b) Q1 and Q2 will be operating at the same VOV ,
⇒ L and
W
L =40
obtained as follows:
4,5 = 20
= L
45 I1W
7
ro4 =ro5 = |VAp| = 10 =100k
=μCV2 3 2 n ox L OV
2I ⇒VOV = W
I/2 0.1
ro1 =ro2 = VAn = 10 =100k
3μn Cox L vod
I/2 0.1 Ad = gm1,2(ro1,2 ∥ ro4,5)
(c) Ad ≡ vid 2RD
50 = gm1,2(100 ∥ 100) ⇒ gm1,2 = 1 mA/V But
=1+1 gm1 gm2
g m1,2
= 2(I/2) |VOV 1,2 |
where gm1=2×(I/3)= 2I
VOV 3VOV 2×(2I/3) 4I
0.2
1 = |VOV1,2|
⇒|VOV1,2|=0.2V
The (W/L) ratio for Q1 and Q2 can now be
2RD Ad=3 3
2+4 (VOV/I) 9.25 Refer to Fig. 9.13.
8 IRD =9VOV
gm2= V =3V OV OV
determined from
1
W
All transistors have the same channel length and are carrying a dc current I /2. Thus all transistors
have the same r = |VA | . Also, all transistors are o I/2
operating at the same |VOV | and have equal dc currents, thus all have the same
gm = 2(I/2) = I/|VOV |. Thus all transistors have |VOV |
equal intrinsic gain gmro = 2|VA|/|VOV |. Now, the gainAd isgivenby
Ad = gm(Ron ∥ Rop) = 1gmRon
2
= 1gm(gmro)ro = 1(gmro)2 22
Thus,
Ad =12|VA|2 2 VOV
= 2(|VA|/|VOV |)2 Q.E.D.
0.1 =
× 0.1 × W W
× 0.22 = 50
2
⇒ L = L 1
L
1,2
2
A summary of the results is provided in the table below.
Transistor
W/L
ID(mA)
|V GS |(V)
Q1
50
0.1
0.7
Q2
50
0.1
0.7
Q3
100
0.2
0.7
Q4
20
0.1
0.7
Q5
20
0.1
0.7
Q6
100
0.2
0.7
Q7
40
0.2
0.7
ToobtainAd =500V/Vwhileoperatingall transistors at |VOV | = 0.2 V, we use
500 = 2|VA|2 0.04
⇒ |VA| = 3.16 V
Since |VA′ | = 5 V/μm, the channel length L (for
all transistors) must be 3.16 = 5×L
L = 0.632 μm
To obtain the highest possible gm, we operate at the highest possible I consistent with limiting the power dissipation (in equilibrium) to 0.5 mW. Thus,
VCC2.5V IC1
IC2
RC 5 k
VC2
VBE1 = VBE2 = 0.7 + 0.025 ln
1
= 0.660 V
VE1 =VE2 =−1−0.66=−1.66V
VC1 = VC2 = VCC −IC1.2 RC = 2.5 − 0.198 × 5 = +1.51 V
Chapter 9–11
RC 5 k VC1
0.5 V
Q1
VEE 2.5 V (b)
Q2
0.4 mA
=0.28mA 9.26 Refer to Fig. 9.15(a).
(a) For vB1 = +0.5 V, Q1 conducts all the current I (0.4 mA) while Q2 cuts off. Thus Q1 will have a VBE obtained as follows:
0.99 × 0.4 VBE1 = 0.7 + 0.025 ln 1
= 0.677 V
Thus,
VE =+0.5−0.677=−0.177V
which indicates that VBE2 = +0.177 V, too small to turn Q2 on.
VC1 =VCC −IC1RC =2.5−0.99×0.4×5 = +0.52 V
VC2 = VCC − IC2 × RC = 2.5−0×5 = 2.5 V
Observe that Q1 is operating in the active mode, as implicitly assumed, and the current source has a voltage of 2.323 V across it, more than sufficient for its proper operation.
(b) With vB1 = −0.5 V, Q1 turns off and Q2 conducts all the bias current (0.4 mA) and thus exhibits a VBE of 0.677 V, thus
VE = −0.677 V
which indicated that VBE1 = +0.177 V, which is too small to turn Q1 on. Also, note that the current source has a voltage of −0.677 + 2.5 = 1.823 V across it, more than sufficient for its proper operation.
VC1 =VCC −IC1RC =2.5−0×5=2.5V
VC2 =2.5−0.99×0.4×5=+0.52V
VE
I = 0.5mW (0.9 + 0.9)V
The current I will split equally between Q1 and Q2. Thus,
IE1 =IE2 =0.2mA
IC1 =IC2 =α×0.2=0.99×0.2=0.198mA
0.198
9.27
0.5 V
VCC 2.5 V IC1
IC2
RC 5 k
VC2
RC 5 k VC1
Q1
Q2
VE
VEE 2.5V (a)
0.4 mA
9.28 Refer to Fig. 9.15(a) and assume the current source I is implemented with a single BJT that requires a minimum of 0.3 V for proper operation. Thus, the minimum voltage allowed at the emitters of Q1 and Q2 is
−2.5 V + 0.3 V = −2.2 V. Now, since each of Q1 and Q2 is conducting a current of 0.2 mA, their VBE voltages will be equal:
0.99 × 0.2 1
= 1.2−9.8×10−3 ×82 ≃ 0.4 V
(b) Refer to Fig. 9.15(a).
ThemaximumvalueofVCM islimitedbythe need to keep Q1 and Q2 in the active mode. This is achieved by keeping vCE1,2 ≥ 0.3 V.
Since VC1,2 = 0.4 V,
VEmax = 0.4−0.3 = 0.1 V
and
VCMmax =VBE1,2 +VEmax
VCMmax = 0.574 + 0.1 = 0.674 V
TheminimumvalueofVCM isdictatedbythe need to keep the current source operating properly, i.e. to keep 0.3 V across it, thus
VEmin =−1.2+0.3=−0.9V and
VCMmin =VEmin +VBE1,2
= −0.9 + 0.574 = −0.326 V
Thus, the input common-mode range is −0.326 V ≤ VICM ≤ +0.674 V
(c) Refer to Fig. 9.15(d).
iE1 =11μA, iE2 =9μA
iC1 = 10.78 μA, iC2 = 8.82 μA
10.78 × 10−3 vBE1 = 0.69 + 0.025 ln 1
VBE1,2 = 0.7 + 0.025 ln
= 0.660 V
Chapter 9–12
Thus,theminimumallowableVCM is
VCMmin =−2.2+0.660=−1.54V
TheupperlimitonVCM isdictatedbytheneedto keep Q1 and Q2 operating in the active mode, thus
VCMmax =0.4+VC1,2
= 0.4+(2.5−0.99×0.2×5)
= +1.91 V
Thus, the input common-mode range is −1.54 V ≤ VICM ≤ 1.91 V
9.29
= 0.5767 V
vBE2 = 0.69 + 0.025 ln
= 0.5717 V Thus,
vB1 =vBE1 −vBE2
= 0.5767 − 0.5717 = 0.005 V = 5 mV
8.82 × 10−3 1
The solution is given on the circuit diagram. 9.30 (a) Refer to Fig. 9.15(a).
IE1 =IE2 = I =10μA
2 CC
replaced by
IC1 =IC2 =α×10=0.98×10=9.8μA
9.31 Refer to Fig. 9.15(a) with V (VCC +vr).
vC1 =(VCC +vr)−αIRC 2
=(VCC −αIRC)+vr 2
vC2 =(VCC +vr)−αIRC 2
=(VCC −αIRC)+vr 2
VBE1 = VBE2 = 0.690+0.025 ln
= 0.574 V
Thus,
VE =−0.574V
VC1 =VC2 =VCC −ICRC
9.8 × 10−3 1
vod ≡vC2 −vC1 =0
Thus, while vC1 and vC2 will include a ripple component vr, the difference output voltage vod will be ripple free. Thus, the differential amplifier rejects the undesirable supply ripple.
9.34 Requirevod =1Vwhenvid =10mVand I = 1 mA.
Using Eq. (9.48), we obtain
iE1 = 1 (mA) = 0.599 mA
iE2 = I −iE1 = 1−0.599 = 0.401 mA
vod =vC2−vC1
= (VCC − iC2RC) − (VCC − iC1RC)
= (iC1 − iC2)RC
≃ (iE1 − iE2)RC
= 0.198RC
9.32 Refer to Fig. 9.14. (a)V =V−IR
CMmax CC 2C
(b) ForVCC =2VandVCMmax =1V,
Chapter 9–13
1 + e−10/25
1 = 2 − 1 (IRC ) 2
Forvod =1V,wehave 1
⇒IRC =2V I/2
RC = 0.198 = 5.05 k VC1 =VC2 =VCC − IRC
(c) IB = β + 1 ≤ 2 μA
I ≤2×101×2=404μA Select
I = 0.4 mA
then
RC=2=5k 0.4
9.33 △iE1 = iE1 −(I/2) II
i
= E1 −0.5
I
Using Eq. (9.48), we obtain △iE1 = 1 −0.5
2
= 5−0.5×5.05 ≃ 2.5 V
With a signal of 10 mV applied, the voltage at one collector rises to 3 V and at the other falls to 2 V. To ensure that the transistors remain in the active region, the maximum common-mode input voltage must be limited to (2 − 0.4) = +1.6 V.
9.35 Refer to Fig. 9.14.
vod =vC2−vC1
= (VCC − iC2RC) − (VCC − iC1RC)
=R(i −i ) CC1 C2
Using Eqs. (9.48) and (9.49) and assuming α ≃ 1, sothatiC1 ≃iE1 andiC2 ≃iE2,weget
1 1
−
1 + evid /VT =5 1+e−vid/VT −1+evid/VT
This relationship can be used to obtain the data in thetablebelow.
I 1 + e−vid /VT
v =IR od C
Observethatforvid <10mVtheproportional transconductance gain is nearly constant at about 10.Thegaindecreasesasvid furtherincreases, indicating nonlinear operation. This is especially pronouncedforvid >20mV.
This table belongs to Problem 9.33.
This table belongs to Problem 9.35.
1 + e−vid /VT
1 1
vid (mV)
2
5
8
10
20
30
40
△i
I
E1 /vid
(V−1)
9.99
9.97
9.92
9.87
9.50
8.95
8.30
vid (mV)
2
5
10
15
20
25
30
35
40
vod(V)
0.2
0.498
0.987
1.457
1.90
2.311
2.685
3.022
3.320
Gain = vod vid
100
99.7
98.7
97.1
95.0
92.4
89.5
86.3
83.0
Chapter 9–14
The figure shows vod versus vid and the gain versus vid . Observe that the transfer characteristic is nearly linear and the gain is nearly constant for vid ≤ 10 mV. As vid increases, the transfer characteristicbendsandthegainisreduced. However,forvid evenaslargeas20mV,thegain is only 5% below its ideal value of 100.
where we have denoted the scale current of Q1 by IS and that of Q2 as 2IS . Dividing (1) by (2), we get
iC1 = 1e(vB1−vB2)/VT iC2 2
For iC1 = iC2, we obtain vB1 −vB2 =VT ln2
= 25 ln 2 = 17.3 mV
0.1 9.37 (a) VBE = 0.69 + 0.025 ln 1
= 0.632 V
(b) Using Eq. (9.48), we obtain
I
iC1 =αiE1 ≃ 1+e−vid/VT
9.36
(c) Forvid =200mVwhileiC1 =138μAand iC2 = 62 μA: Since iC1 and iC2 have not changed, vBE1 and vBE2 also would not change. Thus,
vB1 −vB2 =vBE1 +iE1Re −iE2Re −vBE2 =(vBE1 −vBE2)+Re (iE1 −iE2) 200=20+Re (iC1 −iC2)
= 20+Re (138−62)
⇒Re = 180mV =2.37k 76 μA
(d) Without Re,
vid = 20 mV → iC1 − iC2 = 76 μA
Forvid =20mV,
iC1 = 200μA =138μA
1 + e−20/25
iC2 = 200−138 = 62 μA
0.5 mA B1
Q1
1 mA B2
Q2
2 1.5 mA
Gm = 76μA =3.8mA/V 2 1 20mV
SinceQ hastwicetheEBJareaofQ,the1.5-mA bias current will split in the same ratio, that is,
With Re,
vid = 200 mV → iC1 − iC2 = 76 μA
Gm = 76μA =0.38mA/V 200 mV
Thus, the effective Gm has been reduced by a factor of 10, which is the same factor by which the allowable input signal has been increased while maintaining the same linearity.
9.38 gm = IC = α×0.2 ≃8mA/V VT 0.025
Rid =2rπ =2β =2×160=40k
iE2 = 2 iE2
Thus,
iE2 =1mA and iE1 =0.5mA
To equalize the collector currents, we apply a signal
vid =vB1−vB2
Now,
i = IS e(vB1−vE)/VT (1) C1 α
iC2 = 2IS e(vB2−vE)/VT (2)
α gm8
9.39 Rid =2rπ =20k 9.42 rπ =10k
β =10k RC gm
VCC
RC
Chapter 9–15
100 = 10 gm
⇒gm =10mA/V Ad =100=gmRC
RC = 100 = 100 = 10 k gm 10
gm=IC ≃I/2 VT VT
⇒ I = 2VT gm
= 2×0.025×10 = 0.5 mA 9.40 vid = 10 mA/V
Input signal to half-circuit = 5 mV. For
I = 200 μA, the bias current of the half-circuit is 100 μA and,
vod
Re
Re
I
re = 25mV =250 0.1 mA
Gain of half-circuit = − RC
= − 10 0.25
vid = 100 mV appears across (2 re + 2 Re). Thus the signal across (re + Re ) is 50 mV. Since the signal across re is 5 mV, it follows that the signal acrossRe mustbe50−5=45mVandthus
Re = 9re
TheinputresistanceRid is
Rid =(β+1)(2re +2Re)
=2(100+1)(re +Re)
=2×101×(re +9re)
= 2×101×10re
ToobtainRid =100k,
100 = 2×101×10×re
⇒re ≃50
Since
re = VT , IE
VEE
= −40 V/V
re
At each collector we expect a signal of 40×5mV=200mV.Betweenthetwo collectors, the signal will be 400 mV.
9.41 (a) re = 25mV =100 0.25 mA
The 0.1-V differential input signal appears across (2re +2Re),thus
ie = 100mV 200+2×400
=0.1mA
50 =
25mV
vbe = 0.1×100 = 10 mV
(b) The total emitter current in one transistor is
I +ie =0.35mAandintheothertransistor 2
I −ie =0.15mA. 2
(c) At one collector the signal voltage is −αieRC ≃−ieRC =−0.1×10=−1Vandat the other collector the signal voltage is +1 V.
(d) Voltagegain= 2V =20V/V 0.1 V
IE
⇒IE =0.5mA
I = 1 mA
Re =9re =9×50=450
Gain= α×2RC 2re + 2Re
≃ RC
re + Re
But the gain required is
Gain= vod = 2V =20V/V vid 0.1 V
Thus,
20= RC
0.05 + 0.45 ⇒RC =10k
The determination of a suitable value of VCC requires information on the required input common-mode range (which is not specified). Suffice it to say that the dc voltage drop across RC is 5 V and that each collector swings ±1 V. A supply voltage VCC = 10 V will certainly be sufficient.
9.43 (a) The maximum allowable value of the bias current I is found as
where
Ad =gmRC ≃I/2RC
Chapter 9–16
= IRC 2VT
Thus,
VT
IRC =AdVT (2) 2
Substituting from (2) into (1), we obtain
vˆ
vC1min =VCC −Ad VT + id (3)
I =
We choose to operate at this value of I. Thus
to keep Q1 in the active mode, vB1 ≤ 0.4 + vC1min
Thus,
VCMmax+vˆid =0.4+VCC−Ad VT+vˆid 22
⇒VCMmax =VCC +0.4−vˆid − vˆ 2
2
P
(VCC +VEE)
= 1 mW = 0.2 mA 5V
Since
vB1 = VCMmax + vˆid 2
gm =
IC VT
=
α(0.2/2) 0.025
≃ 4 mA/V
Ad =gmRC
60 = 4×RC ⇒RC=15k
Ad VT+ id Q.E.D. (4) I2
VC1 = VC2 = VCC − 2RC =2.5− 0.2 ×15
2
= +1 V
(b) Rid =2rπ =2β
gm
= 2 × 100 = 50 k 4
(c) vod =Ad ×vid
= 60 × 10 = 600 mV = 0.6 V
Thus, there will be ±0.3 V signal swing at each collector. That is, the voltage at each collector will range between 0.7 V and +1.3 V.
(d) To maintain the BJT in the active mode at all times,themaximumallowableVCM islimitedto
(b) VCC =2.5V, vˆid =10mV,
Ad=50V/V,
VCMmax = 2.5+0.4−0.005−50(25+5)×10−3
≃ 1.4 V
vˆod =Ad ×vˆid =50×10=500mV
= 0.5 V
Using Eq. (2), we obtain
IRC = 2AdVT = 2×50×0.025
= 2.5 V
To limit the power dissipation in the quiescent state to 1 mV, the bias current must be limited to
I = Pmax = 1 = 0.2 mA VCC +VEE 5
Using this value for I , we get RC = 2.5 =12.5k
0.2
(c) To obtain VCMmax = 1 V, we use Eq. (4) to
determine the allowable value of Ad ,
1 = 2.5 + 0.4 − 0.005 − Ad (25 + 5) × 10−3
⇒A =63.2V/V d
VCMmax =0.4+vCmin = 0.4+0.7 = 1.1 V
9.44 (a) Consider transistor Q1,
v = (V − I R ) − A vˆid C1min CC2C d2
(1)
Thus, by reducing VCM max from 1.4 V to 1 V, we are able to increase the differential gain from
50 V/V to 63.2 V/V.
9.45 Ad = gmRC = IC RC
VT
≃ (I/2)RC
9.46 See figure on next page. The circuit together with its equivalent half-circuit are shown in the figure.
Chapter 9–17
Ad = gm1,2(ro1,2 ∥ ro3,4) For
ro1,2 = ro3,4 = VA ≃ 2VA
α(I/2) gm1,2 = IC1,2 ≃ I
VT 2VT
I2V 2V Ad= A∥A
2VT I I = I × VA = VA
I
VT IR
=C 2VT
= 4
2 × 0.025
= 80 V/V VC1 =VC2 =VCC − IRC
=
2VT I 20
2 × 0.025
2VT
= 400 V/V
2
=5−2=3V
vC1 =3−80×0.005sin(ωt)
= 3 − 0.4 sin(ωt)
vC2 = 3 + 0.4 sin(ωt)
vC2 − vC1 = 0.8 sin(ωt)
The waveforms are sketched in the figure below.
9.47
RC
vod/2
Both circuits have the same differential half-circuit shown in the figure. Thus, for both
Ad = αRC re + Re
Rid =(β+1)(2re+2Re) =2(β+1)(re +Re)
Withvid =0,thedcvoltageappearingatthetop end of the bias current source will be
I (a)VCM−VBE− 2 RC
(b) VCM −VBE
Since circuit (b) results in a larger voltage across the current source and given that the minimum valueofVCM islimitedbytheneedtokeepa certain specified minimum voltage across the current source, we see that circuit (b) will allow a larger negative VCM .
vid 2
12 Rid Re Biased
at (I/2)
This figure belongs to Problem 9.46.
Chapter 9–18
VCC
VQ3Q Q3
BIAS
vid VCM 2
4
vod
vod/2
Q1 Q2 v vid Q1 V id 2
CM
2
Biased at I/2
VEE
I
Equivalent half-circuit
9.48
Substituting for RC from (2), for Re from (1), and forre =VT/(I/2),weobtain
Ad = α(120VT/αI) (2VT /I) + (8VT /I)
RC Q1
RC
L 2+8
vod R
Q2
= 120 =12V/V
9.50 vid = Rid (1)
Rid =(β+1)(2re+2Re)
thus,
vid = 2(β + 1)(re + Re) (2) vsig 2(β + 1)(re + Re) + Rsig
v od = α × Total resistance between collectors vid Total resistance in emitters
vsig Rid +Rsig where
A = α Total resistance between collectors d Total resistance in the emitter circuit
= α (2RC ∥ RL ) 2re
9.49 Refer to Fig. P9.47(a). IRe =4VT
2
⇒ Re = 8VT (1) I
= 2αRC 2re + 2Re
vod = αRC vid re +Re
Using (2) and (3), we get
Gv ≡vod = 2α(β+1)RC
vsig 2(β+1)(re +Re)+Rsig
(3)
α I R =60V
2CT β
RC =
Ad =α
αI
Total resistance in collector circuit
(2)
120V T
Sinceα= β+1,α(β+1)=β,wehave 2βRC
Total resistance in emitter circuit 2re +2Re re +Re
If vid = 0.5 vsig, then from (1) we obtain Rid = Rsig
Ad=α2RC =αRC
Gv = 2(β + 1)(r + R ) + R (4) e e sig
This figure belongs to Problem 9.50.
Chapter 9–19
RC Rsig/2
VCC
v od
RC
Rsig/2
Q1
Q2
vsig
VCM vsig
2
Re
Re VEE
I
Substituting for Rsig = Rid = 2(β + 1)(re + Re) into Eq. (4) gives
9.52 Refer to Fig. P9.52.
Gv = 2βRC 4(β+1)(re +Re)
= 1 αRC (5) 2re +Re
vo vi
=
= α × Total resistance in collectors Total resistance in emitters
0.99 × 25 2re + 2 × 0.25
2
If β is doubled to 2β while Rsig remains at its old value, we get
Rsig = 2(β + 1)(re + Re) (6)
thenthenewvalueofGv isobtainedby replacing β by 2β in Eq. (4) and substituting for Rsig from (5):
Gv = 4βRC
2(2β +1)(re +Re)+2(β +1)(re +Re)
where
re = VT = 25mV =250
IE 0.1 mA Thus,
vo = vi
0.99×25 ≃25V/V 2×0.25+2×0.25
≃
4RC = 2 RC 6(re +Re) 3re +Re
Rin =(β+1)(2re +2Re) = 2×101×(0.25+0.25) = 101 k
9.53 Refer to Fig. P9.53.
re = VT = 25mV =250
Thus the gain increases from approximately
1RC/(re + Re) to 2RC/(re + Re). 23
9.51 Rid =2rπ =2β gm
IC 0.2
gm = V ≃ 0.025 = 8 mA/V
IE 0.1 mA
α × Total resistance in collectors
vo T=
2 × 100 8 Rid
=25k α(2RC ∥RL)
Total resistance in emitters 0.99×25k
Rid = Gv =
2re Gv=R+R ×2gm(2RC∥RL)
vi
= 2re +500
0.99 × 25 k
= 500+500 ≃25V/V
Rin =(β+1)(2re +500)
= 101×(2×250 +500 ) = 101 k
Rid + Rsig Rid
1
id sig
= 25 × 1 × 8 × (40 ∥ 40)
25+100 2 = 16 V/V
9.54 (a) Refer to the circuit in Fig. P9.54. As a differential amplifier, the voltage gain is found from
9.56 Refer to Fig. P9.2.
I =0.25mA=1μC W |V |2 D 2 p ox L OV
Chapter 9–20
vo = α × Total resistance in collectors
vi Total resistance in emitters 1
= α×RC 0.25= 2 ×4×|VOV|
2
2re = αRC
2re
(b) The circuit in Fig. P9.54 can be considered as the cascade connection of an emitter follower Q1 (biased at an emitter current I /2) and a common-gate amplifier Q2 (also biased at an emitter current of I /2). Referring to the figure below:
⇒ |VOV | = 0.353 V
gm = 2ID = 2×0.25 =1.416mA/V
|VOV | 0.353
|Ad|=gmRD =1.416×4=5.67V/V
R 2RSS
2×30
= 1.33 × 10−3 V/V
CMRR = 4252.5 or 72.6 dB
9.57 Refer to Fig. P9.57.
(a) Assume vid = 0 and the two sides of the
differential amplifier are matched. Thus, ID1 =ID2 =0.5mA
| Acm | =
= 4 ×0.02
RD
D
△R D
RC
vo
Q1
vi
Q2
re1
Rin2 re2 ve1,2=re2 =1
1 W I=μCV2
vi re1 +re2
vo =αRC v e1,2 re2
2
D1,2 2noxLOV 1 2
Thus,
vo =1×αRC =αRC
0.5=2×2.5×VOV ⇒VOV =0.632V
vi 2 re2 2re
which is identical to the expression found in (a)
above.
VCM =VGS +1mA×RSS = Vt + VOV + 1 × RSS
= 0.7+0.632+1
= 2.332 V
(b)gm=2ID =2×0.5=1.58mA/V VOV 0.632
Ad =gmRD
8 = 1.38×RD
⇒ RD = 5.06 k
(c) VD1 =VD2 =VDD −IDRD =5−0.5×5.06=2.47V
9.55 g = 2μ C W I
√
m n ox L D
=
2×3×0.1 = 0.77 mA/V
|Ad|=gmRD =0.77×10=7.7V/V R △R
| Acm| = D 2RSS
D RD
10
= 2×100 ×0.01=5×10 V/V
|Ad|
CMRR= |Acm| =1.54×104 or83.8dB
−4
(d)
where
gm = 2ID = 2(0.1/2) = 0.5 mA/V
VOV 0.2
For CMRR of 80 dB, the CMRR is 104; thus
104 =2×0.5×RSS/0.02
RSS =200k
For the current source transistor to have ro = 200 k,
Chapter 9–21
RD
ΔVD1 ΔVCM Q1
1/gm
2RSS 2 k
The figure shows the common-mode half-circuit,
VA′ × L
200 =
0.1 mA
△VD1 △VCM
△VD1 △VCM
= −
= −
RD
1 +2RSS gm
L= 200×0.1 =4μm 5
9.60 It is required to raise the CMRR by 40 dB, thatis,byafactorof100.Thus,thecascodingof the bias current source must raise its output resistance RSS by a factor of 100. Thus the cascode transistor must have A0 = 100. Since
A0=gmro= 2I VA =2VA VOV I VOV
100= 2VA 0.2
⇒ VA = 10 V VA = VA′ ×L 10=5×L ⇒L=2μm
9.61 Refer to Fig. P9.61.
(a) v o = vid
α Total resistance across which vo appears Total resistance in the emitter
=α× 2k re1 + re2
Todeterminere1 =re2 =re = VT ,whereIE is IE
the dc emitter current of each of Q1 and Q2, we use
VE = VB − VBE = 0 − 0.7
= −0.7 V
5.06
1 + 2 1.58
= −1.92 V/V
(e) For Q1 and Q2 to enter the triode region VCM +△VCM =Vt +VD1 +△VD1
Substituting VCM = 2.332, Vt = 0.7 V,
VD1 = 2.47 V, and △VD1 = −1.92△VCM results in
2.332+△VCM = 0.7+2.47−1.92△VCM ⇒△VCM =0.287V
Withthischange,VCM =2.619Vand VD1,2 = 1.919 V; thus VCM = Vt + VD1,2.
9.58 The new deliberate mismatch △RD /RD cancels the two existing mismatch terms in the expression for Acm given in the problem statement so as to reduce Acm to zero. Thus,
RD ×△RD =−0.002 2RSS RD
5 × △RD = −0.002 2×25 RD
⇒ △RD = −0.02 or − 2% RD
(Note the sign of the change is usually determined experimentally.)
9.59 |Acm| = |Ad|=gmRD
RD 2RSS
△(W/L) W/L
IE = 0.5 mA
25 mV
2IE = −0.7−(−5) = 1 mA 4.3
|Ad| CMRR=|A |=2gmRSS
cm
vo 2 k
v =α×0.1k≃20V/V
id
△(W/L) W/L
re1 =re2 = 0.5mA =50
Chapter 9–22
(b)
Figure (a) shows the differential half-circuit. IE =0.5mA, IC =αIE ≃0.5mA
gm = IC = 0.5mA =20mA/V VT 0.025 V
re = 25mV =50 0.5 mA
ro = VA = 100 = 200 k IC 0.5
Ad =α×Totalresistanceincollectors Total resistance in emitters
≃ 10k∥10k (50 + 150)
= 5 = 25 V/V 0.2
We have neglected ro because its equivalent value at the output will be ro[1 + (Re/re)] =
200[1 + (150/50)] = 800 k which is much greater than the effective load resistance of 5 k.
Rid = 2×(β +1)(50 +150 ) = 2 × 101 × 0.2 (k) = 40.4 k
The common-mode half-circuit is shown in the figure,
vo =− α×2k vicm (0.05 + 8.6) k
≃ −0.23 V/V
v
o =0.23V/V
vicm
(c)CMRR=|v/v |=0.23=86.5
|vo/vid | o icm
20
(d) vo =−0.023sin2π×60t
+0.2 sin2π ×1000 t volts
9.62
R △R C C
or 38.7 dB
2RSS RC
| Acm| ≃
|Acm|= 10 ×0.02=0.001V/V
200
To obtain Ricm, we use Eq. (9.96):
Ricm ≃ βREE
where 2REE = 200 k, thus REE = 100 k and
Ricm = 100 × 100 1 + (10/(100 × 200)) 1+ 10+200
200
= 4.88 M
9.63 (a) gm = IC ≃ 0.1mA =4mA/V VT 0.025 V
Ad =gmRC =4×25=100V/V
(b) Rid = 2rπ = 2 β = 2 × 100 = 50 k
1+(RC/βro)
1+
RC + 2REE ro
gm 4 R △R
(c) |Acm|= C C 2REE RC
= 25 × 0.01 2×500
=2.5×10−4 V/V
(d) CMRR = |Ad| = 100
| Acm| 2.5 × 10−4
or 112 dB
= 4×105
(e) ro = VA ≃ 100 =1000k
(c) If the bias current I is generated using a Wilson mirror,
Chapter 9–23
IC
R ≃ β R icm EE
0.1
1 + (RC /β ro )
RC +2REE 1+ ro
REE = Ro|Wilson mirror 1
= 100 × 500 1 + (25/(100 × 1000)) 1 + 25 + 1000
1000
≃ 25 M
9.64 REE = VA = 20 =100k
I 0.2
For the transistors in the differential pair, we have
VA 20
ro = I/2 = 0.1 =200k
= 2βro
where ro is that of the transistors in the Wilson
mirror, then 50
ro = 0.5 =100k
REE =1×100×100=5M 2
| Acm| = 5
2 × 5, 000
× 0.1
=5×10−5 V/V
50 6
1 + (RC /β ro )
RC +2REE ro
ForRC ≪ro,
Ricm ≃βREE 1+ EE
CMRR= 5×10−5 =10 or 120 dB
9.66 See figure on next page. vbe1 = 2.5 sin(ωt), mV and
vbe2 = −2.5 sin(ωt), mV I
vC1 ≃ VCC − 2 RC −gmRC ×2.5×10−3 sin(ωt)
where
gm = I/2 = I mA
VT 0.05 V Thus,
vC1 = 5− I ×10− I ×10×2.5×10−3 sin(ωt) 2 0.05
= 5 − 5I − 0.5I sin(ωt)
Similarly,
vC2 = 5 − 5I + 0.5I sin(ωt)
To ensure operation in the active mode at all times withvCB =0V,weuse
vC1min = 0.005
5 − 5.5I = 0.005
⇒ I ≃ 0.9 mA
With this value of bias current, we obtain
0.9
gm = =18mA/V
0.05
Ad =gmRC =18×10=180V/V
At each collector there will be a sine wave of 180 × 2.5 = 450 mV = 0.45 V amplitude superimposed on the dc bias voltage of
5 − 0.45 × 10 = 0.5 V. Between the two collectors there will be a sine wave with 0.9 V peak amplitude. The figure illustrates the waveforms obtained.
R ≃ β R icm EE
1+
2R
50×100
2×100 =2.5M 200
ro
=
1+
9.65 For the differential-pair transistors, we have
IC ≃0.25mA
g = 0.25 =10mA/V
m 0.025
ro = VA = 50 = 200 k
IC 0.25
(a) Ad =gmRC =10×5=50V/V
where we have neglected the effect of ro since ro ≫RC.
(b) If the bias current is realized using a simple current source,
REE = ro|current source = VA = 50 = 100 k
|Acm|= C 2REE
C RC
I R △R
0.5
5
= 2 × 100 × 0.1 =2.5×10−3 V/V
CMRR = |Ad| = | Acm|
or 86 dB
50
2.5 × 10−3
= 2×104
Chapter 9–24
9.67 vo1 = −100 V/V vid
vo1,2 = −0.1 V/V v icm
Rid =10k
I = 2 mA
IE1 =IE2 =1mA
re1 =re2 =25
gm1 = gm2 = 40 mA/V
vo2 = +100 V/V vid
rπ1 = rπ2 = β = 100 = 2.5 k gm 40
SinceRid >rπ,weneedemitterresistances,as shown in the figure.
VCC
RC
vo1
Q1
RC
vo2 Q2
Re
vid
Re
I 2 mA
Rid 10 k 10=(β+1)(2re +2Re)
re + Re = 10 ≃ 50 2×101
Re = 25 vo1=− αRC
vid 2(re +Re) −100 = −αRC
2(0.025 + 0.025) ⇒RC ≃10k
To allow for ±2 V swing at each collector, VCC − I RC − 2 ≥ 0
2
assuming that VCM = 0 V. Thus,
VCC = 2 × 10 + 2 = 12 V 2
WecanuseVCC =15VtoallowforVICM ashigh as +3 V.
20log 2 =34dB △RC /RC
⇒ △RC =0.04=4% RC
9.69 If Q1 has twice the base-emitter junction
area of Q2, the bias current I will split 2 I in Q1 13
and 3 I in Q2. This is because with B1 and B2
grounded the two transistors will have equal VBE ’s. Thus their currents must be related by the ratio of their scale currents IS , which are proportional to the junction areas.
Chapter 9–25
| Acm | (to each collector) ≃
For | Acm| = 0.1,
0.1= 10 2REE
⇒REE =50k
RC
2REE
This is the minimum value of Ro of the bias current source. If the current source is realized by a simple current mirror, we obtain
REE = ro = VA I
Thus,
50 = VA 2
⇒VA =100V
The common-mode input resistance is
RC
Q1 2
iC1
ie1
iC2
ie2
R EE
RC
vicm
vo1
vo2
R ≃ βR 1 + RC /βro icm EE RC +2REE
vicm
Q2
ve
vicm
1+ ro
where ro is the output resistance of each of Q1 and
Q2,
ro=VA =100=100k
Ricm = 100 × 50 1 + (10/(100 × 100)) 1+ 10+100
100
= 2.4 M
9.68 If the output is taken single-endedly, then |Acm|= RC
2REE |Ad|=1gmRC
vicm REE
I/2 1
2
CMRRs = |Acm| =gmREE
With a common-mode input signal vicm applied, as shown in the figure, the current (vicm/REE) will split between Q1 and Q2 in the same ratio as that of their base-emitter junction areas, thus
2 vicm ie1=3REE
and
i =1vicm
e2 3 REE Thus,
vo1 = −ic1RC ≃ −ie1RC = −2 RC vicm 3 REE
and
vo2=−3R vicm
|Ad|
If the output is taken differentially, then
| Acm| = RC 2REE
| Ad | = gmRC
CMRRd = 2gmREE/
△R C
RC
1 RC EE
△RC RC
Thus,
CMRRd = CMRRs
2
△RC /RC
With the output taken differentially, we have
1 RC vo2−vo1=3R vicm
EE
Acm=1RC =1×12=0.008V/V
3 REE 3 500
9.70 gm = 2 k′n(W/L)ID
9.72 The offset voltage due to △Vt is VOS =±5mV
The offset voltage due to △RD is
I gm
VOS =
The offset voltage due to △(W/L) is
Chapter 9–26
= k ′n ( W / L ) I Ad =gmRD
2ID VOV==
gm
V △R 0.3
OV D = ×0.02=3mV 2RD 2
V△R
VOS = OV D 2 RD
For I = 160 μA, we have √
gm = 4 × 0.16 = 0.8 mA/V Ad =0.8×10=8V/V
VOV = 0.16 =0.2V 0.8
VOS = 0.2 ×0.02=2mV 2
For I = 360 μA, we have
g =√4×0.36=1.2mA/V
Ad =1.2×10=12V/V VOV = 0.36 =0.3V
1.2
VOS =0.3×0.02=3mV 2
Thus by increasing the bias current, both the gain and the offset voltage increase, and by the same factor (1.5).
(1)
(2) determine I and then Eq. (1) to determine Ad . The
results are as follows:
Weobservethatbyacceptingalargeroffsetwe are able to obtain a higher gain. Observe that the gain realized is proportional to the offset voltage one is willing to accept.
VOV △(W/L)
VOS = 2 (W/L) = 2 ×0.02=3mV
The worst-case offset voltage will be when all three components add up,
VOS =5+3+3=11mV
The major contribution to the total is the
variability of Vt . Tocompensateforatotaloffsetof11mVby
appropriately varying RD, we need to change RD by △RD obtained from
0.3
m
V △R 11mV= OV × D
2 RD
⇒ △RD = 11×2 = 0.0733
RD 300 or 7.33%
9.73 VOV =
I/2
1k′n(W/L)
2
=
I k′n(W/L)
0.2×10
0.1
D=0.04⇒VOS=OV D RD 2 RD
9.71 (a) gm = 2knID = knI Ad=gmRD= knIRD
VOV=I/2=I 1k kn
= △R
= 0.224 V
V △R
VOS =
Thus,
△(W/L)=0.04⇒VOS = VOV △(W/L) (W/L) 2 (W/L)
2n V△R
OV D 2 RD
= 0.224 × 0.04 = 4.5 mV
2
= 0.224 × 0.04 = 4.5 mV 2
△Vt =5mV⇒VOS =△Vt =5mV
Worst-caseVOS =4.5+4.5+5=14mV
If the three components are independent,
V =1I/k △RD
OS 2 n RD
(b) ForeachvalueofVOS weuseEq.(2)to
VOS = 4.52 +4.52 +52 =8.1mV △R
VOS (mV)
1
2
3
4
5
I (mA)
0.04
0.16
0.36
0.64
1.00
Ad (V/V)
4
8
12
16
20
9.74V=V C OS T RC
= 25×0.1 = 2.5 mV
9.75 V = V OS T
△I S
IS
= 25×0.1 = 2.5 mV
9.76 With both input terminals grounded, a mismatch △RC between the two collector resistors gives rise to an output voltage
I VO=α 2 △RC
Thus,
VOS =VT(α1−α2) Substituting, we obtain
β1 α1 = β1 + 1
(1) With a resistance RE connected in the emitter of
Chapter 9–27
each transistor, the differential gain becomes |A|= α×2RC = αRC
d 2(re +RE) RE +re
The input offset voltage VOS is obtained by
(2)
and
α2= β2
β2 +1 ββ
β1β2 +β1 −β1β2 −β2 (β1 + 1)(β2 + 1)
dividingVO in(1)by|Ad|in(2),
V
OS
= V 1 − 2
T β1 +1 β2 +1
I
VOS= (re+RE)
△R C
RC
△R C
=VT
2 Sincere = I/2,
1
β1 − β2
T (β1 +1)(β2 +1)
β1−β2 ≃VT ββ
VT
= V
VOS=(VT+ IRE)
2 RC
12 =V 1−1
Q.E.D. Forβ1 =50andβ2 =100,wehave
9.77
T β2 β1 11
RC (a1I/2)
VCC
VO
RC (a2I/2)
VOS =25 100−50 =−0.25mV
9.78 For the MOS amplifier:
Q2 22
I
VOS = VOV △RD 2 RD
Q1 II
= 200 × 0.04 2
= 4 mV
For the BJT amplifier:
△R V=VC
The current I splits equally between the two emitters. However, the unequal β’s will mean unequal α’s. Thus, the two collector currents will be unequal,
IC1 = α1I/2
IC2 =α2I/2
and the collector voltages will be unequal,
VC1 = VCC − α1(I/2)RC
VC2 = VCC − α2(I/2)RC
Thus a differential output voltage VO develops: VO =VC2 −VC1
= 1IRC(α1 −α2) 2
The input offset voltage VOS can be obtained by dividing VO by the differential gain Ad :
Ad =gmRC ≃I/2RC =IRC VT 2VT
OS T RC
= 25 × 0.04 = 1 mV
If in the MOS amplifier the width of each device is increased by a factor of 4 while the bias current is kept constant, VOV will be reduced by a factor of 2. Thus VOS becomes
VOS =2mV
9.79 Since the only difference between the two
sides of the differential pair is the mismatch in VA,
we can write
V
IC1 =IC 1+ CE1 VA1
V IC2=IC 1+ CE2
VA2 IC1 + IC2 = αI
IC 2+VCE1 +VCE2 =αI VA1 VA2
⇒IC =αI
IC1 =
VV 2+ CE1 + CE2
VA1 VA2 1 + VCE1
Consider only the incremental currents involved.
Assume the mismatch RS is split between the two base (source) resistances. The emitter currents will be different, as shown.
Equating the voltage drop from each grounded input to the common emitters, we have
R I I IB1RS+S+−re
2 2 2
Chapter 9–28
αI
2 1+VCE1 +VCE2
VA1 2VA1 2VA2
V VA1 VA2
αI 1 VCE1 IC1≃ 1+ −
2 2VA1
V
For CE1 ≪1and CE2 ≪1wehave
1 VCE2
2VA2
αI 1V 1V IC2 ≃ 1+ CE2 − CE1
2 2 VA2 2 VA1
The voltage VO between the two collectors will be
=I R−RS +I+Ir B2 S 2 2 2 e
Subtracting out the I re terms, we have 2
VO=VC2−VC1
IB1 RS+RS −Ire 22
=IC1RC −IC2RC
αI V V
R I =IB2RS−S+re
2 2
In terms of the emitter currents, this becomes
= RC× CE1−CE2 2 VA1 VA2
(1)
SincewestillhaveIC1 ≃IC2 =αI,the differential gain is still given by
2 2 RS + RS − I re
I I 2−
IC RC αIRC
Ad=gmRC=V =2V (2)
(β + 1)
I I
2 2
TT +
Dividing(1)by(2)gives
VV V=V CE1−CE2
OS T VA1 VA2
As a first-order approximation, we can assume
VCE1 ≃VCE2 =10V
andsubstituteVA1 =100VandVA2 =200Vto determine VOS as
10 10 VOS =25 100−200
= 25×0.05 = 1.25 mV 9.80
= 2 2 RS − RS + Ire (β+1) 22
Subtracting IRS
2 (β + 1)
each side, we obtain
IRS − IRS
and − IRS from 4(β + 1)
4(β+1) = − IRS
2(β+1)
−Ire 2
IRS
2 (β + 1)
IRS = IRS +Ire 2 (β + 1) (β + 1)
+
+ Ire 2
4 (β + 1)
Combining terms, we have
VCC RR
R IR
I S +re = S sothat
(β + 1) 2 (β + 1) I=IRS·1
C C
R VC R
2 (β + 1) RS (β+1)e
+ r
VC =ICRC. If β+1 ≈1,wehave
RS S RS S 22β
Q1
I I 22
VEE
Q2
IB1
IB2
VC = IRSRC · 1 2 (β + 1) RS
(β + 1)
Now VOS can be obtained by dividing VC by Ad = gmRC,
I I I 22
+ re
IRSRC · 1
9.82 IBmax = 400 ≃2.5μA 2 × 81
400
IBmin = 2×201 =1μA
Chapter 9–29
2 (β + 1)
RS (β+1) e
V=VC= OS Ad
+ r
=
IRS
2 (β + 1)
·
1
gm RC + r
= 200 − 200 ≃ 1.5 μA
RS
m (β+1) e
I
OSmax
81
201
g
VOS = IRS · 2
1
gm RS +(β+1)regm
9.83
VCC
a2I aI R3R3
VC2
Since(β+1)re =rπ andrπ gm =β,wehave
I·R C C 2β S
VOS =
9.81 Refer to Fig. P9.81.
(a) RC1 = 1.04×5 = 5.20 k
RC2 = 0.96×5 = 4.80 k
To equalize the total resistance in each collector, we adjust the potentiometer so that
RC1 +x×1k=RC2 +(1−x)×1k
5.2+x = 4.8+1−x
⇒ x = 0.3 k
(b) If the area of Q1 and hence IS1 is 5% larger than nominal, then we have
IS1 = 1.05IS
and the area of Q2 and hence IS2 is 5% smaller
than nominal,
IS2 = 0.95IS
Thus,
IE1 =0.5×1.05=0.525mA IE2 =0.5×0.95=0.475mA Assuming α ≃ 1, we obtain
g R Q.E.D. VC1 VO 1+mS
β Q1Q2
2
2I I 33
I
(a)
Vod
(b)
RC
Q1
RC
vid
re1
Q2
re2
From Fig. (a) we see that the transistor with twice the area (Q1) will carry twice the current in the other transistor (Q2). Thus
IE1 = 2I, 3
IE2 = I 3
IC1 = α2I, C1C2 32
IC2 = αI the potentiometer so that VC1 = VCC − α2I RC
I =0.525mA I =0.475mA
To reduce the resulting offset to zero, we adjust
Thus,
V=V 3
C1 C2
⇒V −(R +x)I =V −(R +1−x)I
VC2 =VCC − αIRC 3
and the dc offset voltage at the output will be VO = VC2 − VC1
VO = 1αIRC 3
CC C1 C1 CC C2 C2 IC1(RC1 +x)=IC2(RC2 +1−x)
0.525(5 + x) = 0.475(5 + 1 − x)
⇒ x = 0.225
To reduce this output voltage to zero, we apply a dc input voltage vid in the direction shown in Fig. (b). The voltage vid is required to produce vod in the direction shown which is opposite in direction to VO and of course |vod | = |VO|, thus
adjustment mechanism raises one RC and lowers the other, then each need to be adjusted by only (1.6 k/2) = 0.8 k.
If a potentiometer is used (as in Fig. P9.81), the total resistance of the potentiometer must be at least 1.6 k. If specified to a single digit, we use 2 k.
9.85Gm=2mA/V WithRL=∞, Ad=GmRo
and
vo = GmRovid WithRL=20k,
RL vo=GmRovidRL+Ro
=GR20v=1GRv m o20+R id 2 m o id
Advid = 1αIRC 3
ThegainAd isfoundasfollows:
A = α × Total resistance in collectors d Total resistance in emitters
= α × 2RC re1 + re2
(1)
V V 3V 1.5V
Chapter 9–30
where re1=T=T=T= T
IE1 2I/3 2I re2=VT =VT =3VT
IE2 I/3 I thus,
I
A=2αRC=2αIRC (2) d 4.5 V /I 4.5 V
TTo
Substituting in Eq. (1) gives
vid =0.75VT =18.75mV
Now, using large signal analysis:
vid =VB2 −VB1 =(VB2 −VE)−(VB1 −VE)
IC1 = IS1e(VB1−VE )/VT
IC2 = IS2e(VB2−VE )/VT
where IS1 = 2 IS2.
To make IC1 = IC2, IS1e(VB1−VE)/VT = IS2e(VB2−VE)/VT
e(VB2−VB1)/VT = 2
VB2 − VB1 = VT ln 2
Thus,
vid = 17.3 mV
which is reasonably close to the approximate value obtained using small-signal analysis.
9.84 A 2-mV input offset voltage corresponds to a difference △RC between the two collector resistances,
2=V △RC T RC
= 25 × △RC 20
⇒△RC =1.6k
Thus a 2-mV offset can be nulled out by adjusting
one of the collector resistances by 1.6 k. If the
Thus,
Ro =20k
Ad (withRL =∞)=GmRo =2×20=40V/V
(3) 2(I/2) 9.86 Gm = gm1,2 =
(4) VOV Ro =ro2 ∥ro4
For
ro2 =ro4 = |VA| = |VA′|L
I/2 I/2 = 2×5×0.5 = 5
II Ro =1×5=2.5
2II Thus,
=
I I
VOV 0.25
=
Ad=GmRo= I ×2.5=10V/V 0.25 I
I1W 9.87=μC V2
2 2 n ox L OV 12
0.1 = 2 ×0.2×50×VOV ⇒VOV =0.14V
2×(I/2) 2×0.1
gm1,2 = V = 0.14 = 1.4 mA/V
OV
ro2 = ro4 = |VA| = |VA′|×L = 5×0.5
=25k
I/2 I/2 0.1
Ad = gm1,2(ro2 ∥ ro4) = 1.4×(25 ∥ 25) = 17.5 V/V
9.88 Ad = gm1,2(ro2 ∥ ro4)
g = 2k′ W I m1,2 nLD
√ √ = 4I =2 I
ro2 =ro4 = |VA| = 2|VA| = 2×5 = 10
For Q5, Q6, Q7, and Q8: ID = 0.2 mA
0.2 = 1 × 5 × V 2 2 OV
⇒VOV =0.28V
VGS =0.5+0.28=0.78V
From the figure we see that for each transistor to operateatVDS atleastequaltoVGS,thetotal powersupplyisgivenby
VDD +VSS =VDS4 +VDS2 +VDS7 +VDS6 =VGS4 +VGS2 +VGS7 +VGS6 =0.7+0.7+0.78+0.78
= 2.96 ≃ 3.0 V
Chapter 9–31
I/2 I
1 10 10
I
I
√
Ad =2 I×2× I =√I
10 20 = √
I
⇒I =0.25mA
9.90
9.89
Q7
Q5
Q8
Q6
VDD
Q3
Q4
Ro6
vo
VBIAS
Q1 Q2
Q1
Q2
I
Ro4 Q3 Q4
I
Q8 Q7
Q5 Q6
VSS For Q1, Q2, Q3 and Q4:
(a) See figure.
(b) Ad = gm1,2(Ro4 ∥ Ro6)
gm1,2 = 2(I/2) = I VOV VOV
Ro6 = gm6ro6ro8
Since all transistors are operated at a bias current (I /2) and have the same overdrive voltage |VOV | and the same Early voltage, |VA|, all have the samegm =I/|VOV|andthesame
|VA|
ro = I/2 =2|VA|/I.Thus,
Ro6 =gmro2
Ro4 = gm4ro4ro2 = gmro2
Ad = gm(gmro2 ∥ gmro2)
= 1(gmro)2 2
I 1 W
= μC V2
2 2 n ox L OV 0.1=1×5×V2
2 OV ⇒ VOV = 0.2 V
VGS =Vt +|VOV|
= 0.5+0.2 = 0.7 V
This figure belongs to Problem 9.91.
Chapter 9–32
gmro = I × 2|VA| = 2|VA| |VOV | I |VOV |
Ad = 2(|VA|/|VOV |)2 Q.E.D.
For |VOV | = 0.2 V and |VA| = 10 V, we have 10 2
Ad =2 0.2 =5000V/V
9.91 Thecurrentsi1 toi13 areshownonthecircuit diagram. Observe that i11 = i7 = i3 (the current that enters a transistor exits at the other end!). Also observe that the mirror Q3 and Q4 is indeed functioning properly as the drain currents of Q3
and Q4 are equal (i12 = i2 = 1 gmvid ). However, 4
the currents in their ro’s are far from being equal!
There are some inconsistencies that result from the approximations made to obtain the results shown in Fig. P9.91, namely, gmro ≫ 1. Note for instance that although we find the current in ro of
Q2 to be 1gmvid , the voltages at the two ends of
9.92 Gm =gm1,2 = 2(I/2) = 0.2 =1mA/V VOV 1,2 0.2
ro2 = VAn = 20 = 200 k I/2 0.1
ro4 = |VAp| = 12 =120k I/2 0.1
Ro =ro2 ∥ro4 =200∥120=75k Ad = GmRo = 1×75 = 75 V/V
The gain is reduced by a factor of 2 with RL = Ro = 75 k.
9.93
VDD
Q3
Q4
12 IO ro are 2(gmro)vid andvid/4;thusthecurrentmust
1 1
be vid 2gmro − 4 ro, which is approximately
1gmvid. 2
The purpose of this problem is to show the huge imbalance that exists in this circuit. In fact, Q1
has |vgs| = 1vid while Q2 has |vgs| = 3vid . This 44
I
Q1 Q2
imbalance results from the fact that the current
mirror is not a balanced load. Nevertheless, we VSS know that this circuit provides a reasonably high
common-mode rejection.
(a) Let
At the output node, we have IO =ID4 −ID2
△(W/L) =ID3 1+ M −ID2
= ID1
=
W W 1 W L = L +2△ L
Chapter 9–33
1AA
(W/L)M
W = W −1△ W L2 LA2LA
Q1 and Q2 have equal values of VGS and thus of VOV , thus
1 W 1 W
I = k′ + △ V2 D1 2n L 2 L OV
△(W/L) 1 + M
− ID2
(W/L)M △(W/L)M
I
2 (W/L)M
1
W
A V2
= k′ 2 n
1+ Since, in the ideal case
OV
VOS=G =I/V
m OV
V △(W/L) = OV M
2 (W/L)M
0.2
2 ×0.02=2mV
A
A 1 △(W/L)
and the corresponding VOS will be IO IO
L A
I =I=1k′ W V2
Q.E.D.
2 (W/L)A
D1 2 2 n L OV A
I 1△(W/L) ID1=1+ A
(c) VOS|Q1,Q2 mismatch = 0.2
2 2 (W/L)A
Similarly, we can show that
VOS |Q3 ,Q4 mismatch = 2 × 0.02 = 2 mV Worst-caseV =2+2=4mV
9.94 IE1 = IE2 = 0.25 mA IC1 = IC2 ≃ 0.25 mA
gm1,2 = IC1,2 = 0.25mA =10mA/V VT 0.025 V
ro=|VA|= 10V =40k IC 0.25 mA
Rid =2rπ =2β =2×100=20k gm 10
Ro =ro2 ∥ro4 =40∥40=20k Gm = gm1,2 = 10 mA/V
Ad =GmRo =10×20=200V/V IfRL =Rid =20k,then
I 1△(W/L) ID2=1− A
OS
2 2 (W/L)A The current mirror causes
ID4 = ID3 = ID1 Thus,
IO =ID4 −ID2 =ID1−ID2
= I △(W/L)A 2 (W/L)A
The input offset voltage is
VOS = IO Gm
where Gm=gm1,2=2(I/2)= I
VOV VOV
Thus,
VOS = (VOV /2) △(W/L)A
Gv =200×
RL RL + Ro
(W/L)A (b) ID1 = ID2 = I
Q.E.D.
20 = 100 V/V 20+20
= 200 ×
2 ID3 = ID1
9.95 Using Eq. (9.145), we obtain 2VT
If the (W/L) ratios of the mirror transistors have a mismatch △(WL)M , the current transfer ratio of the mirror will have an error of
[△(W/L)M /(W/L)M ]. Thus
VOS = − βp −2 = − 2 × 25
βp ⇒ βp = 25
△(W/L)
ID4=ID3 1+ M (W/L)M
9.96
9.97
Chapter 9–34
Q3
Q4
Q5
aI 2 (1 2 ) bP2
i
aI/2
I/2
aI/2
I/2
Q1
Q2
The figure shows a BJT differential amplifier loaded in a base-current-compensated current mirror. To determine the systematic input offset voltage resulting from the error in the current-transfer ratio of the mirror, we ground the two input terminals and determine the output current △i as follows:
△i=I −I C2 C4
The figure shows a BJT differential amplifier loaded with a Wilson current mirror. To determine the systematic input offset voltage resulting from the error in the current-transfer ratio of the mirror, we ground the two input terminals and determine the output current △i as follows:
=αI−αI 2
≃αI 2=αI 2 β2 β2
1
2 1+(2/β2)
I
I I 1 △i=α2−α2 1+(2/βp2)
ppp
αI/2
1− 1
1 + (2/βp2)
=αI 2
≃−αI 2 =−αI 2 βp2 βp2
Dividing △i by Gm = gm1,2 = αI gives 2VT
2V VOS=− T βp2
For βp = 50,
VOS=−2×25=−20μV 502
Dividing△ibyGm =gm1,2 = input offset voltage VOS :
2VT VOS = − βp2
For βp = 50,
VOS =−2×25 =−20μV
502
9.98 Refer to Fig. P9.98.
A =GR d mo
VT
providesthe
where
Gm = gm1,2 ≃ I/2
VC1,2 = VBIAS − VBE3,4
= 1.4 − 0.7 = +0.7 V
The upper limit on VCM is 0.4 V above VC1,2: VCMmax =0.7+0.4=+1.1V
9.100
Chapter 9–35
VT Ro =Ro4 ∥Ro7
Here Ro4 is the output resistance of the cascode amplifier (looking into the collector of Q4), thus
Ro4 = gm4ro4(ro2 ∥ rπ4) Usually rπ4 ≪ ro2,
Ro4 ≃ gm4rπ4ro4 = β4ro4
The resistance Ro7 is the output resistance of the
Wilson mirror and is given by
Ro7 = 1β7ro7 2
Thus
1
Ro = (β4ro4) ∥ 2β7ro7
Since all β and ro are equal, we obtain
1 Ro =(βro)∥ 2βro
= 1βro 3
and
and
Ad = 1βgmro 3
(a) WithvI =0, IE1 = IE2 = I
Q.E.D. Forβ=100andVA =20V,wehave
2 IC1=IC2=β I
gmro=ICVA=VA=20=800 VT IC VT 0.025
β+12 IE4 =IC2 = β I
Ad = 1 ×100×800=2.67×104 V/V
3 β+12
9.99 Refer to Fig. P9.98.
(a) VB7 =+5−VEB6 −VEB7 =5−0.7−0.7 = +3.6 V
vOmax = VB7 + 0.4 = +4 V
(b) Thedcbiasvoltageshouldbe VO=vOmax−1.5
= 4 − 1.5 = +2.5 V
(c) For vO to swing negatively (i.e., below the dc bias value of 2.5 V) by 1.5 V, that is, to +1 V with Q4 remaining in saturation, VBIAS should be
VBIAS =vOmin +0.4 = 1.4 V
(d) With VBIAS = 1.4 V, the bias voltage at the collectorsofQ1 andQ2 is
IB4= IE4 = 1 β I β+1 β+1β+1 2
IE3 = IC1 + IB4 =βI+1βI
β+12 β+1β+1 2 βI1
=β+12 1+β+1
IE3 β 1 I
IB3=β+1=(β+1)2 1+β+1 2 Since IB3 is the input current to the Q7 − Q8
mirror and IC8 is its output current, we have
IC8 = 1 = β IB3 1+2 β+2
β
Thus,
IC8 = (β+1)2(β+2)
β2
1+ β+1 2
1 I
At the input node, we have IB = IB1 − IC8
I/2 β2 1I = β+1 − (β+1)2(β+2) 1+ β+1 2
IB= 2 I/21− β 1+1
β + 1 (β + 1)(β + 2) β + 1 I/2 β2 β+2
(β + 1)2 2β + 1
ie3=ic1−ib4= β vid − β vid
Chapter 9–36
βv1 = id1−
β+1 2re
(β+1)2 2re
β+1 2re β+1 β 2 vid
= β+1 2r e
=β+1 1−(β+1)(β+2) β+1 = I/2 (β+1)2−β2
i=ie3=β2 vid b3 β + 1 (β + 1)3 2re
i=i1=iβ
c8 b3 2 b3β+2
β+1 I/2
1+β (β+1)3 β+2 2re
At the input node, we have
ii = ib1 − ic8
= ≃
= ≃ =
=β+1
≃ I/2 2β
= β3
1 vid
(β + 1)2 β+1 β2
I/2 β =β+1 2
Thus, including the current mirror Q7 − Q8 reduces the input bias current by a factor equal to (β/2), a substantial decrease!
(b)
=vid/2re − β3 1
β+1 (β+1)3 β+2 2re
vid vβ3 1
id 1−
2(β +1)re (β +1)2 β +2
v β3 id 1−
2(β + 1)re (β + 1)3
v1 id 1−
2(β + 1)re (1 + 1/β)3 vid 3
2(β + 1)re β
v β
id
2(β + 1)re 3
The analysis follows the same process used above, except that here we deal with signal quantities.
ie = vid 2re
where re = re1 = re2
Thus the input current is reduced by a factor (β/3),whichresultsinRid increasingbyafactor (β/3).
9.101 To maximize the positive output voltage swing, we select VBIAS as large as possible while maintaining the pnp current sources in saturation. For the latter to happen, we need a minimum of 0.3 V across each current source. Thus the maximum allowable voltage at the emitters of Q3 andQ4 isVCC −0.3=5−0.3=+4.7V.Then, the maximum allowable value of
VBIAS =4.7−0.7=+4V.TokeepQ4 in saturation,
vOmax = VBIAS + 0.4 = 4.4 V
If the dc voltage at the output is 0 V, then the
maximum positive voltage swing is 4.4 V. In the negative direction,
vOmin =−VEE +VBE7 +VBE5 −0.4
ic1 =ic2 = ie4 = ic2 =
i = ie4 b4 β + 1
β vid β+1 2re
βv β+1 2re
= β vid
(β + 1)2
2re
id
= −5 + 0.7 + 0.7 − 0.4 = −4 V
Thus,
−4V≤vO ≤+4.4V
Gm =gm1,2 ≃ 0.25mA =10mA/V 0.025 V
Ro4 =β4ro4 =50×|VA| I/2
100 V
=50× 0.25mA =20M
Ro5 = 1β5ro5 = 1 ×100× 100 2 2 0.25
= 20 M
Ro =Ro4 ∥Ro5 =20M∥20M=10M Ad = GmRo = 10×10,000 = 105 V/V
9.102 The overdrive voltage, |VOV |, at which Q1 and Q2 are operating is found from
I = 1k′p(W/L)|VOV|2 2 2
0.1= 1 ×6.4×|VOV|2 2
W W
⇒ = =50
L3 L4
(b) Gm =gm1,2 = 2(I/2) = I
= 0.2 = 0.2
Chapter 9–37
1 mA/V
Ad =GmRo
50 = 1×Ro ⇒Ro =50k But
Ro =ro2 ∥ro4
VOV VOV
andro2 =ro4 (Q2 andQ4 havethesameID = I
2
and the same VA). Thus
ro2 =ro4 =100k= |VA|
I/2 |VA|= I ×100k=10V
2
10 = |VA′ |L = 20 L
⇒ L = 0.5 μm
(c) vOmin =VCM −Vtn
⇒ |VOV | = 0.18 V Gm =gm1,2 = 2(I/2)
= 0 − 0.5 = −0.5 V
vOmax =VDD −|VOV|=1−0.2=0.8V Thus,
−0.5V≤vO ≤0.8V
(d) RSS = |VA| = 10 =50k I 0.2
|VOV| = 0.2 = 1.13 mA/V
The CMRR can be obtained using Eq. (9.159): CMRR = (gmro)(gmRSS )
= (1 × 100)(1 × 50)
= 5000 or 74 dB
9.104 The CMRR is given by Eq. (9.158): CMRR = [gm1,2(ro2 ∥ ro4)] [2 gm3RSS]
(a) Current source is implemented with a simple current mirror:
|V| A
0.18
ro2 = |VAp| = 10 = 100 k
I/2 0.1
ro4 = |VAnpn| = 30 = 300 k
I/2 0.1
Ro =ro2 ∥ro4 =100k∥300k=75k Ad =GmRo =1.13×75=85V/V
9.103 (a) For Q1 and Q2,
I 1 W = μC
V2 2 2 n ox L OV
RSS = ro|QS =
gm1,2 = gm3 = 2(I/2) = I
VOV VOV ro2 = ro4 = |VA| = 2|VA|
1,2
1W I
0.1 = 2 × 0.4 × W W
L × 0.04 1,2
⇒ L = L For Q3 and Q4,
I1W 2=2μnCox L |VOV|2
× 0.04
= 12.5
12 I/2I
3,4
1 W
Thus,
CMRR= I ×1×2|VA|×2× I ×|VA| VOV 2 I VOV I
V 2
= 2 A Q.E.D. VOV
0.1 = 2 × 0.1 × L
3,4
(b) Current source is implemented with the modified Wilson mirror in Fig. P9.89:
RSS = gm7ro7ro9
Transistor Q7 has the same k′(W/L) as Q1 and Q2, butQ7 carriesacurrentI twicethatofQ1 andQ2. Thus
Rim = 1 ∥ ro3 gm3
where
gm3 = gm1 = gm2 = 1 mA/V
ro3 =ro2 =ro4 =50k
Rim =1k∥50k=0.98k 1
Am =1 1+gmro3 1
= 1 1 + = 0.98 A/A 1 × 50
Rom =ro4 =50k
Ro2 = ro2 + 2RSS + 2gm2ro2RSS =50+50+2×1×50×25 =2600k
Acm = −(1 − Am)Gmcm(Rom ∥ Ro2)
Acm =−(1−0.98)×0.02×(50∥2600) = −0.0196 V/V
Chapter 9–38
√ √ VOV7 = 2VOV1,2 = 2VOV
and
gm7 = V = √
2I 2I √2I
OV 7
ro7 =ro9 = VA
2VOV
= V OV
√2V2 A
VOV I
Thus,
RSS =
VOV
I
=
I
√2I V 2 A
I
and
√2VA2
VOV 2 I VOV VOVI
1
2|VA|
I
CMRR= ×× ×2× ×
√ V 3 =2 2 A
A CMRR= d =
Acm
or 62.1 dB
Alternatively, using the approximate expression in Eq. (9.157), we obtain
Acm ≃ − 1 = − 1 = −0.02 V/V 2gm3RSS 2 × 1 × 25
and
CMRR= 25 =1250 0.02
or 61.9 dB
9.106 From Eq. (9.153), we have
Acm = −(1 − Am)Gmcm(Rom ∥ Ro2) where
Gmcm = 1 = 1 =0.011mA/V 2RSS 2 × 45
Using the fact that Ro2 ≫ Rom, we obtain
Acm ≃−(1−0.98)×0.011×45
=3000
Q.E.D.
For k′(W/L) = 4 mA/V2 and I = 160 μA,
25 0.0196
=1274
VOV
0.080 = 1 × 4 × |VOV |2 2
⇒ |VOV | = 0.2 V For |VA| = 5 V: For case (a),
CMRR = 2 × For case (b),
5 2
= 1250 or 62 dB
= 4.42 × 104
0.2
√ 5 3
CMRR = 2 2 or 93 dB
0.2
9.105 Gm = gm1,2 = 2(I/2) = 0.2 = 1 mA/V VOV 0.2
|VA| 5
ro2 =ro4 = I/2 = 0.1 =50k
Ro =ro2 ∥ro4 =50k∥50k = 25 k
Ad =GmRo =1×25=25V/V
R =|VA|= 5 =25k SS I 0.2
=−0.01V/V
A 30
CMRR= d =
Acm 0.01
or 69.5 dB
A 9.107 CMRR = d
11 Acm
Gmcm = 2R = 2 × 25 = 0.02 mA/V CMRR = 60 dB or equivalently 1000. Thus, SS
1000 = 50 |Acm|
⇒ | Acm| = 0.05 V/V
But from Eq. (9.153), we obtain
| Acm| = (1 − Am)Gmcm(Rom ∥ Ro2)
Since Rom ≪ Ro2 and Gmcm = 1/2RSS , we have
thus
Ro =800k∥800k=400k Ad =GmRo =5×400=2000V/V
IB = I/2 ≃ 0.125mA =1.25μA β+1 100
The lower limit on VICM is determined by the lowest voltage allowed at the collector of Q5 while Q5 is in the active mode. This voltage is −5 + 0.3 = −4.7 V. Thus
VICMmin =−4.7+VBE1,2 =−4.7+0.7 = −4 V
TheupperlimitonVICM isdeterminedbythe need to keep Q1 in the active mode. Thus
VICMmax =VC1 +0.4
= 4.3+0.4 = 4.7 V
Thus the input common-mode range is
−4V≤VICM ≤+4.7V
The common-mode gain can be found using Eq. (9.165):
Acm=− ro4 β3 REE
| A | = (1 − A ) Rom cm m 2RSS
0.05=(1−Am)× 20 2×20
⇒ (1 − Am) = 0.1
9.108
Chapter 9–39
VCC 5 V
Q3
Q1
Q4
Q2
vO
Here,
ro4 = |VA| = 100 =800k
I
R
I
I/2 0.125 β3 = 100
Q
6
Q
REE =ro5 = |VA| = 100 =400k I 0.25
5
Thus
Acm = − 800 = −0.02 V/V
5 V Gm =gm1,2 ≃ I/2
VT
5 = I/2 VT
⇒I =0.25mA
100 × 400
The CMRR can be found as
Utilizing two matched transistors, Q5 and Q6, the value of R can be found from
I = 0−(−5)−0.7 = 0.25 mA
CMRR = |Ad| = 2000 = 100,000 |Acm| 0.02
or 100 dB
9.109 See figure on next page.
From the solution to Problem 9.108, we know that I = 0.25 mA. For the Widlar current source, use R = 2 k. Thus
IREF = 5−0.7 = 2.15 mA 2
The value of RE can be found from I
IRE=VBE6−VBE5=VTln REF I
2.15 0.25 × RE = 0.025 ln 0.25
R =215 E
R ⇒ R = 17.2 k
β
Rid =2rπ =2 gm
Ro = ro2 ∥ ro4 where
=2×
100 5
=40k
ro2 =ro4 = |VA| = 100 =800k I/2 0.125
5 V
Ro = 200 k ∥ 200 k = 100 k Ad =GmRo =8×100=800V/V Rid = 2rπ = 2β/gm
= 300 = 37.5 k 8
REE = |VA| = 40 =100k I 0.4
The common-mode gain can be found using Eq. (9.165):
Acm=− ro4 β3REE
= − 200 = −0.013 V/V 150 × 100
Chapter 9–40
Q3
Q1
Q4
Q2
vO
R
IREF
I
Q6
Q5
The CMRR can be obtained from CMRR = |Ad| = 800 = 60,000
RE
|Acm| 0.013 or 96 dB
5 V
The output resistance of the Widlar current source
is given by Eq. (8.102). Thus REE =[1+gm5(RE ∥rπ5)]ro5 where
gm5 = I = 0.25 mA = 10 mA/V VT 0.025 V
rπ5 = β = 100 = 10 k gm5 10
ro5 = VA = 100 =400k I 0.25
REE =[1+10(0.215∥10)]×400 = 1.24 M
Rid,Ro,Ad,IB,andtherangeofVICM willbethe same as in Problem 9.108. The common-mode gain, however, will be lower:
Acm =− ro4 β3 REE
=− 800 100 × 1240
Gv = Rid ×Ad Rid +Rsig
=
37.5 × 800 = 444.4 V/V 37.5 + 30
=6.45×10−3 V/V and the CMRR will be
9.111 Refer to Fig. P9.111. To determine the bias current I, which is the current in the collector of Q5, we first find the reference current through the 6.65-k resistor:
IREF = 9−(−5)−0.7 = 2 mA 6.65
Assuming Q5 and Q6 are matched, we have I = 2 mA
(a) gm1,2 ≃ I/2 = 1mA =40mA/V VT 0.025 V
Rid = 2rπ = 2β/gm1,2 = 2×100 =5k
40
(b) Ad =GmRo
where
Gm = gm1,2 = 40 mA/V Ro =ro2 ∥ro4
ro2 =ro4 = |VA| = 60 =60k I/2 1
Ro =60k∥60k=30k
Ad =40×30=1200V/V
(c) Acm can be found using Eq. (9.165),
Acm =− ro4 β3REE
CMRR = |Ad| = |Acm|
or 110 dB
2000 6.45×10−3
= 3.1×105
I/2 0.2
9.110 Gm =gm1,2 ≃ V = 0.025 =8mA/V
T
Ro = ro2 ∥ ro4
ro2 =ro4 = |VA| = 40 =200k I/2 0.2
where
REE =ro5 = |VA| = 60 =30k
(c) Acm can be found from Eq. (9.165): Acm =− ro4
I Acm = − 60
2
= −0.02 V/V
β3REE
where REE is the output resistance of the Wilson
Chapter 9–41
100 × 30
CMRR = |Ad| = 1200 = 60,000
mirror,
REE = gm7ro7ro5
where
gm7= 2I =2×0.12
VOV 0.35 = 0.7 mA/V
r =r = |VA| = 60 =500k o7 o5 I 0.12
REE =0.7×5002 =175M
| Acm| 0.02 or95.6dB
9.112 Refer to Fig. P9.112. To determine the bias currentI,whichisthedraincurrentofQ7,we analyze the Wilson mirror circuit as follows: All four transistors, Q5 – Q8, are conducting equal currents (I ) and have the same VGS ,
VGS =Vt +VOV
Thus
IR = 15−(−5)−2 VGS 144I = 20−2 Vt −2 VOV But
I = 1k′ (W/L)V2 2 n OV
1
= ×2×V2 =V2
2 Thus
144 V2 OV
Acm =− 1
100 × 175
=5.7×10−5 V/V
CMRR = |Ad| = 1200 |Acm| 5.7×10−5
or 146 dB
= 21×106
OV OV
9.113 Refer to Fig. 9.40.
W6 can be determined using Eq. (9.172):
(W/L)6 (W/L)7 =2
(W/L)4 (W/L)5
(W /0.5)6 = 2 (60/0.5) (10/0.5) (60/0.5)
⇒W6 =20μm
For all devices we can evaluate ID as follows: ID8 = IREF = 225 μA
I =I (W/L)5 =I =225μA D5 REF (W/L) REF
8 I = ID5 = 225 μA
1
ID1 = ID2 = 2ID5 = 112.5 μA
ID3 =ID4 =ID1 =112.5μA
ID6 =ID7 =IREF =225μA
WithID ineachdeviceknown,wecanuse
= 20−2×0.7−2V OV
144V2 +2V −18.6=0 OV OV
⇒VOV =0.35V
and
I=0.352 =0.12mA (a) Rid = 2rπ = 2β/gm where
gm =gm1,2 ≃ I/2 = 0.06 =2.4mA VT 0.025
Rid = 2×100 =83.3k 2.4
(b) Ad = gm1,2Ro where
Ro = ro2 ∥ ro4 But
ro2 =ro4 = |VA| = 60 =1M I/2 0.06
Ro = 500 k
Ad = 2.4×500 = 1200 V/V
1 W IDi = 2μCox L
|VOVi|2
i
to determine |VOVi| and then
|VGSi| = |VOVi| + |Vt|
The values of gmi and roi can then be determined
from
gmi = 2IDi
roi = |VA| IDi
|VOVi|
Chapter 9–42 The results are summarized in the following table.
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
ID (μA)
112.5
112.5
112.5
112.5
225
225
225
225
|VOV | (V)
0.25
0.25
0.25
0.25
0.25
0.25
0.25
0.25
|VGS | (V)
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
gm (mA/V)
0.9
0.9
0.9
0.9
1.8
1.8
1.8
1.8
ro (k)
80
80
80
80
40
40
40
40
A1 =−gm1(ro2 ∥ro4)
= −0.9 × (80 ∥ 80) = −36 V/V
A2=−gm6(ro6∥ro7)
=−1.8×(40∥40)=−36V/V
A0 =A1A2 =−36×−36=1296V/V
The upper limit of VICM is determined by the need to keep Q5 in saturation, thus
VICMmax =VDD −|VOV5|−|VSG1| =1.5−0.25−1=+0.25V
ThelowerlimitofVICM isdeterminedbytheneed tokeepQ1 andQ2 insaturation,thus
VICMmin =VG3 −|Vt|
=−VSS +|VGS3|−|Vt|
= −1.5 + 1 − 0.75 = −1.25 V Thus
−1.25 V ≤ VICM ≤ +0.25 V
The output voltage range is
−VSS +VOV6 ≤vO ≤VDD −|VOV7| that is,
−1.25V≤vO ≤+1.25V
9.114 1 (a)I =I =100= μC
ID5 =ID7 =ID8 =200μA
Thus
200= μC V2
1 W 2noxL OV
= 1 ×400× 2
5,7,8
W ×0.04
W
=
L 5,7,8
W L5L7L8
=
ID6 =200= 2μpCox L
= 25
W 1 W
|VOV|2 ×0.04
= 100
The results are summarized in the following table:
Ideally, the dc voltage at the output is zero.
(b) The upper limit of VICM is determined by the
need to keep Q1 and Q2 in saturation, thus VICMmax =VD1 +Vt
=VDD−|VSG4|+Vt
=0.9−|Vt|−|VOV4|+Vt
=0.9−0.2=+0.7V
ThelowerlimitofVICM isdeterminedbytheneed to keep Q5 in saturation,
VICMmin =−0.9+|VOV5|+|VGS1| =−0.9+0.2+0.2+0.4=−0.1V Thus
−0.1V≤VICM ≤+0.7V
(c) vOmax =VDD −|VOV6| = 0.9 − 0.2 = +0.7 V
1 W
6
200= 2 ×100× L
W
6
L 6
Transistor
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
W/L
12.5
12.5
50
50
25
100
25
25
D1 D2
V2
W
2 n ox L OV
100= 1 ×400× 2
W
L 1,2
1,2
|VOV|2
W W ⇒ =
×0.04 = 12.5
L1 L2
1 W
ID3 =ID4 =100= 2μpCox L 1 W
W W
⇒ = =50 L3 L4
3,4
100= ×100× ×0.04 2 L 3,4
vOmin =−VSS +|VOV7|
= −0.9 + 0.2 = −0.7 V Thus
−0.7V≤vO ≤+0.7V (d) A1 = −gm1,2(ro2 ∥ ro4) where
gm1,2 = 2×0.1 = 1 mA/V 0.2
ro2 =ro4 = |VA| = 6 =60k 0.1 mA 0.1
A1 =−1×(60∥60)=−30V/V A2 = −gm6(ro6 ∥ ro7)
where
gm6 = 2×0.2 =2mA/V 0.2
ro6 =ro7 = |VA| = 6 =30k 0.2 0.2
A2 =−2×(30∥30)=−30V/V A0 =A1A2 =30×30=900V/V
(b) A1 is proportional to gm1,2, thus A1 increases by a factor of 2 and the overall voltage gain increases by a factor of 2.
(c) Since the input offset voltage is proportional to |VOV 1,2 |, it will decrease by a factor of 2. This, however,doesnotapplytoVOS dueto△Vt.
9.116 If (W/L)7 becomes 48/0.8, ID7 will become I =I (W/L)7
D7 D8 (W/L)8
VO = 18×10−3 ×(111 ∥ 92.6)
=909mV
The corresponding input offset voltage will be
VOS=VO A0
= 909 = 0.82 mV 1109
9.117 Refer to Fig. 9.40 and let the two input terminals be grounded. Then,
ID1 = ID2 = I 2
If Q3 has a threshold voltage Vt and Q4 has a threshold voltage Vt + △Vt then
ID3 = I = 1 kn3(VGS3 −Vt)2 22
Chapter 9–43
⇒ VGS3 = Vt + I/kn3 12
ID4=2kn4(VGS4−Vt−△Vt)
(W/L)2 by a factor of 4 reduces |VOV 1,2 | by a factor of 2. Thus
Since kn4 = kn3 and VGS4 = VGS3, we have
ID4 = I kn3(VGS3 −Vt −△Vt)2 2
1
= 2kn3( I/kn3−△Vt)2
9.115 (a) Increasing (W/L)1 and
gm1,2 = 2ID/|VOV1,2| increase by a factor of 2.
2 = 1kI1−√△Vt
2 n3kn3 I/kn3
I △V2 =1−t
2 VOV 3
The output current of the first stage will be IO = ID2 − ID4
I I △V2 =−1−t
(48/0.8) REF (40/0.8)
2 2
△Vt For V
OV 3
VOV3
≪ 1 we obtain
= I
= 90 × 1.2 = 108 μA
I 2△V 2 2 VOV 3
= 2(I/2) △Vt VOV 3
= gm3 △Vt Q.E.D.
The corresponding input offset voltage will be
VOS=IO gm1,2
= gm3 △Vt gm1,2
VOS = gm3 △Vt gm1,2
Thus ID7 will exceed ID6 by 18 μA, which will result in a systematic offset voltage,
VO = 18 μA(ro6 ∥ ro7) where
ro6 = 111 k
and ro7 now becomes
ro7 = 10 =92.6k 0.108
Thus
I
IO≃ − 1− t
9.118
a
Q3
VDD 1.2 V
Q4
Chapter 9–44
1 W
6
The results are summarized in the following table:
(b) The upper limit on VICM is determined by the need to keep Q1 and Q2 in saturation, thus
VICMmax = VD1,2 +|Vt|
=VDD −|Vt|−|VOV|+|Vt|
= 1.2 − 0.15 = 1.05 V
The lower limit on V is determined by the ICM
need to keep Q5 in saturation, thus VICM =|VOV5|+VGS1,2
= 0.15+0.15+0.35 = 0.65 V Thus
0.65V≤VICM ≤1.05V
Note that the input dc voltage in part (a) falls outside the allowable range of VICM ! Thus, part (a) shouldhavespecifiedaVICM greaterthan0.65V. The results of part (a), however, will not change.
(c) 0.15V≤vO ≤(1.2−0.15) that is,
0.15V≤vO ≤1.05V
200= ×540× 2
L 1,2
|VOV|2 W
IREF 200 A
Q6
vo
×0.152
Q1 Q2
Q8 Q Q7 5
(a) With the two input terminals connected to a dcvoltageofVDD/2=+0.6VandforQ1 −Q4 to conduct a current of 200 μA, we have
×0.152
×0.152
1
W L 6
1 W I=k′ V2
×100× W
400=
2
D1,2 2n L OV 1,2
⇒=356
L
Transistor
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
ID (μA)
200
200
200
200
400
400
400
200
W/L
32.9
32.9
178
178
65.8
356
65.8
32.9
W L 1,2
⇒
ID3,4 = 2k′p L
= 32.9 1W
1
200= ×100×
2
W
⇒ = 178
L
3,4
1W 400 = k′ V 2
3,4
L 3,4
Transistor Q5 must carry a current of 400 μA, thus
2n L OV 5
= 1 ×540× W ×0.152 2L5
⇒
W L5
= 65.8
Similarly, Q7 is required to conduct a current of 400 μA, thus
W
=
W
L = 65.8
L
Transistor Q8 conducts a current of 200 μA, thus
W 1W
= = 32.9
L82L5
Finally, Q6 must conduct a current equal to that of Q7,thatis,400μA,thus
7
5
(d) gm1,2 = 2 × 0.2 = 2.67 mA/V 0.15
ro2 = ro4 = |VA| = 1.8 = 9 k 0.2mA 0.2
A1 = −gm1,2(ro2 ∥ ro4) = 2.67(9 ∥ 9) = −12 V/V
gm6 = 2×0.4 = 5.33 mA/V 0.15
where RC5 is the total resistance in the collector of Q5. Since ro5 = ∞, RC5 is simply the input resistance of the emitter follower Q6, we have
RC5 =Ri6 =(β+1)(re6 +RL) where
re6=VT =25mV=25 IE6 1 mA
Ri6 = (100 + 1)(0.025 + 1)
= 103.5 k
Thus
A2 =−20×103.5=−2070V/V Thegainofthethirdstageisgivenby
A3 = vo = RL = 1 = 0.976 V/V v5 RL +re6 1+0.025
The overall voltage gain can now be obtained as A0≡vo =A1A2A3
Chapter 9–45
ro6 =ro7 = |VA| 0.4 mA
= 1.8 =4.5k 0.4
A2 = −gm6(ro6 ∥ ro7) =−5.33(4.5∥4.5)=12V/V
A0 =A1A2 =−12×−12=144V/V
9.119 Refer to Fig. P9.119.
(a) With the inputs grounded and the output
at 0 V dc, we have
IE1 = IE2 = 1 × 0.4 = 0.2 mA 2
IE3 =IE4 ≃0.2mA
IE5 ≃ 0.5 mA
IE6 = 1 mA
(b) The short-circuit transconductance of the first stage is
Gm =gm1,2 = IC1,2 ≃ 0.2mA =8mA/V VT 0.025 V
vid =−40×−2070×0.976=8.07×104 V/V
9.120
The voltage gain of the first stage can be obtained
by multiplying Gm by the total resistance at the output node of the stage, i.e., the common
collectors of Q2 and Q4 and the base of Q5. Since vid ro2 =ro4 =∞,theresistanceatthisnodeisequal
to the input resistance of Q5 which is Rπ5,
5 k ic3 ib3
Q3
ic1
ib1 25
Q1
50 50
5 k Q4
25
Q2
50
50
rπ5 = β gm5
where
gm5 = IC5 = 0.5 =20mA/V
Rin
VT 0.025 rπ5 = 100 = 5 k
20
Thus the voltage gain of the first stage is given by
v b5
Rin2 = 2(β + 1)(25 + 25) =2×101×50≃10k
Effective load of first stage = Rin2 ∥ (5 + 5) = 10 ∥ 10 = 5 k
A1 =
α Total resistance between collectors of Q1 and Q2
thus
= −Gmrπ5 = −8 × 5 = −40 V/V
A1 ≡ v
The voltage gain of the second stage is
Total resistance in emitters of Q1 and Q2 ≃ 5k =25V/V
id
A2≡vc5 =−gm5RC vb5
4 × 50
Rin =(β+1)(4×50)
= 101×200 ≃ 20 k
ic1
ib1
ib3
= 10+10 = 0.5 ic3 = ic3 × ib3 × ic1 = 100×0.5×100
The gain of the second stage will now be vo2 3 k ∥ Ri3
=β1 =100
(5+5) 10
A2 = v =−α2×0.025+2×0.025 o1
Chapter 9–46
= (5+5)+R
i c1
ic3 ib3
= 5000 A/A
9.121 Refer to Fig. 9.41. From Example 9.7, we
obtain
IC1 = IC2 = 0.25 mA IC4 =IC5 =1mA IC7 = 1 mA
IC8 = 5 mA
Thus
25 mV
re1 =re2 ≃ 0.25mA =100
r =r = 25mV =25 e4 e5 1mA
With 100- resistance in the emitter of each of Q1 and Q2, we have
Rid = (β + 1)(2re1,2 + 2Re1,2)
= 101×(2×0.1+2×0.1)
= 40.4 k
Thus, R increases by a factor of 2. With 25- id
resistance in the emitter of each of Q4 and Q5, the input resistance of the second stage becomes
Ri2 = (β + 1)(2re4,5 + 2Re4,5) = 101 (2×0.025+2×0.025) = 10.1 k
Thus, Ri2 is increased by a factor of 2. The gain of the first stage will be
in2 =β3 =100
From Example 9.8, Ri3 = 234.8 k, thus 3 ∥ 234.8
Thus
ib1 ib3 ic1 ib1
A2 ≃− 0.1 =−29.6V/V
which is about half the value without the two 25- emitter resistances. The gain of the third stage remains unchanged at −6.42 V/V, and the gain of the fourth stage remains unchanged at 1 V/V. Thus the overall voltage gain becomes
vo = A1A2A3A4 vid
= 20×−29.6×−6.42×1
= 3800.6 V/V
which is less than half the gain obtained without the emitter resistances. This is the price paid for doubling Rid .
9.122 The output resistance is mostly determined byR5.ToreduceRo byafactorof2,weuse
152 R Ro= =R6∥re6+ 5
β+1 5 + 5
⇒R5 =7.37k
This change in R5 will affect the gain of the third
stage, which will now become A3 =−R5 ∥(β+1)(re8 +R6)
R4 + re7
= − 7.37 ∥ (101)(0.005 + 3)
2.3 + 0.025 = −3.1 V/V
which is about half the original value (not surprising since R5 is about half its original value). To restore the gain of the third stage to its original value, we can reduce R4. This will, however, change Ri3 and will reduce the gain of the second stage, though only slightly. For instance, to restore the gain of the third stage to −6.42 V/V, we use
2.3 + 0.025 = 6.42 R4 + 0.025 3.1
⇒ R4 = 1.085 k
NowRi3 =101×(1.085+0.025)=112kand
the gain of the second stage becomes A2 =−3k∥112k =−58.4V/V
30
which is a slight decrease in magnitude from the original value of −59.2 V/V.
2
76 = 3000 ∥
R 101
v
vid
α × Total resistance between the collectors of Q1 and Q2
o1 =
Total resistance in emitters of Q1 and Q2
≃ 40k∥10k =20V/V 2×0.1+2×0.1
Thus the gain of the first stage decreases but only slightly. Of course, the two 100- resistances in the emitters reduce the gain but some of the reduction is mitigated by the increase in Ri2, which increases the effective load resistance of the first stage.
9.123 Refer to Fig. 9.41(a). With R5 replaced with a 1-mA constant-current source with a high output resistance, the total resistance in the collector of Q7 now becomes the input resistance ofQ8,whichis
Ri4 =(β+1)(re8 +R6)
= 101 × (0.005 + 3) = 303.5 k
Thus the gain of the third stage now becomes A =−α 303.5
3 2.3+0.025 ≃ −130.5 V/V
and the overall voltage gain increases to
vo 130.5 5
v =8513× 6.42 =1.73×10 V/V
id
Refer to Fig. (a) for the dc analysis. Replacing the 68 k-33 k divider network by its Thévenin equivalent, we obtain
33
VBB =−5V+ 33+68 ×10V
=−1.73V
RBB =68k∥33k=22.2k
Now, we can determine IE1 from
101
IC1 =α1 ×0.52=0.99×0.52≃0.52mA
The collector current IC1 and the 8.2-k resistor it feeds can be replaced by a Thévenin equivalent as shown in Fig. (b). Thus
Chapter 9–47
VBB −(−5)−0.7 RBB
IE1 =
= −1.73 + 5 − 0.7 = 0.52 mA
4.7 + β + 1 4.7 + 22.2
(b) The output resistance now becomes
very large resistance
Ro = 3 k ∥ re8 + β + 1 ≃ 3 k
When the amplifier is loaded with RL = 100 , Gv =1.73×105 RL =
5 V
1.73 × 105 × Gv = 5581 V/V
RL + Ro 100
3.3 k IE2
Q2 IC2
3000 + 100
If the original amplifier is loaded in RL = 100 ,
0.74 V
8.2 k
(b)
100
Gv = 8513× 152+100 = 3378 V/V
Thus, although the output resistance of the original amplifier is much lower than that of the modified one, the overall voltage gain realized when the original amplifier is loaded in 100- resistance is much lower than that obtained with the modified design. Thus, replacing the 15.7-k resistance with a constant-current source is an excellent modification to make!
9.124 (a)
IE2 = 5 − 0.74 − 0.7 3.3 + 8.2
101
= 1.05 mA
IC2 ≃ 1.04 mA
The collector current IC2 and the 5.6-k resistance it feeds can be replaced by a Thévenin equivalent as shown in Fig. (c). Thus
IE3 = 0.824−0.7−(−5) 2.4 + 5.6
ic1 = gm1vi = 20.8vi β
= 2.1 mA
(b) R =68k∥33k∥r
where
IC2 1.04 mA in π1 T
Chapter 9–48
101
VO =−5+2.1×2.4=0V
Ri2 = rπ2 = gm2
gm2 = V = 0.025V =41.6mA
where rπ1 = β
gm1
gm1 = IC1 = 0.52 = 20.8 mA/V
VT 0.025 rπ1 = 100 =4.81k
20.8
Rin =68k∥33∥4.81≃4k
5.6 k Rout=2.4k∥ re3+β+1
where
re3 = VT = 25mV =11.9
rπ2 = 100 =2.4k 41.6
i =g v 8.2 =16.1v b2 m1 i8.2+2.4 i
ic2 = β2ib2 = 100 × 16.1vi = 1610vi Ri3 = (β + 1)(re3 + 2.4 k)
= 101(0.0119 + 2.4) = 243.6 k
ib3 = ic2 × 5.6 = 0.0225ic2 5.6 + 243.6
= 0.0225 × 1610vi = 36.18vi ie3 =(β+1)ib3
= 101 × 36.18 = 3654vi
vo = ie3 × 2.4 k
= 3654 × 2.4vi = 8770vi Thus
vo = 8770 V/V vi
9.125 From the figure we observe that the controlled source gm1 vgs1 can be replaced by a resistance 1/gm1, thus
IE3 Rout = 2.4 ∥
2.1 mA
5.6
0.0119 + 101 (c) Refer to Fig. (d)
= 65.5
1 vgs1=ii ro1∥gm1
Ri ≡ vgs1 = 1 ∥ ro1 ii gm1
1
iosc = gm2vgs2 = gm2vgs1 = gm2 g m1
1
i gro1
A ≡ osc =g m1 is i m21
∥ ro1 ii
i +ro1 gm1
This figure belongs to Problem 9.125.
d2, g1, g2
iosc
Ro
i
Ri
ro1
vgs1 vgs2
r o2
i
gm1vgs1
gm2vgs2
= gm2 1 gm1 1+ 1
gm1 ro1 Since gm1ro ≫ 1,
g 1
and since the output resistance is Ro =ro6 ∥ro8 = 1 |VA|
Ais≃m2 1−
then
vo =4idRo =4×
Thus
A ≡ vo = |VA| d vid |VOV |
I 2|VOV |
×1 |VA|×vid 2 I
gm1 = Ais |ideal
where
Ais |ideal =
gm1 ro1 1
Chapter 9–49
2I
1−gm1ro1 gm2
Q.E.D.
gm1
Finally, from inspection,
(c) See figure on next page. With vicm applied to both input terminals, we can replace each of Q1 and Q2 with an equivalent circuit composed of a controlled current, vicm/2RSS in parallel with a very large output resistance (Ro1 and Ro2 which are equal). The resistances Ro1 and Ro2 will be much larger than the input resistance of each of the mirrors Q3 − Q5 and Q4 − Q6 and thus we can neglect Ro1 and Ro2 altogether. The short-circuit output current of the Q4 − Q6 mirror will be
Ro = ro2
9.126 (a) Refer to Fig. P9.126. The current ID in each of the eight transistors can be found by inspection. Then, gm of each transistor can be determined as 2ID/|VOV | and ro as |VA|/ID. The results are given in the table below:
(b) See figure below. Observe that at the output nodethetotalsignalcurrentis4id where
i=g vid d m1,22
I
= 2|VOV|vid
This table belongs to Problem 9.126.
gm4 gm4 ro4 2RSS |V |v
io6=gm6 1− 1 vicm
= 1− OV 2|VA |
icm RSS
Transistor
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
ID
I
2
I
2
I
2
I
2
I
2
I
I
2
I
gm
I
|VOV |
I
|VOV |
I
|VOV |
I
|VOV |
I
|VOV |
2I |VOV |
I
|VOV |
2I |VOV |
ro
2|VA | I
2|VA | I
2|VA | I
2|VA | I
2|VA | I
|VA| I
2|VA | I
|VA| I
This figure belongs to Problem 9.126, part (b).
Q5 id
id
Q7
Q3
Q4
Q6 2id
4vid 2id
Q8
id
id
vid vid
22 0V
Q1 Q2
vo
This figure belongs to Problem 9.126, part (c).
Chapter 9–50
Q5 Q3Q4 Q6
io5 ro5
( 1 //r ( gm7 o7
Q7
and the output resistance will be ro6 . The short-circuit output current of the Q3 − Q5 mirror will be
g io5=m5 1−
vicm 2RSS
io6
ro6 vicm vo
2RSS Ro2 ro8 io8
Ro1
Q8
| Acm | = ro6 ∥ ro8 1 RSS gm7ro7
|VA| (d)RSS= I
VA Ad=|V|
Q.E.D.
1 v gm3ro3 2RSS
icm
gm3
= 1 − |VOV | vicm 2|VA | 2RSS
OV
1 |VA |/I 1
and the output resistance will be ro5. Since ro5 is much larger than the input resistance of the
Q7 −Q8 mirror(≃1/gm7),mostofio5 willflow into Q7, resulting in an output short-circuit current io8:
i=gm81−1 i o8g gro5
|Acm| = 2
|VA|/I [I/|VOV | ] [2|VA|/I]
|Acm| =
2
1 1 |V | 1 V
× OV = 2 |VA|
OV VA
4 Q.E.D.
m7
m7 o7
V 2 CMRR=4A
VOV
(e) The upper limit on VICM is determined by Q1
and Q2 remaining in saturation, thus VICMmax =VDD −|VSG|+|Vt|
= VDD − |VOV |
ThelowerlimitonVICM isdeterminedbythe need to keep the bias current source in saturation, i.e. maintaining a minimum voltage across it of |VOV|,thus
VICMmin = −VSS + |VOV | + |VGS |
= −VSS + 2|VOV | + |Vt|
Thus
−VSS +|Vt|+2|VOV|≤VICM ≤VDD −|VOV| The output linear range is
VDD −|VOV|≤vO ≤−VSS +|VOV|
1 = 2 1 − g r
io5
=1−OV 1− icm
m7 o7 |V |
1 v 2|VA| gm7ro7 RSS
andtheoutputresistanceisro8.Thus,atthe output node we have a net current
|V | io6−io8= 1− OV
1 gm7 ro7
v RSS
icm
2|VA | 1 v
≃ icm gm7ro7 RSS
This current flows into the output resistance (ro6 ∥ ro8) and thus produces an output voltage
ro6 ∥ro8 vo = R
SS
1
g r vicm m7 o7
and the common-mode gain becomes
9.127 (a)
QF
100 A 100 A
F
4.3 V
5 V 2
QG
200 A
100 A
Chapter 9–51
QE 3.6 V
E
R 100
A
G
100 A
100 A
Q3
100
A Q4
Q1
Q2
1 mA D 0 V 0 mA
IREF 100 A
R = +3.6−(−4.3) = 79 k 0.1 mA
See Figure (a) for the dc analysis.
VA =−4.3V VB =−0.7V VC =+0.7V
VD =0V VE =+3.6V VF =+4.3V
VG = +4.3 V
(b) See table below. Results are obtained from Fig. (a) and
I gm = C VT
ro = |VA| IC
B
200 A
C Q5 100 A
1 mA
(c) See figure (b) on next page. Total resistance at the collector of Q3 is
β3ro3 ∥ roC ∥ β4(roD ∥ ro4)
= (100 × 2) ∥ 2 ∥ 100 × (0.2 ∥ 0.2) = 200 ∥ 2 ∥ 10 = 1.65 M
vc3 =1×gm1,2×1.65M vid 2
13
= 2 ×4×1.65×10 =3300V/V
vo ≃1 vc3
QA A QB QC QD 4.3 V
1 2 1 10 5 V
(a)
Thus
vo = 3300 V/V
vid
Observe that the polarity of the two input
Transistor
IC (mA)
gm (mA/V)
ro (M)
Q1
0.1
4
2
Q2
0.1
4
2
Q3
0.1
4
2
Q4
1.0
40
0.2
Q5
0
0
∞
QA
0.1
QB
0.2
QC
0.1
2
QD
1.0
0.2
QE
0.1
QF
0.1
QG
0.2
1
terminals are correct. (d) Rid = 2 rπ1,2
=2× β =2×100=50k gm1,2 4
Ro=ro4∥roD∥ re4+ oC β+1
= 0.2 ∥ 0.2 ∥ 0.025×10−3 +
o3
r∥βr
2 ∥ 200 101
≃ (0.2 ∥ 0.2 ∥ 0.02) M
= 16.7 k
(e) VICMmax is limited by Q2 saturating, VICMmax = VG + 0.4 = +4.7 V
This figure belongs to Problem 9.127, part (c).
Chapter 9–52
This figure belongs to Problem 9.127, part (g).
VICMmin is limited by QB saturating, VICMmin = VA −0.4+0.7
= −4.3 − 0.4 + 0.7 = −4 V
(f) The voltage at the base of Q4 can rise to (VB3 + 0.4) before Q3 saturates, i.e. to +3.6+0.4=+4V.ThusvO cangoto
+4 − VBE4 = +3.3 V. The output voltage can go down to the value that causes the voltage at C to be 0.4 V below the base voltage of QC . Thus
vOmin =−4.3−0.4+VEB5 =−4V Thus
−4.0V≤vO ≤+3.3V
(g) With vO at its maximum positive value of +3.3 V, and RL small enough to cause Q2 to cut off, the conditions in the circuit become as shown inFig.(c).
The value of RL can be found from RL = 3.3 = 363
9.1
With vO at its maximum negative value of −4 V and with RL sufficiently small to cause Q1 to cut off, Q2 will conduct 200 μA which leaves Q3 with zero current (cut off). Transistor Q4 also cuts off, and the circuit conditions become as shown in Fig. (d).
Thus
RL = 9.1 =360
4
9.128 DC analysis
(a) I =10μA=1×40×5V
(c)
Transistor ID VGS gm ro
REF 2 ⇒VGSA =1.71V≈1.7V
5 GSA
−V2
t (μA) (V)
(μA/V) (M) 28.3 5 28.3 5 28.3 5 56.6 2.5 28.3 5 200 1
Chapter 9–53
10=1×20×5VGSEF −12 25
Q1 10 Q2 10 Q3 10 Q4 20 Q5 10 Q6 50
1.7 1.7 1.7 1.7 1.7 1.5
⇒VGSEF =2V
R= 1−(−3.3) =430k
0 –1.5* 0 ∞
10 μA
(b) See figure (a) below.
Q7
QA
QB
QC
QD
QE
QF
* Cut-off.
(d) Refer to
source of the cascode transistor Q5 is (ro2 ∥ ro4). Thus the output resistance of the cascode transistor will be
Ro = gm5ro5(ro2 ∥ ro4)
and the total resistance at the drain of Q5 will be
Rtotal = Ro ∥ roC = [gm5ro5(ro2 ∥ ro4)] ∥ roC = [(28.3 × 5)(5 ∥ 2.5)] ∥ 5
= 4.9 M
VGS1 =VGS2 =VGSA ≈1.7V 2×10
10 1.7 20 1.7 10 1.7
28.3 5 56.6 2.5 28.3 5
VGS3 = 10 +1=1.71V≈1.7V 20× 5
50 10 10
1.7 141.4 1 2 20 5 2 20 5
VGS5 =VGS3 =1.7V
For Q6: 50 = 1 × 40 × 50(VGS6 − Vt)2
2 5 ⇒VGS6 =1.50V
VA =−3.3V, VB =−1.7V VC = +1.5 V, VD = 0 V
VE =+1V, VF =+3V VG =+3.3V, VH =+2.7V
This figure belongs to Problem 9.128, part (a).
Fig. (b). The total resistance at the
5 V
F G 20A
2.7 V 10 A
Q5
2 VQF
2 VQE
1 V 10 A
3.3 V A
Q3
1.7 V
Q4
F
0V
0V
10 A
50 A Vo
0V 0 A
3.3 V
10 A 10 A Q1
1.7 V
Q2
1.5 V
0
Q7
Q6
0
D
5
20 A
B
C
10 A
B
QA QQQD
BC 1.7 V
5 V
(a)
This figure belongs to Problem 9.128, part (d).
Chapter 9–54
Q3
gm1,2 (vid) 2
Q4
gm1,2 (vid) 2
(vid) gm1,2 2
gm1,2 vid
Q5
vid
2 2Ro
(vid)
ro6
vo
roD
Q1 Q2
r r o2 o4
roC
Q6
QD
QC
The voltage gain to the drain of Q5 can be found as
vd5 = gm1,2Rtotal = 28.3 × 4.9 = 138.7 V/V vid
The gain of the source-follower output stage is
(f) vOmax = VCmax − VGS6 =VE +|Vt|−VGS6
= 1+1−1.5 = 0.5 V vOmin =VA −|Vt| =−3.3−1=−4.3V Thus
vo = vd5
(ro6 ∥roD) (r ∥r )+ 1
(b)
=
o6 oD 1∥1
gm6 ≃1V/V
−4.3V≤vO ≤+0.5V
(g) The circuit conditions are depicted in Fig. (c).
D 1 V 50 A
(1 ∥ 1) + 1 200
and the overall voltage gain is vo = 138.7 V/V
vid
Rin = ∞
Ro =roD ∥ro6 ∥ =1∥1∥ 1
200
RL
1 gm6
QD
50 = 1 V RL
⇒RL =20k
(h) WithRL =2kandvO isatitsmaximum allowable value (to be determined), the circuit conditions are as indicated in Fig. (d).
(c)
≃ 5 k
(e)VICMmax =VG+|Vt|
= 3.3 + 1 = +4.3 V
VICMmin = VBmin + VGS1,2 =VA −|Vt|+VGS1,2
= −3.3 − 1 + 1.7 = −2.6 V Thus
−2.6V≤VICM ≤4.3V
Observe that Q6 is cut off and Q7 has not yet conducted. Thus all the load current is sourced by QD. It follows that the maximum negative load current must be 50 μA
Chapter 9–55
VCmax Q6
D ˆ Vo
QD
(d)
WithRL =2kandvO isatitsminimum allowable value (to be determined), the circuit conditions become as shown in Fig. (e).
Vo 50A RL
ˆ
RL 2 k
Here Q7 turns on and its current becomes Here
VCmax =VE +|Vt|=2V Now
Vˆ o
ID6 = R +50μA
ID7= Vˆo−0.05 mA 2
But
ID7 = μpCox
= Vˆo+0.05 mA Thus,
2 Vˆo −0.05 = 1 ×20×20×10−3(−Vˆo +4.3−1)2
But 22
1
L 2L7
W
(−Vˆo −VCmin −|Vt|)2
1 W
⇒Vˆ =1.45V (VCmax −Vˆo −|Vt|)2 o
Thus
−1.45V≤vO ≤+0.17V
ID6 = 2μnCox L
Vˆo +0.05= 1 ×40×10×10−3 (2−Vˆo −1)2
22 ⇒Vˆo =0.17V
6