CS计算机代考程序代写 js Chapter 17

Chapter 17
Solutions to Exercises within the Chapter
Ex:17.1 ItPLH =CVDD 2
⇒tPLH =CVDD/2I
ToobtaintPLH =10pswithC =10fFand VDD = 1.2 V, we need a current I obtained as follows:
10×10−12 = 10×10−15 ×1.2 2I
⇒e−tPLH/τ =0.5
⇒tPLH =τln2=0.69τ ForC=10fFandRonu =20k􏱹,then τ = 10×10−15 ×20×103 = 200 ps and
tPLH =0.69×200=138ps
NextwedeterminetPHL byconsideringthe situation depicted in Fig. 1(b). Here, PU has just opened, leaving v O (0+) = VD D . Capacitor C then discharges through the on resistance of the pull-down switch, Rond, toward 0 V, thus vO(∞) = 0, thus
vO =0−(0−VDD)e−t/τ
=VDDe−t/τ
Att=tPHL,vO =VDD/2andweget
VDD =VDDe−tPHL/τ 2
⇒tPHL =τln2=0.69τ
Here,
τ = C Rond
= 10×10−15 ×10×103 = 100 ps Thus,
tPHL=69ps
The propagation delay tP can now be obtained as
Exercise 17–1
⇒ I = Ex: 17.2
VDD Ronu
= 0.6 mA
vO
1.2 × 10−14 2 × 10−11
vO VDD VDD
C
PD 2
0 tPLH Figure 1(a)
t
VDD
PU
vO vO VDD
VDD
2 0
Rond
C
Figure 1(b)
tPHL t 1
tP = 2(tPLH +tPHL)
To obtain tP L H , consider the situation in Fig. 1(a). Here, PD has just opened (at t = 0) leaving
vO =0Vatt=0+.CapacitorCthencharges through the on resistance of the pull-up switch, Ronu, toward VDD, thus
= 1(138+69)=104ps 2
vO(t)=V∞ −(V∞ −V0+)e−t/τ = V − (V − 0)e−t/τ
Ex: 17.3
vO 0.9V VDD
DD DD
= VDD(1−e−t/τ) Att=tPLH,vO =VDD/2,thus
DD
VDD =VDD(1−e−tPLH/τ) 2
0.1VDD
tf
t2
Figure 1
t
0
t1

Figure 1 shows the exponential discharge curve and the two points that define the extent of the fall time, t f . Here,
vO(t) = VDDe−t/τ
vO(t1) = 0.9VDD = e−t1/τ (1)
vO(t2) = 0.1VDD = e−t2/τ (2)
Dividing (1) by (2) gives
9 = e−(t1−t2)/τ 9 = et f /τ
⇒tf =τln9=2.2τ
For C = 100 fF and R = 2 k􏱹,
τ = 100×10−15 ×2×103 = 200 ps and
tf =2.2×200=440ps=0.44ns
73V V2 Ex:17.4αn=2 − tn+ tn
50×10−12 =0.69× 30×1 ×103×20×10−15 (W/L)p
⇒ (W/L)p = 8.3
Note: If the 0.69 factor is replaced by 1 to account
for the fact that the pulse edges are not ideal, then
(W/L)n =5 (W/L)p =12
Ex: 17.6 With an additional 0.1 pF, C becomes C = 0.866 fF+10 fF = 10.866 fF
Thus,
10.866 tPHL =4.18× 0.866
Exercise 17–2
= 52.4 ps
tPLH =5.58×10.866
0.866 = 70.0 ps
4 VDD 7 3×0.5 0.52
VDD
= 2.01
Thus,
tP = 1(52.4+70.0) 2
= 61.2 ps
Ex:17.7 C =2×0.024+2×0.024+0.03+ 0.03 + 4 × 0.105 + 4 × 0.105 + 0.5 = 1.496 fF
= 2 tPHL =
4 − 1.8 + αnC
1.8
=
= 24.8 ps
k′n(W/L)nVDD 2.01 × 10 × 10−15
300×10−6 ×1.5×1.8
1.496 = 8.43 ps 0.866
4 VDD VDD t = αpC
Ex: 17.8
Refer to Example 17.3.
= 2.01
PLH k′ (W/L) V
(a) Cint = 2Cgd1 + 2Cgd2 + Cdb1 + Cdb2 = 2×0.024+2×0.024+0.03+0.03 = 0.156 fF
Cext =Cg3 +Cg4 +Cw
= 0.105 + 0.105 + 0.5
= 0.71 fF
(b) To reduce the extrinsic component of tP by a factor of 2, we need to scale (W/L)n and (W/L)p by a factor
S=2
(c) The original value of tP = 4.88 ps is
composed of an intrinsic component tP,int = tP × Cint
C
= 4.88 × 0.156 = 0.88 ps 0.866
tP = (4.88ps)
7 3|V| V 2 αp=2 − tp+ tp
p pDD
= 2.01 × 10 × 10−15 75×10−6 ×3×1.8
= 49.6 ps
tP = 1(tPHL +tPLH)
2
= 2 (24.8 + 49.6)
1
= 37.2 ps
Ex:17.5 tPHL =0.69RNC
12.5×1 (W/L)n
×103 ×20×10−15
50×10−12 = 0.69×
⇒ (W/L)n = 3.5 tPLH =0.69RPC

This component remains unchanged. The extrinsic component
tP,ext =4.88−0.88=4
is reduced by a factor of 2. Thus, tP becomes
4
tP =0.88+2=2.88ps
(d) Area=WnL+WpL = L(Wn + Wp)
By scaling Wn and Wp by a factor of 2, the area increases by a factor of 2.
Ex:17.9 L=0.18μm,n=1.5,p=3
(a) Four-inputNORgate:RefertoFig.17.8.
For NMOS transistors: W/L = n = 1.5 = 0.27 0.18
2.16 For PMOS transistors: W/L = 4p = 12 = 0.18
(b) Four-input NAND gate: Refer to Fig. 17.9. For NMOS transistors: W/L = 4n = 6 = 1.08
0.18
Area of NOR gate
= 4×0.18×0.27+4×0.18×2.16 = 1.7496 μm2
Area of NAND gate
= 4×0.18×1.08+4×0.18×0.54 = 1.1664
Ex: 17.12 P = f C V 2 dyn DD
= 250×106 ×80×10−15 ×1.22 = 28.8 μW
Ex:17.13P =fCV2 dyn DD
C decreases by a factor (0.13/0.5) and VDD decreasesfrom5Vto1.2V;thusforthesame f, the power dissipation will decrease by a factor
= 0.5 × 5 =66.8 0.13 1.2
Ex:17.14PDP=fCV2 t DD P
When f = fmax =1/2tP,
Exercise 17–3
PDP = 1CV2 2 DD
= 0.35 fJ
EDP = 1CV2 t
Ex: 17.15 Since dynamic power dissipation is 1
= 1 ×0.866×10−15 ×0.92 2
= 0.35×10−15×4.88×10−12
0.18 For PMOS transistors: W/L = p = 3 = 0.54
scaled by S2 and propagation delay is scaled by 1,hence,PDPisscaledby 1 × 1 = 1 = 1.
2 DD P =1.7×10−27 Js
Thus, NOR area
NAND area
= 1.7496 = 1.5 1.1664
Ex: 17.16 If VDD and Vt are kept constant, the entries in Table 17.1 that change are as follows:
1
Obviously, VD D and Vt do not scale by S anymore. They are kept constant!
tP ∝ αC :sinceαisafunctionof Vt ,then k′VDD VDD
α remains unchanged, while C is scaled by 1 , ′S
S S2 S S3 8 Thus, PDP decreases by a factor of 8.
Ex: 17.10 Refer to Fig. 17.9.
(a) Maximum charging current is the current supplied by the four identical PMOS transistors. Minimum charging current is the current supplied by one of the PMOS transistors. Thus, the ratio of maximum to minimum currents is 4.
(b) There is only one possible configuration for discharging a load capacitance, namely, when all 4 NMOS transistors are conducting. So, as far as capacitor discharge is concerned, the ratio is one.
Ex:17.11 P = fCV2 dyn DD
=1×109 ×0.866×10−15 ×0.92 = 0.70 μW
and k is scaled by S, therefore tP is scaled by 1/S = 1
S S2
Energy/Switching cycle, i.e., C V 2
, is scaled
1
by
S Pdyn ∝
DD
C V 2
DD and thus is scaled by
1/S 1/S2
= S
2tP
thus Pdyn increases.
The power density, i.e.,
S =S3 1/S2
Pdyn
devicearea
, is scaled by

Solutions to End-of-Chapter Problems
17.1 (a) Switch opens at time t = 0, thus
v O (0+) = 0 V. The capacitor then charges by a constant current I , thus
⇒vO(t)= Ct
(b) For I =1mAandC =10pFthetimet for
17.4
VDD
Chapter 17–1
It = CvO(t) I
Ronu
vO VDD
C VDD
PD 2
vO
vO toreach1Vcanbefoundas 1×10−3
0tPLH t Figure 1(a)
vO v VDD
O
0 tPHL t Figure 1(b)
1=10×10−12 t
⇒t =10−8 s=10ns
17.2 (a) Capacitor C is charged to 10 V and the switch closes at t = 0, thus
vO(0+) = 10 V
Capacitor C then discharges through R
exponentially with v O (∞) = 0
v O (t ) = 0 − (0 − 10) e−t /τ
⇒ vO(t) = 10e−t/τ
(b) ForC=100pFandR=1k􏱹,wehave τ = 100×10−12 ×1×103 = 100 ns
tPHL =0.69τ =0.69×100=69ns t f = 2.22τ = 2.2 × 100 = 220 ns
17.3 VOH =VDD
Att=0,vI goeslowandthetransistorturnsoff
instantly,thus
v O (0+) = VO L
Now capacitor C charges through R toward
vO(∞) = VDD, thus
v (t)=V −(V −V )e−t/τ
VDD
PU
Rond
C
VDD
2
VDD =VDD(1−e−tPLH/τ) ODDDDOL 2
To obtain tP L H , consider the situation in Fig. 1(a). Here, PD has just opened (at t = 0), leaving
vO =0Vatt=0+.CapacitorCthencharges through the “on” resistance of the pull-up switch, Ronu, toward VDD, thus
vO(t)=V∞ −(V∞ −V0+)e−t/τ =VDD −(VDD −0)e−t/τ
= VD D (1 − e−t /τ ) Att=tPLH,vO =VDD/2,thus
Att=tPLH,
vO = 1(VOL +VOH)= 1(VOL +VDD),thus
22
1(VOL +VDD)=VDD −(VDD −VOL)e−t/τ 2
⇒tPLH =0.69τ
ForR=10k􏱹andwewishtolimitτPLH to100 psthenthemaximumvaluethatCcanhaveis found from
0.69×C ×10×103 = 100×10−12 ⇒ C = 1.45 × 10−14 F
= 14.5 fF
⇒e−tPLH/τ =0.5 ⇒tPLH =τ ln2=0.69τ
ForC=20fF,Ronu =2k􏱹,then tPLH =0.69×20×10−15 ×2×103 = 27.6 ps
NextwedeterminetPHL byconsideringthe situation depicted in Fig. 1(b). Here, PU has just opened, leaving v O (0+) = VD D . Capacitor C then discharges through the on resistance of the pull-down switch, Rond, toward 0 V, thus vO(∞) = 0, thus

vO =0−(0−VDD)e−t/τ
= VDDe−t/τ
Att=tPHL,vO =VDD/2andweget
=0.69×0.1×10−12 ×2×103 = 138 ps
Finally,weobtainτP as
VDD =VDDe−tPHL/τ 22
Chapter 17–2
τP=1(tPLH+tPHL)
= 1(138+138)=138ps
2
17.6 (a) tP =1(tPLH +tPHL) 2
Since tP = 45 ps, then
tPLH +tPHL =90ps (1) Now, since Icharge is half Idischarge, then
tPLH =2tPHL (2) Using(1)togetherwith(2)yields
tPLH =60ps
tPHL =30ps
(b) Since the propagation delay is directly proportional to C, then the increase in propagation delay by 50%, when the capacitance is increased by 0.1 pF, indicates that the original total capacitance is 0.2 pF.
(c) The reduction of propagation delays by 40% when the load inverter is removed indicates that the load inverter was contributing 40% of the total capacitance found in (b), that is,
Cout =0.12pF Cload = 0.08 pF
17.7 See figure on next page.
(a) For a rising input, time to the full change of
output of second gate is
150+200+ 250 =475ps 2
(b) For a falling input, time to the full change of output of the second gate is
200 + 150 + 100 = 400 ps 2
The propagation delay is
tP =1(tPLH +tPHL) 2
= 1(200+150)=175ps 2
⇒tPHL =0.69τ
Here,
τ=CRond
= 20×10−15 ×1×103 = 20 ps Thus,
tPHL =0.69×20≃13.8ps ThepropagationdelaytP cannowbeobtainedas
tP = 1(tPLH +tPHL) 2
= 1(27.6+13.8)=20.7ps 2
17.5 (a) VOL =0V VO H = VD D = 1.2 V
NML =VIL −VOL = VDD −0 2
= 0.6 V
NM
H
= V
O H
− V
I H
= V
D D
− VDD 2
=0.6V
(b) Capacitor C discharges through Ron of PD ,
vO(0+)=VDD =1.2V
vO(∞) = 0 V
Thus,
vO(t) = VDDe−t/τ
⇒tPHL =0.69τ
= 0.69×0.1×10−12 ×2×103
= 138 ps
(c) Here the capacitor charges through Ron of PU toward VD D . Thus,
vO(0+) = 0, vO(∞) = VDD, vO(t)=VDD(1−e−t/τ)
Att =tPLH,vO(t)=VDD/2,thus tPLH =0.69τ

This figure belongs to Problem 17.7.
Chapter 17–3
vI
vO1
200 300
vO2
500
500 475
500
vI
vO1
vO2
0
0
0
100
400
400
600
600 575
600
700 800 900 825
1000 t
1000 t
1000 t
100 150 200 300
700 800
700 800
900
900
17.8 αn =2
− tn + tn 4 VDD VDD
17.9 αn =2 − tn + tn 4 VDD VDD
100 200 225
300 350 400
73VV2 73VV2
850
=2
= 2.44
7 3×0.35 0.35 2 4− 1.0 + 1.0
=2
7 3×0.35 0.35 2 4− 1.0 + 1.0
αnC k′n(W/L)nVDD
= 2.44
For a matched inverter, we have
tPHL =tPLH =tP FortP ≤25ps, tPHL ≤25ps But,
n
tPHL =
= 2.44×4×10−15
500×10−6 ×2×1.0 =9.8ps
αp = αn = 2.44
t
PLH
tPHL =
2.44×10×10−15 −12
= αpC
k′ (W/L) V
αnC
k′ (W/L)nVDD
p pDD
2.44×4×10−15
500 ×10−6 ×4×1.0
4 = 19.5 ps
tP = 1(tPHL +tPLH) 2
= 1(9.8+19.5)=14.7ps 2
500×10−6(W/L)n ×1.0 ≤ 25×10 (W/L)n ≥ 1.95
(W/L)p ≥ 7.8
=
12.5×1 12.5
17.10 RN = (W/L) = 1.5 =8.33k􏱹
tPHL =0.69CRN
n

= 0.69×10×10−15 ×8.33×103 = 57.5 ps
RP = 30×1 =30=10k􏱹 (W/L)p 3
tPLH =0.69CRP
= 0.69 × 10 × 10−15 × 10 × 103 = 69 ps
tP =1(57.5+69)=63.3ps 2
12.5 × 1
17.11 RN = 1 =12.5k􏱹
RP = 30 × 1 = 30 k􏱹 1
tPHL =0.69CRN
= 0.69×20×10−15 ×12.5×103 = 172.5 ps
tPLH =0.69CRP =0.69×20×10−15 ×30×103 = 414 ps
1
tP = 2(172.5+414)
= 293.3 ps
17.12 For
tPHL = tPLH = tP ≤ 15 ps we use
tPHL =0.69CRN
=0.69C×8×1.5×103 (W/L)n
0.69×5×10−15 × 36 (W/L)p
⇒ (W/L)p ≥ 8.28
×103 ≤ 15×10−12
Chapter 17–4
17.13 Refer to Example 17.2.
The method of average currents yields tPHL =15.0ps
The method of equivalent resistance yields tPHL =27.6ps
If the discrepancy is entirely due to the reduction incurrentduetovelocitysaturationintheNMOS transistor, then the factor by which the current decreases is 15.0/27.6 = 0.54.
ThevalueoftPLH doesnotchange(infactthere isaslightdecreaseduetovariousapproxi- mations). We may therefore conclude that the effect of velocity saturation is minimal in the PMOS transistor.
17.14 αn =2
=2 7−3×0.35+ 0.35 2
= 2.43
tPHL =
73VV2 − tn + tn
4 VDD VDD 4 1 1
αnC k′n(W/L)nVDD
12
(W/L)n
= 0.69 C × 24×1.5 ×103 (W/L)p
Thus,
×103 ≤ 15×10−12
= 2.43×10×10−15
470×10−6 ×1.5×1 = 34.4 ps
tPLH = αpC
k′ (W/L) V
p p DD Since |Vtp| = Vtn, we have
and thus obtain
0.69×5×10−15 ×
αp =αn =2.43
Thus,
t = 2.43×10×10−15 P L H 190 × 10−6 × 3 × 1
= 42.6 ps
tP = 1(34.4+42.6)=38.5ps
2
The theoretical maximum switching frequency is
f =1= 1 ≃13GHz max 2tP 2 × 38.5 × 10−12
W ⇒ L
Similarly,
≥ 2.76
tPLH =0.69C RP
n

17.15 C = 2.5×0.13+2.5×0.13+2 = 2.65 fF
73VV2 αn=2 − tn+ tn
4 VDD VDD =2 7−3×0.35+ 0.35 2
4 1.0 1.0 = 2.44
t = αnC PHL W
k′n L VDD n
65
= 500 × 260 = 1040 nm 125
C =2Cgd1 +2Cgd2 +Cdb1 +Cdb2 +Cg3 +Cg4 +Cw
where
Cgd1 =0.3×Wn =0.3×0.26=0.078fF
Cgd2 =0.3×Wp =0.3×1.04=0.312fF
Cdb1 =0.5×Wn =0.5×0.26=0.13fF
Cdb2 =0.5×Wp =0.5×1.04=0.52fF
Cg3 = 0.26×0.065×25+2×0.3×0.26 = 0.5785 fF
Cg4 = 1.04×0.065×25+2×0.3×1.04 = 2.314 fF
Thus,
C =2×0.078+2×0.312+0.13+0.52+ 0.5785+2.314+2
= 6.32 fF
3×0.35 0.35 2 =2 4− 1.0 + 1.0
Chapter 17–5
2.44 × 2.65 × 10−15 500×10−6 × 130 ×1.0
=
= 6.5 ps
αp =αn =2.44 tPLH = αpC
k′ W
p DD
V
Lp 73VV2
2.44 × 2.65 × 10−15 500 ×10−6 × 130 ×1.0
αn=2 − t+ t 4 VDD VDD
=
= 25.9 ps
7
4 65 1
= 2.44
tPHL = W
tP =2(6.5+25.9)=16.2ps
If the design is changed to a matched one, then
αnC
k′n L
2.44 × 6.32 × 10−15
VDD
Wp =4Wn =4×130=520nm C = 2.5×0.13+2.5×0.52+2 = 3.625 fF
αn =αp =2.44
tP H L = 2.44 × 3.625 × 10−15 500×10−6 × 130 ×1.0
=
n
500×10−6 ×
260 ×1.0 65
= 8.8 ps
65
2.44 × 3.625 × 10−15
× 1.0
Since the inverter is matched,
tPLH = tPHL = 7.7 ps
and
tP =7.7ps
The propagation delay increases by 50% if C is increased by 50%, that is, by 6.32/2 = 3.16 fF.
17.17 To reduce tP by 15 ps, we need to reduce the extrinsic part by 15 ps. Now the original value of the extrinsic part is
tP =30× 30 =22.5ps 30+10
A reduction by 15 ps requires the use of a scale factor S,
S=3
tP L H = 500 −6 520 × 10 ×
4 65 = 8.8 ps
1
tP = 2 (8.8 + 8.8) = 8.8 ps
17.16 Wn = 260 nm
Wp=μnCox ×Wn μpCox
= 7.7 ps

This is the factor by which (W/L)n and (W/L)p must be scaled. The inverter area will be increased by the same ratio, that is, 3.
17.18 (a) Examination of Eq. (17.19) reveals thattheNMOStransistors Q1 and Q3 contribute
Cn =2Cgd1 +Cdb1 +Cg3 (1) and the PMOS transistors Q and Q contribute
= 0.69 × 30 Wp/Wn
20.7 × 103 = W/W C
1
(c) tP = 2(tPHL +tPLH)
1 3 20.7×103 = 2 8.625 × 10 C + W /W C
n
n W
w
= 8.625 ⇒W =2.4
Chapter 17–6
× ×103C Q.E.D.
pn
Cp =2Cgd2 +Cdb2 +Cg4 (2)
The only difference in determining the corresponding capacitances in Eqs. (1) and (2) is thetransistorwidthW.Thuseachofthe components in Eq. (2) can be written as the corresponding component in Eq. (1) multiplied by (Wp/Wn). Overall, we can write
C =C Wp p nWn
and the total capacitance C can be expressed as C = Cn + Cp + Cw
ForWp =Wn,wehave tP =14.66×103C
tP =14.66×103 Cn
1+ Wp Wn
+Cw
(3)
24 pn
= 14.66 × 103(2Cn + Cw)
(d) In the matched case, we have
=C +C Wp +C
n
Thus,
(W/L)n
For (W/L)n = 1, we have
tPLH =tPHL
From the results in (b), the required ratio
(Wp/Wn) can be determined as
In this case, we have
C=Cn(1+2.4)+Cw=3.4Cn+Cw
and
tP =tPLH =8.625×103(3.4Cn +Cw) (4)
(e) (i) For Cw = 0, we have
Wp =Wn tP =29.32×103Cn
Wp = 2.4 Wn tP = 29.32×103Cn
Thus, in the case where C is entirely intrinsic, scaling does not affect tP . This is what we found inEq.(17.26).
(ii) For Cw ≫ Cn, we have
Wp =Wn tP =14.66×103Cw
Wp =2.4Wn tP =8.625×103Cw
Here C is entirely extrinsic, thus scaling the PMOS transistors has resulted in a decrease in tP .
We conclude that using a matched design reduces tP only when C is dominated by external capacitances. The matched design, of course, has the drawback of increased area.
20.7 Wp/Wn
1 +
(b) RN =12.5×1k􏱹
C = Cn
+ Cw
Q.E.D.
W Wn
W p n
p
RN =12.5k􏱹
Thus,
tPHL = 0.69CRN
= 0.69×12.5×103C = 8.625 × 103C
RP = 30×1 k􏱹 (W/L)p
Q.E.D.
= 30 k􏱹 (Wp/Wn)(W/L)n
For (W/L)n = 1, we have
RP = and
30 k􏱹 Wp/Wn
tP L H
= 0.69C RP

Chapter 17–7
17.19
Figure 1
Figure 1
equal to that of the corresponding transistor in the basic inverter, each transistor is sized at twice that of the inverter. Including the two inverters required to obtain the complemented variable, the area is
A = 2WnL +2WpL +4×2WnL +4×2WpL =10L(Wn +Wp)
= 10×28(56+84)
= 39,200
17.21 When the devices are sized as in Fig. 17.9, tPLH thatresultswhenonePMOStransistoris conducting (worst case) is
tPLH =0.69RpC
=0.69× Reff,P ×(W/L)p ×C
p
andtPHL isobtainedbynotingthattheequivalent
W/L of the discharge path is 4n/4 = n and thus
tPHL =0.69RNC
=0.69× Reff,N ×(W/L)n ×C n
For the case in which all p-channel devices have W/L = p and all n-channel devices have
W/L = n, we have
Reff,P ×(W/L)p
tPLH =0.69× p ×C
which is the same as in the first case. However,
Figure 1 shows the CMOS logic gate with the (W/L) ratios selected so that the worst-case tP L H andtPHL areequaltothecorrespondingvaluesof the basic inverter with (W/L)n = n and
(W/L)p = p. Observe that the worst case for discharging a capacitor occurs through the three seriestransistors QNA, QNC,and QND.Tomake the equivalent W/L for these three series transistors equal to n, we select each of their (W/L) ratios to be equal to 3n. Finally, for the discharge path (QN A, QN B) to have an equivalent W/L equal to n, we selected W/L of QNB equalto1.5n.
For the PUN, the worst-case charging path is that through QPB and one of QPC or QPD. Thus we selecteachofthesethreetransistorstohave
W/L = 2p. Finally, we selected W/L of QP A equal to p.
17.20
n = 56 , p = 84 28 28
Figure 1 shows the circuit with the W/L ratio of each of the eight transistors indicated. Observe that the worst-case situation for both charging and discharging is two transistors in series. To achieve an equivalent W/L ratio for each path

tPHL =0.69× Reff,N ×(W/L)n ×C n/4
= 90 × 9000 = 810,000 nm2
Thus circuit (a) required 1305900/810000 = 1.61 times the area of circuit (b).
17.23
Chapter 17–8
4 × R
which is four times the value obtained in the first
× (W/L) n
eff,N
L =0.90nm, Wn =180nm, Wp =360nm, n = 180/90, p = 360/90
(a) Circuit (a) uses a six-input NOR gate and one inverter.
The six-input NOR requires:
6 NMOS transistors each with W/L = n
and
6 PMOS transistors each with W/L = 6p
The inverter requires
1 NMOS transistor with W/L = n
and
1 PMOS transistor with W/L = p
Thus,
Area = 6Wn L + 6 × 6Wp L + Wn L + Wp L
=L(7Wn +37Wp)
= 90(7×180+37×360)
= 90 × 14, 510 = 1,305,900 nm2
(b) Circuit (b) uses two three-input NOR gates and one two-input NAND gate.
Each three-input NOR gate requires
3 NMOS transistors, each with W/L = n 3 PMOS transistors, each with W/L = 3p The two-input NAND gate requires
2 NMOS transistors, each with W/L = 2n 2 PMOS transistors, each with W/L = p Thus,
Area = 2 × 3 × Wn L + 2 × 3 × 3 × Wp L
+ 2 × 2 × Wn L + 2 × Wp L =L(10Wn +20Wp)
= 90(10×180+20×360)
=0.69× case.
n ×C
17.22
Figure 1
RefertothecircuitinFig.1.For QNA and QNB, (W/L) is equal to that of the NMOS transistor in the basic matched inverter. Thus,
kNA =kNB =k
ForQPA andQPB,(W/L)isequaltotwicethe value of the PMOS transistor of the basic matched inverter. Since for the matched inverter kp =kn =k,herewehave
kPA =kPB =2k (a)
1V
(V􏰒0.35) to (V􏰀0.35)
Figure 2
Figure 2 shows the circuit for the case input A is grounded. Note that Q N A will be cut-off and has

beeneliminated.SwitchingwilloccuratvI =V which will be near VDD/2. At this point, QN B and QPB will be in saturation and QP A will be in the triode region with a very small voltage VX across it. All transistors will be conducting the samecurrentID.ForQPA wecanwrite
I D = 2 k ( 1 − 0 . 3 5 ) V X − 1 V X2 2
or
ID = k(1.3 VX − VX2) (1) For QPB we can write
ID = 1 ×2k(1−VX −V −0.35)2 2
or
ID =k(0.65−VX −V)2 (2) Finally,forQNB wecanwrite
ID = 1k(V −0.35)2 (3) 2
Next, we solve Eqs. (2) and (3) together to obtain VX intermsofV.EquatingEqs.(2)and(3)gives
1
±√ (V−0.35)=0.65−VX −V 2
±0.707(V − 0.35) = 0.65 − VX − V (4) First try the solution corresponding to the + sign
V =0.53V
which is reasonable. The other solution gives −0.707(V − 0.35) = 0.65 − VX − V
⇒ VX = 0.403−0.293 V
For VX ≃ 0, this equation gives
V =1.37V
which is obviously impossible! Thus Eq. (5) is the solution that is physically meaningful. Next we substitute for VX . From Eq. (5) into Eq. (1) to obtain
ID = k 1.3(0.897 − 1.707 V) − k(0.897 − 1.707 V)2
= k(0.361 + 0.843 V − 2.914 V2) (6) Equating this value of ID to that in Eq. (3) gives (V − 0.35)2 = 2(0.361 + 0.843 V − 2.914 V2) ⇒ 6.83 V2 −2.39 V−0.6 = 0
⇒V =0.54V
This is a reasonable value: It is greater than
(VDD/2),whichisrequiredsinceQNB hasa conductance parameter k while Q P B has a parameter 2k. Of course, VSG of QPB is smaller thanthatofQNB becauseofVX.Thelatter, however, is small. It can be found by substituting for V = 0.54 in Eq. (5),
VX = 0.89−1.707×0.54 ≈ 0 V
(b) Figure 3 shows the circuit when the
corresponding input terminals are connected
Chapter 17–9
on the left-hand side of (4):
0.707(V −0.35)=0.65−VX −V ⇒ VX = 0.897−1.707 V SinceVX ≃0,thisequationgives
This figure belongs to Problem 17.23, part (b).
(5)
ID
vI
VDD
QPA (2k) QPB (2k)
vO
QNB (k)
V
Figure 3
VDD 􏰔 1 V
QPE (k)
VO 􏰔 (V􏰒0.35) to (V􏰀0.35) QNE (2k)
QNA (k)

together. The two parallel NMOS transistors can be replaced by an equivalent NMOS transistor QNE havingaW/L=2nandthusa transconductance parameter 2k. The two series PMOS transistors can be replaced by an equivalentPMOStransistorQPE havinga
W/L = (2p/2) = p and thus a transconductance parameter k. We are now ready to determine the threshold voltage, denoted V as before. Here, both QN E and QP E will be operating in saturation and conducting a current ID. Thus, for QPE we can write
1
ID= 2k(VDD−V−0.35)2 or
ID= 1k(0.65−V)2 (7) 2
tP =4xCR
= 4 × 6.32C R = 25.3C R
(b) Let the number of the inverters be n. Optimum performance is obtained when
xn=CL =1600 C
and
x =e=2.718
n= ln1600 =7.4≃7
ln e
Thus, we use 7 inverters. The actual scaling
factor required can be found from
x7 =1600
⇒ x = (1600)1/7 = 2.87
The value of tP realized will be tP =7×2.87CR
= 20.1C R
which represents a reduction in tP by about 20.6%. Thus adding three inverters reduces the delay by 20.6%.
17.25 (a) Refer to Fig. 17.11(c). By inspection we see that
tP =τ1 +τ2 +…+τn−1 +τn But,
τ1 =τ2 =…=τn−1 =xCR and
R
τn = xn−1 CL
Thus,
Chapter 17–10
and for Q N E , we can write ID = 1 ×2k(V −0.35)2
2
ID = k(V − 0.35)2
The value of V can be obtained by solving (7) and (8) together. Equating (7) and (8) gives
1(0.65 − V)2 = (V − 0.35)2 2
One solution is
1
⇒√ (0.65−V)=V−0.35 2
⇒V =0.47V
or
(8)
This is a reasonable, physically meaningful answer and thus there is no need to find the other solution. As expected, V is lower than (VD D /2), whichisaresultofthefactthatQNE hasalarger (twice as large) transconductance parameter than QPE.Thus,QNE needsasmallerVGS thatVSG of QPE to provide an equal ID.
17.24 (a) n = 4
Minimum delay is obtained when the scaling
factor x is given by xn = CL
1
tP =(n−1)xRC+xn−1RCL
∂x CC
Q.E.D. (1) (b) Differenting tP in Eq. (1) relative to x gives
∂tP =(n−1)RC−(n−1)RCL
∂x
Equating ∂tP
xn
to zero gives
xn = CL
(c) Differenting tP in Eq. (1) relative to n gives
Q.E.D. (2)
Here,
x4 = 1600C =1600 ∂tP =xRC− 1 (lnx)RCL
C ∂n xn−1 ⇒ x = 6.32

Equating ∂tP ∂n
becomes 0.694 × 10 = 6.94 mW. Since
Pdyn is proportional to f, reducing f by the same factor as the supply voltage (0.83) results in reducing the power dissipation further by a factor of 0.83, i.e.,
Additional savings in power = (1 − 0.83) × 6.94 = 1.16 mW
17.30 tPLH = 1.3 ns, tPHL = 1.2 ns tP =1(1.3+1.2)=1.25ns
Chapter 17–11
xn C CL
to zero gives
= ln x Q.E.D. (3)
To obtain the value of x for optimum performance, we combine the two optimality conditions in (2) and (3). Thus
ln x = 1
⇒x=e Q.E.D.
17.26 E=CV2
DD 2
= 3×10−15 ×1.22 = 4.32 fJ
For 5 × 106 inverters switched at f = 2.5 GHz, PD = 5×106 ×2.5×109 ×4.32×10−15
= 54 W
IDD=PD =54=45A VDD 1.2
17.27P =fCV2 dyn DD
= 2.5×109 ×5×10−15 ×1 = 12.5 μW
17.28
current of
Iav = 15 + 0 = 7.5 μA
2
Since Iav = 60 μA, then the average current corresponding to the dynamic power dissipation is52.5μA.Thus,
Pdyn =1.2×52.5×10−6 =63μW
But,
P =fCV2 dyn DD
Thus,
PDav = 1(0.1 + 0.2) = 0.15 mW 2
PDP =0.15×10−3 ×1.25×10−9 =0.188pJ
17.31 (a)
VDD
R
Figure 1
Figure 1 shows the circuit as the switch is opened (t = 0+). Capacitor C will charge through R, and its voltage will increase from the initial value of VOL to the high value VOH,
vO =vO(∞)−vO(∞)−vO(0+)e−t/τ
12.5 × 10−6 IDD = 1
􏰀
C vO 􏰒
=12.5μA
Each cycle, the inverter draws an average
To reach the 50% point, 1(VOH + VOL) the time −662 2
=VOH −(VOH −VOL)e−t/τ1 where
τ1 =CR
Q.E.D.
63×10 =250×10 ×1.2 ×C ⇒C=0.175pF
required,tPLH,canbefoundasfollows:
1(VOH +VOL)=VOH −(VOH −VOL)e−tPLH/τ1
2
(V −V )e−tPLH/τ1 = 1(V −V )
17.29 Since P isproportionaltoV2 ,
dyn DD OHOL 2OHOL
reducing the power supply from 1.2 V to 1.0 V reduces the power dissipation by a factor of
1.0 2
1.2 = 0.694. The power dissipation now
⇒tPLH =τ1 ln2
= 0.69τ1 = 0.69C R
Q.E.D.

(b) Figure 2(a) shows the circuit after the switch closes (t = 0+). At this instant the capacitor voltage in VO H . The capacitor then discharges and eventually reaches the low level VO L . To
v O (t ) = v O (∞) − v O (∞) − v O (0)e−t /τ1 =VOL −(VOL −VOH)e−t/τ2
when
τ2 =C(Ron ∥ R)≃CRon ThevalueoftPHL canbefoundfrom
vO(tPHL)= 1(VOH +VOL) 2
Chapter 17–12
ID D = VD D ≃ VD D R + Ron R
flows, and the power dissipation is
V2 PD=VDDIDD= DD
R
Now, if the inverter spends half the time in each state, the average power dissipation will be
1V2
P= DD Q.E.D.
2R
(e) ForVDD =1.8VandC =2pF,wehave
tP =0.35×2×10−12 R
If tP is to be smaller or equal to 1.4 ns, we must
have
0.35×2×10−12R≤1.4×10−9 ⇒R≤2.03k􏱹
If P istobesmallerorequalto2mW,wemust have
1 1.82 ×≤2
2R
where R is in k􏱹, thus
R ≥ 1.23 k􏱹
Thus, to satisfy both constraints, R must lie in the
range
1.23 k􏱹 ≤ R ≤ 2.03 k􏱹
Selecting R = 1.5 k􏱹 yields
tP = 0.35×2×10−12 ×1.5×103 = 1.04 ns
and
R//Ron
􏰀􏰀
determine τ
, we simplify the circuit to that in Fig.2(b).Usingthiscircuit,wecanexpressvO as
PHL
=VOL −(VOL −VOH)e−tPLH/τ2 ⇒tPHL =τ2 ln2
= 0.69τ2
= 0.69C Ron
Q.E.D. (c) tP = 1(tPLH +tPHL)
2
= 1(0.69CR+0.69CRon) 2
tP =1×0.69C(R+Ron) 2
Since Ron ≪ R,
tP ≃0.35CR Q.E.D.
(d) During the low-input state, the switch is open, the current is zero, and the power dissipation is zero.
During the high-input state, the switch is closed and a current
This figure belongs to Problem 17.31, part (b).
VDD R
V Ron
Ron C v DDR􏰀R C v
O on O
􏰒􏰒
(a)
(b)
Figure 2

1 1.82
P=2 1.5=1.08mW
Both values are within the design specifications. 17.32 (a) The currents decrease by a factor of
1.2 = 0.67; that is, the new current values are 1.8
0.67 of the old current values. However, the voltage swing is also reduced by the same factor. The result is that tP remains unchanged. The PDP will be reduced by a factor of 0.44.
Since the maximum operating frequency is proportional to 1/tP , it also will remain unchanged.
(b) If current is proportional to V 2 , the currents DD
become 0.672 of their old values. This together with the reduction of voltage swing by a factor of 0.67 will result in tP increasing by a factor of (1/0.67) and the maximum operating frequency being reduced by a factor of 0.67. The PDP decreases by a factor of 0.67.
1 E=2Ipeak×VDD×􏱺t
= 1 × 10 μA × 1.2 × 0.34 ns 2
= 2 fJ
P = f × E = 100×106 ×2×10−15 = 0.2 μW.
Chapter 17–13
0.33 ns
αC
17.34 (a) tP ∝ k′ V
0.67 ns

, and k is scaled by S, and 1
S = 2 ⇒ tP is scaled by 1 (tP decreases) 2
1 2tp
S =1 v S×1S
IS
DD
CandVDD arescaledby S;thustP isscaledby
1
17.33
1.2 0.8
0.4
The maximum operating speed is therefore is scaled by 2.
and
0.33 1 0.67
t
(ns)
Pdyn = fmaxCV2DD and thus is scaled by S×1× 1 = 1 =1(Pdyndecreases).
From Eq. (17.40), we have
area
= 1, i.e., remains unchanged.
1 1 PDPisscaledby S3 powerisscaledby S2 and
11
delay by and thus it is scaled by (PDP
S8 decreases).
(b) If VDD and Vtn remain unchanged while S = 2, we have
t = αC andα= p k′VDD
1 W V
peak 2 n ox L 2 tn
The time when the input reaches Vt is 0.4
2
n S2
S S2 S2 4
Power density = Pdyn and thus is scaled by
1
S2
I=μC DD−V 1
1 μA1.2 2
Ipeak = 2 ×500 V2 2 −0.4 =10μA
1.2 × 1 = 0.33 ns
The time when the input reaches VD D − Vt is
1.2−0.4×1=0.67ns 1.2
So the base of the triangle is
􏱺t = 0.67 − 0.33 = 0.34 ns
2 soα
7 3V V 2 − tn + tn
4 VDD remains unchanged and tP is scaled by
VDD

Chapter 17–14
1 ID = 1 × 0.4(1.4 − 0.44)2 = 0.184 mA S=1=1 2
S S2 4
The maximum operating speed is 1 and
therefore is scaled by 4.
ForVtn =0.4−10%=0.36V,wehave 1 2
2tP Pdyn = fmaxCV2DD and thus is scaled by
1
4× 2 ×1=2
Power density = Pdyn is thus scaled by area
ID = 2 × 0.4(1.4 − 0.36) = 0.216 mA
Thus, ID will range from 0.184 mA to 0.216 mA (i.e.,0.2±8%,mA).
(b) If the time for a 0.1-V change of the capacitor voltage is denoted T , then
IDT=C△V 11 C△V
2 =2=8 S2 4
T=
For ID =0.184mA,wehave
T = 100×10−15 ×0.1 = 54.3 ps 0.184 × 10−3
PDPisscaledby2× 1 = 1 42
17.35 ID = 1kn(VGS −Vtn)2 2
0.2 = 1 ×0.4(VGS −0.4)2 2
⇒VGS =1.4V
(a) ForVtn =0.4+10%=0.44V,wehave
For ID = 0.216 mA, we have 100×10−15 ×0.1
ID
T = 0.216 × 10−3 = 46.3 ps
Thus, the discharge time ranges from 46.3 ps to 54.3ps.