6.1 Design the circuit in Fig. 1 to obtain a dc voltage of +0.1v at each of the drains of Q1 and Q2 when 𝑣𝐺1 = 𝑣𝐺2 = 0𝑣. Operate all transistors at Vov= 0.15v and assume that for the process
technology in which the circuit is fabricated, Vin=0.4v and 𝜇𝑛𝐶𝑜𝑥 = 400 𝜇𝐴/𝑉2. Neglect channel- length modulation. Determine the values of R, RD, and W/L ratios of Q1, Q2, Q3, and Q4. What is the input common-mode voltage range for your design?
6.2 Figure 2 shows a MOS differential amplifier with the drain resistors RD implemented using diode-connected PMOS transistors, Q3 and Q4. Let Q1 and Q2 be matched, and Q3 and Q4 be matched.
(a) Find the differential half-circuit and use it to derive an expression for Ad in terms of gm1,2, gm3,4, ro1,2, and ro3,4.
(b) Neglecting the effect of the output resistances ro, find Ad in terms of 𝜇𝑛, 𝜇𝑝, (𝑊)1,2, (𝑊)3,4. 𝐿𝐿
(c) if 𝜇𝑛=4 𝜇𝑝 and all four transistors have the same channel length, find (W1,2/W3,4) that results in Ad=10 V/V.
6.3 Figure 3 shows a circuit for a differential amplifier with an active load. Here Q1 and Q2 form the differential pair, while the current source transistors Q4 and Q5 form the active loads for Q1 and Q2, respectively. The dc bias circuit that establishes an appropriate dc voltage at the drains of Q1 and Q2 is not shown. It is required to design the circuit to meet the following specifications:
(a) Differential gain Ad = 50 V/V.
(b) IREF=I=200 𝜇𝐴
(c) The dc voltage at the gates of 𝑄6 and 𝑄3 is +0.8V.
(d) The dc voltage at the gates of 𝑄7, 𝑄4, and 𝑄5 is -0.8V.
The technology available is specified as follows: 𝜇𝑛𝐶𝑜𝑥 = 2.5𝜇𝑝𝐶𝑜𝑥 = 250𝜇𝐴/𝑉2; Vtn = |Vtp|= 0.5V, VAn = |VAp| = 10 V. Specify the required value of R and the W/L rations for transistors. Also specify LD and |VGS| at which each transistor is operating. For dc bias calculations you may neglect channel-length modulation.