Ex: 7.1 Refer to Fig. 7.2(a) and 7.2(b).
Coordinates of point A: Vt and VDD; thus 0.4 V and 1.8 V. To determine the coordinates of point B, we use Eqs. (7.7) and (7.8) as follows:
√2kRV +1−1 VOV= nDDD
Av =−knVOVRD
−10=−0.4×10×VOV ×17.5
Thus,
VOV =0.14V
Exercise 7–1
VGS =Vt +VOV =0.4+0.14=0.54V √ 1W
B knRD 2×4×17.5×1.8+1−1
Thus,
V =V =0.213V DS B OV B
Thus, coordinates of B are 0.613 V and 0.213 V. At point C, the MOSFET is operating in the triode region, thus
1 iD=kn (vGSC−Vt)vDSC−2v2DSC
If v is very small, DS C
i ≃ k ( v − V ) v D nGSC tDSC
= 4(1.8 − 0.4)v DS C
=5.6v ,mA DS C
But
I = k′ V2 D 2n L OV
= 1 ×0.4×10×0.142 =0.04mA 2
RD = 17.5 k
VDS =VDD −RDID
= 1.8 − 17.5 × 0.04 = 1.1 V Ex: 7.3
Av =−ICRC VT
1×RC
−320=− 0.025 ⇒RC =8k
VC=VCC−ICRC
= 10 − 1 × 8 = 2 V
Since the collector voltage is allowed to decrease to +0.3 V, the largest negative swing allowed at the output is 2 − 0.3 = 1.7 V. The corresponding input signal amplitude can be found by dividing 1.7 V by the gain magnitude (320 V/V), resulting in5.3mV.
= 4×17.5 = 0.213 V
VGS B =Vt +VOV B =0.4+0.213=0.613V
and
VDD −vDSC
VDD
1.8
= 17.5 = 0.1 mA
iD =
Thus,v = 0.1 =0.018V=18mV,which
≃ R DD
R
DSC 5.6
Ex: 7.4
vi
5 V
R RD G
is indeed very small, as assumed.
Ex: 7.2 Refer to Example 7.1 and Fig. 7.4(a). Design 1:
VOV =0.2V, VGS =0.6V
ID = 0.8 mA
Now,
Av =−knVOVRD
Thus,
−10 = −0.4 × 10 × 0.2 × RD ⇒RD =12.5k
VDS =VDD −RDID
= 1.8 − 12.5 × 0.08 = 0.8 V Design 2:
RD = 17.5 k
vo
Refer to the solution of Example 7.3. From Eq. (7.47), Av ≡ vo = −gmRD (note that RL
vi
is absent).
Thus,
gmRD =25
Substituting for gm = knVOV , we have knVOV RD = 25
wherekn =1mA/V2,thus
VOV RD = 25
Next, consider the bias equation VGS =VDS =VDD −RDID Thus,
Vt+VOV =VDD−RDID
Substituting Vt = 0.7 V, VDD = 5 V, and
I =1kV2 =1×1×V2 =1V2 D 2nOV 2 OV 2OV
(1)
it = vt +i= vt +gmvt ro ro
∴Req=vt =ro∥1
Exercise 7–2
it
gm
Ex: 7.6
vGS
VDD
we obtain
0.7+V =5−1V2 R
iD
RD
OV2OVD
Equations (1) and (2) can be solved to obtain VOV =0.319V
and
RD =78.5k
The dc current ID can be now found as
(2)
v
v DS
gs
I=1kV2 =50.9μA D 2nOV
VGS
VDD = 5 V VGS = 2 V Vt =1V λ=0
To determine the required value of RG we use Eq. (7.48), again noting that RL is absent:
Rin= RG 1+gmRD
0.5M= RG 1+25
⇒RG =13M
Finally, the maximum allowable input signal vˆi
canbefoundasfollows:
vˆi= Vt = 0.7V =27mV
k′n =20μA/V2
RD =10k
|Av|+125+1 Ex: 7.5
I =1k′WV2 =200μA
W
= 20
L
(a)VGS =2V⇒VOV =1V
D 2nLOV
VDS =VDD −IDRD =+3V
0
D Req it vt
i
ro
(b)g =k′ WV =400μA/V=0.4mA/V m nLOV
(c)Av = vds =−gmRD =−4V/V vgs
(d)vgs =0.2sinωtV
vds=−0.8sinωtV
vDS =VDS +vds ⇒2.2V≤vDS ≤3.8V (e) Using Eq. (7.28), we obtain
G12
g1 m
S
i
iD = 2kn(VGS −Vt)
+kn(VGS −Vt)vgs + 1knv2gs
2 + 8 sin2 ωt, μA
iD =200+80sinωt
=[200+80sinωt+(4−4 cos2ωt)] = 204 + 80 sinωt − 4 cos2ωt, μA
ID shiftsby4μA.
Thus,
ˆi 2 ω 4 μ A
2HD=ˆ =80μA=0.05(5%)
iω Ex: 7.7
(a) gm = 2ID VOV
I =1k′WV2 =1×60×40×(1.5−1)2 D 2 n L OV 2
ID =300μA=0.3mA,VOV =0.5V gm = 2×0.3 =1.2mA/V
= 1 ×60× 16 × (1.6−1)2 2 0.8
Exercise 7–3
ID =216μA
2ID 2×216
gm = |VOV| = 1.6−1 =720μA/V = 0.72 mA/V
11 λ=0.04⇒VA′ = λ = 0.04 =25V/μm
ro = VA′ ×L = 25×0.8 =92.6k ID 0.216
Ex: 7.11
2ID VA 2VA gmro=V ×I =V
OV D OV V A′ × L = V A
0.5 2×12.5×0.8
ro = VA = 15 = 50 k ID 0.3
(b)I =0.5mA⇒g = 2μC WI
L=0.8μm⇒gmro = 0.2 = 100 V/V
Ex: 7.12
D m
n ox L D
3 = 2×60×40×0.5×10
g =1.55mA/V m
ro = VA = 15 = 30 k ID 0.5
Ex: 7.8
ID =0.1mA,gm =1mA/V,k′n =50μA/V2
2ID 2×0.1
gm = V ⇒ VOV = 1 = 0.2 V
OV
I=1k′WV2 ⇒W=2ID D2nLOV Lk′V2
∂i Given:gm = C
∂vBE iC=IC where IC = IS eVBE /VT
∂iC ISeVBE/VT IC ∂v = V =V
n OV
Thus,
gm=IC VT
Ex: 7.13
gm = IC VT
Ex: 7.14
BE T T
2 × 0.1 50 × 0.22
1000
Ex: 7.9
= 0.5mA =20mA/V 25 mV
=
= 100
W
gm = μnCox L VOV
IC =0.5mA(constant) β = 50 β = 200
g =IC =0.5mA m VT 25 mV
Samebiasconditions,sosameVOV andalsosame L and gm for both PMOS and NMOS.
μnCoxWn = μpCoxWp ⇒ μp = 0.4 = Wn μn Wp
= 20 mA/V = 20 mA/V IC 0.5 0.5
Wp Wn
IB = β = 50 = 200
= 10 μA = 2.5 μA
= 2.5 Ex: 7.10
I =1k′W(V −|V|)2 D2pLSG t
⇒
rπ = β =50=200 gm 20 20
= 2.5 k = 10 k
Ex:7.15
ic =βib =βvbe
rπ
= r vbe=gmvbe
Exercise 7–4
β=100 IC=1mA 1mA
β π
gm = 25mV =40mA/V
re=VT =αVT ≃25mV=25
ie =ib +βib =(β+1)ib =(β+1)vbe rπ
IE IC 1mA
β 100
rπ=g =40=2.5k
m
Ex: 7.16
gm = IC = 1mA =40mA/V VT 25 mV
Av = vce = −gmRC vbe
= −40 × 10
= −400 V/V
VC =VCC −ICRC
= 15 − 1 × 10 = 5 V
vC(t)=VC +vc(t)
=(VCC −ICRC)+Avvbe(t)
= (15 − 10) − 400 × 0.005 sinωt
= 5 − 2 sinωt
= vbe =vbe
rπ (β + 1) Ex: 7.18
B
ib = vbe −gmvbe re
1 =vbe r−gm
e
re
C
ib
g v m be
re
vbe
E
i(t)=I +i(t)
BBb
where
IB=IC =1mA=10μA
=v1−β be rπ/β+1 rπ
β 100 and ib(t) = gmvbe(t)
vbe πππ
β+1 β =vbe r −r =r
β
= 40×0.005sinωt 100
=2sinωt, μA
Thus,
iB(t) = 10 + 2 sinωt, μA
Ex: 7.17
Ex: 7.19
vi
10 V
CC1
ib
ic
RE 10 k
CC2
vo
RC 7.5 k 10 V
BC
vbe rp
E
bib
IE = 10−0.7 =0.93mA 10
VE =−0.1−0.7=−0.8V
(b)gm = IC = 0.99 ≃40mA/V
VT 0.025
V = −10 + I R CCCm
=−10+0.92×7.5=−3.1V Av = vo = αRC
vi re
wherere = 25mV =26.9
0.93 mA 0.99×7.5×103
ro = VA = 100 =101≃100k IC 0.99
(c)Rsig =2k RB =10k rπ =2.5k gm =40mA/V
RC =8k RL =8k ro =100k
Vy =Vπ ×Vy Vsig Vsig Vπ
Exercise 7–5
IC =αIE =0.99×0.93
= 0.92 mA β
100
rπ = g = 40 ≃ 2.5 k
Av= 26.9 =276.2V/V
Forvˆi =10mV, vˆo =276.2×10=2.76V
Ex: 7.20
=
RB ∥rπ × −gm (RC ∥RL ∥ro ) (RB ∥rπ ) + Rsig
10 ∥ 2.5 × −40(8 ∥ 8 ∥ 100) (10∥2.5)+2
10V
8 k
=
−0.5 × 40 × 3.846 = −77 V/V
Y
If ro is negelected, Vy Vsig
of 3.9%.
Ex: 7.21
= −80, for an error
X
10 k
I 1 mA
gm=2ID =2×0.25=2mA/V VOV 0.25
Rin = ∞
Avo =−gmRD =−2×20=−40V/V
Ro =RD =20k
RL 20 Av =AvoR +R =−40×20+20
Lo
=−20V/V
Gv =Av =−20V/V
vˆi = 0.1×2VOV = 0.2×2×0.25 = 0.05 V vˆo =0.05×20=1V
Z
IE =1mA
IC = 100 ×1=0.99mA
101
IB = 1 ×1=0.0099mA 101
(a)VC =10−8×0.99=2.08≃2.1V VB =−10×0.0099=−0.099≃−0.1V
This figure belongs to Exercise 7.20c.
Vsig
Rsig
XY
Vp Vy RBgmVp RL
Z
rp
ro
RC
Ex: 7.22
IC =0.5mA
gm = IC = 0.5mA =20mA/V
VT 0.025V
rπ = β = 100 = 5 k
gm 20 Rin =rπ =5k
Avo =−gmRC =−20×10=−200V/V Ro =RC =10k
R
ˆ ˆ
ib ie/(b1)
Exercise 7–6
sig
ˆ
ie vˆp re
vˆp re
v voRL +Ro = −66.7 V/V
5+10 5 ×−66.7
5 + 5
vˆsig
E
A=A RL =−200× 5
Re
Gv = Rin
Rin + Rsig
Av =
=−33.3V/V
vˆπ =5mV⇒vˆsig =2×5=10mV vˆo =10×33.3=0.33V
Although a larger fraction of the input signal reaches the amplifier input, linearity considerations cause the output signal to be in fact smaller than in the original design!
Ex: 7.23 Refer to the solution to Exercise 7.21. If vˆsig =0.2Vandwewishtokeepvˆgs =50mV,
then we need to connect a resistance Rs = 3 in gm
ForIC =0.5mAandβ=100,
re = VT = αVT = 0.99×25 ≃50
IE IC 0.5 rπ =(β+1)re ≃5k
thesourcelead.Thus,
Rs = 3 =1.5k
Gv =−β
RC∥RL
Rsig +(β+1)(re +Re)
For vˆsig = 100 mV, Rsig = 10 k and with vˆπ limited to 10 mV, the value of Re required can be found from
Re 10 100=101+ +
50 5
Rin =(β+1)(re +Re)=101×(50+350)
⇒ Re = 350 = 40.4 k
2 mA/V
Gv =Av =− RD∥RL
= −100
10 = −19.8 V/V 10+101×0.4
1 +Rs gm
Ex: 7.25
1 =Rsig =100 gm
⇒gm = 1 =10mA/V 0.1 k
But
2ID gm = VOV
vˆ π vˆ π ⇒ I D = 1 m A =(β+1)rRsig+vˆπ+r Re Rin
ee Gv=×gmRD R R Rin+Rsig
vˆsig =vˆπ 1+ e + sig Q.E.D =0.5×10×2=10V/V re rπ
20∥20 =−0.5+1.5 =−5V/V
vˆo =Gvvˆsig =5×0.2=1V(unchanged)
Ex: 7.24
From the following figure we see that vˆsig =ˆibRsig +vˆπ +ˆieRe
= ie Rsig +vˆπ +ˆieRe
β+1 0.2
Thus, 10= 2ID
Ex: 7.26
IC =1mA
re=VT ≃VT =25mV=25
IE IC 1 mA Rin =re =25
Avo =gmRC =40×5=200V/V Ro =RC =5k
1 =200 gm
⇒gm =5mA/V
But
W gm=k′n L VOV
Thus,
5=0.4× W ×0.25
5 5+5
25
= 25+5000 ×100 = 0.5 V/V
Ex: 7.27
A
v
= A RL voRL +Ro
L ⇒ L =50
Exercise 7–7
= 200 × Gv=R+R ×Av
= 100 V/V
Rin
in sig
I
W =1k′WV2
D
2 n L OV 12
Rin =re =50
⇒ IE = VT = 25 mV = 0.5 mA
=
2
= 0.625 mA
RL =1kto10k Correspondingly,
Gv= RL = RL
RL + Ro RL + 0.2
will range from
×0.4×50×0.25
re 50 IC ≃IE =0.5mA
Gv = RC∥RL re + Rsig
40 = RC∥RL (50 + 50)
RC∥RL =4k
Ex: 7.28 Refer to Fig. 7.41(c). Ro =100
Thus,
1 =100⇒gm =10mA/V gm
But
gm = 2ID
1 =0.83V/V 1+0.2
Gv =
to
Gv = 10 10+0.2
Ex: 7.30
=0.98V/V
VOV
ID = 10×0.25 =1.25mA
IC =5mA
re=VT ≃VT =25mV=5
IE IC 5 mA Rsig =10k RL =1k
Rin =(β+1)(re +RL) = 101 × (0.005 + 1)
= 101.5 k
Gvo =1V/V
Rsig Rout = re + β + 1
=5+ 10,000 =104 101
RL +re + Rsig β+1
= 1 = 0.91 V/V 1 + 0.104
Thus,
2
vˆo = vˆi × RL RL + Ro
= 1 ×
1
1 + 0.1
= 0.91 V
1
vˆ=vˆgm =1×0.1=91mV
gs i 1 +R gL
m
Ex: 7.29
Ro =200
0.1+1
Gv=RL =RL
RL +Rout
v =v re
π sig Rsig
R vˆsig=vˆπ 1+ L+
re
VS =−5+6.2×0.49=−1.96V
VD =5−6.2×0.49=+1.96V
R should be selected in the range of 1 M to G
10 M to have low current.
Ex: 7.33
I =0.5mA=1k′WV2 D 2 n L OV
⇒V2 =0.5×2=1 OV 1
⇒VOV =1V⇒VGS =1+1=2V = VD ⇒ RD = 5 − 2 = 6 k
0.5
⇒RD =6.2k(standardvalue).ForthisRD we
have to recalculate ID:
ID = 1 ×1×(VGS −1)2
2
= 1(VDD −RDID −1)2 2
re +RL + β+1
1000
vˆsig =5 1+ 5 +101×5 =1.1V/V
sig
Exercise 7–8
10,000
R
(β + 1) re
Correspondingly,
vˆo =Gv ×1.1=0.91×1.1=1V
Ex:7.31
I=1k′W(V −V)2 D 2 n L GS t
0.5= 1 ×1(VGS −1)2 2
⇒VGS =2V IfVt =1.5V,then
1
ID = 2 ×1×(2−1.5) =0.125mA
⇒ID =0.125−0.5=−0.75=−75% ID 0.5
Ex: 7.32
RD=VDD−VD =5−2=6k
2
(VGS =VD =VDD −RDID) 1 2 ∼
ID = 2(4−6.2ID) ⇒ ID =0.49mA VD = 5−6.2×0.49 = 1.96 V
ID →RD =6.2k
0.5
Ex: 7.34 Refer to Example 7.12. (a)Fordesign1,RE =3k,R1 =80k,and
1 W I = k′
1
V2 ⇒0.5= ×1×V2
R2 =40k.Thus,VBB =4V. V −V
D 2nLOV 2 OV ⇒VOV =1V
⇒VGS =VOV +Vt =1+1=2V ⇒VS =−2V
IE=BB BE RE+R1∥R2
VS − VSS
RS = I =
D →RS =6.2k
−2 − (−5) 0.5
=6k
β+1 Forthenominalcase,β=100and
IE = 4−0.7 =1.01≃1mA 3 + 40∥80
101 For β = 50,
IE = 4−0.7 =0.94mA DS D 3+40∥80
IfwechooseR =R =6.2k,thenI will
change slightly: 51
VGS =−VS =5−RS ID
2ID = (4 − 6.2ID)2
⇒ 38.44 ID2 − 51.6 ID2 + 16 = 0 ⇒ ID = 0.49 mA, 0.86 mA
ID =0.86resultsinVS >0orVS >VG,whichis not acceptable. Therefore ID = 0.49 mA and
ID = 1 × 1 × (VGS − 1)2. Also For β = 150, 2 4−0.7
40∥80 =1.04mA 151
IE =
Thus, IE varies over a range approximately 10%
3+
of the nominal value of 1 mA.
(b)Fordesign2,RE =3.3k,R1 =8k,and R2 =4k.Thus,VBB =4V.Forthenominal case, β = 100 and
IE = 4−0.7 =0.99≃1mA 3.3 + 4∥8
101
4 − 0.7 IE= 4∥8
3.3 + For β = 150,
IE = 4−0.7 =0.995mA 3.3 + 4∥8
151
Thus, IE varies over a range of 1.1% of the nominal value of 1 mA. Note that lowering
the resistances of the voltage divider considerably decreases the dependence on the value of β, a highly desirable result obtained at the expense
of increased current and hence power
dissipation.
Ex: 7.35 Refer to Fig. 7.53. Since the circuit is to be used as a common-base amplifier, we can dispense with RB altogether and ground the base; thus RB = 0. The circuit takes the form shown in the figure below.
To maintain active-mode operation at all times, the collector voltage should not be allowed
to fall below the value that causes the CBJ to become forward biased, namely, −0.4 V. Thus, the lowest possible dc voltage at the collector is −0.4 V + 2V = +1.6 V. Correspondingly,
RC = 10−1.6 ≃ 10−1.6 =8.4k IC 1 mA
Ex: 7.36 Refer to Fig. 7.54. For IE = 1 mA and VC =2.3V,
IE = VCC − VC RC
1= 10−2.3 RC
⇒RC =7.7k
Now, using Eq. (7.147), we obtain IE = VCC −VBE
RC+ RB β+1
Exercise 7–9
For β = 50,
= 0.984 mA
51
10−0.7
1= RB
7.7 +
101
10 V
RC
vo
⇒RB =162k
Selecting standard 5% resistors (Appendix J), we
use
RB =160k and RC =7.5k The resulting value of IE is found as
IE = 10−0.7 =1.02mA 7.5 + 160
101
and the collector voltage will be
VC =VCC −IERC =2.3V Ex: 7.37 Refer to Fig. 7.55(b).
VS =3.5andID =0.5mA; thus RS=VS=3.5=7k
ID 0.5
VDD=15VandVD=6V;thus
RD = VDD − VD = 15 − 6 = 18 k ID 0.5 mA
RE
vi
5V To establish IE = 1mA,
5−V IE= BE
RE
1 mA = 5 − 0.7 RE
⇒RE =4.3k
The voltage gain v
To obtain VOV , we use I =1kV2
vo iT
IC = gmRC, where gm = V
=
D 2nOV 0.5 = 1 × 4V 2
40 mA/V. To maximize the voltage gain, we
select RC as large as possible, consistent with obtaining a ±2-V signal swing at the collector.
2 OV ⇒VOV =0.5V
Thus,
VGS =Vt +VOV =1+0.5=1.5V
We now can obtain the dc voltage required at the gate,
VG =VS +VGS =3.5+1.5=5V
Using a current of 2 μA in the voltage divider, we
Ex: 7.40 Refer to Fig. 7.56(a). For VB = 5 V and 50-μA current through RB2, we have
RB2 = 5 V = 100 k 0.05 mA
The base current is
IB = IE ≃ 0.5 mA = 5 μA
The current through RB1 is
IR =IB +IR =5+50=55μA B1 B2
Since the voltage drop across RB1 is
VCC −VB =10V,thevalueofRB1 canbe foundfrom
10 V
RB1 = 0.055 μA = 182 k
The value of RE can be found from I =VB−VBE
have
RG2 = 5V =2.5M
Exercise 7–10
β+1 100
2 μA
The voltage drop across RG1 is 10 V, thus
RG1 = 10V =5M 2 μA
This completes the bias design. To obtain gm and ro, we use
gm=2ID =2×0.5=2mA/V VOV 0.5
ro = VA = 100 =200k ID 0.5
Ex: 7.38 Refer to Fig. 7.55(a) and (c) and to the values found in the solution to Exercise 7.37 above.
Rin =RG1∥RG2 =5∥2.5=1.67M Ro = RD∥ro = 18∥200 = 16.5 k
Gv =− Rin gm(ro∥RD∥RL) Rin + Rsig
=− 1.67 ×2×(200∥18∥20) 1.67 + 0.1
= −17.1 V/V
Ex: 7.39 To reduce vgs to half its value, the unbypassed Rs is given by
Rs = 1 gm
From the solution to Exercise 7.37 above, gm = 2 mA/V. Thus
Rs = 1 = 0.5 k 2
Neglecting ro, Gv is given by
R ∥R D L
1 +Rs gm
1.67 18∥20 = − 1.67 + 0.1 × 0.5 + 0.5
= −8.9 V/V
E RE
⇒R = 5−0.7 =8.6k
E 0.5
The value of RC can be found from
VC =VCC −ICRC
6 = 15−0.99×0.5×RC
RC ≃18k
This completes the bias design. The values of gm, rπ , and ro can be found as follows:
g = IC ≃ 0.5mA =20mA/V m VT 0.025 V
rπ = β = 100 =5k gm 20
ro = VA ≃ 100 = 200 k IC 0.5
Ex: 7.41 Refer to Fig. 7.56(b) and to the solution of Exercise 7.40 above.
Rin = RB1∥RB2∥rπ
= 182∥100∥5 = 4.64 k
Ro = RC∥ro = 18∥200 = 16.51 k
Gv = − Gv = −
Rin gm(RC∥RL∥ro) Rin + Rsig
4.64 × 20 × (18∥20∥200) 4.64+10
R
Gv =− in ×−
=−57.3V/V
Ex: 7.42 Refer to the solutions of Exercises 7.40 and 7.41 above. With Re included (i.e., left unbypassed), the input resistance becomes [refer to Fig. 7.57(b)]
Rin +Rsig
Rin = RB1∥RB2∥[(β + 1)(re + Re)] Thus,
10 = 182 ∥100 ∥[101(0.05 + Re )]
where we have substituted re = VT = IE
25
0.5 = 50 . The value of Re is found from the
equation above to be
Re = 67.7
The overall voltage gain can be found from
R R∥R Gv=−αin CL
= 50 × 20(8∥8) 50 + 50
= 40 V/V
vˆo =40vˆsig =40×10mV=0.4V
Ex: 7.44 Refer to Fig. 7.59. Consider first
the bias design of the circuit in Fig. 7.59(a). Since the required IE = 1 mA, the base current
IB = IE = 1 ≃0.01mA.Foradcvoltage β+1 101
Exercise 7–11
Rin +Rsig re +Re Gv =−0.99× 10
drop across RB of 1 V, we obtain 1V
18∥20
10 + 10 0.05 + 0.0677
RB = 0.01mA =100k Theresultisabasevoltageof–1Vandanemitter
= −39.8 V/V
Ex: 7.43 Refer to Fig. 7.58.
IC =αIE ≃IE =0.5mA
VC =VCC −RCIC
ForVC =1V andVCC =5V,wehave vo 1=5−RC ×0.5 vi ⇒RC =8k Gv
voltage of –1.7 V. The required value of RE can now be determined as
RE = −1.7−(−5) = 3.3 =3.3k IE 1 mA
Rin = RB∥[(β + 1)[re + (RE∥ro∥RL)] wherero = VA = 100V =100k
IC 1 mA
Rin =100∥(100+1)[0.025+(3.3∥100∥1)]
Rin =50=re∥RE ≃re r = 50 = VT
e IE ⇒IE =0.5mA
= 44.3 k
vi = vsig
= ≡
Rin = Rin + Rsig
44.3 = 0.469 V/V 44.3 + 50
RE∥ro∥RL
re + (RE∥ro∥RL)
= 0.968 V/V
vo = 0.469 × 0.968 = 0.454 V/V
To obtain the required value of RE , we note that thevoltagedropacrossitis(VEE −VBE)=4.3V. Thus,
4.3
RE = 0.5 =8.6k
Gv = Rin gm(RC∥RL) Rin + Rsig
R∥+R β+1
v sig
Rout=ro∥RE∥re+ B sig
= 100∥3.3∥ = 320
0.025 +
100 ∥50 101
7.1 Coordinates of point A: v = V = 0.5 V GS t
The lowest instantaneous voltage allowed at the
outputisVDS B =0.22V.Thusthemaximum allowable negative signal swing at the output is VDSQ −0.22=1−0.22=0.78V.The corresponding peak input signal is
0.78V 0.78
vˆgs = |Av| = 40 =19.5mV
7.4 From Eq. (7.18):
V −V
|Avmax|=DD OVB VOV B /2
andvDS =VDD =5V.
To obtain the coordinates of point B, we first use
Eq.(7.6)todetermineV as GS B
√2knRDVDD +1−1 VGSB =Vt + knRD
√
Thus,
1 2 1 2
Now, using Eq. (7.15) at point B, we have
A=−kVR v B n OV B D
Thus,
−14=−knRD×0.25
⇒knRD =56
To obtain a gain of −12 V/V at point Q:
−12=−kRV n D OV Q
= −56VOV Q
IDB=2knVDSB=2×5×0.5 =0.625mA The value of RD required can now be found as
Chapter 7–1
2×10×20×5+1−1 10 × 20
= 0.5 + =0.5+0.22=0.72V
The vertical coordinate of point B is VDS B ,
V =V −V=V =0.22V DS B GS B t OV B
7.2 V = V = 0.5 V DS B OV B
2−V OV B
14=
⇒ V = 0.25 V
OV B
VOV B/2
V −V R=DD DSB
D
ID =0.625=7.2k
B
5 − 0.5
If the transistor is replaced with another having
twice the value of k , then I will be twice as nDB
large and the required value of RD will be half that used before, that is, 3.6 k.
7.3 BiaspointQ:VOV =0.2VandVDS =1V. I =1kV2
Thus,
V =12=0.214V
OVQ 56
ToobtaintherequiredV ,weuseEq.(7.17),
DQ 2nOV 1
VOV Q/2
V −V Av=−DD DSQ
DS Q
= 2 × 10 × 0.04 = 0.2 mA
−12=−2−VDS Q 0.214/2
VDD −VDS RD= I
DQ
5−1
= 0.2 =20k
⇒VDSQ =0.714V 7.5
Coordinates of point B: Equation (7.6):
√2kRV +1−1 VGSB =Vt + n D DD
V DD
iD
vDS
vgs VGS
= 0.5 +
knRD √
2×10×20×5+1−1 10 × 20
RD
= 0.5+0.22 = 0.72 V Equations (7.7) and (7.8):
√2kRV +1−1 VDSB = n D DD
=0.22V
= −10 × 20 × 0.2 = −40 V/V
knRD Av =−knRDVOV
V =5V, k′ W =1mA DD nLV2
RD =24k, Vt =1V
(a) Endpoints of saturation transfer segment:
PointAoccursatVGS =Vt =1V,iD =0
Point A = (1 V,5 V) (VGS,VDS )
PointBoccursatsat/triodeboundary(VGD =Vt )
VGD =1V⇒VGS −[5−iDRD]=1 1
VGS −5+ 2 (1)(24)[VGS −1]2 −1=0 12V2 −23V +6=0
7.6 RD =20k k′n =200μA/V2 VRD = 1.5 V
VGS =0.7V
Av =−10V/V Av =−knVOVRD
V =I R = 1k V2 R RD DD 2nOVD
Av =−2=−10 VRD VOV 1.5
∴VOV =0.30V
Vt = VGS−VOV = 0.40 V kn = Av = −10
Chapter 7–2
GS GS VGS =1.605V
iD =0.183mA VDS =0.608V
Point B = (+1.61 V,0.61 V)
(b) For VOV = VGS−Vt = 0.5 V, we have VGS =1.5V
ID = 1kn(VGS −Vt)2 2
= 1 × 1(1.5 − 1)2 2
I =0.125mA V =+2.00V D DS
PointQ=(1.50V,2.00V) Av =−knVOVRD =−12V/V
(c) From part (a) above, the maximum instantaneous input signal while the transistor remains in saturation is 1.61 V and the corresponding output voltage is 0.61 V. Thus, the maximum amplitude of input sine wave is
(1.61 − 1.5) = 0.11 V. That is, vGS ranges from 1.5−0.11=1.39V,atwhich
VOVRD
−0.3×20
= 1.67 mA/V2
k =k′ W =1.67mA/V2
nnL
∴ W = 8.33 L
7.7 At sat/triode boundary v = V + vˆ
GS B GS gs
v =V −vˆ DS B DS
o
vˆo = max downward amplitude , we get v = v − V = V + vˆ o − V
DSB GSB t GS |Av| t
=VDS −vˆo
VOV + vˆo = VDS − vˆo | Av |
VDS − VOV
vˆo = 1+ 1 (1)
1 |Av|
iD = 2 ×1×(1.39−1)2 =0.076mA and
vDS = 5−0.076×24 = 3.175 V andvGS =1.5+0.11=1.61Vatwhich
vDS = 0.61 V.
Thus, the large-signal gain is
0.61 − 3.175 = −11.7 V/V 1.61 − 1.39
whose magnitude is slightly less (−2.5%) than the incremental or small-signal gain (−12 V/V). This is an indication that the transfer characteristic is not a straight line.
ForVDD =5V,VOV =0.5V,and k′ W =1mA/V2,weuse
nL
−2(VDD −VDS) Av= V
OV
and Eq. (1) to obtain
VDS
Av
vˆo
vˆi
1V
−16
471 mV
29.4 mV
1.5 V
−14
933 mV
66.7 mV
2V
−12
1385 mV
115 mV
2.5 V
−10
1818 mV
182 mV
ForVDS =1V, Av =−16=−knVOVRD ∴RD =32k
IDRD = 4 V, ID = 0.125 mA
Substituting VDD = 5 V, rearranging the equation to obtain a quadratic equation in knRD, and solving the resulting quadratic equation
results in
knRD = 213.7
which can be substituted into Eq. (2) to
obtain
VDS B = 0.212 V
The value of VDS at the bias point can now be
7.8
vDS
VDSQ VDSB
found from Eq. (1) as
V =0.212+0.5=0.712V
Q
VDSB
To obtain maximum gain while allowing for a −0.5-V signal swing at the output, we bias the MOSFET at point Q where
DS Q
(b) The gain achieved can be found as Av =−knRDVOV
= −213.7 × 0.2 = −42.7 V/V
Chapter 7–3
VOV
Vt
0.5 V B
vˆgs
vGS
vˆgs = 0.5 = 0.5 =11.7mV | Av | 42.7
(c) ID = 100 μA V −V
RD = DD DS Q ID
= 5−0.712 = 42.88 k 0.1
(d) kn = 213.7 = 4.98 mA/V2 42.88
W = 4.98 = 24.9 L 0.2
V =V +0.5V DS Q DS B
(1)
(2)
(3)
7.9
as indicated in the figure above. Now, V
DS B
given by Eq. (7.8) [together with Eq. (7.7)],
VDD
Q2
vO
Q1 iD
[VDD −vO −Vt ]2 [vI−Vt]2
is
√2kRV +1−1 VDSB = n D DD
knRD From the figure we see that
V = V + vˆ DS B OV
gs
whereVOV =0.2V(given)and
vˆgs = 0.5 V |Av|
= 0.5 knRDVOV
Thus,
vI
=
0.5 knRD × 0.2
= 2.5 knRD
VDSB =0.2+k R
given Vt1 = Vt2 = Vt
1 W ForQ2,iD = 2k′n L
2.5 nD2
Substituting for V from Eq. (2), we obtain DSB
√2knRDVDD+1−1=0.2+ 2.5 knRD knRD
W
2
ForVt ≤vI ≤vO +Vt,
1 ForQ1,iD= k′n
L 1
equateiD1 andiD2
max+vO =5−4.5=0.5V max−vO =4.5−0.3=4.2V Similarly →
W
[VDD −vO +Vt ]2
W
= L [vI−Vt]2
1 [VDD−vO−Vt]= (W/L)1 ·[vI−Vt]
v=V −V+V (W/L)1 O DD t t(W/L)2
−v ( W/L )1 I (W/L)2
Chapter 7–4
L
2
IC
(mA)
VCE
(V)
Av (V/V)
POS vO (V)
Neg vO (V)
0.5
4.5
–20
0.5
4.2
1.0
4.0
–40
1.0
3.7
2.5
2.5
–100
2.5
2.2
4.0
1.0
–160
4.0
0.7
4.5
0.5
–180
4.5
0.2
(W/L)2
50
√
For (W/L)1 =0.5= 10, (W/L)2 5
7.12
0.5
√
Av =− 10=−3.16V/V
7.10 Refer to Fig. 7.6. Av =−VCC −VCE
VT
=−5−1 =−160V/V 0.025
ThetransistorenterssaturationwhenvCE ≤0.3V, thus the maximum allowable output voltage swing is 1 − 0.3 = 0.7 V. The corresponding maximum input signal permitted vˆ be is
vˆbe = 0.7 V = 0.7 = 4.4 mV |Av| 160
ICRC VCC −VCE Av=−V =− V
TT
7.11
On the verge of satuation
VCE −vˆce =0.3V
For linear operation, vce = Av vbe VCE −|Avvˆbe|=0.3
(5−ICRC )−|Av|×5×10 But
|Av|=ICRC VT
Thus,
ICRC =|Av|VT
and
5−|Av|VT −|Av|×5×10−3 =0.3 | Av |( 0.025 + 0.005 ) = 5 − 0.3
| Av | = 156.67. Note AV is negative. ∴Av =−156.67V/V
5 V IRC
C 1 k vO
−3
= 0.3
vbe VBE
ForIC =0.5mA,wehave
Av =−ICRC =− 0.5 =−20V/V
VT
VCE =VCC −ICRC
= 5 − 0.5 = 4.5 V
0.025
Now we can find the dc collector voltage. Referring to the sketch of the output voltage, we see that
VCE = 0.3+|Av|0.005 = 1.08 V
7.13 To determine | Av max |, we use Eq. (7.23),
|Avmax|= VCC −0.3 VT
Then, for VCE = VCC we obtain 2
The resulting gain will be
VCC − VCE Av=− VT
which results in VCC of
VCC =VCE +|Av|VT
Thus the minimum required VCC will be VCCmin =VCEsat +P+|Av|VT
but we have to make sure that the amplifier can support a positive peak amplitude of P, that is,
Chapter 7–5
VCC − VCC 2
| Av | = = VCC
2VT
Finally, if a negative-going output signal swing of 0.4 is required, the transistor must be biased at VCE = 0.4 + 0.3 = 0.7 V and the gain achieved becomes
|Av|= VCC −0.7. VT
The results are as follows:
|A|V≥P VT vT
In the results obtained, tabulated below, VCEsat = 0.3 V and VCC is the nearest 0.5 V to VCCmin.
Case
Av (V/V)
P (V)
| Av|VT
VCC min
VCC
a
−20
0.2
0.5
1.0
1.0
b
−50
0.5
1.25
2.05
2.5
c
−100
0.5
2.5
3.3
3.5
d
−100
1.0
2.5
3.8
4.0
e
−200
1.0
5.0
6.3
6.5
f
−500
1.0
12.5
13.8
14.0
g
−500
2.0
12.5
14.8
15.0
VCC
1.0
1.5
2.0
3.0 (V)
VCC − 0.3
0.7
1.2
1.7
2.7 (V)
|Avmax|
28
48
68
108 (V/V)
VCC /2
0.5
0.75
1.0
1.5 (V)
|Av|
20
30
40
60 (V/V)
VCC − 0.7
0.3
0.8
1.3
2.3 (V)
|Av|
12
32
52
92 (V/V)
7.14 To obtain an output signal of peak amplitude P volts and maximum gain, we bias the transistor at
7.15 See figure below
Av =−ICRC =−0.3×5 =−60V/V
VT 0.025
7.16 (a) See figure on next page
(b) See figure on next page
Note that in part (b) the graph is shifted right by
VCE = VCEsat + P
This figure belongs to Problem 7.15.
5 V
10 k
vI 0.3 mA
+5 V and up by +5 V.
vO 10 k
Thévenin
vI
2.5 V
5 k
0.3 mA
vO
This figure belongs to Problem 7.16(a).
Chapter 7–6
vO 0.5 V
vI
B
0
vI 0.3 V
5 V
vO RC
5 V
A
This figure belongs to Problem 7.16(b).
vI
7.17 iC = ISevBE/VT
5 V
vO RC
vO 5V
4.7 V
0
B
0
A
4.5 V 5 V vI
v
Substituting ICRC = VCC − VCE, we obtain Av =−(VCC −VCE)/VT Q.E.D
VCC−VCE 1 + VA + VCE
ForVCC =5V,VCE =3V,andVA =100V, 5−3
1 + V
CE
VA
I =IeVBE/VT 1+ CE
C S
vCE =VCC −RCiC
VCE =VCC −RCIC dv
V 1
= −RCIS 1 + CE eVBE/VT
VA VT
dv 1 −RC IS eVBE /VT CE
dvBE VA
VA
Av= CE
dvBE vBE=VBE, vCE=VCE
Av (without the Early effect) = − 0.025 = −80 V/V
(with the Early effect) = = −78.5 V/V
−80 2
100+3
Av
1+
1I1 V−V5−2
=−R I −R C A 7.18 I = CC CE = =3mA
CCVCVCEVv CR1 T1+A C
Thus,
Av =
VA
−IC RC /VT Q.E.D
1+ ICRC VA +VCE
Av=−VCC−VCE=−3 =−120V/V VT 0.025
Using the small-signal voltage gain with △vBE =+5mV,wehave
△vO =Av ×△vBE =−120×5mV=−0.6V
Using the exponential characteristic yields
iC = ICevBE/VT
= 3×e5/25 = 3.66 mA
Thus, △iC = 0.66 mA and
△vO =−△iCRC
= −0.66 × 1 = −0.66 V
Repeatingfor△vBE =−5mVas follows.
Using the small-signal voltage gain:
△vO = −120 × −5 = +0.6 V
Using the exponential characteristic:
iC = ICevBE/VT
= 3×e−5/25 = 2.46 mA
Thus,△iC =2.46−3=−0.54mAand △vO =0.54×1=0.54V
Thus, using the small-signal approximation underestimates |△vO| for positive △vBE by about 10% and overestimates |△vO| for negative △vBE by about 10%.
7.19 (a) Using Eq. (7.23) yields VCC −0.3 3−0.3
(e) Assuming linear operation around the bias point, we obtain
vce=Av×vbe =−60×5sinωt=−300sinωt, mV =−0.3sinωt,V
(f)ic=−vce=0.1sinωt,mA RC
(g)IB = IC = 0.5mA =0.005mA β 100
ib=ic =0.1sinωt=0.001sinωt,mA β 100
(h) Small-signal input resistance ≡ vˆbe vˆb
Chapter 7–7
5 mV
= 0.001mA =5k
(i)
vBE VBE
0
vCE VCE
0
5 mV
vbe
1.8 V
1.2 V
0.673 V
t
1.5 V
t
0.5 mA
△vBE
△vO (exp)
△vO (linear)
+5 mV
−660 mV
−600 mV
−5 mV
+540 mV
+600 mV
v
ce
|Avmax|= V = 0.025 =108V/V
T iC
0.3 V
0.1 mA
(b)UsingEq.(7.22)withAv =−60yields −60=−VCC −VCE =−3−VCE
VT 0.025 ⇒VCE =1.5V
(c)IC =0.5mA
ICRC =VCC −VCE =3−1.5=1.5V
1.5
RC = 0.5 = 3 k
(d)IC =ISeVBE/VT 0.5×10−3 =10−15eVBE/0.025
⇒ VBE = 0.673 V
(mA)
IC
0
iB (A)
0.6 mA 0.4 mA
I 1A B
0
ib
t
6 A 5A
4 A
t
7.20 Av =− But
I
C RC
VT
Eq.ofL1 ⇒iC =IC(1+vCE/VA) = 5 ( 1 + v CE /100 )
= 5 + 0.05vCE
A≡△vO =−△iCRC=−gR v△v△v mC
Thus,
V−v
Chapter 7–8
BE
BE
Loadline⇒iC = CC
CE =10−vCE
gm =IC/VT
For a transistor biased at IC = 0.5 mA, we have
gm = 0.5 =20mA/V 0.025
7.21
RC ∴10−vCE =5+0.05vCE
VCE =vCE =4.76V
IC =iC =10−vCE =5.24mA
Now for a signal of 30-μA peak superimposed on IB = 50 μA, the operating point moves along the load line between points N and M. To obtain the coordinates of point M, we solve the load line and line L2 to find the intersection M, and the load line and line L3 to find N:
For point M:
iC =8+(8/100)vCE andiC =10−vCE
∴i =8.15mA, v =1.85V C M CE M
For point N:
iC =2+0.02vCE andiC =10−vCE
v =7.84V, i =2.16mA
Peak-to-peakvC swing=4−1=3V For point Q at VCC/2 = 2.5 V, we obtain VCE =2.5V, IC =2.5mA
IB =25μA
IB = VBB −0.7 =25μA RB
⇒VBB =IBRB +0.7=2.5+0.7=3.2V
7.22 See the graphical construction that follows. For this circuit:
CE N
C N
VCC =10V,
RC =1k,
IB = 50 μA (dc bias),
AtvCE =0,iC =βiB
∴IC =50×100
= 5 mA (dc bias)
β=100,
VA =100V,
Thus the collector current varies as follows:
Given the base bias current of 50 mA, the dc or
bias point of the collector current IC , and voltage VCE can be found from the intersection of the load line and the transistor line L1 of iB = 50 μA. Specifically:
8.15 mA 5.24 mA 2.16 mA
2.91 mA
i 5.99 mA, peak to peak
3.08 mA
And the collector voltage varies as follows:
gm = knVOV = 10 × 0.2 = 2 mA/V which is an identical result.
7.25(a)I=1k(V −V2) D 2 n GS t
= 1 × 5(0.6 − 0.4)2 = 0.1 mA 2
VDS = VDD −IDRD = 1.8−0.1×10 = 0.8 V (b) gm = knVOV = 5 × 0.2 = 1 mA/V
(c)Av =−gmRD =−1×10=−10V/V
7.84 V 4.76 V 1.85 V
3.08 V
v 5.99 V
2.91 V
Chapter 7–9
7.23 Substituting vgs = Vgs sin ωt in Eq. (7.28), iD = 1kn(VGS −Vt)2 +kn(VGS −Vt)Vgs sinωt
2 −11
(d)λ=0.1V , VA= =10V λ
VA 10
1 ro = = = 100 k
= 2kn(VGS −Vt)2 +kn(VGS −Vt)Vgs sinωt ID 0.1
Av =−gm(RD∥ro)
1
+ k V2 sin2ωt
2ngs
+1k V2 (1 − 1 cos 2 ωt) 2 n gs 2 2
Second-harmonic distortion 1k V2
=−1(10∥100)=−9.1V/V
7.26 Av =−10=−gmRD =−gm ×20
gm = 0.5 mA/V
To allow for a −0.2-V signal swing at the drain while maintaining saturation-region operation, the minimum voltage at the drain must be at least equal to VOV . Thus
VDS =0.2+VOV Since
VDD − VDS Av=− 1
2VOV
−10=−1.8−0.2−VOV 0.5VOV
⇒VOV =0.27V
ThevalueofID canbefoundfrom
gm = 2ID VOV
0.5= 2×ID 0.27
⇒ID =0.067mA
The required value of kn can be found from
I=1kV2 D 2nOV
0.067 = 1kn ×0.272 2
⇒ kn = 1.83 mA/V2
Since k′n = 0.2 mA/V2, the W/L ratio must be
W = kn = 1.83 = 9.14 L k′n 0.2
4 n gs
=k(V −V)V ×100
n GS t =1Vgs ×100
4 VOV
gs
Q.E.D
For Vgs = 10 mV, to keep the second-harmonic distortion to less than 1%, the minimum overdrive voltage required is
VOV = 1 × 0.01×100 =0.25V 4 1
7.24I =1kV2 =1×10×0.22=0.2mA D 2nOV 2
vGS =VGS +vgs, wherevgs =0.02V vOV = 0.2+0.02 = 0.22 V
iD = 1knv2OV = 1 ×10×0.222 =0.242mA 22
Thus,
id =0.242−0.2=0.042mA
For
vgs =−0.02V, vOV =0.2−0.02=0.18V
iD = 1knv2OV = 1 × 10 × 0.182 = 0.162 mA 2 2
Thus,
id = 0.2−0.162 = 0.038 mA
Thus, an estimate of gm can be obtained as follows:
gm = 0.042 + 0.038 = 2 mA/V 0.04
Alternatively, using Eq. (7.33), we can write
Finally,
VGS = Vt +VOV = 0.4+0.27 = 0.67 V
7.27 Av = −gm RD
Upon substituting for gm from Eq. (7.42), we can
VOV = mvˆi = 15×20 = 0.3 V
VDS = 0.3+0.02+2×2.5×(0.02/0.3)
1 + 2(0.02/0.3)
Chapter 7–10
= 0.576 V
2(VDD − VDS )
= −
2(2.5 − 0.576) 0.3
Av = − V OV
write
Av =−2IDRD
= −12.82 V/V
VOV
= −2(VDD − VDS)
(1)
vˆo =|Av|vˆi =12.82×20mV=0.256V
To operate at ID = 200 μA = 0.2 mA,
RD = 2.5−0.576 =9.62k 0.2
ID=1knV2 2OV
1 2 0.2= 2kn ×0.3
⇒ kn = 4.44 mA/V2
The required W/L ratio can now be found as
W = k n = 4.44 = 44.4 L k ′n 0.1
7.28 Given μn = 500 cm2/V·s,
μp =250cm2/V·s,andCox =0.4fF/μm2, k′n = μnCox = 20 μA/V2
k′p = 10 μA/V2
See table below.
Q.E.D vGSmax =VGS +vˆi =Vt +VOV +vˆi
VOV
v =V −|A|vˆ
DSmin DS vi
To just maintain saturation-mode operation,
vGS max=vDS min+Vt
which results in
VOV +vˆi =VDS −|Av|vˆi
Substituting for | Av | from Eq. (1) yields
VOV + vˆi = VDS − 2(VDD − VDS ) vˆi VOV
VDS [1 + 2(vˆi /VOV )]
= VOV + vˆi + 2VDD(vˆi/VOV )
VOV + vˆi + 2VDD(vˆi/VOV ) ⇒ VDS = 1 + 2(vˆi/VOV )
For
VDD =2.5V,vˆi =20mVandm=15
Q.E.D
7.29 Given μnCox = 250 μA/V2, vd = −RD
V =0.5V, vi 1 +R tgS
= −gmRD 1+gmRS
VDD
L = 0.5 μm
Forgm =2mA/V2 andID =0.25mA,
g = 2μ C W I ⇒ W = 32 m noxLDL
∴W =16μm
VOV = 2ID = 0.25 V
gm
∴VGS =VOV +Vt =0.75V
m
7.31
RG
10 M
I 500 μA
Chapter 7–11
7.30
vo 10 k
VDD
RD
RS
V SS
vi
RL
vi
vd vs
Vt =0.5V
VA = 50 V
GivenVDS =VGS =1V.Also,ID =0.5mA.
VOV =0.5V,gm = 2ID =2mA/V VOV
ro = VA = 100 k ID
vo =−gm (RG ∥RL ∥ro )=−18.2V/V D vd vi
ForID =1mA:
R√ gmvgs D VOV increasesby 1 = 2to
vG√ i
0.5
2 × 0.5 = 0.707 V.
1 vgs gm
VGS =VDS =1.207V
g =2.83mA/V,r =50kand mo
S
RS
vs
vo = −23.6 V/V vi
7.32 For the NMOS device: I =100=1μC WV2
v=gv1+R
D 2 n ox L OV = 1 × 400 × 10 × V 2
i mgs g S m
vd =−gmvgsRD
vs = +gmvgsRS
∴vs = RS
vi 1 +R
2 0.5 OV ⇒VOV =0.16V
2ID VOV
2×0.1mA 0.16
= 1.25 mA/V VA=5L=5×0.5=2.5V
r =VA =2.5=25k
gm =
=
= +gmRS 1+gmRS
g S mD
o I 0.1
For the PMOS device:
I =100=1μC WV2
Since the drain voltage (+7 V) is higher than the gate voltage (+5 V), the transistor is operating in saturation.
Fromthecircuit
VD =VDD −IDRD =15−0.5×16=+7V,as assumed
Finally,
VGS =1.5V, thusVOV =1.5−Vt =1.5−1
D 2 p ox L OV = 1 ×100× 10 ×V2
Chapter 7–12
2 0.5OV ⇒VOV =0.316V
gm = 2ID = 2×0.1 =0.63mA/V VOV 0.316
VA =6L=6×0.5=3V ro=VA = 3 =30k
ID 0.1
7.33 (a) Open-circuit the capacitors to obtain the bias circuit shown in Fig. 1, which indicates the givenvalues.
15 V
10 M
1.5 V
= 0.5 V
I =1kV2 =1×4×0.52=0.5mA
D 2nOV 2
which is equal to the given value. Thus the bias
0.5 mA
16 k 7 V
0.5 mA
7 k
calculations are all consistent.
2ID 2 × 0.5
(b)gm = V = 0.5 =2mA/V
OV
ro = VA = 100 = 200 k
ID 0.5
(c) See Fig. 2 below.
(d) Rin = 10 M ∥ 5 M = 3.33 M vgs = Rin = 3.33
vsig Rin + Rsig 3.33 + 0.2 = 0.94 V/V
vo = −gm(200∥16∥16) vgs
5 M
= −2 × 7.69 = −15.38 V/V
vo = vgs × vo =−0.94×15.38
Figure 1 From the voltage divider, we have
VG=15 5 =5V 10+5
From the circuit, we obtain
VG =VGS +0.5×7
= 1.5 + 3.5 = 5 V
which is consistent with the value provided by the voltage divider.
vsig vsig vgs = −14.5 V/V
vsig
gmvgs
10 M
5 M
200 k
16 k
16 k
7.34 (a) Using the exponential characteristic: ic =ICevbe/VT −IC
giving ic =evbe/VT −1 IC
(b) Using small-signal approximation:
ic = gmvbe = IC VT
· vbe
This figure belongs to Problem 7.33, part (c).
Rsig 200 k
vgs
Figure 2
vo
Rin
Thus, ic = vbe IC VT
See table below.
For signals at ±5 mV, the error introduced by the small-signal approximation is 10%.
The error increases to above 20% for signals at ±10 mV.
Voltage gain, Av = vce = −0.55 V vbe 5 mV
= −110 V/V
Using small-signal approximation, we write Av =−gmRC
where
gm = IC = 0.5mA =20mA/V VT 0.025 V
Av =−20×5=−100V/V
Thus, the small-signal approximation at this signal level (vbe = 5 mV) introduces an error of −9.1% in the gain magnitude.
7.36 At IC = 0.5 mA,
gm = IC = 0.5mA =20mA/V
Chapter 7–13
vbe (mV)
ic/IC Exponential
ic/IC Small signal
Error (%)
+1
+0.041
+0.040
–2.4
–1
–0.039
–0.040
+2.4
+2
+0.083
+0.080
–3.6
–2
–0.077
–0.080
+3.9
+5
+0.221
+0.200
–9.7
–5
–0.181
–0.200
+10.3
+8
+0.377
+0.320
–15.2
–8
–0.274
–0.320
+16.8
+10
+0.492
+0.400
–18.7
–10
–0.330
–0.400
+21.3
+12
+0.616
+0.480
–22.1
–12
–0.381
–0.480
+25.9
VT 0.025 V rπ = β = 100
gm 20 mA/V
re=VT =αVT IE IC
= 5 k
where
α= β = 100 =0.99
re = 0.99×25mV ≃50 0.5 mA
AtIC =50μA=0.05mA, gm = IC = 0.05 =2mA/V
VT 0.025 rπ=β= 100 =50k
gm 2 mA/V
re = αVT = 0.99×25mV ≃500
IC 0.5 mA
7.37 gm = IC = 1mA =40mA/V
β + 1 100 + 1
7.35
5 V
0.5 mA
vBE
5 k
VC
WithvBE =0.700V
VC =VCC −RCIC
= 5−5×0.5 = 2.5 V
ForvBE =705mV⇒vbe =5mV
iC = ICevbe/VT
=0.5×e5/25 =0.611mA
vC =VCC −RCiC =5−5×0.611=1.95V
v =v −V =1.95−2.5=−0.55V ce C C
re = α = gm
rπ = β = gm
0.99 40 mA/V
100 40 mA/V
≃ 25 =2.5k
VT 0.025 V
Av =−gmRC =−40×5=−200V/V vˆo =|Av|vˆbe =200×5mV=1V
7.38 For gm = 30 mA/V,
gm = IC ⇒IC =gmVT =30×0.025=0.75mA
VT
rπ = β = β
gm 30 mA/V
For rπ ≥ 3 k, we require β ≥ 90
That is, βmin = 90.
7.39 rπ = β gm
where
gm = IC VT
Nominally, gm = 40 mA/V. However, IC varies by ±20%, so gm ranges from 32 mA/V to 48 mA/V. Thus
then VCC−ICRC−VˆbeICRC=0.3
VT
which can be manipulated to yield ICRC=VCC−0.3 (1)
1 + Vˆbe VT
Since the voltage gain is given by
Av =−ICRC VT
then
VCC − 0.3 Av = VT +Vˆbe
ForVCC =3VandVˆbe =5mV, ICRC = 3−0.3 =2.25V
Thus,
VCE =VCC −ICRC
= 3−2.25 = 0.75 V
Chapter 7–14
rπ = 50 to 150 32 to 48 mA/V
Thus, the extreme values of rπ are 50 48
= 1.04 k
RC = 2 k
and 150 = 4.7 k. 32
7.40 VCC =3V,
IC = 3 − 1 = 1 mA
2
1+5 25
VC =1V,
IC 1 mA
gm = V = 0.025V =40mA/V
T
vbe = 0.005 sin ωt
ic =gmvbe =0.2sinωt, mA iC(t)=IC +ic =1+0.2sinωt, mA vC(t)=VCC −RCiC
= 3−2(1+0.2 sinωt) =1−0.4sinωt, V
iB(t) = iC(t)/β
= 0.01 + 0.002 sin ωt, mA
Av = vc =− 0.4 =−80V/V v be 0.005
Vˆo = VCE −0.3 = 0.75−0.3 = 0.45 V 3−0.3
Av = −0.025 + 0.005 = −90 V/V Check:
Av =−gmRC =−ICRC =− 2.25 =−90V/V VT 0.025
Vˆo =|Av|×Vˆbe =90×5=450mV=0.45V 7.42
Transistor
a
b
c
d
e
f
g
α
1.000
0.990
0.980
1
0.990
0.900
0.940
β
∞
100
50
∞
100
9
15.9
IC (mA)
1.00
0.99
1.00
1.00
0.248
4.5
17.5
IE (mA)
1.00
1.00
1.02
1.00
0.25
5
18.6
IB (mA)
0
0.010
0.020
0
0.002
0.5
1.10
gm (mA/V)
40
39.6
40
40
9.92
180
700
re ()
25
25
24.5
25
100
5
1.34
rπ ()
∞
2.525 k
1.25 k
∞
10.1 k
50
22.7
7.41 Since Vˆbe is the maximum value
acceptable linearity, the largest signal
collector will be obtained by designing for maximum gain magnitude. This in turn is achieved by biasing the transistor at the lowest VCE consistent with the transistor remaining in the active mode at the negative peak of vo. Thus
for at the
VCE −|Av|Vˆbe =0.3
where we have assumed V
CE sat
VCE =VCC −ICRC and
|Av|=gmRC=ICRC VT
= 0.3 V. Since
IC 1 mA T
β=100, VA =100V gm = V = 0.025V =40mA/V
7.43 IC =1mA,
rπ = β = 100 =2.5k gm 40 mA/V
ro=VA =100V=100k IC 1 mA
This figure belongs to Problem 7.43.
Chapter 7–15
ib
BCBC
vp rp ro rp
EE rp 2.5 k, gm 40 mA/V ro 100 k,
CC
BB
ro
b 100
ro
a 0.99
Q.E.D
gmvp
bib
gmvp re
ai re
vp
re 24.75 ,
ro
i
α= β = 100 =0.99 β + 1 100 + 1
ro 100 k, gm
EE
gm 40 mA/V
V αV re=T= T=
0.99×25mV 1 mA
ib =vbe α −gm =gv 1−α
IE
IC
=24.75
gmvbe
re
mbe α gmvbe
7.44
=β
Rin ≡ vbe = β = rπ
ib gm
ib
B
7.45 Refer to Fig. 7.26. ic =αie =αvbe = αvbe
re re = gmvbe Q.E.D
vbe
7.46 The large-signal model of Fig. 6.5(d) is shown in Fig. 1.
iB
BC
vBE DB biB (ISB IS )
b
Figure 1
For vBE undergoing an incremental change vbe
from its equilibrium value of VBE , the current iB
vbe E
Rin
1 =vbe r−gm
e
Since
re = α gm
i = vbe −g v
b r mbe
e
E
changes from IB by an increment ib, which is related to vbe by the incremental resistance of DB at the bias current IB. This resistance is given by VT /IB, which is rπ .
The collector current βiB changes from βIB to β(IB + ib). The incremental changes around the equilibrium or bias point are related to each other by the circuit shown in Fig. 2,
C
aiE ie
re
E
Figure 2
which is the small-signal T model of Fig. 7.26(b). Q.E.D.
7.48 Refer to Fig. P7.48: VC=3−0.2×10=1V
re=VT =25mV=125 IE 0.2 mA
Replacing the BJT with the T model of
Fig. 7.26(b), we obtain the equivalent circuit shown below.
Chapter 7–16
B vbe
ib BC
vbe rp
E
bib
Figure 2
which is the hybrid-π model of Fig. 7.24(b). Q.E.D.
7.47 The large-signal T model of Fig. 6.5(b) is shown below in Fig. 1.
C
aiE B
If iE undergoes an incremental change ie from its equilibrium or bias value IE, the voltage vBE will correspondingly change by an incremental amount vbe (from its equilibrium or bias value VBE ), which is related to ie by the incremental resistance of diode DE . The latter is equal to
VT /IE, which is re.
The incremental change ie in iE gives rise to an incremental change αie in the current of the controlled source.
The incremental quantities can be related
by the equivalent circuit model shown in Fig. 2,
vBE
Figure 1
iE
D
E
(I IS)
SE
a
E
vc =−ie ×10k
where
ie=−vi=− vi
re 0.125 k
Thus,
vc = 10k vi 0.125 k
= 80 V/V
This figure belongs to Problem 7.50.
Chapter 7–17
7.51 Replacing the BJT with the T model of Fig. 7.26(b), we obtain the circuit shown below.
C ix
aie
ib=vbe v
rπ Bx
7.49 vce =|Av|vbe
|Av|=gmRC =50×2=100V/V For vce being 1 V peak to peak,
vbe = 1V =0.01Vpeaktopeak 100
where
rπ = β = 100 = 2 k
gm 50 Thus,
i = 0.01V =0.005mApeaktopeak b 2 k
7.50
ie
re
E
r v x ix
Since vx appears across re and ix = ie = vx , the
re small-signal resistance r is given by
vπ
Rin≡i=rπ vv
b
vπ = rπ
vsig rπ +Rsig vo =−gmvπRC
vo =−gmRC vπ
The overall voltage gain can be obtained as follows:
r≡x=x=re ix ie
7.52 Refer to Fig. P7.52. Replacing the BJT with the T model of Fig. 7.26(b) results in the following amplifier equivalent circuit:
C
aie B ib
vo = vo vπ vsig vπ vsig
=−gR rπ
m Crπ+Rsig
ie
vi E
Rin
re
Re vo
R =−gr C
m π rπ + Rsig =− βRC
Q.E.D.
rπ +Rsig
Rin ≡ vi = vi
ib (1 − α)ie
From the circuit we see that
ie= vi
re + Re
Thus,
re+Re Rin= 1−α
The input resistance Rin can be found by inspection to be
Rin = re = 75
To determine the voltage gain (vo/vi) we first
Chapter 7–18
find ie:
ie=−vi =−vi=−vi
But 1−α=
1 β+1
Rsig+re 150 0.15k The output voltage vo is given by
vo =−αie(RC∥RL)
=−0.99ie ×(12∥12)=−0.99×6ie
Thus,
Rin = (β + 1)(re + Re)
Q.E.D.
=−0.99×6× −vi 0.15
From the equivalent circuit, we see that vo and vi are related by the ratio of the voltage divider formed by re and Re:
vo= Re Q.E.D. vi Re +re
7.53 Refer to Fig. P7.53. The transistor is biased atIE =0.33mA.Thus
re = VT = 25mV =75 IE 0.33 mA
Replacing the BJT with its T model results in the following amplifier equivalent circuit.
Thus,
vo = 39.6 V/V
vi
7.54 Refer to Fig. P7.54.
This figure belongs to Problem 7.54.
α= β = 200 =0.995 β+1 201
IC =α×IE =0.995×10=9.95mA
VC =ICRC =9.95×0.1k=0.995V≃1V
Replacing the BJT with its hybrid-π model results in the circuit shown below.
gm = IC ≃ 10mA =400mA/V VT 0.025 V
rπ = β = 200 = 0.5 k gm 400
Rib =rπ =0.5k
Rin = 10 k∥0.5 k = 0.476 k
vπ = Rin = 0.476 = 0.322 V/V vsig Rin + Rsig 0.476 + 1
vo =−gmRC =−400×0.1=−40V/V vπ
vo = −40 × 0.322 = −12.9 V/V v sig
vo
Rsig 1 k
vb
vsig
vp rp gv RC
10 k m p
Rib
Rin
This figure belongs to Problem 7.55.
B
C
RL very high
Chapter 7–19
vsig
gmvp
vp rp rvo o
For
vo = ±0.4 V/V
vb = vπ = ±0.4 = ∓0.01 V = ∓10 mV −40
vsig = ±0.4 =∓31mV −12.9
7.55 The largest possible voltage gain is obtained when RL → ∞, in which case
vo =−gmro=−IC VA vsig VT IC
= − VA VT
ForVA =25V, vo =− 25 v sig 0.025
= −1000 V/V
ForVA =125V, vo =− 125
7.57
5 V
Rsig 50
Rin re 50
RE
RC
vsig
re = 50 = VT IE
⇒IE =0.5mA Thus,
vo
0.025
5 V
v sig
= −5000 V/V
7.56 Refer to Fig. 7.30:
Rin ≃re
To obtain an input resistance of 75 ,
re =75= VT IE
Thus,
IE = 25mV =0.33mA
5−VE =0.5mA RE
where
VE ≃0.7V ⇒RE =8.6k
75
This current is obtained by raising RE to the value
To obtain maximum gain and the largest possible signal swing at the output for veb of 10 mV, we select a value for RC that results in
VC +|Av|×0.01V=+0.4V
which is the highest allowable voltage at the collector while the transistor remains in the active region. Since
VC =−5+ICRC ≃−5+0.5RC then
−5+0.5RC +gmRC ×0.01 = 0.4
found from
IE = 10−0.7 =0.33mA
RE
⇒ RE = 28.2 k
Note that the dc voltage at the collector remainsunchanged.Thevoltagegain now becomes
vo = αRC = 0.99×14.1 =186V/V vi re 0.075
Substituting gm = 20 mA/V results in
RC =7.7k
For α ≃ 1,
re=VT =25mV=50
vR vo1 o= in ×gmRC vi
3.6 = 0.986 V/V 3.6 + 0.05
Chapter 7–20
The overall voltage gain achieved is IE 0.5 mA
vsig Rin + Rsig
50 vo2
=
= − 3.3
= 0.904 V/V
= 50+50 ×20×7.7 vi
3.6 + 0.05
= 77 V/V
7.58 Refer to Fig. P7.58. Since β is very large,
the dc base current can be neglected. Thus the dc voltage at the base is determined by the voltage divider,
100
VB =5100+100 =2.5V
and the dc voltage at the emitter will be
VE =VB −0.7=1.8V
The dc emitter current can now be found as
VE 1.8
IE=R =3.6=0.5mA
E
and
IC ≃IE =0.5mA
Replacing the BJT with the T model of
Fig. 7.26(b) results in the following equivalent circuit model for the amplifier.
ie= vi RE +re
v=iR=v RE
o1 eE iRE+re
vo1 = RE Q.E.D. vi RE +re
vi
vo2 =−αieRC =−αR +r RC
Ee v =−R +r Q.E.D.
If vo1 is connected to ground, RE will in effect be short-circuited at signal frequencies, and vo2/vi will become
vo2 αRC 3.3
v=−r =−0.05=−66V/V
ie
7.59 See figure on next page. Rin RL
Gv=R+R AvoR+R in sig L o
= 100 ×100× 2 100+20 2+0.1
= 79.4 V/V vo
io = RL
v sig
ii = Rsig + Rin
io = vo Rsig +Rin
ii vsig RL = G Rsig + Rin
v RL
= 79.4× 20+100 = 4762 A/A
7.60(a) R +R =0.95 in sig
2 Rin
vo2 αRC
iEe in
Rin
Rin +100
= 0.95 ⇒R =1.9M
This figure belongs to Problem 7.58.
vi
100 100 k k
vo2 aie RC
ie
re
vo1 RE
This figure belongs to Problem 7.59.
Rsig 20k
Ro 100
vi Rin Av ovi RL vo 100 k 2 k
Avo 100
Chapter 7–21
vsig
This figure belongs to Problem 7.60.
Rsig
vsig
(b) With RL = 2 k,
2
vo =Avovi2+R o
With RL = 1 k, v=Av1
Ro
vi Rin Avovi RL vo
7.61 The circuit in Fig. 1(b) (see figure on next page) is that in Fig. P7.61, with the output current source expressed as Gm v i . Thus, for equivalence, we write
Gm=Avo Ro
To determine Gm (at least conceptually), we short-circuit the output of the equivalent circuit in Fig. 1(b). The short-circuit current will be
io=Gmvi
o vo i 1+Ro Thus the change in vo is
2 1 vo=Avovi 2+R −1+R
oo
To limit this change to 5% of the value with RL = 2 k, we require
Thus Gm is defined as
2 1 2 2+R − 1+R 2+R
=0.05
Gm = io
vi RL=0
ooo
andisknownastheshort-circuit transconductance. From Fig. 2 on next page,
vi = Rin vsig Rin + Rsig
vo =Gmvi(Ro∥RL) Thus,
1
⇒ Ro = 9 k = 111
(c)G=10= Rin A RL
v
= 1.9 1.9 + 0.1
The values found about are limit values; that is, we require
Rin ≥ 1.9 M Ro ≤111
Avo ≥11.1V/V
R+R voR+R in sig L o
×Avo × ⇒Avo =11.1V/V
2
2 + 0.111
vo = vsig
7.62
Rin Gm(Ro ∥RL) Rin + Rsig
v Gvo= o
vsig RL=∞
Now, setting RL = ∞ in the equivalent circuit in Fig. 1(b), we can determine Gv o from
This figure belongs to Problem 7.61.
Ro io
Avovi
io
Chapter 7–22
vi
Figure 1
Norton
vi
Avovi
Ro
Gmvi
Rin
(a)
Rsig
vo equivalent of output
Rin
R vo o
circuit
(b)
vsig
vi Rin Gmvi Ro RL vo
Figure 2
This figure belongs to Problem 7.62.
Rsig
vsig
Rsig
Rout
vi Rin Gvovsig RL vo
(a)
Ro
vsig vi Rin Avovi RL vo
Figure 1
Gvo =
Denoting Rin with RL = ∞ as Ri , we can express
Gvo as
Gvo = Ri Avo Q.E.D.
From the equivalent circuit in Fig. 1(a), the overall voltage Gv can be obtained as
R in
RL
RL + Rout
(b)
Gv =Gvo
7.63 Refer to Fig. P7.63. To determine Rin, we
simplify the circuit as shown in Fig. 1, where Rin≡vi =R1∥R′in, whereR′in≡vi
ii if vi =ifRf +(if −gmvi)(R2∥RL)
Rin+Rsig RL=∞
Avo
Q.E.D.
Ri + Rsig
This figure belongs to Problem 7.63.
Chapter 7–23
Thus,
controlled source gmvi. Thus, looking between the output terminals (behind RL), we see R2 in parallel with Rf ,
Ro=R2∥Rf Q.E.D.
ForR1 =100k, Rf =1M, gm =100mA/V R2 =100andRL =1k
Rin = 100∥ 1000+(0.1∥1) = 100∥99.1 1+100(0.1∥1)
= 49.8 k
Without Rf present (i.e., Rf = ∞), Rin = 100 k
and
Avo =−100×0.11−(1/100×1000)
1+0.1 1000
≃ −10 V/V
Without Rf , −Avo = 10 V/V and Ro =0.1∥1000≃0.1k=100 Without Rf , Ro = 100 .
Thus the only parameter that is significantly affected by the presence of Rf is Rin, which is reduced by a factor of 2!
Figure 1
vi[1+gm(R2∥RL)]=if[Rf +(R2∥RL)]
R′in≡vi = Rf +(R2∥RL) if 1+gm(R2 ∥RL)
and
Rf +(R2 ∥RL) =R1∥ 1+gm(R2∥RL)
R =R ∥R′ in 1 in
Q.E.D.
To determine Avo, we open-circuit RL and use the circuit in Fig. 2, where
Rf
if
vo
vi
R1 gmvi
R2 R2
vo
Figure 2
if = gmvi + vo R2
vi(1−gmRf)=vo 1+ f R2
Thus,
Avo≡vo =1−gmRf vi 1 + Rf R2
vi=ifRf+vo= gmvi+ o R2 R
Rf+vo
Gv=R +R AvoR+R in sig L o
v RinRL
With Rf ,
Gv = 49.8
49.8 + 100 =−3V/V
×−10×
1
1 + 0.1
Without Rf ,
100 1
whichcanbemanipulatedtotheform A =−g R 1−1/gmRf Q.E.D.
Gv = 100+100 ×−10× 1+0.1 =−4.5V/V 7.64 Rsig =1M, RL =10k
gm = 2 mA/V, RD = 10 k
vo m 21+(R2/Rf)
Finally, to obtain Ro we short-circuit vi in the circuit of Fig. P7.63. This will disable the
Gv=−gm(RD∥RL)
= −2(10 ∥ 10) = −10 V/V
(b)gm1=gm2=2ID =2×0.3=3mA/V VOV 0.2
RD1 =RD2 =10k
RL =10k
Gv = vgs2 × vo
vgs1 vgs2
= −gm1RD1 × −gm2(RD2 ∥ RL)
= 3×10×3×(10∥10) = 450 V/V
IC 0.5 mA
7.68 gm = V = 0.025V =20mA/V
= 5 k
Ro =RC =10k
Avo =−gmRC =−20×10=−200V/V
RL 10 Av =AvoR +R =−200×10+10
Lo
7.65 Rin =∞ 1 W
Chapter 7–24
V2 D 2noxLOV
I = μC 1
320= ×400×10×V2 2 OV
⇒VOV =0.4V
gm = 2ID = 2×0.32 =1.6mA/V
VOV 0.4
Avo =−gmRD =−1.6×10=−16V/V
T
rπ = β = 100
Ro = RD = 10 k G =A RL
v voRL +Ro =−16× 10
7.66 RD =2RL =30k VOV =0.25V
Gv =−gm(RD∥RL)
−10 = −gm(30∥15) ⇒gm =1mA/V
gm = 2ID VOV
gm 20mA/V Rin =rπ =5k
10+10 Peakvalueofvsig = 8
=−8V/V
=25mV.
0.2V
=−100V/V
Gv = Rin Av
Rin+Rsig
= 5 ×−100
5+10 =−33.3V/V
1=
2×ID 0.25
For vˆπ = 5 mV, vˆsig can be found from
Rin 5 vˆπ =vˆsig×R +R =vˆsig×5+10
in sig ⇒ vˆsig = 15 mV
Correspondingly, vˆo will be
vˆo = Gvvˆsig
= 15 × 33.3 = 500 mV = 0.5 V
⇒ID =0.125mA=125μA If RD is reduced to 15 k,
Gv =−gm(RD∥RL)
= −1 × (15 ∥ 15) = −7.5 V/V
7.67 (a) See figure below.
This figure belongs to Problem 7.67.
Rsig 200 k
vsig vgs1 gm1vgs1 RD1 vgs2 gm2vgs2 RD2 RL vo
7.69 |Gv | = R′L (Rsig/β) + (1/gm)
R′L =10k, Rsig =10k, gm = IC
That is,
8 = 10
Chapter 7–25
=
1 0.025
= 40 mA/V
0.2+(1/gm)
⇒ g =0.3orgm =3.33mA/V
0.1+(1/gm) VT 1
m
Nominal β = 100
(a) Nominal |Gv | =
= 80 V/V
10 (10/100) + 0.025
|Gv | Gv
10
nominal = 0.1 + 0.3 = 25 V/V
10
min = 0.2 + 0.3
(b) β = 50, |Gv | = 10
= 20 V/V (−20% of nominal)
We need to check the value obtained for
(10/50) + 0.025 10
(c)For|Gv |tobewithin±20%ofnominal(i.e., ranging between 64 V/V and 96 V/V), the corresponding allowable range of β can be found as follows:
64 = 10 (10/βmin) + 0.025
⇒ βmin = 76.2 96 = 10
(10/βmax ) + 0.025 ⇒ βmax = 126.3
(d) By varying IC , we vary the term 1/gm in the denominator of the | Gv | expression. If β varies in the range 50 to 150 and we wish to keep |Gv | within ±20% of a new nominal value of | Gv | given by
β = 150,
10
= 44.4 V/V β=150,|Gv|=
|Gv max =10/150+0.3=27.3V/V which is less than the allowable value of
(10/150) + 0.025
Thus, | Gv | ranges from 44.4 V/V to 109.1 V/V.
1.2 |G = 30 V/V. Thus, the new bias v nominal
= 109.1 V/V
current is
IC =gm ×VT =3.33×0.025=0.083mA
|G = 25 V/V v nominal
7.70 (a) See figure below. (b) RC1 = RC2 = 10 k RL =10k
Rsig = 10 k
gm1 =gm2 = IC = 0.25mA =10mA/V VT 0.025 V
β 100 rπ1=rπ2=g =10=10k
m
rπ1 =
vπ1 vsig vπ2 vπ1
vπ2
= −10(10 ∥ 10) = −50 V/V
=
10 = 0.5 V/V 10 + 10
rπ1 + Rsig
= −gm1(RC1 ∥ rπ2) = −10(10 ∥ 10)
|G = 10
= −50 V/V
vo =−gm2(RC2∥RL)
v nominal then
0.8|G
v nominal
(10/100) + (1/gm)
=
10 (10/50) + (1/gm)
This figure belongs to Problem 7.70.
Rsig 10 k
vsig vp1 rp1 vp2 rp2 vo gm1vp1 RC1 gm2vp2 RC2 RL
vo =vo ×vπ2×vπ1
vˆsig=5×30.3+10=6.65mV 30.3
vˆo = vˆsig × |Gv |
= 6.65 × 15 ≃ 100 mV
7.75 Rin = (β + 1)(re + Re) 15=75(re +Re)
re +Re = 15k =200 75
vˆ =vˆ Rin re
Chapter 7–26
vsig vπ2 vπ1 = −50 × −50 × 0.5
vsig
= 1250 V/V
7.71g = gm
m effective 2= 5
1 + gmRs
1+5Rs
⇒Rs =0.3k=300
π
5 = 150 × ⇒ re
7.72 The gain magnitude is reduced by a factor of (1 + gmRs). Thus, to reduce the gain from −10 V/V to −5 V/V, we write
2 = 1 + gmRs
⇒Rs= 1 =1=0.5k
gm 2
7.73 Including Rs reduced the gain by a factor of
2, thus 1+gmRs =2
⇒gm = 1 = 1 =2mA/V Rs 0.5
The gain without Rs is −20 V/V. To obtain a gain of−16V/V,wewrite
16 = 20 = 20
1 + gm Rs 1 + 2Rs
⇒Rs =125
7.74 gm = IC = 0.5 =20mA/V
VT 0.025 re ≃ 1 = 50
gm
Rin =(β+1)(re +Re)
sig Rin + Rsig re + Re
15 r e
15+30 re+Re = 0.1
re+Re
Butre +Re =200,thus
re = 20
which requires a bias current IE of
IE = VT = 25mV =1.25mA re 20
IC ≃IE =1.25mA Re =180
Gv = Rin
Rin + Rsig
× −α × Total resistance in collector Total resistance in emitter
= 101(50 + 250) = 30.3 k
Avo =− αRC =−0.99×12 ≃−40V/V
7.76 Using Eq. (7.113), we have RC ∥RL
15 × −0.99 × 6
=
≃ −10 V/V
15+30
vˆ0 =0.15×|Gv|=1.5V
0.2
re + Re Ro = RC = 12 k
A=A RL
v vo RL + Ro
= −40 × 12 12+12
0.3
Gv =−βRsig +(β+1)(re +Re) ≃ − RC ∥ RL
(Rsig/β) + (re + Re) 10
= −20 V/V Gv= Rin ×Av
|Gv | = (10/β) + 0.025 + Re Without Re,
Rin + Rsig 30.3
|Gv | = 10 (10/β) + 0.025
=30.3+10×−20=−15V/V
For the nominal case, β = 100,
G = 10 =80V/V
vˆ =5mV⇒vˆ =vˆ in π sig π
sig
R +R
Rin
v nominal 0.1+0.025 For β = 50,
G = 10
v low 0.2 + 0.025
For β = 150,
G = 10
Thus, | Gv | ranges from 44.4 V/V to 109.1 V/V with a nominal value of 80 V/V. This is a range of −44.5% to +36.4% of nominal.
Tolimittherangeof|Gv |to±20%ofanew nominal value, we connect a resistance Re and find its value as follows. With Re,
7.78 Adding a resistance of 100 in series with the 100- Rsig changes the input voltage divider ratio from
1/gm to 1/gm (1/gm) + 100 1/gm + 200
Since this has changed the overall voltage gain from 12 to 10, then
12 = (1/gm) + 200 , where gm is in A/V 10 (1/gm)+100
0.2
⇒ gm = 80 A/V = 2.5 mA/V
ForI =0.25mA D
2.5=2ID =2×0.25 VOV VOV
⇒VOV =0.2V
7.79 ForRin =Rsig =50, re = 50
and, with α ≃ 1,
IC ≃ VT = 25mV =0.5mA re 50
gm = IC/VT = 20 mA/V
= 44.4 V/V
Chapter 7–27
v high (1/15) + 0.025
=109.1V/V
G = v nominal
10
= 0.125 + R
Now, β = 50, G= 10
10 (10/100) + 0.025 + R
we use 10
10 0.125 + Re
e
e
nominal,
v low 0.225+Re
To limit this value to −20% of
= 0.8 ×
⇒Re =0.275k=275
Gv
0.225 + Re
With this value of Re,
G nominal = 10
v 0.125 + 0.275
G= 10
v low 0.225+0.275
= 25 V/V
Gv = Gv =
Rin gm(RC ∥RL) Rin + Rsig
= 20 V/V (−20% of nominal) G = 10
= 50 V/V
v high (1/15) + 0.025 + 0.275 = 27.3 V/V (+9.1% of nominal)
2 mA/V ×gm(RD∥RL)
7.80 Refer to the circuit in Fig. P7.80. Since
Rsig ≫ re, most of isig flows into the emitter of the BJT. Thus
i ≃i
e sig
and
ic =αie ≃isig Thus,
vo =icRC =isigRC
7.81 Rin =re = VT = 25mV =125 IE 0.2 mA
gm = IC ≃ 0.2mA =8mA/V VT 0.025 V
Rin
Gv=R +R gm(RC∥RL)
in sig
50 50+50
×20×(10∥10)
7.77 Rin = 1 = 1 =0.5k
gm Gv = Rin
= =2V/V
Rin +Rsig
0.5 × 2(5 ∥ 5)
0.5 + 0.75
ForRin =Rsig =0.75k
1 =0.75⇒gm =1.33mA/V gm
Sincegm = 2knID,thentochangegm byafactor 1.33 = 0.67, ID must be changed by a factor of
2 (0.67)2=0.45.
= 0.125 × 8(10∥10) = 8 V/V 0.125 + 0.5
vˆ=vˆ Rin
π sig Rin + Rsig
10 = vˆ 0.125
sig 0.125 + 0.5
⇒ vˆsig = 50 mV
vˆo = Gv vˆsig = 8 × 50 = 400 mV = 0.4 V
RL RL + Ro
7.83
Chapter 7–28
Rsig
i
i
1
50 mV (peak)
gm
0.5 V (peak)
vsig
7.82 Av =
A = 2
RL
v nominal
2 + Ro 1.5
A
v low
=
From the figure above, we have
1
g =0.1×RL m
= 0.1 × 2 = 0.2 k
gm =5mA/V
gm = 2kn ID
5= 2×5×ID
ID = 2.5 mA
At the peak of the sine wave,
id = 0.5V =0.25mA, thus 2k
iDmax = ID + 0.25 = 2.75 mA
iDmin = ID − 0.25 = 2.25 mA
vˆsig =vˆgs +vˆo =0.05+0.5=0.55V
1.5+Ro 5
Av high = vv
5+Ro
For A high = 1.1 A nominal
5 = 1.1 × 2 5+Ro 2+Ro
⇒ Ro = 0.357 k 2
Av nominal = 2.357 = 0.85 V/V A = 5
v high 5.357 = 0.93
(+10% above nominal) A= 1.5
v low 1.5 + 0.357
= 0.81 (−5% from nominal)
1 =Ro =0.357k gm
⇒gm =2.8mA/V
To find ID, we use
7.84
Rsig/(b + 1)
gm = 2knID ⇒I =g2/2k
r vbe e
vsig
Dmn
2.82
= 2×2.5 =1.6mA
I=1kV2 D 2nOV
vo RL
1
1.6= ×2.5×V2
vˆo=0.5V RL=2k vˆbe=5mV
2OV ⇒VOV =1.13V
From the figure above we see that
(b)
re = 5mV RL 500 mV
⇒re=RL =20 100
IE = VT = 25mV =1.25mA re 20
Rsig
B
ai
Chapter 7–29
i
vbe re
At the peak of the output sine wave, we have ˆ vˆo 0.5
vsig
ie=R = 2 =0.25mA
Lv RL o
Thus,
iEmax = 1.25 + 0.25 = 1.5 mA and
iEmin =1.25−0.25=1.0mA From the figure, we have
Rin
Gv=vo = vsig
RL
RL +re + Rsig
vˆbe =10mV vˆo = RL ×vˆbe
re
=500×10 12.5
=
2
2 + 0.02 + 200 101
β + 1 = 0.5 V/V
= 400 mV = 0.4 V
vˆ = vˆo = 0.4 = 0.488 V
Thus,
vˆsig=G =0.5V/V=1V
sig Gv 0.82 (c)Gvo =1
vˆo 0.5V v
7.85 IC =2mA
VT VT 25
re=I ≃I =2=12.5
E C
(a) Rin =(β+1)(re +RL)
= 101 × (12.5 + 500) = 51.76 k
Rout =re+ Rsig =12.5+10,000
β+1 = 111.5
101
Thus,
Gv =GvoRL+Rout
RL
vb = Rin vsig Rin +Rsig
= 0.84 V/V
v v v
=
51.76 51.76+10
= 1 × 500 = 0.82 V/V 500+111.5
which is the same value obtained in (a) above. For RL = 250 ,
RL
Gv = Gvo RL +Rout
250
= 1 × 250 + 111.5 = 0.69 V/V
7.86 Rout = re + Rsig β+1
re=VT ≃VT =25mV=50 IE IC 0.5mA
Rout =50+ 10,000 =50+99=149 101
o=b×o vsig vsig vb
= 0.84 ×
RL RL + re
0.5 =0.84× 0.5+0.0125
=0.82V/V
RL
Gv= R=
RL
RL +Rout
ic RC =−i
ib RB + e (re +RE)
Chapter 7–30
RL +re + sig
β+1 ib
= 1000 = 0.87 V 1000 + 149
RC
RB +(β+1)(re +RE)
If β varies between 50 and 150, then we have 10,000
= −β
ve = −ieRE
Routmax =50+ 51 =50+196 = 246
Routmin =50+ 151 =50+66.2 = 116
vsig ibRB + ie(re + RE)
= RE
10,000
Gvmin=RL =1000
RL + Routmax 1000 + 246
ic
ie RE
Y
ic = −icRC = −αieRC vc=−icRC =αRC
vsig ie(re +RE) re +RE
vc RC
RB
β+1 (b)
+ re + RE
= 0.80 V/V
Gvmax=RL =1000
RL + Routmin 1000 + 116 = 0.90 V/V
7.87 Rout = re + Rsig
β+1
150 = re + 5000 (1) β+1
250 = re + 10,000 (2) β+1
Subtracting Eq. (1) from Eq. (2), we have 100 = 5000
β+1 β + 1 = 50
Substituting in Eq. (1) yields
150 = re + 5000 50
ie=− vsig re + RE
vsig
⇒re =50 Gv = RL
7.89 With the Early effect neglected, we can write
Gv = −100 V/V
With the Early effect taken into account, the effective resistance in the collector is reduced from RC = 10 k to (RC ∥ro), where
ro = VA = 100V =100k IC 1 mA
(RC ∥ro) = 10∥100 = 9.1 k Thus, Gv becomes
=
RL+re+ Rsig β+1
1000 = 0.8 V/V 1000 + 50 + 10, 000
50 7.88 (a) Refer to Fig. P7.88.
v −i R c= cC
vsig ibRB + ie(re + RE)
Gv = −100 × = −91 V/V
9.1 k 10 k
7.90
Rsig
Thus,
|Gv|= 10∥ro (1)
where ro and 1 are in kilohms and are given by gm
ro=VA=25V (2) IC IC mA
1 =VT =0.025V (3)
Chapter 7–31
0.1+ 1 gm
i
i
1
gm
ro
0
G
v vg
sig RL v
o
gm IC
IC mA
IC (mA)
1/gm (k)
ro (k)
|Gv |(V/V)
0.1
0.250
250
27.5
0.2
0.125
125
41.2
0.5
0.050
50
55.6
1.0
0.025
25
57.1
1.25
0.020
20
55.6
vg =vsig
Noting that ro appears in effect in parallel with RL, vo is obtained as the ratio of the voltage divider formed by (1/gm ) and (RL ∥ ro ),
Gv=vo =vo= vsig vg
With RL removed,
Gv = ro
ro + 1
(RL∥ro) (RL∥ro)+ 1
gm
Q.E.D.
=0.98 With RL = 500 ,
(1)
(2)
Observe that initially | Gv | increases as IC is increased. However, above about 1 mA this trend reverses because of the effect of ro. From the table we see that gain of 50 is obtained for IC between 0.2 and 0.5 mA and also for IC above 1.25 mA. Practically speaking, one normally uses the low value to minimize power dissipation. The required value of IC is found by substituting for ro and 1/gm from Eqs. (2) and (3), respectively, in Eq.(1)andequatingGv to50.Theresult(after some manipulations) is the quadratic equation.
IC2 − 2.25IC + 0.625 = 0
The two roots of this equation are IC = 0.325 mA and 1.925 mA; our preferred choice is
IC = 0.325 mA.
gm
Gv = (500∥ro)
= 0.49
(500∥ro)+ 1 gm
From Eq. (1), we have 1 = ro
gm 49
Substituting in Eq. (2) and solving for ro gives ro =25,000=25k
Thus
1 = 25,000
gm 49
⇒gm =1.96mA/V
7.91 Adapting Eq. (7.114) gives Gv=−β RC∥RL∥ro
Rsig + (β + 1)re
=− RC∥RL∥ro Rsig +β+1r
ββe
= − RC ∥ RL ∥ ro Rsig + 1 β gm
7.92
VDD 9 V
RG1 VG
RG2
ID RD
RS
VD VS
ID = 1 mA I = 1 k V 2
7.93
D 2nOV 1=1×2×V2
5 V
RD 0 ID
RS
Chapter 7–32
2 OV ⇒VOV =1V
VGS =Vt +VOV =1+1=2V Now, selecting VS = VDD = 3 V
3
VG0 RG
10 M
IDRS =3
RS = 3 = 3 k
1
Also,
IDRD=VDD =3V
5 V
ForI =0.5mA 3D
3 ⇒RD=1=3k
VG = VS + VGS =3+2=5V
Thus the voltage drop across RG2(5 V) is larger than that across RG1(4 V). So we select
RG2 =22M
and determine RG1 from
RG1 = 4 V RG2 5V
⇒ RG1 = 0.8RG2 = 0.8×22 = 17.6 M
0.5= 1k V2 2n OV
= 1 × 1 × V 2 2 OV
⇒VOV =1V
VGS =Vt +VOV =1+1=2V Since
VG =0V, VS =−VGS =−2V
which leads to
RS = VS − (−5) = −2 + 5 = 6 k
Using only two significant figures, we RG1 =18M
Note that this will cause VG to deviate slightly from the required value of 5 V. Specifically,
V=V RG2
G DD RG2 + RG1
= 9 × 22 = 4.95 V 22+18
It can be shown (after simple but somewhat tedious analysis) that the resulting ID will be
ID = 0.986 mA, which is sufficiently close to the desired1mA.SinceVD =VDD −IDRD ≃+6V and VG ≃ 5 V, and the drain voltage can go down toVG −Vt =4V,thedrainvoltageis2Vabove the value that causes the MOSFET to leave the saturation region.
and
have 5−2
IC 0.5
VD is required to be halfway between cutoff
(+5 V) and saturation (0 − Vt = −1 V). Thus
VD = +2 V
RD = 0.5 =6k 7.94
10 M
VDD 15 V
RG1 RD
5.1 M RG2
RS
V = V RG2
G DD RG1 + RG2
=15× 5.1 =5.07V 10 + 5.1
kn = 0.2 to 0.3 mA/V2 Vt =1.0Vto1.5V
D 2n GS t WithRS =0,
Chapter 7–33
which is the maximum value. The minimum value can be obtained by using kn = 0.2 mA/V2 andVt =1.5VinEq.(1),
ID = 1 × 0.2(3.57 − 0.62ID)2 2
= 0.1(3.572 − 2 × 3.57 × 0.62ID + 0.622 ID2 ) 0.038 ID2 − 1.442ID + 1.274 = 0 whichresultsin
ID =37mAor0.91mA
Here again, the physically meaningful answer is ID = 0.91 mA, which is the minimum value of ID. Thus with a 0.62-k resistance connected in the source lead, the value of ID is limited to the range of0.91mAto1.5mA.
7.95
VDD
1.5= 1 ×0.3(VGS −1)2
2 ID
1
I = k(V −V2)
I =1k(V −V2) D2nGt
IDmax is obtained with Vtmin and knmax: 1
IDmax = 2 ×0.3(5.07−1)2 =2.48mA
IDmin is obtained with Vtmax and knmin:
IDmin = 1 × 0.2(5.07 − 1.5)2 = 1.27 mA 2
With RS installed and Vt = 1 V,
kn = 0.3 mA/V2, we required ID = 1.5 mA:
⇒VGS =4.16V
Since VG = 5.07 V,
VS = VG −VGS = 5.07−4.16 = 0.91 V Thus,
RS =VS =0.91=607 ID 1.5
From Appendix J, the closest 5% resistor is 620.WithRS =620,
VS = IDRS = 0.62ID
VGS = VG −VS = 5.07−0.62ID
ID = 1kn(VGS −Vt)2 2
= 1kn(5.07 − 0.62ID − Vt)2 2
Forkn =0.3mA/V2 andVt =1, ID =1×0.3(4.07−0.62ID)2
2
= 0.15(4.072 − 2 × 4.07 × 0.62ID + 0.622 ID2 )
0.058ID2 − 1.757ID + 2.488 = 0
which results in
ID = 28.8 mA, or 1.49 mA
The first value does not make physical sense. Thus,
ID =1.49mA≃1.5mA
RG1 RD VG 5 V
RG2
VS =IDRS =3ID
VGS = 5−VS = 5−3ID
ID = 1kn(VGS −Vt)2 2
= 1 ×2(5−3ID −1)2 2
= 16 − 24ID + 9ID2
9ID2 −25I+16=0
ID =1.78mAor1mA
ID
RS
3 k
The first answer is physically meaningless, as it would result in VS = 5.33 V, which is greater than VG , implying that the transistor is cut off. Thus,ID =1mA.
If a transistor for which kn = 3 mA/V2 is used, then
ID = 1 × 3(5 − 3ID − 1)2 2
= 1.5(16 − 24I + 9ID2 )
9ID2 − 24.67ID + 16 = 0
whose physically meaningful solution is ID = 1.05 mA
5 V
ID
D
RS
5 V
Maximum gain is obtained by using the largest
possible value of RD, that is, the lowest possible value of VD that is consistent with allowing negative voltage signal swing at the drain of 1 V. Thus
VD −1=vDmin =VG −Vt =0−1 ⇒ VD = 0 V
where we have assumed that the signal voltage at the gate is small. Now,
VD = 0 = VDD −IDRD 0 = 5 − 0.5 × RD ⇒RD =10k
Chapter 7–34
7.96
RD
VD RG I VS
VG 5 V
ID
VDD
RD ID
VS 2 V RS 2 k
ID = 2 V = 1 mA 2 k
But
ID = 1kn(VGS −Vt)2 2
1
1= ×2(VG−VS−Vt)2
2
1 = (5 − 2 − Vt )2
Vt =2V
IfVt =1.5V,thenwehave VS =IDRS =2ID
VGS =VG −VS =5−2ID
7.98
VDD 10 V IG
R1 RS
ID V
ID = 1 ×2(5−2ID −1.5)2 2S
4ID2 −15ID +12.25=0 ID = 1.2 mA
VS =2.4V
7.97 ID = 0.5 mA = 1 × 4(VGS − 1)2 2
⇒VGS =1.5V
SinceVG =0V,VS =−1.5V,and
RS = −1.5−(−5) =7k 0.5
VG
VD 3 V ID 1 mA
R2 RD
ID =1mAandVD =3V Thus,
RD = VD = 3V =3k ID 1 mA
For the transistor to operate 1 V from the edge of saturation
VD =VG +|Vt|−1
Thus,
3=VG +|Vt|−1
VG +|Vt|=4V
(a)|Vt|=1V andkp =0.5mA/V2 VG = 3 V
R2=VG= 3V =0.3M IG 10 μA
R1=VDD−VG= 7V =0.7M
7.99
Chapter 7–35
VDD
0V
RD ID
RG
V
I GS D
RS
VSS
IG RD =3k
10 μA
VD = 3 V 1
(a)VGS +IDRS =VSS
But
ID = 2kp(VSG −|Vt|)2 1 2
I =1k′ W (V −V)2 D 2 n L GS t
1 = 2 × 0.5(VSG − 1)
⇒VSG =3V
VS =VG +3=3+3=6V
=K(VGS −Vt)2
ID
⇒VGS =Vt + K Thus,
RS=VDD−VS
ID K
10 − 6
= 1 =4k
(b)|Vt|=2Vandkp =1.25mA/V2 VG=4−|Vt|=2V
R2 = VG = 2V =0.2M IG 10μA
1 1∂I I ∂I 0+√ D−D+RD=0
Vt+ ID+IDRS=VSS Differentiating relative to K , we have
2 ID/K K ∂K K2 ∂IDK 1
S ∂K
∂K I =1+2√KI R DDS
SID =1/[1+2KI R ] K DS
R = VDD −VG = 8V =0.8M
Q.E.D (b)K =100μA/V2, K =±0.1,and
1 IG VD = 3 V
10 μA
K
Vt =1V.WerequireID =100μAand
ID = ±0.01. Thus, ID
SID =ID/ID =0.01=0.1 K K/K 0.10
Substituting in the expression derived in (a), 0.1= √1
1+2 0.1×0.1RS ⇒RS =45k
To find VGS ,
ID = K(VGS − Vt)2 100=100(VGS −1)2
RD =3k
I =1k(V −|V|)2
D 2p SG t
1 =
1 2
× 1.25(VSG − 2)2
VSG = 3.265 V
VS = VG +3.265 = 2+3.265
= 5.265 V
10 − 5.265
RS = 1 =4.7k
VGS =2V
VGS +IDRS =VSS
DifferentiatingrelativetoVt,wehave 1+ √ 1 2 ∂ID +R ∂ID =0
2+0.1×45=6.5V (c) For V = 5 V and V
2 2ID/kn kn ∂Vt ∂I1
S
∂Vt = −1
Chapter 7–36
SS IDRS =3V
GS
= 2 V,
D √
∂Vt 2knID
∂ID =−
∂Vt √1
+ RS 1
RS= 3 =30k 0.1
SID= √ 1
+RS SID=∂IDVt=− Vt
=1 K 1+2 0.1×0.1×30 7
2k n ID
Vt ∂Vt ID ID +IDRS
2kn
ID 1 K 1
I =7× K =7×±10%=±1.4%
D
7.100 (a) With a fixed VGS ,
1
ID = kn(VGS −Vt)2
2
∂ID =−kn(VGS −Vt) ∂Vt
But
I=1kV2 ⇒V = 2ID
D 2nOV OV kn Thus
2V SID =− t
Q.E.D ForVt =0.5V, t =±5%,and
Vt
VOV =0.25V,tolimit I to+5%we
require SID =1
Vt VOV +2IDRS V
∂I V k(V −V)V
ID D
SID≡ D t=−n GS
t t
Vt ∂Vt ID =−kn(VGS −Vt)Vt
1
2kn(VGS −Vt)2
= − 2Vt = − 2Vt VGS −Vt VOV
ID
Q.E.D
2 × 0.5 ⇒IDRS =0.375V
Vt
Thus −1=−0.25+2IDRS
ForVt =0.5V, Vt =±5%,and Vt
VOV =0.25V,wehave
ForID =0.1mA, 0.375
VDD 10 V
RD 10 k
ID
ID
I
D =SID
ID Vt
V t
Vt
RS= 0.1 =3.75k 7.101
= − 2 × 0.5 × ±5% 0.25
= ∓20%
(b) For fixed bias at the gate VG and a resistance
RS in the source lead, we have VG =VGS +IDRS
where VGS is obtained from
ID = 1kn(VGS −Vt)2 2
R
0
⇒ VGS = Vt + Thus
2ID kn
VDS
VGS
Vt+ 2ID+IDRS=VG kn
G
10 M
VGS =VDD −IDRD
= 10 − 10ID
(a)Vt =1V andkn =0.5mA/V2
7.103
Chapter 7–37
VDD 5 V ~–1 mA
1 mA
ID = 1kn(VGS − Vt)2
2 RD
ID = 1 ×0.5(10−10ID −1)2 2
⇒ID2 −1.84ID +0.81=0 ID = 1.11 mA or 0.73 mA
The first root results in VD = −0.11 V, which is physically meaningless. Thus
ID = 0.73 mA
VG =VD =10−10×0.73=2.7V (b)Vt =2V andkn =1.25mA/V2
ID = 1 ×1.25(10−10ID −2)2 2
⇒ID2 −1.616ID +0.64=0 ID = 0.92 mA or 0.695 mA
The first root can be shown to be physically meaningless, thus
ID = 0.695 mA
VG = VD = 10−10×0.695 = 3.05 V
RG1
RG2
2 ID = 2knVOV
1 = 1 × 8V 2 2 OV
VD
1
7.102
⇒VOV =0.5V
Since the transistor leaves the saturation region of
operation when vD < VOV , we select VD =VOV +2
VD =2.5V
Since IG ≪ ID, we can write
RD = VDD −VD = 5−2.5 =2.5k ID 1
VGS =Vt +VOV =0.8+0.5=1.3V
Thus the voltage drop across RG2 is 1.3 V and that across RG1 is (2.5 − 1.3) = 1.2 V. Thus RG2 is the larger of the two resistances, and we select RG2 = 22 M and find RG1 from
RG1 = 1.2 ⇒RG1 =20.3M RG2 1.3
Specifying all resistors to two significant digits, wehaveRD =2.5k,RG1 =22M,and
RG1 = 20 M.
7.104 RB1 × 3 = 0.710 RB1 + RB2
⇒ RB2 = 3.225 RB1
Given that RB1 and RB2 are 1% resistors, the maximum and minimum values of the ratio RB2/RB1 will be 3.225 × 1.02 = 3.2895 and 3.225 × 0.98 = 3.1605. The resulting VBE will be 0.699 V and 0.721 V, respectively. Correspondingly, IC will be
5 V
0
RD ID
R
V V V
D G GS
ID = 0.2 = 1 × 10(VGS − Vt )2 2
⇒VGS =1.2V
5 − 1.2
RD= 0.2 =19k
IG
G
ICmax = 1 × e(0.710−0.699)/0.025 = 1.55 mA
and
ICmin = 1 × e(0.710−0.721)/0.025
ICmin = 0.64 mA
VCE will range from
VCEmin =3−1.55×2=−0.1V
which is impossible, implying that the transistor will saturate at this value of dc bias!
VCEmax =3−0.64×2=1.72V
It should be clear that this biasing arrangement is useless, since even the small and inevitable tolerances in RB1 and RB2 caused such huge variations in IC that in one extreme the transistor left the active mode of operation altogether!
7.106
Chapter 7–38
0.06 mA
0.6 mA
VCC 9 V
R RC 3 V 1
VCE 3 V
R 3V R2 E
7.105
Initial design: β = ∞ RC = RE = 3 V = 5 k
0.6
R1+R2= 9 =150k 0.06
VB =VE +VBE =3+0.7=3.7V R2 = 3.7 =61.7k
0.06
R1 =150−61.7=88.3k
Using 5% resistors from Appendix J, and selecting R1 and R2 so as to obtain a VBB that is slightly higher than 3.7 V, we write
R B
VCC 3 V
IB
RC 2 k VCE
R1 =82kandR2 =62k RE =5.1kandRC =5.1k
= 9 × 62 62 + 82
RB =R1∥R2 =62∥82=35.3k
V = V R2
BB CC R1 + R2
= 3.875
To obtain IC = 1 mA, we write
IE=VBB−VBE RE+ RB
1 mA 100
I IB= C =
β
RB = VCC −VBE ≃ 3−0.7 =230k
IB 0.01
Sinceβ rangesfrom50to150andIB isfixedat 0.01 mA, the collector current IC will range from 0.01 × 50 = 0.5 mA to 0.01 × 150 = 1.5 mA. Correspondingly, VCE will range from
(3 − 0.5 × 2) = 1 V to (3 − 1.5 × 2) = 0 V. The latter value implies that the high-β transistor will leave the active region of operation and saturate. Obviously, this bias method is very intolerant of the inevitable variations in β. Thus it is not a good method for biasing the BJT.
β+1 where
=0.01mA
Thus,
I = 3.875−0.7 =0.58mA E 35.3
5.1+ 91
VE = 0.58×5.1 = 3.18
VB = 3.88 V 90
IC =αIE = 91 ×0.58=0.57mA
VC =6.1V
IR2 = VB = 3.88 =0.063mA R2 62
IB = IE = 0.58 =0.006mAand β+1 91
0.57 = β 3.774 − 0.7 β + 1 5.1 + 18 ∥ 13
β+1 5.1(β + 1) + 7.548
Chapter 7–39
IR1 = 0.069 mA 7.107
0.3 mA
β × 3.074 ⇒ β = 75.7
=
VCC 9 V
R1 R 3 V C
0.6 mA
7.108 Refer to Fig. 7.52. (a)IE= VBB−VBE
RE+ RB β+1
= VBB − VBE RB
VB
R2
Initial design: β = ∞ RC=RE= 3V =5k
0.6 mA
3 V
3V
I
E nominal
RE
RE + 101 I =VBB−VBE
E high RB RE + 151
I=VBE−VBE
E low
RB RE + 51
9 0.3
to be equal to IE low
= 30 k VB =VE +VBE =3.7V
R1 + R2 = 3.7
0.95VBB − VBE RE + RB
= VBB − VBE RE + RB
Let’s constrain IE
0.95 and then check IE high :
×
nominal
R2 = 0.3 =12.3k
101
51
R1 =30−12.3=17.7k
1+ RB/RE 101
1+ RB/RE 51
If we select 5% resistors, we will have
RE =RC =5.1k
0.95 =
R1 =18k, R2 =13k 13
⇒RB=5.73 RE
VBB =9× 13+18 =3.774V
VBB − VBE 3.774 − 0.7
For this value,
I =0.946VBB−VBE
18∥13= β+1 91
IE= R∥R = RE+1 2 5.1+
0.593 mA
VE =IERE =3.02V VB = 3.72 V
E nominal RE
V−V
IE low = 0.90 BB
BE
= 0.95 IE nominal
I high =0.963 VBE −VBE CEERE
I =αI = 90 ×0.593=0.586mA
91 E
RE
=1.02I nominal Thus, the maximum allowable ratio is
VC = VCC −ICRC = 9−0.586×5.1 = 6 V
IC falls to the value obtained in Problem 7.106, namely, 0.57 mA at the value of β obtained from
IC =α
VBB − VBE RE+R1∥R2
VBB − VBE
RB RE
(b)IE =
β+1 β+1
= 5.73
RE 1+RB/RE
IERE = VBB −VBE 1+ 5.73
β+1
VCC = VBB − VBE 3 1 + 5.73 101
⇒ VBB = VBE + 0.352VCC (c)VCC =5V
VBB = 0.7+0.352×5 = 2.46 V
7.109
Chapter 7–40
5 V
RC
IB
IC
VC
VE IE
RE
5 V
RE = VCC/3 = 5/3 =3.33k
IE 0.5 RB
RB =5.73×RE =19.08k V=V R2
BB CC R1 + R2 2.46 = 5 R2
R1 + R2
2.46R =5 R1R2 1R+RB
= 5 × 19.08
Required:IC =0.5mAandVC =VE +2. (a) β = ∞
VB = 0
VE =−0.7V
⇒R1 =38.8k 1
R2 = 1 −
= 37.5 k
= R
VC =VE +2=−0.7+2=+1.3V
1
2
=5R
1
RBR1 EE
VE − (−5) IE = 0.5 = R
4.3
(d)VCE =VCC −RCIG
1 = 5−RC ×0.99×0.5 ⇒RC =8.1k
Check design:
V =V R2 =5× 37.5
BB CC R1 +R2 37.5+38.8
= 2.46 V
RB =R1∥R2 =37.5∥38.8=19.07k
2.46−0.7
IE nominal = 19.07 = 0.5 mA
3.33+ 101
I = 2.46−0.7 =0.475mA E low 19.07
⇒RE =8.6k
RC =
VCC −VC 5−1.3
I = 0.5 =7.4k
C
(b) βmin = 50
IBmax = IE = 0.5 ≃0.01mA
51 51
IERE = 0.5×8.6 = 4.3 V
IBmaxRBmax = 0.1IERE = 0.43 V RBmax = 0.43 =43k
0.01
(c) Standard 5% resistors:
RB =43k
RE =8.2k
R =7.5k 3.33+ C
51
which is 5% lower than I , and
(d)β =∞:
VB =0, VE =−0.7V
IE = −0.7−(−5) =0.52mA 8.2
IC = 0.52 mA
VC = 5−0.52×7.5 = 1.1 V
E
I high =
2.46−0.7
E nominal =0.509mA
3.33 +
19.07 151
which is 1.8% higher than I . E nominal
β = 50:
IE = 5−0.7 =0.48mA
VE =−5+0.48×8.2=−1.064V VB =−0.364V
IC =αIE = 50 ×0.48=0.47mA 51
where β is the increased value of 150, IC = 150 ×0.435mA
151
= 0.432 mA
Thus,
IC =0.432−0.39=0.042mA for a percentage increase of
IC ×100 = 0.042 ×100 = 10.8%
Chapter 7–41
8.2 + 43 51
VC = 5−0.47×7.5 = 1.475 V
7.110
3 V
IC
7.111
RB
VC =VCEsat +1V = 1.3 V
RC
VC
0.7 V
0.39
IE/(b 1)
3 V IE
RC
IC
IE
VC
0.4 mA
RE
3 V RE = −0.7 − (−3)
0.4
IE = 3−1.3 =0.5mA RC
=5.75k
⇒RC =3.4k
IB = IE = 0.5 ≃ 0.005 mA
To maximize gain while allowing for ±1 V signal swing at the collector, design for the lowest possible VC consistent with
VC −1=−0.7+VCEsat =−0.7+0.3=−0.4V
VC =0.6V
RC = VCC −VC = 3−0.6 =6.2k
IC 0.39
As temperature increases from 25◦C to 125◦C,
(i.e., by 100◦C), VBE decreases by 2 mV × 100 =
0.2V −200mV.ThusIE increasesby R =
E
0.2 V = 0.035 mA to become 0.435 mA. The 5.75 k
collector current becomes
IC = β ×0.435 β+1
β + 1 101 VC = VBE + IB RB
1.3=0.7+0.005×RB ⇒RB =120k Standard 5% resistors: RC =3.3k
RB =120k
If the actual BJT has β = 50, then
IE = VCC −VBE = 3−0.7 =0.41mA
RC + RB 3.3+ 120 β+1 51
VC = 3−IERC = 3−0.41×3.3 = 1.65 V Allowable negative signal swing at the collector
is as follows:
VC −VCEsat =1.65−0.3=1.35V
An equal positive swing is just possible. For β = 150:
IE = 3−0.7 =0.56mA 3.3+ 120
151
VC = 3−IERC = 3−0.56×3.3 = 1.15 V
Allowable negative signal swing at the collector = 1.15 − 0.3 = 0.85 V. An equal positive swing is possible.
3 V
Chapter 7–42
IC 2IB 2IB
RB1
0.7 V
IB
RC
IC 1 mA
7.112
RB
3 V 1.01 mA
0.01 mA
1 mA
Figure 1
IB2 IB
RB2
Figure 2
IC 1
β = 100 = 0.01 mA
RC
IB
=
1.5 V
RB2 = 0.7 = 0.7 IB2 0.01
= 70 k
1.5 = 2IBRB1 + 0.7 0.8 = 2×0.01×RB1 RB1 = 40 k
(a) From the circuit diagram of Fig. 1, we can write
RC = 3−1.5 ≃1.5k 1.01 mA
1.5 = 0.01RB + VBE
= 0.01RB + 0.7
⇒RB =80k (b)Selecting5%resistors,wehave RC =1.5k
RB =82k
IE = VCC −VBE
RC+ RB β+1
= 3−0.7 =0.99mA 1.5+ 82
101
IC =αIE =0.99×0.99=0.98mA
VC = 3−1.5×0.99 = 1.52 V (c) β = ∞:
IC =IE = VCC −VBE = 3−0.7 =1.53mA RC 1.5
VC =0.7V
(d) From the circuit diagram of Fig. 2, we can write
RC = 3−1.5 = 1.5 =1.47k IC +2IB 1.02
For β = ∞:
IB =0, IB2 = 0.7 = 0.7 =0.01mA
RB2 70 IB1 = IB2 = 0.01 mA
VC = 0.01RB1 +0.7 = 0.01×40+0.7 = 1.1 V
IC +0.01= 3−1.1 = 3−1.1 =1.29
IC =1.28mA 7.113
IB
I
IC
VC
RC
1.47
RB
IC =1mA 7.115 I = IC + IB
=11+β
I = 1.01 mA
VC =1.5V=IBRB +VBE 1.5 = 0.01×RB +0.7
RB =80k
7.114 Refer to the circuit in Fig. P7.114. Replacing VCC together with the voltage divider (R1 , R2 ) by its Thévenin equivalent results in the circuit shown below.
IOaIE
IE /(b1)
RB
VBB IE
RE
VCC
β R1I
Chapter 7–43
= IC + IC 1
IO
RE
Q1
I
R2
0
VB
Q2
IO
I =
VCC − VBE1 − VBE2 R1 + R2
VB = IR2 +VBE2 +VBE1
VE3 = VB − VBE3
VE3 =IR2 +VBE2 +VBE1 −VBE3
=(VCC −VBE1 −VBE2) R2 +VBE1 R1 + R2
+VBE2 − VBE3
VE α
IO=R =R (VCC−VBE1−VBE2)R+R
R2 EE 12
+VBE1 +VBE2 −VBE3
Now, for R1 = R2 and the currents in all junctions
equal,
VBE1 = VBE2 = VBE3 = VBE
where V=V2
11 (VCC −2VBE)× +VBE
R
BB CC R1 + R2
IO =
IO = 2R
RE 2
and
RB =(R1∥R2) Now,
VBB = IE RB +VBE +IERE β+1
I= VBB−VBE
E R +(R ∥R)/(β+1)
VCC E
Q.E.D
I=(VB−2VBE)/R2= E12 2
Thus,
IORE = VCC 2
V = VCC +V
B 2 BE
V CC −VBE R2
IC =αIE
=αVCC[R2/(R1 +R2)]−VBE RE +(R1∥R2)/(β+1)
But since I must be equal to IO , we have
VCC = VCC/2−VBE 2RE R2
Thus,
V
ForVCC =10V andVBE =0.7V,
10 − 1.4
R1 =R2 =RE 10 =0.86RE
7.117 Refer to the equivalent circuit in Fig. 7.55(b).
Gv =− Rin gm(RD∥RL∥ro) Rin + Rsig
R =R =R 1 2 E
CC
− 2V BE
To obtain IO = 0.5 mA, 0.5= VCC = 10
2RE 2RE ⇒ RE = 10 k
R1 =R2 =8.6k 7.116
5 V
IE 50.7 R
= −
=− 10 ×3×(10∥20∥100)
VCC
Chapter 7–44
RG gm (RD ∥ RL ∥ ro ) RG +Rsig
10+1 =−17V/V
7.118 (a) Refer to Fig. P7.118. The dc circuit can be obtained by opening all coupling and bypass capacitors, resulting in the circuit shown
in Fig. 1.
R
0.7 V
IO
IO =αIE ≃0.5mA IE =0.5mA
Figure 1
See analysis on figure.
VGS =2−1=1V
VOV =VGS −Vt =1−0.7=0.3V
SinceVD at2.5Vis1.2Vhigherthan
VS +VOV =1+0.3=1.3V,thetransistoris
R R vgs r R R vo G1 G2 gmvgs o D L
⇒R= 5−0.7 =8.6k 0.5
vCmax =0.7−VECsat =0.7−0.3 = +0.4 V
This figure belongs to Problem 7.118.
Rsig
vsig
Rin RGRG1//RG2
5 k 5 k Figure 2
indeed operating in saturation. (Equivalent
VD =2.5VishigherthanVG −Vt =1.3Vby 1.2 V.)
I =1kV2 D 2nOV
0.5= 1kn ×0.33 2
⇒ kn = 11.1 mA/V2
(b) The amplifier small-signal equivalent-circuit
model is shown in Fig. 2.
Rin =RG1∥RG2 =300k∥200k=120k
gm = 2ID = 2×0.5 =3.33mA/V VOV 0.3
ro = VA = 50 =100k
7.119 Refer to Fig. P7.119.
(a) DC bias:
|VOV|=0.3V⇒VSG=|Vtp|+|VOV|=1V
SinceVG =0V,VS =VSG =+1V,and
2.5−1
ID= R =0.3mA
Chapter 7–45
S
⇒ RS = 1.5 = 5 k
0.3 (b)Gv =−gmRD
where
2ID gm = V
OV
2×0.3 = 0.3
= 2 mA/V
ID Gv =−
0.5
Rin gm(ro∥RD∥RL)
Thus,
−10=−2RD ⇒RD =5k
(c)vG =0V(dc)+vsig
vGmin =−vˆsig
vˆD = VD + |Gv |vˆsig
where
VD =−2.5+IDRD =−2.5+0.3×5=−1V To remain in saturation,
vˆD ≤ vˆG +|Vtp|
−1 + 10 vˆsig ≤ −vˆsig + 0.7
Satisfying this constraint with equality gives vˆsig = 0.154 V
and the corresponding output voltage
vˆd =|Gv |vˆsig =1.54V
(d) If vˆsig = 50 mV, then
VD + |Gv |vˆsig = −vˆsig + |Vtp|
where
VD =−2.5+IDRD =−2.5+0.3RD
and
|Gv | = gmRD = 2RD
Thus
−2.5 + 0.3RD + 2RDvˆsig = −vˆsig + |Vtp| −2.5+0.3RD +2RD ×0.05=−0.05+0.7 0.4RD =3.15
⇒RD =7.875k
Gv =−gmRD =−2×7.875=−15.75V/V
=−
120 120 + 120
×3.33×(100∥5∥5)
Rin +Rsig
= −4.1 V/V
(c)VG =2V,
vˆGS =2+vˆgs, vˆDS =2.5−|Av|vˆgs where
|Av| = gm(ro ∥RD ∥RL) = 8.1 V/V To remain in saturation,
vˆDS ≥vˆGS −Vt
2.5−8.1vˆgs ≥ 2+vˆgs −0.7
This is satisfied with equality at
vˆgs = 2.5−1.3 =0.132V 9.1
VD =2.5V
The corresponding value of vˆsig is 120 + 120
vˆsig =vˆgs 120 =2×0.132=0.264V The corresponding amplitude at the output
willbe
|Gv |vˆsig = 4.1 × 0.264 = 1.08 V
(d) To be able to double vˆsig without leaving saturation, we must reduce vˆgs to half of what would be its new value; that is, we must keep vˆgs unchanged. This in turn can be achieved by connecting an unbypassed Rs equal to 1/gm,
1
Rs = 3.33mA/V =300
Since vˆgs does not change, the output voltage also will not change, thus vˆo = 1.08 V.
7.120 Refer to Fig. P7.120. Ri2 = 1 =50
=− 10 ×2×(100∥12.5∥10) 10+1
=−9.6V/V
(d) If terminal Y is grounded, the circuit becomes
a CD or source-follower amplifier:
gm2
⇒ gm2 = 50 A/V = 20 mA/V
1
If Q1 is biased at the same point as Q2, then
vz vx
=
=
(RS ∥ro) (RS∥ro)+ 1
gm
Chapter 7–46
gm1 =gm2 =20mA/V id1 = gm1 × 5 (mV) =20×0.005=0.1mA vd1 = id1 × 50
= 0.1 × 50 = 5 mV vo =id1RD =1V
R = 1V =10k D 0.1 mA
7.121 (a) DC bias: Refer to the circuit in Fig. P7.121 with all capacitors eliminated:
Rin atgate=RG =10M
VG =0,thusVS =−VGS,whereVGS canbe
(9.5∥100) = 0.946 V/V (9.5∥100)+ 1
obtained from I=1kV2
2
Looking into terminal Z, we see Ro:
Ro = RS ∥ ro ∥ 1 gm
=9.5∥100∥1 =473 2
(e) If X is grounded, the circuit becomes a CG amplifier.
RD
vsg
RS isig50A
Rsig 100 k
The figure shows the circuit prepared for signal
vy
D 2nOV
0.4 = 1 × 5 × V 2
2 OV ⇒VOV =0.4V
VGS =Vt +0.4=0.8+0.4=1.2V VS = −1.2 V
RS = −1.2−(−5) =9.5k 0.4
To remain in saturation, the minimum drain voltagemustbelimitedtoVG −Vt =
0 − 0.8 = −0.8 V. Now, to allow for 0.8-V negative signal swing, we must have
VD = 0 V and
RD = 5−0 =12.5k 0.4
(b)gm = 2ID = 2×0.4 =2mA/V VOV 0.4
ro = VA = 40 = 100 k ID 0.4
(c)IfterminalZisconnectedtoground,the circuit becomes a CS amplifier,
Gv =−vy = RG ×−gm(ro∥RD∥RL) vsig RG +Rsig
calculations. v =i × R ∥R ∥ 1
sg sig sig
S gm 1
100 ∥ 9.5 ∥
= 50 × 10−3(mA)
2
(k)
= 0.024 V
vy =(gmRD)vsg
= (2 × 12.5) × 0.024 = 0.6 V
7.122 (a) Refer to the circuit of Fig. P7.122(a): vo1 10 10
Avo ≡ v = 1 = 1 =0.99V/V i 10+ 10+
gm 10
Ro = 1 ∥10k=0.1∥10=99 gm
(b)RefertoFig.P7.122(b): VD =5VGS =5×0.8=4V
Rin =10k∥
ID = knV2 1+ DS 2OV VA
1 4 ID = 2 ×5×0.22 1+ 60
= 0.107 mA
The current in the voltage divider is
I= VD = 4 =1.6μA=0.0016mA R1 + R2 2.5
Thus the current through RD will be (0.107 + 0.0016) ≃ 0.109 mA and
=10∥0.1=99 v = 1/g =10(5∥2)=14.3V/V
Chapter 7–47
1 1V
vo5∥2 i2 m
gm
(c) vi2 = (Avovi) Rin Rin + Ro
= 0.99 × vi × ≃ 0.5vi
99 99+99
vo = 14.3 × vi2 = 14.3 × 0.5vi
VDD 10 V RD
v vi
o =7.15V/V 7.123 (a)DCbias:
V −V RD= DD D=
10−4 0.109
=55k (b)gm = 2ID = 2×0.107 =1.07mA/V
0.109
VOV 0.2
R2 2 M
ro = VA = 60 = 561 k ID 0.107
(c) Upon replacing the MOSFET with its hybrid-π model, we obtain the small-signal equivalent circuit of the amplifier, shown in Fig. 2.
Node equation at the output:
vo +vo+vo−vgs+gmvgs=0
RD ro R2
VD
ID
VGS
VGS=Vt+VOV
= 0.6+0.2 = 0.8 V
From the voltage divider (R1 , R2 : see Fig. 1), we can write
1 1 1 1 vo R+r+R =−gm 1−gR vgs
R1 0.5 M Do2m2
Figure 1
A
Thus,
1
R 0.5 V =V 1 =V
vo=−gm(RD∥ro∥R2) 1−gR vgs (1) m2
Next, we express vgs in terms of vsig and vo using superposition:
v=v R2 +v R1 (2)
GS DR+R D0.5+2 12
gs
(vo vgs)⁄R2 R2
gmvgs
sigR +R 1 2
oR +R 1 2
This figure belongs to Problem 7.123(c).
vsig
R1
vgs
vo
RD
ro
Figure 2
Substituting for vgs from Eq. (2) into Eq. (1) yields
v =−Av o
where
A=gm(RD∥ro∥R2) 1−gmR2
Thus,
R1 +R2 v −AR2
o = R1+R2
vsig1+AR1 12
R2 −Av R1 sigR +R oR +R
VOV = 0.2 V VGS = Vt + VOV
=0.6+0.2=0.8V
From the voltage divider (R1 , R2 : see Fig. 1), we
0.5 VD =0.5VD 0.5 + 0.5
Chapter 7–48
12 12 1
canwrite
VGS = R1 VD =
R R vo1+A1 =−A2vsig
R1 + R2
VD =2VGS =1.6V
Thus
R1 +R2
I=1kV2 D 2n OV
R1+R2 = −R2/R1
1+ 1+R2/R1 A
=2×5×0.2 =0.1mA VD 1.6 V
R2/R1 VDD−VD
Thus,
vo =− vsig
Substituting numerical values yields
2/0.5 1+(2/0.5)
Idivider = 1M = 1M =1.6μA IRD = 0.1 + 0.0016 ≃ 0.102 mA
1+R2/R1 RD = 1 + gm(RD ∥ ro ∥ R2)(1 − 1/gmR2)
IRD
VOV 0.2
=82.4k
=
(b)gm = 2ID = 2×0.1 =1mA/V
10−1.6 0.102
Q.E.D
vo vsig
(c) Replacing the MOSFET with its T model results in the amplifier equivalent circuit shown in Fig. 2. At the output node,
−
= 1+
vo =i[RD∥(R1+R2)] vo =iR′D
1.07(55∥561∥2000)(1−1/1.07×2000) =− 4
1+5 52.6
= −3.65 V/V
Note that the gain is nearly equal to −R2/R1 = − 4, which is the gain of an op amp connected in the inverting configuration.
(1) vo
R2 bvo
R1
i
1/gm
RD
0
7.124 (a) DC bias:
i
V DD
10 V
RD
VD
vsig where R′D = RD ∥ (R1 + R2). The voltage at the
R2 0.5 M
VGS
Figure 2
gate is a fraction β of vo with β= R1
R1 0.5 M
Figure 1
R1 + R2
Now, the current i can be found from
i= vsig −βvo =gmvsig −βgmvo (2) 1/gm
Substituting for i from Eq. (2) into Eq. (1) yields
7.125 Refer to the circuit of Fig. P7.125. IC = α(VBB −VBE)
RE+ RB β+1
where
R2 15
VBB =VCC R +R =15× 15+27 =5.357V
2 1
RB =R1∥R2 =15∥27=9.643k
IC = 0.99(5.357 − 0.7) = 1.85 mA 2.4 + 9.643
101 1.85 mA
vo =(gmvsig −βgmvo)R′D
Chapter 7–49
Thus
v o = gm R′D vsig 1+βgmR′D
1/β = 1/β
=
1+g R′ mD
1 + (R2/R1)
Q.E.D
(3)
1 + R /R 1+ 2 1
gmR′D
The input resistance Rin can be obtained as
follows: Rin = vsig
i
Substituting for i from Eq. (1) yields
R = vsig R′ in vo D
and replacing vsig by the inverse of the gain vo
expression in Eq. (3) gives
1 1
IC gm = V
= 0.025 V = 74 mA/V rπ = β = 100 = 1.35 k
gm 74
Replacing the BJT with its hybrid-π model results in the equivalent circuit shown at the bottom of the page:
Rin = R1 ∥R2 ∥rπ = RB ∥rπ = 9.643∥1.35 = 1.18 k
vπ = Rin = 1.18 =0.371V/V
T
Rin = R′D g R′ + 1 + (R /R ) mD21v
1.18 + 2
vsig Rin + Rsig
1 R 1+g R′ 1
m 1 2
(d) Substituting numerical values:
R =
ing mDR+R
Q.E.D
o =−gm(RC∥RL) vπ
= −74(3.9∥2) = −97.83
vo = −0.371 × 97.83 = −36.3 V/V
vsig
7.126 RefertothecircuitofFig.P7.125. DC design:
vo vsig
=
1 + (0.5/0.5)
1 + (0.5/0.5)
1×(82.4∥1000) = 1.95 V/V
=
1 + 2
1+2 76.13
VB =5V, VE =4.3V For
VBE =0.7V
Notethatthegain≃1+ R2 =2,similartothat R1
of an op amp connected in the noninverting configuration!
RE = VE = 4.3 = 2.15 k 1 0.5 IE2
Rin = 1 1+1×(82.4∥1000)0.5+0.5 = 39.1 k
This figure belongs to Problem 7.125.
Rsig
IE = 2 mA,
IR2 =0.2mA, R2 = 5 =25k
0.2 IB=IE =2≃0.02mA
vo vsig RRvprpgmvpRCRL
12
β+1 101
Rin
IR1 = IR2 + IB = 0.2 + 0.02 = 0.22 mA VCC −VB 15−5
which is slightly higher than the required gain, andwewillobtain
VC =15−5.1×1.84=5.6V
which allows for only 1.2-V negative signal
swing.
7.127 Refer to the circuit of Fig. P7.125: IC = α(VBB −VBE)
RE+ RB β+1
R2 47
VBB =VCCR +R =15×47+82=5.465V
2 1
RB =R1∥R2 =47∥82=29.88k
0.99(5.465 − 0.7)
IC = 29.88 = 0.63 mA
7.2 +
R1 = I = 0.22 =45.5k R1
Chapter 7–50
Choosing 5% resistors:
RE =2.2k, R1 =47k, For these values,
IE= VBB−VBE
RE+ RB β+1
where
R2 =24k
24
VBB =VCCR +R =15×24+47=5.07V
where
R2
1 2
RB =R1∥R2 =47∥24=15.89k
IE = 5.07 − 0.7 2.2 + 15.89
= 1.85 mA
VB = IERE +VBE = 1.85×2.2+0.7 = 4.8 V
101
I =αI =0.99×1.85=1.84mA
101
IC 0.63
gm = V = 0.025 =25.2mA/V
CET
gm=IC =1.84=73.4mA/V VT 0.025
rπ = β = 100 =1.36k gm 73.4
rπ=β=100=4k gm 25.2
Rin =R1∥R2∥rπ =RB∥rπ = 29.88∥4 = 3.5 k
vπ = 3.5 =0.636V/V vsig 3.5 + 2
vo = −gm(RC ∥RL) vπ
= −25.2(12 ∥ 2) = −43.2 V/V
vo = −0.636 × 43.2 = −27.5 V/V
v sig
Comparing the results above to those of Problem 7.125, we see that raising the resistance values has indeed resulted in increasing the transmission from source to transistor base, from 0.371 V/V to 0.636 V/V. However, because IC has decreased and gm has correspondingly decreased, the gain from base to collector has decreased by a larger factor (from 97.83 V/V to 43.2 V/V), with the result that the overall gain has in fact decreased (from 36.3 V/V to 27.5 V/V). Thus, this is not a successful strategy!
7.128 Refer to the circuit of Fig. P7.128.
DCvoltagedropacrossRB =0.2V,and
Rin =R1∥R2∥rπ =47∥24∥1.36=1.25k vπ = Rin = 1.25 = 0.385 V/V
vsig Rin + Rsig 1.25 + 2 For an overall gain of −40 V/V,
vo =− 40 =−104V/V
v π
But
vo vπ
0.385
= −gm(RC ∥RL)
−104 = −73.4 (RC ∥ 2)
(RC ∥ 2) = 1.416
RC =4.86k
We can select either 4.7 k or 5.1 k. With 4.7 k, the gain will be
vo =−0.385×73.4×(4.7∥2)=−39.6V/V v sig
which is slightly lower than the required −40 V/V, and we will obtain
VC =15−4.7×1.84=6.4V
allowing for about 2 V of negative signal swing at the collector. If we choose 5.1 k, the gain willbe
vo =−0.385×73.4×(5.1∥2)=−40.6V/V vsig
IBRB = 0.2 V I
β+1RB =0.2V
IR =0.2×101 (1) B
Rin =RB∥rπ =10k RB∥VT =10
= 10
RB + 0.025 × 101 I
⇒RC =21.2k
Selecting 5% resistors, we find
RB =91k
RC =22k
and specifying I to one significant digit gives I=0.2mA
gm=αIC≃0.2=8mA/V VT 0.025
Avo =−gmRC =−8×22=−176V/V
β 100 rπ=g=8=12.5k
m
Rin =RB ∥rπ =91∥12.5=11k
11
Gv = −20 + 11 × 8(22∥20)
= −29.7 V/V
7.129 Refer to the circuit of Fig. P7.129.
(a) IE = 0.5 mA. Writing a loop equation for the base–emitter circuit results in
= 10 0.025×101
R × 0.025 × 101
B I=10
Chapter 7–51
IB
RB ∥ 0.025
I/(β + 1) RB ∥ I
0.025 × 101RB IRB + 0.025 × 101
(2)
= 10
Substituting for IRB from Eq. (1) yields
0.025 × 101R
B = 10
0.2×101+0.025×101
0.025RB = 10 0.225
⇒RB =90k
I =
0.2 × 101 90
= 0.22 mA
To maximize the open-circuit voltage gain between base and collector while ensuring that the instantaneous collector voltage does not fall below(vB −0.4)whenvbe isashighas5mV,we impose the constraint
VC −|Avo|×0.005 = VB +0.005−0.4 where
VC =VCC −ICRC
= 5 − 0.99 × 0.22RC
IBRsig +VBE +IERE =3
IE Rsig +VBE +IERE =3
β+1
0.5 ×2.5+0.7+0.5RE = 3
= 5 − 0.22RC |Avo| = gmRC =
and
0.99×0.22
0.025 RC = 8.7RC
101
⇒RE =4.6k
(b)IC =αIE ≃0.5mA VC = 0.5 = 3−0.5RC ⇒RC =5k
(c)gm = IC = 0.5mA =20mA/V VT 0.025 V
rπ = β = 100 = 5 k gm 20
vsig
= −44.4 V/V
gmvp RC
VB =−0.22 ×90=−0.2V 101
Thus,
5 − 0.22RC − 8.7RC × 0.005 = −0.2 − 0.395
This figure belongs to Problem 7.129.
Rsig
vsig rp vp
Gv = vo =− 5 ×20×(5∥10)
5 + 2.5
vo
RL
This figure belongs to Problem 7.130.
Chapter 7–52
7.130 Refer to the circuit of Fig. P7.130. (a) DC analysis of each of the two stages:
gm = IC ≃ 0.1mA =4mA/V VT 0.025 V
Note that the emitter has a resistance Re = 250 .
Rin =200k∥(β+1)(re +Re) = 200 ∥ [101 × (0.25 + 0.25)] =200∥50.5=40.3k
vb vsig
vo
V = V R2 = 15 47
BB CC R1 +R2 100+47
RB =R1∥R2 =100∥47=32k IE = VBB −VBE
RE+ RB β + 1
3.9 + 101
VC = VCC −ICRC = 15−1×6.8 = 8.2 V
(b) See figure above. gm = IC = 40 mA/V
VT
rπ = β = 2.5 k gm
(c)Rin1 =R1∥R2∥rπ =RB∥rπ =32∥2.5
= 2.32 k
= 4.8 V
4.8−0.7 32
=
= −α Total resistance in emitter
= 0.97 mA ≃ 1 mA IC =αIE ≃1mA
=
Total resistance in collector
Rin = 40.3 = 0.668 V/V Rin +Rsig 40.3+20
vb1 Rin 2.32
≃− 20∥20 =−20V/V 0.25+0.25
Gv = vo =−0.668×20=−13.4V/V v sig
For vbe to be limited to 5 mV, the signal between base and ground will be 10 mV (because of the
5 mV across Re). The limit on vsig can be obtained by dividing the 10 mV by vb/vsig,
vˆsig = 10mV =15mV 0.668
Correspondingly, at the output we have
vˆo =|Gv|vˆsig =13.4×15=200mV=0.2V
v =R +R =2.32+5=0.32V/V sig in sig
v
b
(d)Rin2 =R1∥R2∥rπ =Rin1 =2.32k vb2 =vb2 =−gm(RC∥Rin2)
7.132 (a)
200 k
vb1 vπ1
= −40(6.8 ∥ 2.32) = −69.2 V/V
(e) vo = vo = −gm(RC ∥RL) vb2 vπ2
0.5 mA
VC
0.495 mA
0.5 mA
200
= −40(6.8 ∥ 2) = −61.8 V/V
(f) vo = vo × vb2 × vb1 = −61.8
vsig vb2 vb1 vsig
× − 69.2 × 0.32 = 1368.5 V/V
7.131 Refer to the circuit in Fig. P7.131: IE =0.1mA
re=VT =25mV=250 IE 0.1 mA
0.005 mA
Figure 1
From Fig. 1 we see that
IC = 0.495 mA
VC =IB ×200k+IE ×0.2k+VBE = 0.005×200+0.5×0.2+0.7
= 1.18 V
(b)
100 k
vo ie 5 k
Chapter 7–53
ie
re 50
Rsig 50
Rin re 50
vv oi
200 200 k
vi
vo
vsig
i
re 50 200
20 k
i
= −vsig = −vsig 100 0.1 k
At the output node,
vo =−αie(5∥100)
= αvsig (5∥100) 0.1
Figure 2 FromFig.2,wehave
vo = α5∥100 ≃ 47.6 V/V vsig 0.1
7.134 (a)IE = 3−0.7 1+ 100
g =IC =0.495≃20mA/V m VT 0.025
VT
re=I =50
E
i= vi = vi
β = 50: IE =
β+1
2.3
100 =0.78mA
re + Re = vi =
50 + 200
vi =4vi, mA
1+51
VE =IERE =0.78V
VB =VE +0.7=1.48V β = 200:
250
Node equation at the output:
0.25k vo +αi+vo−vi =0
2.3
100 =1.54mA
20 200 vo+0.99×4vi+vo −vi =0
200 200
IE =
VE =IERE =1.54V
20
1 1
1+201
vo 20 + 200
vo = −71.9 V/V
VB =VE +0.7=2.24V
(b)Rin =100∥(β+1)[re +(1∥1)] = 100∥(β + 1)(re + 0.5)
β = 50:
re = VT = 25mV =32.1 IE 0.78mA
Rin =100∥[51×(0.0321+0.5)] = 21.3 k
β=200:
re = VT = 25mV =16.2 IE 1.54 mA
1 =−vi 4×0.99− 200
vi
7.133 Refer to the circuit in Fig. P7.133.
Thedcemittercurrentisequalto0.5mA,and IC =αIE ≃0.5mA;also,
re=VT =25mV=50 IE 0.5 mA
Rin =re =50
ie = −vsig = −vsig re + Rsig 50 + 50
Rin = 100∥[201×(0.0162+0.5)]
= 50.9 k
(c)vb=Rin vsig Rin+Rsig
vo= (1∥1) = 500 (rein)
io = vo × 130.4 = 0.964×65.2 ii vb 2
7.136 Refer to the circuit in Fig. P7.136.
For dc analysis, open-circuit the two coupling
capacitors. Then replace the 9-V source and the two 20-k resistors by their Thévenin equivalent, namely, a 4.5-V source and a 10-k series resistance. The latter can be added to the 10-k resistor that is connected to the base. The result is the circuit shown in Fig. 1, which can be used to calculate IE .
Chapter 7–54
= 62.9 A/A
Rout=3.3∥ re+β+1
vb (1∥1)+re β = 50:
500+re = 0.68 V/V
100 100
=3.3∥ 0.0463+ = 0.789 k = 789
vb vsig
vo vb
=
21.3 21.3 + 10
101
v vsig
o
=
500 500 + 32.1
= 0.94 V/V = 0.68 × 0.94 = 0.64 V/V
β = 200:
vb = vsig
vo = vb
50.9 50.9 + 10
= 0.836 V/V = 0.969 V/V
500 500 + 16.2
9 V
vo = 0.836 × 0.969 = 0.81 V/V v sig
7.135 Refer to the circuit in Fig. P7.135.
4.5 V
20 k
IE =
3 − 0.7 3.3 + 100
IE
2 k
2.3
β+1
= 0.54 mA
=
re = VT = 25mV =46.3 IE 0.54 mA
Rin =(β+1)[re +(3.3∥2)]
= 101 × (0.0463 + 1.245)
3.3 + 100 101
Figure 1 (a)IE = 4.5−0.7
20 2+ β+1
3.8 = 1.73 mA 2+ 20
= 130.4 k
vb = Rin =
vsig Rin + Rsig = 0.566 V/V
vo = 3.3∥2
vb (3.3∥2)+re
=
IC =αIE =0.99×1.73mA
130.4 130.4 + 100
101 = 1.71 mA
IC
gm = = 68.4 mA/V
=
1.245 1.245+0.0463
VT
re = VT = 25mV =14.5
IE 1.73 mA = 0.0145 k
rπ =(β+1)re =101×0.0145 =1.4645k
= 0.964 V/V
vo = 0.566 × 0.964 = 0.55 V/V
vsig
io= vo
ii=vi= vb
Rin 130.4 k
2 k
(b) Replacing the BJT with its T model (without ro) and replacing the capacitors with short circuits
Chapter 7–55
results in the equivalent-circuit model shown in Fig. 2.
Figure 2 From Fig. 2 we see that
re
ve= ie+ie10 (10∥2)
re vb=ve+iere=ie(10∥2) 1+10 +iere
i =(1−α)i +i re i ee10
=ie +ire β + 1 e 10
Figure 3
Thus,
Rin = 20 k∥Rib =20k∥(β+1)(Re +2) = 20 ∥ 101 × 2.0145
= 18.21 k
which is greatly reduced because of the absence of bootstrapping. The latter causes the lower node of the 10-k base-biasing resistor to rise with the output voltage, thus causing a much reduced signal current in the 10-k resistor and a correspondingly larger effective resistance across the amplifier input.
The reduced Rin will result in a reduction in vb/vsig,
18.21 28.21
We can now obtain Rin from
re
vb (10∥2) 1+10 +re Rin≡i= 1 re
v R
i + b=in=
β+1 10 vsig Rin + Rsig re = 0.646 V/V
(β +1)(10∥2) 1+ 10 +(β +1)re
=re vo2
1+(β +1) 10
= Gv ≡
= 0.993 vo = 0.646 × 0.993
= 101×(10∥2)×(1+0.00145)+101×0.0145 1 + 101 × 0.00145
= 168.577 + 1.4645 = 148.3 k 1 + 0.14645
= 0.64 V/V
which is much reduced relative to the value
obtained with bootstrapping.
7.137
(a) Applying Thévenin’s theorem to the base-biasing circuit of Q1 results in the dc circuit shown below. From our partial analysis on the figure, we can write
IE1 =0.1mA
IE2 =5mA
VB1 can be obtained as
VB1 =2.5−2μA×0.5M=1.5V
vb
2 + 0.0145 v sig
vb vsig
= Rin = 148.3 = 0.937 Rin + Rsig 148.3 + 10
re
vo ve ie 1+10 (10∥2)
v=v= re
b b ie 1+10 (10∥2)+iere
= 1.00145 × (10 ∥ 2) 1.00145 × (10 ∥ 2) + 0.0145
= 0.991 V/V
Gv ≡ vo = 0.937×0.991 = 0.93 V/V
v sig
(c) When CB is open-circuited, the equivalent circuit becomes that shown in Fig. 3.
Chapter 7–56
0.5 M
2.5 V
Rin =0.5M∥[51×(0.25+101.5)]k
= 0.5 M∥5.2 M
100 2 A 51
100 A 0.1 mA
0.05 mA 50 A
50 A
= 456 k
ve1 = Rib =
vb1 Rib + re1 = 0.9975 V/V
101.5 101.5 + 0.25
(d) vb1 = Rin vsig Rin + Rsig
= 456 456 + 100
5 mA
=0.82V/V (e) vo = 0.82 × 0.9975 × 0.995 = 0.814 V/V
and VB2 can be found as VB2 =VB1 −0.7=0.8V
v sig
7.138 We need to raise fH by a factor of
2MHz =4.Thus 500 kHz
1+gmRe =4 ⇒ Re = 3
gm
Since
gm = IC = 1mA =40mA/V
VT 0.025 V Re= 3 =75
0.04
The new value of fL will be
100 Hz 100
fL = 1+g R = 4 =25Hz
me
and the midband gain will become
(b) Refer to the circuit in Fig. P7.137. With a load resistance RL = 1 k connected to the
output terminal, the voltage found as
vo = RL vb2 RL +re1
where
re2=25mV=5 5 mA
vo = 1000 vb2 1000 + 5
gain
v o /v b2
can
be
= 0.995 V/V
Rib2 =(β2 +1)(re2 +RL)
= 101 × 1.005 = 101.5 k
(c) Rin = 1 M∥1 M∥(β + 1)(re1 + Rib2) where
re = VT = 25mV =250=0.25k IE1 0.1 mA
|AM|=
100 = 100 =25V/V 1+gmRe 4