CS计算机代考程序代写 Chapter 16

Chapter 16
SolutionstoExerciseswithintheChapter
Ex: 16.1 Observe the two PMOS transistors in series with gates connected to inputs A and B, and the parallel path with three PMOS transistors in series with gates connected to inputs C, D, and E. Therefore, the PUN realizes the function
Y = A ̄ B ̄ + C ̄ D ̄ E ̄ . Ex: 16.2
VDD 􏰔 􏰀1.0 V ID 􏰔 20 􏱌A RD
⇒ W = 8.22 L
TheparametersVOH,VOL,VIL,VIH andthus NML and NMH do not depend on the value R (but on Vx ) and thus their values will not change.
The current IDD drawn from the power supply during the low-output interval becomes
IDD = VDD − VOL = 1.0 − 0.033 = 96.7 μA R D 1 0
and the power drawn from the supply during the low-output interval is
PD =VDDID =1.0×96.7=96.7μW
Since the inverter spends half of the time in this
Exercise 16–1
VOL 􏰔 40 mV
Substituting in the expression given for r D S , we get
1
× (1.0 − 0.35)
⇒ L =1.42
The value of RD can be obtained from
RD = VDD −VOL ID
1.0 − 0.04
= 0.02 = 48 k􏱹
When the switch is open, ID = 0 and
PDrawn =VDDID =0
When the switch is closed, ID = 20 μA, and PDrawn =VDDID =1.0×20=20μW
Ex: 16.3 If Vx remains unchanged at 0.0225 V, then
state, we have
PDaverage = 1 PD = 48 μW
􏰀1.0 V
RefertoFig.1.
2 Ex:16.4 knRD = 1
Figure 1
Vx For RD = 10 k􏱹 and
kn =k′ W =0.54×1.5=0.81mA/V2 nL
weobtain
1
Vx = 0.81 × 10 = 0.12 V
Now,
VOH =1.0V
From Eq. (16.22) we get
VOL = 1.0 =0.16V 1+ 1.0−0.35
0.12
From Eq. (16.12) we obtain
VIL =Vt +Vx =0.35+0.12=0.47V From Eq. (16.20) we have
VIH = 0.35+1.63√1.0×0.12−0.12 = 0.80 V
Thus,
NML =VIL −VOL =0.47−0.16=0.31V NMH =VOH −VIH =1.0−0.80=0.20V During the output-low interval, we have
VD D − VO L IDD = RD
rDS = VOL = 40mV =2k􏱹 ID 20 μA
2= W
0.540 × W L
knRD = 1 = 1 Vx 0.0225
=44.44
=
1.0−0.16 10
= 84 μA
For RD to be 10 k􏱹,
kn = 44.44 = 4.444 mA/V2
10
and
PD = 1.0×84 = 84 μW Thus,
PDaverage = 1PD =42μW
Thus,
4.444=0.54× W L2

Ex:16.5 (a) ForVM =0.6V= 1 VDD,the
= 1 =2.9k􏱹 0.43 × 4(1.2 − 0.4)
4
The two output resistances are equal because the inverter is matched.
(d) Using Eq. (16.39), we obtain
VM = r(VDD − |Vtp|) + Vtn r+1
where
|Vtp|=Vtn =0.4V
and
r=μpWp=1×1=1 μnWn 4 2
Thus,
VM = 0.5(1.2−0.4)+0.4 = 0.53 V
0.5 + 1
Ex:16.6 ToobtainVM =2.5V= 2VDD,the
inverter must be matched, thus
Exercise 16–2
inverter must be matched, thus
Wp = μn Wn μp
⇒Wp =4 0.13
2
⇒ Wp = 0.52 μm
(b) VOH =VDD =1.2V
VOL =0V
To obtain VI H , we use Eq. (16.35):
V = 1(5V −2V) IH8DD t
1
= 8(5×1.2−2×0.4)
= 0.65 V
To obtain VI L , we use Eq. (16.36):
VIL = 1(3VDD +2Vt) 8
= 1 (3 × 1.2 + 2 × 0.4) 8
= 0.55 V
The noise margins can now be found as
­ ­
1
μCW=μCW
n ox L
p ox L np
W = μpCox L
W 2μpCox L
NM = V − V
HOHIH np
=1.2−0.65=0.55V
NML =VIL −VOL
= 0.55−0 = 0.55 V
W =2 W (1) Lp Ln
ForvI =VDD =5VandvO =0.2V,QN will be operating in the triode region. Thus,
(c) WithvI =VDD andvO low,theoutput W
resistanceisrDSN: iD =μnCox L
r =1 μC W (V −V) DSN noxLDDt
1 2 (VDD −Vt)VDS − 2VDS
n
W 12
L (5−1)×0.2− 2 ×0.2 1n
n
0.2 = 0.05×
⇒ W = 5.13 ≃ 5
Ln
= 2×5.13 = 10.26 ≃ 10 Lp
= 0.43×1(1.2−0.4) = 2.9 k􏱹 WithvI =0VandvO =VDD,theoutput
resistance is r D S P : W
r =1 μC W (V −|V|) DSP poxLDDt
p

Solutions to End-of-Chapter Problems 16.3 16.1 (a) Ron =rDSN
VDD = 1 (1) A Q
Chapter 16–1
(μnCox) W (VDD −Vtn) Ln
PA
B QPB C QPC
= 1
0.540 × 1.5(1 − 0.35)
= 1.90 k􏱹
(b) Ron =rDSP
= 1 (2)
Y
(μpCox) W (VDD −|Vtp|) Lp
= 1 = 10.26 k􏱹 0.100 × 1.5(1 − 0.35)
(c) From (1) and (2) since Vtn = −|Vtp|, then if Ron are to be equal, then
(μnCox) W =(μpCox) W Ln Lp
⇒ W =μnCox W Lp μpCox Ln
= 540 × 1.5 = 8.1 100
A QNA B QNB C QNC
Figure 1
Y=A+B+C
⇒ Y = A + B + C ⇒ PDN Y=ABC ⇒PUN
The circuit realization is shown in Fig. 1.
16.2 (a) For QN , we have Ron = 1
16.4
A
VDD
QPB C QPC
(μnCox) W (VDD −Vtn) Ln
QPA B
A
B QNB C QNC
Figure 1
For Q P , we have
Ron = 1
Y
QNA
(μpCox) W (VDD −|Vtp|) Lp
Since Vtn = |Vtp|, then for Ron of QP to equal Ron ofQN,
(μpCox) W =(μnCox) W Lp Ln
⇒ W =μnCox W Lp μpCox Ln
= 500 × 1.5 = 6.0 125
(b) For both devices, we have
1
Ron = 0.5 × 1.5 × (1.2 − 0.4) = 1.67 k􏱹
Y = ABC
⇒ Y = ABC ⇒ PDN
Y = A + B + C ⇒ PUN
Figure 1 shows the circuit realization.

16.5
Figure 1 shows the complete CMOS circuit where the PUN is obtained as the dual network of the given PDN. The logic function realized can be written from the PDN as
Chapter 16–2
Y = A(B + C) or equivalently Y = A(B + C)
16.7
Figure 1
Figure 1 shows the complete CMOS logic gate where the PUN is obtained as the dual of the given PDN. The function realized can be found from the PDN as
Y = A + BC or
Y = A + BC
16.6
Figure 1
Figure 1 shows the complete CMOS logic circuit where we have obtained the PDN as the dual of the given PUN. The logic function can be written from the PDN as
Y = A + BC D or equivalently Y = A + BC D
16.8 The given Boolean expression can be written as
Y = AB+CDE
from which the PDN of the circuit in Fig. 1 can be directly obtained.
Figure 1

VDD
CE
AB
Y
AC
BD
E
Figure 1
The PUN can then be found as the dual of the PDN. The complete circuit is shown in Fig. 1.
Figure 1 shows a CMOS realization of the Exclusive-OR function. This circuit is obtained by utilizing the PUN in Fig. 16.10(a) and then finding the dual PDN. Note that two additional inverters are needed to generate A and B, for a total of 12 transistors.
16.10 Y = ABC + ABC + ABC (1) Using this expression to directly synthesize the
PUN we obtain the circuit shown in Fig. 1.
This PUN circuit requires 9 transistors plus three inverters for a total of 15 transistors.
This, of course, does not include the transistors required for the PDN which we shall consider shortly. Inspecting the PUN circuit reveals the potential for eliminating two transistors through what is known as “path merging.” Specifically the two transistors in the top row that are controlled by A can be merged into a single transistor, and the two transistors in the bottom row that are controlled by C can be merged into a single transistor. The result is the 7-transistor PUN shown in Fig. 2.
We next consider the realization of the PDN. A straightforward realization can be obtained by finding the dual of the PUN in Fig. 1. This is shown in Fig. 3. It requires nine transistors
Chapter 16–3
D
16.9
VDD
Y
AA
BB
A
AB
Figure 1
A
A
B
C
B
C
Y
ABC
Figure 3
B
plus three inverters. The latter, of course are the same three inverters needed to obtain the complemented variables in PUN. The circuit in Fig. 3 does not lend itself to path merging, at least not in a straightforward way.

This figure belongs to Problem 16.10, part (a).
VDD
VDD
Chapter 16–4
AAAAA
Path
BBBBB
merging
CCCC
B
C
YY
Figure 2
A direct realization of this expression results in the PDN shown in Fig. 4. This circuit requires 8 transistors (not counting the inverters).
Figure 1
There is, however, an alternative way to synthesize a PDN with a lower number of transistors. We simply obtain Y from the expression in Eq. (1) using DeMorgan’s law as follows:
Y = ABC.ABC.ABC
= (A + B + C)(A + B + C)(A + B + C) (2)
Direct synthesis of Eq. (2) results in the circuit of Fig. 3. However, further manipulation of the expression in (2) results in a more economical realization, as follows:
Y
A
B A
B
Y = AB(A + B + C) + AC(A + B + C) +B A(A+B+C)+BC(A+B+C) +C A(A+B+C)+CB(A+B+C) + C(A + B + C)
= ABC + B C + A B + A C = ABC + A(B + C) + B C
(3)
CBCC
Figure 4
16.11 Direct realization of the given expression results in the PUN of the logic circuit shown in Fig. 1. The PDN shown is obtained as the dual of the PUN. Not shown are the two inverters needed to obtain A and B.

Chapter 16–5
16.13 (a) Even-parity checker:
Y = A B C + ABC + ABC + ABC See Fig. 1 on next page.
(b) This expression can be directly realized with the PDN shown in Fig. 1. Note that the circuit requires 12 transistors in addition to the three inverters needed to generate A, B, and C.
(c) From inspection of the PDN in Fig. 1 we see that we can combine the two transistors controlled by A and the two transistors controlled by A. This results in the PDN realization shown in Fig. 2 which requires 10 transistors, not counting those in the inverters. See Fig. 2 on next page.
Figure 1
16.12 Direct realization of the given expression results in the PUN portion of the circuit shown in Fig. 1. The PDN is obtained as the dual of the PUN. Not shown are the three inverters needed to obtain A, B and C.
A
A
VDD
BC
B
C
B
B
C
C
Y
Figure 3
Figure 1
(d) The PUN in Fig. 3 can be obtained as the dual of the PDN in Fig. 2. Combining the PDN and the PUN gives the complete realization of the even-parity checker.
Note: The number of transistors in the PDN of Fig. 2 can be reduced by 2 by combining the two transistors in the bottom row that are controlled by C, and the two transistors that are controlled by C. The resulting 8-transistor realization is shown in Fig. 4. However, it is not easy to obtain a PUN as a dual of this circuit. See Fig. 4 on next page.

This figure belongs to Problem 16.13, part (a).
Chapter 16–6
Y
AAAA
BBBB
CCCC
This figure belongs to Problem 16.13, part (c).
Figure 1
Y
AA
BBBB
CCCC
Figure 2
Y
A
B
16.14 Odd-parity checker:
Y = AB C + A BC + A BC + A B C
= A(BC + BC) + A(BC + B C) (1)
The Boolean expression in Eq. (1) can be directly realized by the PUN in Fig. 1. Recall that we use for the switch control variables the complements of the variables in the equation. It requires 10 transistors in addition to the three inverters needed to provide A, B and C. The dual of the PUN can be obtained and results in the PDN shown in Fig. 1.
A
B
B
B
C
C
Figure 4

This figure belongs to Problem 16.14.
Chapter 16–7
VDD
AA
BB
CC
PUN
Y
PDN
B
C
B
C
B
B
C
C
C
A
A
B
BC
Figure 1
16.15 S = AB C + A BC + AB C + ABC
=A(BC+BC)+A(BC+BC)
This is the same function as that of the odd-parity checker in Problem 16.13. Thus the realization of the S function will be identical to that in Fig. 1 of Problem 16.13.
As for C0 we write
C0 =ABC+ABC+ABC+ABC
This expression can be minimized as follows:
C0 =(A+A)BC+(B+B)AC+(C+C)AB
= BC + AC + AB = A(B + C) + BC
which can be realized directly by the PUN of the circuit in Fig. 1 where the PDN is obtained as the dual network of the PUN. In addition to the 10 transistors, we need three inverters to generate A, B and C.

This figure belongs to Problem 16.15.
Refer to Fig. 1. Slope of the VTC in the transition region is:
Slope= VOH −VOL VIL −VIH
= 1.5−0.3 =−12V/V 1.1 − 1.2
Chapter 16–8
But the slope can also be expressed as Slope= VM −VOH
VM −VIH Thus,
Figure 1
16.16 NMH =VOH −VIH = 1.2−0.7 = 0.5 V
NML =VIL −VOL
= 0.5−0.1 = 0.4 V
16.17 (a) NMH =VOH −VIH = 1.5−1.2 = 0.3 V
NML =VIL −VOL
= 1.1−0.3 = 0.8 V
VM − 0.3 = −12 VM −1.2
⇒VM =1.13V
(c) The voltage gain in the transition region is
equal to the slope found above, thus Gain = −12 V/V
16.18 NMH =VOH −VIH
= 0.8VDD − 0.6VDD = 0.2VDD
NML =VIL −VOL
= 0.4VDD − 0.1VDD = 0.3VDD
Width of transition region = VI H − VI L
= 0.6VDD − 0.4VDD = 0.2VDD
For a minimum noise margin of 0.25 V, we have NMH =0.25
⇒ 0.2VDD = 0.25
⇒VDD =1.25V
(b)
vO VOH 􏰔 1.5 V
VM M VOL 􏰔 0.3 V
VIL VM VIH
1.1 V 1.2 V
Figure 1
2+0.1 VOH =VDD =1.8V
16.19 (a) Refer to Fig. 16.17. V=V Ron
OL DD R+Ron =1.8× 0.1 =0.086V
Slope 􏰔 1
vI
NMH =VOH −VIH
= 1.8 − 0.8 = 1 V
NML =VIL −VOL
= 0.6 − 0.086 = 0.514 V (b) Refer to Fig. 1.
VOH =VDD−N×0.1×R = 1.8 − N × 0.1 × 2
= 1.8 − 0.2N

VDD R
NMH =VOH −VIH = 1.8−0.9 = 0.9 V
The ideal transfer characteristic is shown in Fig. 1, from which we see that
Gain in transition region = ∞ 16.21
N fan-out inverters
Figure 1
NMH =1.8−0.2N−0.8 = 1 − 0.2N
ForNMH 􏲓NML,wehave 1 − 0.2N 􏲓 0.514
⇒ N 􏲔 2.43
which means
N=2
(c) (i) When the inverter output is low,
1.82
= ≃ 1.54 mW
Chapter 16–9
VOH
V 2 PD = D D
Figure 1 shows a sketch of the VTC where we have approximated the VTC in the transition region by a straight line with a slope equal to the maximum possible small-signal gain, namely 50 V/V. We can use the geometry of the VTC to determineVIH andVIL asfollows:
|Slope| = 50
= VM VIH −VM
Thus,
0.4
50 = VI H − 0.4
⇒VIH =0.408V Similarly,
VOH |Slope|= VIH −VIL
50 = 1 0.408 − VI L
⇒VIL =0.388V
NMH =VOH −VIH
= 1−0.408 = 0.592 V
NML =VIL −VOL
= 0.388−0 = 0.388 V
Since we approximated the VTC in the transition region by a straight line, the large-signal voltage gain will be equal to the small-signal voltage gain,
= −50 V/V
N 􏰁 0.1 mA
vO (V) VOH 􏰔 1 V
VM 􏰔 0.4 V VOL 􏰔 0 V 0
Slope 􏰔 􏰒50 V/V
Slope 􏰔 1 V/V
VIL
M
VIH
VM 􏰔 0.4 V
Figure 1
1 V
vI (V)
R + Ron
2 + 0.1
(ii) When the output is high and the inverter is driving two inverters, the current drawn from the supply is 2 × 0.1 = 0.2 mA and thus the power dissipation is
PD =VDDIDD =1.8×0.2=0.36mW 16.20 For an ideal inverter:
VM =1VDD =0.9V 2
VIL =VIH =VM =0.9V VOL =0V
VOH =VDD =1.8V NML =VIL −VOL
= 0.9 − 0 = 0.9 V vO (V)
VDD 􏰔 􏰀1.8 V
VM 􏰔 􏰀0.9 V
0
VOL 􏰔 0
Gain􏰔􏰿
NML
M
NMH
􏰀0.9 V V VM,VIH, VIL
VOH
􏰀1.8 V
vI (V)
Figure 1

16.22 Here,VOH =0.9V,andVOL =0.0V Also,VIH −VIL ≤0.9/3=0.3V (1)
Now, the noise margins are “within 30% of one other.” Thus, NMH = (1 ± 0.3) NML or
NML = (1 ± 0.3) NMH . Thus, they remain “within” either NMH = 1.3NML or
NML =1.3NMH,inwhichcaseeither NML = 0.769NMH or NMH = 0.769NML
For the former case:
0.769(VOH −VIH)=(VIL −VOL)or 0.769(0.9−VIH)=VIL −0,whence
VIL =0.692−0.769VIH Now,from(1),VIH =VIL +0.3
Thus,
VIL = 0.692−0.769(VIL +0.3)
= 0.461 − 0.769VI L
and VI L = 0.461/1.769 = 0.26 V
whence VIH = 0.3+0.26 = 0.56 V Alternatively, NMH = 0.769NML and (VOH −VIH)=0.769(VIL −VOL)or 0.9−VIH =0.769VIL −0and
VIH =0.9−0.769VIL,with(1),
VIL +0.3=0.9−0.769VIL,and 1.769VIL =0.6,whenceVIL =0.34V and VIH = 0.3+0.34 = 0.64
Thus, overall, VOH = 0.9 V, VOL = 0.0 V, VIH rangesfrom0.56Vto0.64V,and
VIL rangesfrom0.26Vto0.34V,in which case the margins can be as low as NML =VIL −VOL =0.26Vand
NMH =VOH −VIH =0.9−0.64=0.26V and as high as 0.34 V.
Equivalent circuit for output-low state
The output-high level for the simple inverter circuit shown in Fig. 16.12 of the text is
VOH =VDD ⇒VDD =1.0V.
When the output is low, the current drawn from
thesupplycanbecalculatedas
I= VDD =30μA RD + Ron
1.0 Therefore:RD+rDS=30×10−6 =33.3k􏱹
Also:
Chapter 16–10
rDS ×VDD RD +rDS
VOL =0.05V=
⇒rDS =33.3k􏱹× 1.0 =1.67k􏱹
0.05
Hence: RD =33.3K−1.67K=31.6k􏱹
1
W
μnCox L (VGS −Vt)
1
=W
540 × 10−6 × L (1.0 − 0.35)
= 1.67 k􏱹 ⇒ W = 1.7
L
When the output is low:
PD =VDDIDD =1.0×30μA=30μW When the output is high, the transistor is off:
PD = 0 W
16.24 Refer to Example 16.2 from the text: VOH =VDD =1.2V
The power drawn from the supply during the low-output state is
PDD =VDDIDD ⇒50μW=1.2×IDD ⇒IDD =41.7μA
In this case:
IDD=VDD−VOL ⇒41.7μA=1.2−0.05 RD RD
⇒ RD = 27.6 k􏱹
In order to determine W , we note that
X
Therefore, we need to first calculate VX using Eq. (16.22) from the text.
rDS =
16.23 VDD RD
Ron 􏲙 rDS
􏰀
L kR=1/Vork′WR=1
v
nDXnLDV
O
􏰒

VOL = VDD or equivalently VOL = 1+ VDD −Vt
VDD
Chapter 16–11
1+(VDD −Vt)/Vx VX VDD
0.05V=
1.2 = V − 0.3V = 0.054VDD 1.2−0.4 1+ DD DD
1+ 0.04VDD
VX
⇒ VX = 0.8 = 0.035 V
23
′ W 1 Hence, kn L RD = V gives
x
500×10−6 × W ×27.6×103 =
L
1 0.035

NMH =VOH −VIH
= VDD − 0.586VDD = 0.414VDD
NML =VIL −VOL
= 0.34V − 0.054V = 0.286V DD DD DD
ForVDD =1.0V:
Vx =0.04V, VOH =1.0V, VIL =0.34V,
VIH = 0.586 V, VOL = 0.054 V,
NMH =0.414V, NML =0.286V
W =2.1 L
Using Eq. (16.12), we obtain
VIL =Vt +VX =0.4+0.035=0.435V From Eq. (16.14) we obtain
­
PD =VDDID V
− V RD
OL
VM=Vt+ 2(VDD−Vt)Vx+V2x−Vx ­
=VDD× DD Substituting for R from
= 0.4 +
2(1.2 − 0.4)0.035 + 0.0352 − 0.035
D RD= 1
PD =VDD(VDD −0.054VDD)×kn ×0.04VDD P =0.038V3 ×k′ W
VM=0.6V
From Eq. (16.20) we get
­
VIH =Vt +1.63 VDDVx −Vx √
=0.4+1.63 1.2×0.035−0.035=0.7V NMH =VOH −VIH =1.2−0.7=0.5V NML =VIL −VOL =0.435−0.05=0.385V
16.25 Vt = 0.3VDD, VM = VDD/2 From Eq. (16.13), we obtain
knVx we obtain
D DDnL
V
2
=0.038×1.03 ×0.54×10−3 W L
=0.021 W ,mW L
For PD = 100 μW = 0.1 mW, we obtain 0.1=0.021 W
DD −Vt
L
=1
0.54 × 4.9 × 0.04
= 9.4 k􏱹
16.26
(a)vI =0,so QN isoff
QP isinthetrioderegionbutconductszero current, so the output voltage is equal to VDD VOH =VDD =1.0V
(b)vI =VDD,andtheoutputislikelylowerthan Vt,suchthatQP isinthesaturationregionand QN is in the triode region
Và V = 2 x VM= DD
⇒ W =4.9 L
2 VDD =(0.5VDD−0.3VDD)2
RD= 1 VDD knVx
⇒Vx =0.04VDD
VOH =VDD
From Eq. (16.12), we get
VIL =Vt +Vx =0.3VDD +0.04VDD = 0.34VDD
From Eq. (16.20), we obtain
­
VIH=Vt+1.63 VDDVx−Vx
­
= 0.3VDD + 1.63
= 0.586VDD
From Eq. (16.22), we get
VDD × 0.04VDD − 0.04VDD

iDP = 1kp(VDD −Vt)2 2
V2 iDN=kn (VDD−Vt)VOL− OL
2
Equating iDP and iDN yields a quadratic equation that can be solved to obtain
­
VOL =(VDD −Vt)(1− 1−kp/kn) ­
(c)VOL =(1−0.35)(1− 1−1/5.4)=63mV 16.27
VDD
QP
iDP
vO
iDN vI QN
Figure 1
ReferringtoFig.1,wecanassumethatVM >Vt, such that QP operates in the triode region. QN operates in the saturation region.
iDP =
k (V −V)(V −V )−(VDD−VM)2
⇒ Wp = 5.4Wn = 5.4×1.5×65 = 527 nm Siliconarea=WnLn +WpLp
= 1.5×65×65+5.4×1.5×65×65
= 1.5×65×65(1+5.4)
= 40, 560 nm2
(b) VOH =VDD =1V
VOL =0V
To obtain VI H , we use Eq. (16.35):
VIH=1(5VDD−2Vt) 8
= 1(5×1−2×0.35) 8
= 0.5375 V
To obtain VI L , we use Eq. (16.36):
VIL = 1(3VDD +2Vt) 8
= 1(3×1+2×0.35) 8
= 0.4625 V
The noise margins can now be found as NMH =VOH −VIH
= 1 − 0.5375 = 0.4625 V
NML =VIL −VOL
= 0.4625−0 = 0.4625 V
The noise margins are equal at approximately 0.46 V; a result of the matched design of the inverter.
(c) Since the inverter is matched, the output resistances in the two states will be equal. Thus,
W
rDSP =rDSN =1 (μnCox) L (VDD −Vt)
n
Chapter 16–12
p DD t DD M
2
iDN =kn(VM−Vt)2 2
Equating iDP and iDN 1kn(VM −Vt)2 =
22
kp (VDD−Vt)(VDD−VM)−(VDD−VM)
⇒1r(V2 −2VV +V2)= 2MtMt
1V2−VV+VV−1V2 2DD DDt Mt 2M
⇒(r+1)V2 −2(r+1)VV +(r+1)V2 = MtMt
V2 −2V V+V2 DD DDt t
16.29 VOH = 2.5 V
VOL=0V
(a) For the matched case we have Wp = 3.5Wn
VM =1VDD =1.25V 2
2 = 1 =1.9k􏱹 0.54×1.5(1−0.35)
⇒(r+1)(VM −Vt)2 =(VDD −Vt)2 V −V
DD t ⇒ VM = Vt + √r + 1
Eq.(16.35):VIH =1(5VDD−2Vt) 8
= 1(5×2.5−2×0.5) 8
= 1.4375 V
16.28 (a) ToobtainVM =VDD/2,theinverter must be matched, thus
Wp =μn =5.4 Wn μp

Eq.(16.36):VIL=1(3VDD+2Vt) 8
1
= 8(3×2.5+2×0.5)
= 1.0625 V
NMH =NML =1.0625V
Siliconarea=WnLn +WpLp
= 1.5×0.25×0.25+3.5×1.5×0.25×0.25
= 4.5×1.5×0.252 = 0.42 μm2
(b) Wp = Wn (minimum-size design): ­­
Eq.(16.40):r = μp Wp = 1 ×1=0.53 μn Wn 3.5
Eq.(16.39):VM =r(VDD−|Vtp|)+Vtn
r+1 nLn
Chapter 16–13
Siliconarea=WnLn +WpLp
= 1.5×0.25×0.25+2×1.5×0.25×0.25
= 3×1.5×0.252
= 0.28 μm2
Compared to the matched case, the silicon area is reduced by 33%.
16.30 QN will be operating in the triode region, thus
IDn=k′n
W1 (VDD−Vtn)VO− VO2
Ln2
For Vtn = 0.3VDD and VO = 0.1VDD, we have
IDn=k′ W
= 0.53(2.5−0.5)+0.5 0.53+1
= 1.02 V
Thus, VM shifts to the left by 0.23 V. Assuming
VIL shiftsbyapproximatelythesameamount, then
VIL ≃ 1.0625−0.23 ≃ 0.83 V
Since NML = VI L , NML will be reduced by approximately 22% (relative to the matched case).
Siliconarea=WnLn +WpLp
= 1.5×0.25×0.25+1.5×0.25×0.25
= 3×0.252 = 0.19 μm2
which is a reduction of 55% relative to the matched case.
1 2 2 (VDD − 0.3VDD) × 0.1VDD − 2 × 0.1 VDD
=k′(W/L)(0.07V2 −0.005V2 ) n n DD DD
=0.065k′(W/L) V2 Q.E.D. n nDD
For VDD = 1.2 V, k′n = 0.5 mA/V2 and IDn = 0.1 mA, we have
0.1 = 0.065 × 0.5(W/L)n × 1.22 ⇒ W =2.14
Ln
16.31 For v I = +1.5 V, Q N will be conducting andoperatinginthetrioderegionwhileQP will be off. Thus, the incremental resistance to the left of node A will be rDSN ,
1
rDSN =kn(VI −Vtn) ­­1
(c) Wp = 2Wn (a compromise design): Eq.(16.40):r = μp Wp = 1 × 2
= 0.25(1.5−0.4) =3.64k􏱹 Thus,
μn Wn 3.5 1 Eq. (16.39): VM = r(VDD − |Vtp|) + Vtn
= 0.756
3.64 3.64 + 100
= 0.756(2.5 − 0.5) + 0.5 0.756 + 1
= 1.15 V
ForvI =−1.5V, QN willbeoffbut QP willbe operating in the triode region with a resistance rDSP,
1
r+1
va = 100 = 3.5 mV
Thus, relative to the matched case the switching point (VM ) is shifted left by (1.25 − 1.15) = 0.1 V.AssumingthatVIL isreducedby approximately the same amount, then
VIL = 1.0625−0.1 = 0.9625 V
Thus, NML which equals VI L is reduced by about 9% (relative to the matched case).
rDSP = kp(VSGP −|Vtp|)
= 1 = 18.2 k􏱹
0.05(1.5 − 0.4) Thus,
va = 100 18.2 = 15.4 mV 18.2 + 100

16.32 FromEq.(16.39)wehave VM = r(VDD − |Vtp|) + Vtn
r+1
rVM +VM =r(VDD −|Vtp|)+Vtn
r(VDD −|Vtp|−VM)=VM −Vtn
r = 0.6×1.0−0.35 1.0−0.35−0.6×1.0
To obtain VI L , we use Eq. (16.36): =51
V −V ⇒r= M tn
ToobtainVIH,weuseEq.(16.35): 1
Q.E.D. ForVDD =1.0V,Vtn =|Vtp|=0.35V,to
Chapter 16–14
A=WnL+WpL=L(Wn +Wp)
= 0.13(0.195 + 0.78) = 0.127 μm2
(b) VOH =VDD =1.3V
VOL =0V
VDD −|Vtp|−VM obtainVM =0.6VDD,weneed
VIH = 8(5VDD −2Vt) 1
= 8(5×1.3−2×0.4) = 0.7125 V
But,
r= μpWp μn Wn
­
5= 1×Wp 5.4 Wn
Wp =52 ×5.4=135 Wn
VIL = 8(3VDD +2Vt) = 1(3×1.3+2×0.4)
8
= 0.5875 V
We can now compute the noise margins as
NMH =VOH −VIH =1.3−0.7125 =0.5875V≃0.59V
NML =VIL −VOL =0.5875−0 = 0.5875 V ≃ 0.59 V
ForvI =VIH =0.7125V,wecanobtainthe correspondingvalueofvO bysubstitutinginEq. (16.34):
vO =VIH − VDD =0.7125−0.65=0.0625V 2
Thus,theworst-casevalueofVOL is
VOmax = 0.0625 ≃ 0.06 V, and the noise margin NML reduces to
NML =0.5875−0.0625=0.5250V or approximately 0.53 V.
From symmetry, we can obtain the value of v O correspondingtovI =VIL as
vO =VDD −0.0625
= 1.3−0.0625 = 1.2375 V ≃ 1.24 V
Thus,theworst-casevalueofVOH is
VO H min ≃ 1.24 V, and the noise margin NMH is reduced to
NMH =VOHmin−VIH
= 1.2375 − 0.7125 = 0.5250 V or approximately 0.53 V.
Note that the reduction in the noise margin (about 0.06 V) is slight.
­
16.33 The current reaches its peak at
v =V = VDD.Atthispoint,bothQ andQ
P
I M 2 N are operating in the saturation region and conducting a current
2 DP DN 2 n L n 2 t
I =I =1k′ W VDD−V
1 1.0 2 = ×540×1.5 −0.35
22 = 9.1 μA
16.34 Refer to Example 16.3 except here:
VDD =1.3V,Vtn =|Vtp|=0.4V,μn =4μp, and μnCox = 0.5 mA/V2. Also, QN and QP have L = 0.13 μm and (W/L)n = 1.5.
(a) ForVM =VDD/2=0.65V,theinvertermust be matched, thus
Wp =μn =4 Wn μp
Since Wn /L = 1.5,
Wn = 1.5 × 0.13 = 0.195 μm. Thus,
Wp = 4×0.195 = 0.78 μm
For this design, the silicon area is

(c) The output resistance of the inverter in the low-output state is
rDSN = 1 μnCox(W/L)n(VDD −Vtn)
1
= 0.5 × 1.5(1.3 − 0.4) = 1.48 k􏱹
Since QN and QP are matched, the output resistance in the high-output state will be equal, that is,
rDSP =rDSN =1.48k􏱹
(d) If the inverter is biased to operate at
vI =vO =VM =0.65V,theneachofQN and QP willbeoperatingatanoverdrivevoltage
VOV =VM −Vt =0.65−0.4=0.25Vandwill be conducting equal dc currents ID of
= −5.8 V/V
When the straight line at M of slope −5.8 V/V is
Chapter 16–15
extrapolated,itintersectsthelinevO =0at 0.65
0.65+ 5.8 =0.762Vandtheline
vO =VDD at 0.65−0.65 =0.538V.Thus
5.8
the width of the transition region can be
1W I=μC V2
considered (0.762 − 0.538) = 0.224 V.
(e) For Wp = Wn, the parameter r can be found from Eq. (16.40):
­­
r= μpWp= 1×1=0.5 μnWn 4
The corresponding value of VM can be determined from Eq. (16.39) as
0.5(1.3 − 0.4) + 0.4
VM = 0.5+1 =0.57V
Thus, VM shifts by only −0.08 V. We can estimate the reduction in NML to be approximately equal to the shift in VM , that is, NML becomes
NML =0.5875−0.08≃0.51V
The silicon area for this design can be computed
as follows:
A = L(Wn + Wp)
= 0.13(1.5 × 0.13 + 1.5 × 0.13)
= 0.051 μm2
This represents a 60% reduction from the matched case!
(f) For Wp = 2Wn, we have
D 2 n ox L OV n
= 1 ×500×1.5×0.252 2
= 23.4 μA
Thus, QN and QP will have equal
transconductances:
gmn = gmp = 2ID = 2 × 23.4 = 0.19 mA/V
VO V 0.25 Transistors QN and QP will have output
resistances ron and rop given by ron = VAn
ID
r = |VAp| op ID
Since no values are given for VAn and VAp we shall use the data in Table K.1, namely
′′­
VAn =5V/μmand|VAp|=6V/μm Thus,
VAn = 5×0.13 = 0.65 V
|VAp| = 6 × 0.13 = 0.78 V
0.65 V
ron = 23.4 μA = 27.8 k􏱹
rop = 0.78V =33.3k􏱹 23.4 μA
We can now compute the voltage gain at M as Av = −(gmn + gmp)(ron ∥ rop)
= −(0.19 + 0.19)(27.8 ∥ 33.3)
11
r= 4×2=√2=0.707
VM = 0.707(1.3 − 0.4) + 0.4 = 0.61 V 0.707 + 1
Thus, relative to the matched case, VM is reduced by only 0.04 V. Correspondingly, NML will be reduced by approximately an equal amount, thus NML becomes
NML ≃ 0.59−0.04 = 0.55 V
In this case, the silicon area required is A=L(Wn +Wp)=L×3Wn
= 0.13×3×1.5×0.13
= 0.076 μm2

whichrepresentsa40%reductionrelativetothe matched case.
16.35 (a)Wp =1.5×2.0×28nm=84nm (b)VOH =0.9V
VOL =0V
VIH = 1(5×0.9−2×0.3)=0.49V 8
VIL = 1(3×0.9+2×0.3)=0.41V 8
NMH =0.9−0.49=0.41V
NML =0.41−0=0.41V
Chapter 16–16
(c)rDSN =
1 =1.11k􏱹 0.75×2×(0.9−0.3)
rDSP =
= 1.11 k􏱹
1
0.75 ×2×1.5×(0.9−0.3)
1.5 ­ 1
(d)r = 1.5 ×1=0.816
0.816×(0.9−0.3)+0.3
VM = 1+0.816 =0.43V