Microelectronic Circuits
THE OXFORD SERIES IN ELECTRICAL AND COMPUTER ENGINEERING
Adel S. Sedra, Series Editor
Allen and Holberg, CMOS Analog Circuit Design, 3rd edition
Bobrow, Elementary Linear Circuit Analysis, 2nd edition
Bobrow, Fundamentals of Electrical Engineering, 2nd edition
Campbell, Fabrication Engineering at the Micro- and Nanoscale, 4th edition Chen, Digital Signal Processing
Chen, Linear System Theory and Design, 4th edition
Chen, Signals and Systems, 3rd edition
Comer, Digital Logic and State Machine Design, 3rd edition Comer, Microprocessor-Based System Design
Cooper and McGillem, Probabilistic Methods of Signal and System Analysis, 3rd edition Dimitrijev, Principles of Semiconductor Device, 2nd edition
Dimitrijev, Understanding Semiconductor Devices
Fortney, Principles of Electronics: Analog & Digital
Franco, Electric Circuits Fundamentals
Ghausi, Electronic Devices and Circuits: Discrete and Integrated
Guru and Hiziroğlu, Electric Machinery and Transformers, 3rd edition
Houts, Signal Analysis in Linear Systems
Jones, Introduction to Optical Fiber Communication Systems
Krein, Elements of Power Electronics
Kuo, Digital Control Systems, 2nd edition
Lathi, Linear Systems and Signals, 2nd edition
Lathi and Ding, Modern Digital and Analog Communication Systems, 4th edition
Lathi, Signal Processing and Linear Systems
Martin, Digital Integrated Circuit Design
Miner, Lines and Electromagnetic Fields for Engineers
Parhami, Computer Architecture
Parhami, Computer Arithmetic, 2nd edition
Roberts and Sedra, SPICE, 2nd edition
Roberts, Taenzler, and Burns, An Introduction to Mixed-Signal IC Test and Measurement,
2nd edition
Roulston, An Introduction to the Physics of Semiconductor Devices
Sadiku, Elements of Electromagnetics, 6th edition
Santina, Stubberud, and Hostetter, Digital Control System Design, 2nd edition
Sarma, Introduction to Electrical Engineering
Schaumann, Xiao, and Van Valkenburg, Design of Analog Filters, 3rd edition
Schwarz and Oldham, Electrical Engineering: An Introduction, 2nd edition
Sedra and Smith, Microelectronic Circuits, 7th edition
Stefani, Shahian, Savant, and Hostetter, Design of Feedback Control Systems, 4th edition Tsividis/McAndrew, Operation and Modeling of the MOS Transistor, 3rd edition
Van Valkenburg, Analog Filter Design
Warner and Grung, Semiconductor Device Electronics
Wolovich, Automatic Control Systems
Yariv and Yeh, Photonics: Optical Electronics in Modern Communications, 6th edition Żak, Systems and Control
SEVENTH EDITION
Microelectronic Circuits
Adel S. Sedra
University of Waterloo
Kenneth C. Smith
University of Toronto
New York Oxford
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Library of Congress Cataloging-in-Publication Data
Sedra, Adel S., author.
Microelectronic circuits / Adel S. Sedra, University of Waterloo, Kenneth C. Smith, University of Toronto. — Seventh edition.
pages cm. — (The Oxford series in electrical and computer engineering) Includes bibliographical references and index.
ISBN 978–0–19–933913–6
1. Electronic circuits. 2. Integrated circuits. I. Smith,
Kenneth C. (Kenneth Carless), author. II. Title. TK7867.S39 2014
621.3815—dc23
France Greece
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Cover Photo: This 3D IC system demonstrates the concept of wireless power delivery and communication through multiple layers of CMOS chips. The communication circuits were demonstrated in an IBM 45 nm SOI CMOS process. This technology is designed to serve a multi-Gb/s interconnect between cores spread across several IC layers for high-performance processors.
(Photo Credit: The picture is courtesy of Professor David Wentzloff, Director of the Wireless Integrated Circuits Group at the University of Michigan, and was edited by Muhammad Faisal, Founder of Movellus Circuits Incorporated.)
Printing number: 9 8 7 6 5 4 3 2 1
Printed in the United States of America on acid-free paper
2014033965
BRIEF TABLE OF CONTENTS
Tables xvi
“Expand-Your-Perspective” Notes xvii Preface xix
PART I DEVICES AND BASIC CIRCUITS 2
1 Signals and Amplifiers 4
2 Operational Amplifiers 58
3 Semiconductors 134
4 Diodes 174
5 MOS Field-Effect Transistors (MOSFETs) 246 6 Bipolar Junction Transistors (BJTs) 304
7 Transistor Amplifiers 366
PART II INTEGRATED-CIRCUIT AMPLIFIERS 506
8 Building Blocks of Integrated-Circuit Amplifiers 508
9 Differential and Multistage Amplifiers 594 10 Frequency Response 696
11 Feedback 806
12 Output Stages and Power Amplifiers 920 13 Operational Amplifier Circuits 994
PART III DIGITAL INTEGRATED CIRCUITS 1086
14 CMOS Digital Logic Circuits 1088
15 Advanced Topics in Digital Integrated-Circuit Design 1166 16 Memory Circuits 1236
PART IV FILTERS AND OSCILLATORS 1288 17 Filters and Tuned Amplifiers 1290
18 Signal Generators and Waveform-Shaping Circuits 1378 Appendices A–L
Index IN-1
v
vi
CONTENTS
Tables xvi “Expand-Your-Perspective”
Notes xvii Preface xix
PART I DEVICES AND BASIC CIRCUITS 2
1 Signals and Amplifiers 4
Introduction 5
1.1 Signals 6
1.2 Frequency Spectrum of Signals
2 Operational Amplifiers 58
Introduction 59
2.1 The Ideal Op Amp 60
1.3 Analog and Digital Signals 1.4 Amplifiers 15
12 15
1.4.1 Signal Amplification
1.4.2 Amplifier Circuit Symbol 1.4.3 Voltage Gain 17
1.4.4 Power Gain and Current Gain 1.4.5 Expressing Gain in Decibels 1.4.6 The Amplifier Power Supplies 1.4.7 Amplifier Saturation 21 1.4.8 Symbol Convention 22
23
29
1.5 Circuit Models for Amplifiers
1.5.1 Voltage Amplifiers 23
1.5.2 Cascaded Amplifiers 25
1.5.3 Other Amplifier Types 28 1.5.4 Relationships between the Four
Instrumentation Amplifier 82 Integrators and Differentiators 87 2.5.1 The Inverting Configuration with
General Impedances 87
2.5.2 The Inverting Integrator 89
2.5.3 The Op-Amp Differentiator 94
DC Imperfections 96
2.6.1 Offset Voltage 96
2.6.2 Input Bias and Offset Currents 100 2.6.3 Effect of VOS and IOS on the Operation
Amplifier Models 28 1.5.5 Determining Ri and Ro 1.5.6 Unilateral Models 29
1.6 Frequency Response of Amplifiers 1.6.1 Measuring the Amplifier
Frequency Response 33 1.6.2 Amplifier Bandwidth 34 1.6.3 Evaluating the Frequency
33
Response of Amplifiers 34
1.6.4 Single-Time-Constant Networks 1.6.5 Classification of Amplifiers Based on
of the Inverting Integrator 103 2.7 Effect of Finite Open-Loop Gain and
Bandwidth on Circuit Performance 105 2.7.1 Frequency Dependence of the
Open-Loop Gain 105
2.7.2 Frequency Response of Closed-Loop
Frequency Response Summary 44
Problems 45
41
9
2.2
2.3
2.4
2.5
2.6
2.1.1 The Op-Amp Terminals 60 2.1.2 Function and Characteristics
of the Ideal Op Amp 61
2.1.3 Differential and Common-Mode
Signals 63
The Inverting Configuration 64 2.2.1 The Closed-Loop Gain 65 2.2.2 Effect of the Finite Open-Loop
Gain 67
2.2.3 Input and Output Resistances 68 2.2.4 An Important Application—The
Weighted Summer 71
The Noninverting Configuration 73 2.3.1 The Closed-Loop Gain 73 2.3.2 Effect of Finite Open-Loop
16
17 18
18
Gain 75
2.3.3 Input and Output Resistance 2.3.4 The Voltage Follower 75 Difference Amplifiers 77
2.4.1 A Single-Op-Amp Difference
Amplifier 78
2.4.2 A Superior Circuit—The
75
35
Amplifiers 107
2.8 Large-Signal Operation of Op Amps 110 2.8.1 Output Voltage Saturation 110 2.8.2 Output Current Limits 110
2.8.3 Slew Rate 112
2.8.4 Full-Power Bandwidth 114 Summary 115
Problems 116
3 Semiconductors 134
Introduction 135
3.1 Intrinsic Semiconductors 136
3.2 Doped Semiconductors 139
3.3 Current Flow in Semiconductors 142
3.3.1 Drift Current 142
3.3.2 Diffusion Current 145
3.3.3 Relationship between D and μ 148
3.4 The pn Junction 148
3.4.1 Physical Structure 149 3.4.2 Operation with Open-Circuit
Terminals 149
3.5 The pn Junction with an Applied
Voltage 155
3.5.1 Qualitative Description of Junction
Operation 155
3.5.2 The Current–Voltage Relationship of
the Junction 158
3.5.3 Reverse Breakdown 162
3.6 Capacitive Effects in the pn Junction 164 3.6.1 Depletion or Junction
Capacitance 164
3.6.2 Diffusion Capacitance 166
Summary 168 Problems 171
4 Diodes 174
Introduction 175
4.1 The Ideal Diode 176
4.1.1 Current–Voltage Characteristic 176 4.1.2 A Simple Application: The
Rectifier 177
4.1.3 Another Application: Diode Logic
Gates 180
4.2 Terminal Characteristics of Junction
Diodes 184
4.2.1 The Forward-Bias Region 184 4.2.2 The Reverse-Bias Region 189 4.2.3 The Breakdown Region 190
4.3 Modeling the Diode Forward Characteristic 190
4.4
4.5
4.6
4.3.1 The Exponential Model 190 4.3.2 Graphical Analysis Using the Exponential Model 191
4.3.3 Iterative Analysis Using the Exponential Model 191
4.3.4 The Need for Rapid Analysis 192 4.3.5 The Constant-Voltage-Drop
Model 193
4.3.6 The Ideal-Diode Model 194 4.3.7 The Small-Signal Model 195 4.3.8 Use of the Diode Forward Drop in
Voltage Regulation 200 Operation in the Reverse Breakdown Region—Zener Diodes 202
4.4.1 Specifying and Modeling the Zener
Diode 203
4.4.2 Use of the Zener as a Shunt
Regulator 204
4.4.3 Temperature Effects 206 4.4.4 A Final Remark 207 Rectifier Circuits 207
4.5.1 The Half-Wave Rectifier 208 4.5.2 The Full-Wave Rectifier 210 4.5.3 The Bridge Rectifier 212 4.5.4 The Rectifier with a
Filter Capacitor—The Peak
Rectifier 213
4.5.5 Precision Half-Wave Rectifier—The
Superdiode 219
Limiting and Clamping Circuits 221 4.6.1 Limiter Circuits 221
4.6.2 The Clamped Capacitor or DC
Restorer 224
4.6.3 The Voltage Doubler 226
4.7 Special Diode Types 227
4.7.1 The Schottky-Barrier Diode
(SBD) 227
4.7.2 Varactors 228
4.7.3 Photodiodes 228
4.7.4 Light-Emitting Diodes (LEDs) 228
Summary 229 Problems 230
5 MOS Field-Effect Transistors (MOSFETs) 246
Introduction 247
5.1 Device Structure and Physical
Operation 248
5.1.1 Device Structure 248 5.1.2 Operation with Zero Gate
Voltage 250
Contents vii
viii Contents
5.1.3 Creating a Channel for Current Flow 250
5.1.4 Applying a Small vDS 252 5.1.5 Operation as vDS Is Increased 5.1.6 Operation for vDS ≥ VOV:
Channel Pinch-Off and Current Saturation 258
256
6.2.3 Dependence of iC on the Collector Voltage—The Early Effect 326
6.2.4 An Alternative Form of the Common- Emitter Characteristics 329
BJT Circuits at DC 333
Transistor Breakdown and Temperature Effects 351
6.4.1 Transistor Breakdown 351
6.4.2 Dependence of β on IC and
5.1.7 The p-Channel MOSFET 5.1.8 Complementary MOS or
261
CMOS 263
5.1.9 Operating the MOS Transistor in the
Subthreshold Region 264
5.2 Current–Voltage Characteristics 264
5.2.1 Circuit Symbol 264
5.2.2 The iD –vDS Characteristics 265 5.2.3 The iD –vGS Characteristic 267 5.2.4 Finite Output Resistance in
Saturation 271
5.2.5 Characteristics of the p-Channel
MOSFET 274
5.3 MOSFET Circuits at DC 276
5.4 The Body Effect and Other Topics 288 5.4.1 The Role of the Substrate—The Body
Effect 288
5.4.2 Temperature Effects 289 5.4.3 Breakdown and Input
Protection 289
5.4.4 Velocity Saturation 290
5.4.5 The Depletion-Type MOSFET 290
Summary 291 Problems 292
6 Bipolar Junction Transistors (BJTs) 304
Introduction 305
6.1 Device Structure and Physical
Operation 306
6.1.1 Simplified Structure and Modes of
Operation 306
6.1.2 Operation of the npn Transistor in the
Active Mode 307
6.1.3 Structure of Actual Transistors 315 6.1.4 Operation in the Saturation
Mode 316
6.1.5 The pnp Transistor 318
6.2 Current–Voltage Characteristics 320 6.2.1 Circuit Symbols and Conventions 320 6.2.2 Graphical Representation of
Temperature 353 Summary 354
Problems 355
7 Transistor Amplifiers 366
Introduction 367
7.1 Basic Principles 368
7.1.1 The Basis for Amplifier Operation 368
7.1.2 Obtaining a Voltage Amplifier 369
7.1.3 The Voltage-Transfer Characteristic
(VTC) 370
7.1.4 Obtaining Linear Amplification by
Biasing the Transistor 371
7.1.5 The Small-Signal Voltage Gain 374
7.1.6 Determining the VTC by Graphical
Analysis 380
7.1.7 Deciding on a Location for the Bias
Point Q 381
7.2 Small-Signal Operation and
Models 383
7.2.1 The MOSFET Case 383 7.2.2 The BJT Case 399
7.2.3 Summary Tables 420
7.3 Basic Configurations 423
7.3.1 The Three Basic Configurations 423 7.3.2 Characterizing Amplifiers 424
7.3.3 The Common-Source (CS)
and Common-Emitter (CE)
Amplifiers 426
7.3.4 The Common-Source (Common-
Emitter) Amplifier with a Source
(Emitter) Resistance 431 7.3.5 The Common-Gate (CG)
and the Common-Base (CB)
Amplifiers 439
7.3.6 The Source and Emitter
Followers 442 7.3.7 Summary Tables and
Transistor Characteristics 325
Comparisons 452
6.3 6.4
7.3.8 When and How to Include the Transistor Output Resistance ro
453
8.4.3 The Body Effect 542
8.4.4 The CB Circuit 543
8.4.5 Output Resistance of an Emitter-
Degenerated CE Amplifier 546 The Cascode Amplifier 546
8.5.1 Cascoding 546
8.5.2 The MOS Cascode Amplifier 547 8.5.3 Distribution of Voltage Gain in a
Cascode Amplifier 552
8.5.4 Double Cascoding 555
8.5.5 The Folded Cascode 555
8.5.6 The BJT Cascode 557 Current-Mirror Circuits with Improved Performance 559
8.6.1 Cascode MOS Mirrors 559 8.6.2 The Wilson Current Mirror 560 8.6.3 The Wilson MOS Mirror 563 8.6.4 The Widlar Current Souce 565
7.4 Biasing 454
7.4.1 The MOSFET Case 7.4.2 The BJT Case 461
455
467
Amplifier 467
7.5.2 A Common-Emitter (CE)
8.5
8.6
7.5 Discrete-Circuit Amplifiers 7.5.1 A Common-Source (CS)
Amplifier 470
7.5.3 A Common-Emitter Amplifier with
an Emitter Resistance Re 7.5.4 A Common-Base (CB)
471
Amplifier 473
7.5.5 An Emitter Follower 7.5.6 The Amplifier Frequency
Response Summary 479 Problems 480
477
PART II INTEGRATED-CIRCUIT AMPLIFIERS 506
8 Building Blocks of Integrated- Circuit Amplifiers 508
Introduction 509
8.1 IC Design Philosophy 510 8.2 IC Biasing—Current Sources,
Current Mirrors, and Current-Steering Circuits 511
8.2.1 The Basic MOSFET Current Source 512
8.2.2 MOS Current-Steering Circuits 515
8.2.3 BJT Circuits 518
8.2.4 Small-Signal Operation of Current
Mirrors 523
8.3 The Basic Gain Cell 525
8.3.1 The CS and CE Amplifiers with Current-Source Loads 525
8.3.2 The Intrinsic Gain 527
8.3.3 Effect of the Output Resistance of the
Current-Source Load 530 8.3.4 Increasing the Gain of the Basic
Cell 536
8.4 The Common-Gate and Common-Base
Amplifiers 537
8.4.1 The CG Circuit 537
8.4.2 Output Resistance of a CS Amplifier
8.7 Some Useful Transistor Pairings 567 8.7.1 The CC–CE, CD–CS, and CD–CE
Configurations 567
8.7.2 The Darlington Configuration 571 8.7.3 The CC–CB and CD–CG
Configurations 572 Summary 575
Problems 576
9 Differential and Multistage Amplifiers 594
Introduction 595
9.1 The MOS Differential Pair 596
9.1.1 Operation with a Common-Mode Input Voltage 597
475
Contents ix
with a Source Resistance 541
9.2 The BJT Differential Pair 614
9.2.1 Basic Operation 614
9.2.2 Input Common-Mode Range 616 9.2.3 Large-Signal Operation 617 9.2.4 Small-Signal Operation 620
9.3 Common-Mode Rejection 627 9.3.1 The MOS Case 628 9.3.2 The BJT Case 634
9.4 DC Offset 637
9.1.2
9.1.3 9.1.4 9.1.5
9.1.6
Operation with a Differential Input Voltage 601
Large-Signal Operation 602 Small-Signal Operation 607
The Differential Amplifier with Current-Source Loads 611 Cascode Differential
Amplifier 612
x Contents
9.4.1 Input Offset Voltage of the MOS Differential Amplifier 637
9.4.2 Input Offset Voltage of the Bipolar Differential Amplifier 640
9.4.3 Input Bias and Offset Currents of the
10.4 Useful Tools for the Analysis of the High-Frequency Response of Amplifiers 739
10.4.1 The High-Frequency Gain
Function 739
10.4.2 Determining the 3-dB
Frequency fH 740
10.4.3 The Method of Open-Circuit
Time Constants 743
10.4.4 Application of the Method of
Open-Circuit Time Constants to
the CS Amplifier 744 10.4.5 Application of the Method of
Open-Circuit Time Constants to
the CE Amplifier 748 10.5 High-Frequency Response of
the Common-Gate and Cascode Amplifiers 748
10.5.1 High-Frequency Response of the
CG Amplifier 748
10.5.2 High-Frequency Response of the
MOS Cascode Amplifier 754 10.5.3 High-Frequency Response of the Bipolar Cascode Amplifier 759
10.6 High-Frequency Response of the Source and Emitter Followers 760 10.6.1 The Source-Follower Case 761 10.6.2 The Emitter-Follower Case 767
10.7 High-Frequency Response of Differential Amplifiers 768
10.7.1 Analysis of the Resistively Loaded
MOS Amplifier 768
10.7.2 Analysis of the Current-Mirror-
Loaded MOS Amplifier 772 10.8 Other Wideband Amplifier
Configurations 778 10.8.1 Obtaining Wideband
Amplification by Source and
Emitter Degeneration 778 10.8.2 The CD–CS, CC–CE, and
CD–CE Configurations 781 10.8.3 The CC–CB and CD–CG
Configurations 786 Summary 788
Problems 789
11 Feedback 806
Introduction 807
11.1 The General Feedback Structure 808
11.1.1 Signal-Flow Diagram 808 11.1.2 The Closed-Loop Gain 809
Bipolar Differential Amplifier 9.4.4 A Concluding Remark 644
9.5 The Differential Amplifier with a Current-Mirror Load 644
9.5.1 Differential to Single-Ended Conversion 644
643
9.5.2 The Current-Mirror-Loaded MOS Differential Pair 645
9.5.3 Differential Gain of the Current-Mirror-Loaded MOS Pair 647
9.5.4 The Bipolar Differential Pair with a Current-Mirror Load 651
9.5.5 Common-Mode Gain and CMRR 655
9.6 Multistage Amplifiers 659 9.6.1 A Two-Stage CMOS
Op Amp 659 9.6.2 A Bipolar Op Amp
Summary 672 Problems 674
664
10 Frequency Response 696
Introduction 697
10.1 Low-Frequency Response of
Discrete-Circuit Common-
Source and Common-Emitter Amplifiers 699
10.1.1 The CS Amplifier 699 10.1.2 The Method of Short-Circuit
Time-Constants 707 10.1.3 The CE Amplifier 707
10.2 Internal Capacitive Effects and the High-Frequency Model of the MOSFET and the BJT 711
10.2.1 The MOSFET 711
10.2.2 The BJT 717
10.3 High-Frequency Response of the CS and CE Amplifiers 722
10.3.1 The Common-Source
Amplifier 722 10.3.2 The Common-Emitter Amplifier 728
10.3.3 Miller’s Theorem 732
10.3.4 Frequency Response of the CS
Amplifier When Rsig Is Low 735
11.1.3 The Loop Gain 810
11.1.4 Summary 814
11.2 Some Properties of Negative
Feedback 815
11.2.1 Gain Desensitivity 815
11.9.3 An Alternative Approach for Investigating Stability 887
11.10 Frequency Compensation 889 11.10.1 Theory 889
11.10.2 Implementation 891
11.10.3 Miller Compensation and Pole
Splitting 892 Summary 895
Problems 896
12 Output Stages and Power Amplifiers 920
Introduction 921
12.1 Classification of Output Stages 922 12.2 Class A Output Stage 923
12.2.1 Transfer Characteristic 924 12.2.2 Signal Waveforms 925 12.2.3 Power Dissipation 926 12.2.4 Power-Conversion
Efficiency 928
12.3 Class B Output Stage 929
12.3.1 Circuit Operation 929
12.3.2 Transfer Characteristic 929 12.3.3 Power-Conversion Efficiency 930 12.3.4 Power Dissipation 931
12.3.5 Reducing Crossover
Distortion 933
12.3.6 Single-Supply Operation 934
12.4 Class AB Output Stage 935 12.4.1 Circuit Operation 935 12.4.2 Output Resistance 937
12.5 Biasing the Class AB Circuit 12.5.1 Biasing Using Diodes 940 12.5.2 Biasing Using the VBE
Multiplier 942
12.6 Variations on the Class AB
Configuration 945 12.6.1 Use of Input Emitter
Followers 945
12.6.2 Use of Compound Devices 946 12.6.3 Short-Circuit Protection 949 12.6.4 Thermal Shutdown 950
11.2.2 Bandwidth Extension 11.2.3 Interference Reduction 11.2.4 Reduction in Nonlinear
816 817
Distortion 819
11.3 The Feedback Voltage Amplifier 820
11.3.1 The Series–Shunt Feedback Topology 820
11.3.2 Examples of Series–Shunt Feedback Amplifiers 821
11.3.3 Analysis of the Feedback Voltage Amplifier Utilizing the Loop Gain 823
11.3.4 A Final Remark 828 11.4 Systematic Analysis of Feedback
Voltage Amplifiers 828 11.4.1 The Ideal Case 829 11.4.2 The Practical Case
831
11.5 Other Feedback Amplifier Types 11.5.1 Basic Principles 840
11.5.2 The Feedback Transconductance
Amplifier (Series–Series) 844 11.5.3 The Feedback Transresistance
Amplifier (Shunt–Shunt) 855 11.5.4 The Feedback Current Amplifier
(Shunt–Series) 865
11.6 Summary of the Feedback Analysis
Method 871
11.7 The Stability Problem 871
11.7.1 Transfer Function of the Feedback Amplifier 871
11.7.2 The Nyquist Plot 873
11.8 Effect of Feedback on the Amplifier
940
Poles 875
11.8.1 Stability and Pole Location 11.8.2 Poles of the Feedback
Amplifier 876
11.8.3 Amplifier with a Single-Pole
Response 877
11.8.4 Amplifier with a Two-Pole
875
Response 878
11.8.5 Amplifiers with Three or More
12.7 CMOS Class AB Output Stages
12.7.1 The Classical Configuration 950 12.7.2 An Alternative Circuit
Utilizing Common-Source
Transistors 953 12.8 IC Power Amplifiers 961
12.8.1 A Fixed-Gain IC Power Amplifier 962
Poles 883
11.9 Stability Study Using Bode Plots
11.9.1 Gain and Phase Margins 11.9.2 Effect of Phase Margin on
885 885
Closed-Loop Response 886
840
Contents xi
950
xii Contents
12.9 Class D Power Amplifiers
13.4.1 Special Performance Requirements 1054
13.4.2 Bias Design 1056
13.4.3 Design of the Input Stage to
Obtain Rail-to-Rail VICM 1058 13.4.4 Common-Mode Feedback to
Control the DC Voltage at the
Output of the Input Stage 1064 13.4.5 Output-Stage Design for Near
Rail-to-Rail Output Swing 1069 13.4.6 Concluding Remark 1073
Summary 1073 Problems 1074
PART III DIGITAL INTEGRATED CIRCUITS 1086
14 CMOS Digital Logic Circuits 1088
Introduction 1089
14.1 CMOS Logic-Gate Circuits 1090
14.1.1 Switch-Level Transistor Model 1090
14.1.2 The CMOS Inverter 1091
14.1.3 General Structure of CMOS
Logic 1091
14.1.4 The Two-Input NOR Gate 1094
14.1.5 The Two-Input NAND
Gate 1095
14.1.6 A Complex Gate 1096
14.1.7 Obtaining the PUN from the PDN
and Vice Versa 1096 14.1.8 The Exclusive-OR
Function 1097
14.1.9 Summary of the Synthesis
Method 1098
14.2 Digital Logic Inverters 1100
14.2.1 The Voltage-Transfer Characteristic (VTC) 1100
14.2.2 Noise Margins 1101
14.2.3 The Ideal VTC 1103
14.2.4 Inverter Implementation 1103
14.3 The CMOS Inverter 1114 14.3.1 Circuit Operation 1114 14.3.2 The Voltage-Transfer
Characteristic (VTC) 1117 14.3.3 The Situation When QN and QP
Are Not Matched 1120 14.4 Dynamic Operation of the CMOS
Inverter 1125
12.8.2 The Bridge Amplifier 966 967
12.10 Power Transistors 971 12.10.1 Packages and Heat
Sinks 971 12.10.2 Power BJTs 972
12.10.3 Power MOSFETs
974
12.10.4 Thermal Considerations Summary 982
Problems 983
13 Operational-Amplifier Circuits 994
976
Introduction 995
13.1 The Two-Stage CMOS Op Amp 996
13.1.1 The Circuit 997
13.1.2 Input Common-Mode Range and
Output Swing 998
13.1.3 DC Voltage Gain 999
13.1.4 Common-Mode Rejection Ratio
(CMRR) 1001
13.1.5 Frequency Response 1002
13.1.6 Slew Rate 1007
13.1.7 Power-Supply Rejection Ratio
(PSRR) 1008
13.1.8 Design Trade-Offs 1009
13.1.9 A Bias Circuit for the Two-Stage
CMOS Op Amp 1010 13.2 The Folded-Cascode CMOS Op
A mp 1016
13.2.1 The Circuit 1016
13.2.2 Input Common-Mode Range and
Output Swing 1018
13.2.3 Voltage Gain 1020
13.2.4 Frequency Response 1021 13.2.5 Slew Rate 1022
13.2.6 Increasing the Input Common-
Mode Range: Rail-to-Rail Input
Operation 1024
13.2.7 Increasing the Output Voltage
Range: The Wide-Swing Current
Mirror 1026
13.3 The 741 BJT Op Amp 1028
13.3.1 The 741 Circuit 1028
13.3.2 DC Analysis 1032
13.3.3 Small-Signal Analysis 1038 13.3.4 Frequency Response 1051 13.3.5 Slew Rate 1053
13.4 Modern Techniques for the Design of BJT Op Amps 1054
14.4.1 Propagation Delay 1125
14.4.2 Determining the Propagation Delay
of the CMOS Inverter 1129 14.4.3 Determining the Equivalent Load
Capacitance C 1136 14.5 Transistor Sizing 1139
14.5.1 Inverter Sizing 1139
14.5.2 Transistor Sizing in CMOS Logic
Gates 1141
14.5.3 Effects of Fan-In and Fan-Out on
15.3.7 Concluding Remarks 1190 15.4 Pass-Transistor
Logic Circuits 1192 15.4.1 An Essential Design Requirement 1193
15.4.2 Operation with NMOS Transistors as Switches 1194
15.4.3 Restoring the Value of VOH to VDD 1198
15.4.4 The Use of CMOS Transmission Gates as Switches 1199
15.4.5 Examples of Pass-Transistor Logic Circuits 1206
15.4.6 A Final Remark 1208
15.5 Dynamic MOS Logic Circuits 1208
15.5.1 The Basic Principle 1209 15.5.2 Nonideal Effects 1212 15.5.3 Domino CMOS Logic 1216 15.5.4 Concluding Remarks 1217
15.6 Bipolar and BiCMOS Logic Circuits 1217
15.6.1 Emitter-Coupled Logic (ECL) 1218
15.6.2 BiCMOS Digital Circuits 1223 Summary 1226
Problems 1227
16 Memory Circuits 1236
Introduction 1237
16.1 Latches and Flip-Flops 1238
16.1.1 The Latch 1238
16.1.2 The SR Flip-Flop 1240 16.1.3 CMOS Implementation of SR
Flip-Flops 1241
16.1.4 A Simpler CMOS Implementation
of the Clocked SR Flip-Flop 1247 16.1.5 D Flip-Flop Circuits 1247
16.2 Semiconductor Memories: Types and Architectures 1249
16.2.1 Memory-Chip Organization 1250 16.2.2 Memory-Chip Timing 1252
16.3 Random-Access Memory (RAM) Cells 1253
16.3.1 Static Memory (SRAM) Cell 1253
16.3.2 Dynamic Memory (DRAM) Cell 1260
16.4 Sense Amplifiers and Address Decoders 1262
Propagation Delay 1145 14.5.4 Driving a Large Capacitance
14.6 Power Dissipation 1149 14.6.1 Sources of Power
1146
Dissipation 1149
14.6.2 Power–Delay and Energy–Delay
Products Summary 1154
Problems 1156
1152
15 Advanced Topics in Digital Integrated-Circuit Design 1166
Introduction 1167
15.1 Implications of Technology
Scaling: Issues in Deep-Submicron Design 1168
15.1.1 Silicon Area 1169
15.1.2 Scaling Implications 1169
15.1.3 Velocity Saturation 1171
15.1.4 Subthreshold Conduction 1177
15.1.5 Temperature, Voltage, and
Process Variations 1178
15.1.6 Wiring: The Interconnect 1178
15.2 Digital IC Technologies, Logic-Circuit Families, and Design Methodologies 1179
15.2.1 Digital IC Technologies and
Logic-Circuit Families 1180 15.2.2 Styles for Digital System
Design 1182
15.2.3 Design Abstraction and Computer
Aids 1182
15.3 Pseudo-NMOS Logic Circuits 1183
15.3.1 The Pseudo-NMOS Inverter 1183
15.3.2 Static Characteristics 1184 15.3.3 Derivation of the VTC 1186 15.3.4 Dynamic Operation 1188 15.3.5 Design 1189
15.3.6 Gate Circuits 1189
16.4.1 The Sense Amplifier 1263
Contents xiii
xiv Contents
16.4.2 The Row-Address Decoder 16.4.3 The Column-Address
Decoder 1273
16.4.4 Pulse-Generation Circuits
1271
17.6.1 The Antoniou Inductance- Simulation Circuit 1322
17.6.2 The Op Amp–RC Resonator 1323 17.6.3 Realization of the Various Filter
Types 1325
17.6.4 The All-Pass Circuit 1325 Second-Order Active Filters
Based on the Two-Integrator-Loop Topology 1330
17.7.1 Derivation of the Two-Integrator-
Loop Biquad 1330
17.7.2 Circuit Implementation 1332 17.7.3 An Alternative Two-Integrator-
Loop Biquad Circuit 1334 17.7.4 Final Remarks 1335
1274 16.5 Read-Only Memory (ROM) 1276
16.5.1 A MOS ROM 1276
16.5.2 Mask Programmable ROMs 16.5.3 Programmable ROMs (PROMs,
EPROMs, and Flash) 1279
16.6 CMOS Image Sensors Summary 1282 Problems 1283
PART IV FILTERS AND OSCILLATORS 1288
17 Filters and Tuned Amplifiers 1290
1281
1278
17.7
Introduction 1291
17.1 Filter Transmission, Types, and
Specification 1292
17.1.1 Filter Transmission 1292 17.1.2 Filter Types 1293
17.1.3 Filter Specification 1293
17.2 The Filter Transfer Function 1296 17.3 Butterworth and Chebyshev
Filters 1300
17.3.1 The Butterworth Filter 1300 17.3.2 The Chebyshev Filter 1304
17.4 First-Order and Second-Order Filter Functions 1307
17.4.1 First-Order Filters 1308 17.4.2 Second-Order Filter
Functions 1311 17.5 The Second-Order LCR
Resonator 1316
17.5.1 The Resonator Natural
Modes 1316
17.5.2 Realization of Transmission
Zeros 1317
17.5.3 Realization of the Low-Pass
Function 1317
17.5.4 Realization of the High-Pass
Function 1319
17.5.5 Realization of the Bandpass
Function 1319
17.5.6 Realization of the Notch
Functions 1319
17.5.7 Realization of the All-Pass
Function 1321
17.6 Second-Order Active Filters Based on
17.8 Single-Amplifier Biquadratic Active Filters 1336
17.8.1 Synthesis of the Feedback Loop 1336
17.8.2 Injecting the Input Signal 1339 17.8.3 Generation of Equivalent
Feedback Loops 1341 17.9 Sensitivity 1344
17.10 Transconductance-C Filters 1347 17.10.1 Methods for IC Filter
Implementation 1347
17.10.2 Transconductors 1348
17.10.3 Basic Building Blocks 1349 17.10.4 Second-Order Gm−C Filter 1351
17.11 Switched-Capacitor Filters 1354
17.12 Tuned Amplifiers 1359
17.12.1 The Basic Principle 1360 17.12.2 Inductor Losses 1362
17.12.3 Use of Transformers 1363 17.12.4 Amplifiers with Multiple Tuned
Circuits 1365
17.12.5 The Cascode and the CC–CB
Cascade 1366
17.12.6 Synchronous Tuning and Stagger
Tuning 1367 Summary 1368
Problems 1369
18 Signal Generators and Waveform-Shaping Circuits 1378
Introduction 1379
18.1 Basic Principles of Sinusoidal
Inductor Replacement 1322
Oscillators 1380
17.11.1 The Basic Principle 17.11.2 Practical Circuits 1356 17.11.3 Final Remarks 1359
1354
18.1.1 The Oscillator Feedback Loop 1380
18.1.2 The Oscillation Criterion
18.1.3 Analysis of Oscillator
Circuits 1382
18.1.4 Nonlinear Amplitude Control 1385
1381
18.6 Generation of a Standardized Pulse: The Monostable Multivibrator 1417
18.7 Integrated-Circuit Timers 1419
18.7.1 The 555 Circuit 1419 18.7.2 Implementing a Monostable Multivibrator Using the 555
IC 1420
18.7.3 An Astable Multivibrator Using
the 555 IC 1420
18.8 Nonlinear Waveform-Shaping
Circuits 1424
18.8.1 The Breakpoint Method 1424 18.8.2 The Nonlinear-Amplification
Method 1426 Summary 1428
Problems 1428 Appendices
A. VLSI Fabrication Technology (on website) A-1
B. SPICE Device Models and Design and Simulation Examples Using
PSpice® and MultisimTM (on website) B-1
C. Two-Port Network Parameters (on website) C-1
D. Some Useful Network Theorems (on website) D-1
E. Single-Time-Constant Circuits (on website) E-1
F. s-Domain Analysis: Poles, Zeros, and Bode Plots (on website) F-1
G. Comparison of the MOSFET and the BJT (on website, also Table G.3 in text) G-1
H. Design of Stagger-Tuned Amplifiers (on website) H-1
I. Bibliography (on website) I-1
J. Standard Resistance Values and Unit
Prefixes J-1
K. Typical Parameter Values for IC Devices
Fabricated in CMOS and
Bipolar Processes K-1
L. Answers to Selected Problems (on
website) L-1
Index IN-1
18.1.5 A Popular Limiter Circuit for Amplitude Control 1386
18.2 Op Amp–RC Oscillator Circuits
18.2.1 The Wien-Bridge
Oscillator 1388
18.2.2 The Phase-Shift Oscillator
18.2.3 The Quadrature Oscillator
18.2.4 The Active-Filter-Tuned
Oscillator 1394
18.2.5 A Final Remark 1396
18.3 LC and Crystal Oscillators 1396
18.3.1 The Colpitts and Hartley Oscillators 1396
18.3.2 The Cross-Coupled LC Oscillator 1400
18.3.3 Crystal Oscillators 1402 18.4 Bistable Multivibrators 1404
1388
1391 1392
18.4.1 The Feedback Loop 1405 18.4.2 Transfer Characteristic of the
Bistable Circuit 1406 18.4.3 Triggering the Bistable
Circuit 1407
18.4.4 The Bistable Circuit as a Memory
Element 1407
18.4.5 A Bistable Circuit with
Noninverting Transfer
Characteristic 1408 18.4.6 Application of the
Bistable Circuit as a
Comparator 1409
18.4.7 Making the Output Levels More
Precise 1411
18.5 Generation of Square and Triangular
Waveforms Using Astable Multivibrators 1412
18.5.1 Operation of the Astable
Multivibrator 1413 18.5.2 Generation of Triangular
Waveforms 1415
Contents xv
xvi
TABLES
FOR REFERENCE AND STUDY
Table 1.1 Table 1.2 Table 2.1 Table 3.1 Table 5.1 Table 5.2 Table 6.1 Table 6.2
Table 6.3 Table 7.1
Table 7.2 Table 7.3 Table 7.4 Table 7.5 Table 8.1
Table 10.1 Table 10.2 Table 11.1
Table 11.2
Table 13.1 Table 14.1 Table 14.2
Table 15.1 Table 15.2 Table 17.1
Table 17.2 Table G.3 Table J.1 Table J.2 Table J.3 Table K.1 Table K.2
The Four Amplifier Types 28
Frequency Response of STC Networks 36
Characteristics of the Ideal Op Amp 62
Summary of Important Semiconductor Equations 169
Regions of Operation of the NMOS Transistor 266
Regions of Operation of the PMOS Transistor 275
BJT Modes of Operation 307
Summary of the BJT Current–Voltage Relationships in the Active Mode 322
Simplified Models for the Operation of the BJT in DC Circuits 334 Systematic Procedure for the Analysis of Transistor Amplifier Circuits 421
Small-Signal Models of the MOSFET 421
Small-Signal Models of the BJT 422
Characteristics of MOSFET Amplifiers 452
Characteristics of BJT Amplifiers 453
Gain Distribution in the MOS Cascode Amplifier for Various Values of RL 554
The MOSFET High-Frequency Model 716
The BJT High-Frequency Model 722
Summary of the Parameters and Formulas for the Ideal Feedback-Amplifier Structure of Fig. 11.1 815
Summary of Relationships for the Four Feedback-
Amplifier Topologies 872
DC Collector Currents of the 741 Circuit (μA) 1038
Important Parameters of the VTC of the Logic Inverter 1102 Summary of Important Characteristics of the CMOS
Logic Inverter 1155
Implications of Device and Voltage Scaling 1170
Regions of Operation of the Pseudo-NMOS Inverter 1187
Design Data for the Circuits Based on Inductance
Simulation (Fig 17.22) 1328
Design Data for the Tow-Thomas Biquad Circuit in Fig 17.26 1335 Comparison of the MOSFET and the BJT G-1
Standard Resistance Values J-1
SI Unit Prefixes J-2
Meter Conversion Factors J-2
Typical Values of CMOS Device Parameters K-1
Typical Parameter Values for BJTs K-1
“EXPAND-YOUR-PERSPECTIVE” NOTES
Chapter 1: Chapter 1: Chapter 2: Chapter 2: Chapter 3: Chapter 4: Chapter 4: Chapter 5: Chapter 5: Chapter 6: Chapter 7: Chapter 7: Chapter 8: Chapter 8: Chapter 9: Chapter 9:
Chapter 10: Chapter 10: Chapter 11: Chapter 11:
Chapter 12: Chapter 12:
Chapter 13: Chapter 13: Chapter 14: Chapter 14:
Chapter 15: Chapter 15: Chapter 16: Chapter 16: Chapter 17: Chapter 17: Chapter 18: Chapter 18:
Analog vs. Digital Circuit Engineers 15 Bode Plots 37
Integrated Instrumentation Amplifiers
Early Op Amps and Analog Computation 88 LCDs, the Face of Electronics 139
The Earliest Semiconductor Diode 219 From Indication to Illumination 229 The First Field-Effect Devices 248 Gordon Moore—His Law 288
The Invention of the BJT 320
Shockley and Silicon Valley 405
Lee de Forest—a Father of the Electronics Age 454 Solid Circuits with “Flying Wires” 511
The Integrated Circuit 525
The Long-Tailed Pair 612
The International Solid-State Circuits Conference (ISSCC) 659
John Milton Miller—Capacitance Multiplication 735 RFID—Identification at a Distance 772 Feedback—Historical Note 823
Harry Nyquist—A Diverse Electronics Fundamentalist 875
Early Power-Op-Amp Product 962
Hans Camenzind—the Inventor of the Class D Amplifier 968
The Genie of Analog 996
The Creator of the μA741—David Fullagar 1031 Frank Marion Wanless—the Inventor of CMOS 1117 Federico Faggin—a Pioneer in Microprocessor Electronics 1141
The Invisible Computer 1182
Grand-Scale Graphics 1213
Flip-Flop Fact 1240
Blinding Flash 1282
A Brief History of Analog Filters 1295
Early Filter Pioneers—Cauer and Darlington 1348 The Wien-Bridge Oscillator 1390
Oscillator Pioneers 1400
85
xvii
PREFACE
Microelectronic Circuits, Seventh Edition, is intended as a text for the core courses in electronic circuits taught to majors in electrical and computer engineering. It should also prove useful to engineers and other professionals wishing to update their knowledge through self-study.
As was the case with the first six editions, the objective of this book is to develop in the reader the ability to analyze and design electronic circuits, both analog and digital, discrete and integrated. While the application of integrated circuits is covered, emphasis is placed on transistor circuit design. This is done because of our belief that even if the majority of those studying this book were not to pursue a career in IC design, knowledge of what is inside the IC package would enable intelligent and innovative application of such chips. Furthermore, with the advances in VLSI technology and design methodol- ogy, IC design itself has become accessible to an increasing number of engineers.
Prerequisites
The prerequisite for studying the material in this book is a first course in circuit analy- sis. As a review, some linear circuits material is included here in the appendices: spe- cifically, two-port network parameters in Appendix C; some useful network theorems in Appendix D; single-time-constant circuits in Appendix E; and s-domain analysis in Appendix F. In addition, a number of relevant circuit analysis problems are included at the beginning of the end-of-chapter problems section of Chapter 1. No prior knowledge of physical electronics is assumed. All required semiconductor device physics is included, and Appendix A provides a brief description of IC fabrication. All these appendices can be found on the book’s website.
Emphasis on Design
It has been our philosophy that circuit design is best taught by pointing out the various tradeoffs available in selecting a circuit configuration and in selecting component values for a given configuration. The emphasis on design has been retained in this edition. In addition to design examples, and design-oriented exercises and end-of-chapter problems (indicated with a D), the book includes on its website an extensive appendix (Appendix B) where a large number of simulation and design examples are presented. These empha- size the use of SPICE, the most valuable circuit-design aid.
xix
xx Preface
New to the Seventh Edition
While maintaining the philosophy and pedagogical approach of the first six editions, several changes have been made to both organization and coverage. Our goal in making structural changes has been to increase modularity and thus flexibility for the instructor, without causing disturbance to courses currently using the sixth edition. Changes in coverage are necessitated by the continuing advances in technology which make some topics of greater relevance and others of less interest. As well, advances in IC process technology require that the numbers used in the examples, exercises and end-of-chapter problems be updated to reflect the parameters of newer generations of IC technologies (e.g., some problems utilize the parameters of the 65-nm CMOS process). This ensures that students are acquir- ing a real-world perspective on technology.
To improve presentation, a number of chapters and sections have been rewritten for greater clarity. Specific, noteworthy changes are:
1. New End-of-Chapter Problems and a New Instructor’s Solutions Manual. The number of the end-of-chapter problems has increased by about 50. Of the resulting 1532 problems, 176 are entirely new and 790 have new data. The new Instructor’s Solutions Manual is written by Adel Sedra.
2. Expand-Your-Perspective Notes. This is a new feature providing historical and application perspectives. About two such notes are included in each chapter. Most are focused on notable circuit engineers and key inventions.
3. Greater Flexibility in Presenting the MOSFET and the BJT. Two short and completely parallel chapters present the MOSFET (Chapter 5) and the BJT (Chapter 6). Here the focus is on the device structure and its physical operation, its current-voltage characteristics, and its applica- tion in dc circuits. The order of coverage of these two chapters is entirely at the instructor’s discretion as they have been written to be completely independent of each other.
4. A Unified Treatment of Transistor Amplifiers. The heart of a first course in electronics is the study of transistor amplifiers. The seventh edition provides a new approach to this subject: A new Chapter 7 begins with the basic principles that underlie the operation of a transistor of either type as an amplifier, and presents such concepts as small-signal operation and mod- eling. This is followed by the classical configurations of transistor amplifiers, biasing methods, and practical discrete-circuit amplifiers. The combined presentation emphasizes the unity of the basic principles while allowing for separate treatment of the two device types where this is warranted. Very importantly, we are able to compare the two devices and to draw conclusions about their unique areas of application.
5. Improved Presentation of Cascoding. Chapter 8 dealing with the basic building blocks of IC amplifiers has been rewritten to improve presentation. Specifically, the development of cas- coding and the key circuit building blocks, the cascode amplifier and the cascode current source, is now much clearer.
6. Clearer and Simplified Study of Feedback. The feedback chapter has been rewritten to improve, simplify and clarify the presentation of this key subject.
7. Streamlined Presentation of Frequency Response. While keeping the treatment of frequency response all together, the chapter has been rewritten to streamline its flow, and simplify and clarify the presentation.
8. Updated Treatment of Output Stages and Power Amplifiers. Here, we have updated the mate- rial on MOS power transistors and added a new section on the increasingly important class-D switching power amplifier.
9. A More Contemporary Approach to Operational Amplifier Circuits. While maintaining cover- age of some of the enduring features and subcircuits of the classical 741 op amp, its total coverage is somewhat reduced to make room for modern IC op amp design techniques.
10. Better Organized and Modernized Coverage of Digital IC Design. Significant improvements have been made to the brief but comprehensive coverage of digital IC design in Part III. These include a better motivated study of CMOS logic circuits (Chapter 14) which now begins with logic gate circuits. The material on logic circuit technologies and design methodologies as well as the advanced topic of technology scaling and its implications have been moved to Chapter 15. This modularly structured chapter now deals with a selection of advanced and somewhat specialized topics. Since bipolar is hardly ever used in new digital design, coverage of ECL has been significantly reduced. Similarly, BiCMOS has become somewhat of a specialty topic and its coverage has been correspondingly reduced. Nevertheless, the complete material on both ECL and BiCMOS is now available on the book’s website. Finally, we have added a new section on image sensors to Chapter 16 (Memory Circuits).
11. Increased Emphasis on Integrated-Circuit Filters and Oscillators. A section on a popular approach to integrated-circuit filter design, namely, Transconductance-C filters, has been added to Chapter 17. To make room for this new material, the subsection on stagger-tuned amplifiers has been removed and placed in Appendix H, on the website. The cross-coupled LC oscillator, popular in IC design, has been added to Chapter 18. The section on precision diode circuits has been removed but is still made available on the website.
12. A Useful and Insightful Comparison of the MOSFET and the BJT. This is now included in Appendix G, available on the website.
The Book’s Website
A Companion Website for the book has been set up at www.oup.com/us/sedrasmith. Its content will
change
frequently to reflect new developments. The following material is available on the website:
1. Data sheets for hundreds of useful devices to help in laboratory experiments as well as in design projects.
2. Links to industrial and academic websites of interest.
3. A message center to communicate with the authors and with Oxford University Press.
4. Links to the student versions of both Cadence PSpice® and National Instruments MultisimTM.
5. The input files for all the PSpice® and MultisimTM examples of Appendix B.
6. Step-by-step guidance to help with the simulation examples and the end-of-chapter problems
identified with a SIM icon.
7. Bonustextmaterialofspecializedtopicswhichareeithernotcoveredorcoveredbrieflyinthe
current edition of the textbook. These include:
• Junction Field-Effect Transistors (JFETs)
• Gallium Arsenide (GaAs) Devices and Circuits • Transistor-Transistor Logic (TTL) Circuits
• Emitter-Coupled Logic (ECL) Circuits
• BiCMOS Circuits
• Precision Rectifier Circuits
8. Appendices for the Book:
• Appendix A: VLSI Fabrication Technology
• Appendix B: SPICE Device Models and Design and Simulation Examples Using PSpice®
and MultisimTM
• Appendix C: Two-Port Network Parameters
• Appendix D: Some Useful Network Theorems
• Appendix E: Single-Time-Constant Circuits
• Appendix F: s-domain Analysis: Poles, Zeros, and Bode Plots
• Appendix G: Comparison of the MOSFET and the BJT
Preface xxi
xxii Preface
• Appendix H: Design of Stagger-Tuned Amplifiers • Appendix I: Bibliography
• Appendix L: Answers to Selected Problems
Exercises and End-of-Chapter Problems
Over 475 Exercises are integrated throughout the text. The answer to each exercise is given below the exercise so students can check their understanding of the material as they read. Solving these exercises should enable the reader to gauge his or her grasp of the preceding material. In addition, more than 1530 end-of-chapter Problems, 65% of which are new or revised in this edition, are provided. The problems are keyed to the individual chapter sections and their degree of difficulty is indicated by a rating system: difficult problems are marked with an asterisk (*); more difficult problems with two asterisks (**); and very difficult (and/or time consuming) problems with three asterisks (***). We must admit, however, that this classification is by no means exact. Our rating no doubt depended to some degree on our thinking (and mood!) at the time a particular problem was created. Answers to sample problems are given in Appendix L (on the website), so students have a checkpoint to tell if they are working out the problems correctly. Complete solutions for all exercises and problems are included in the Instructor’s Solutions Manual, which is available from the publisher to those instructors who adopt the book.
As in the previous six editions, many examples are included. The examples, and indeed most of the problems and exercises, are based on real circuits and anticipate the applications encountered in designing real-life circuits. This edition continues the use of numbered solution steps in the figures for many examples, as an attempt to recreate the dynamics of the classroom.
Course Organization
The book contains sufficient material for a sequence of two single-semester courses, each of 40-50 lecture hours. The modular organization of the book provides considerable flexibility for course design. In the fol- lowing, we suggest content for a sequence of two classical or standard courses. We also describe some vari- ations on the content of these two courses and specify supplemental material for a possible third course.
The First Course
The first course is based on Part I of the book, that is, Chapters 1–7. It can be taught, most simply by starting at the beginning of Chapter 1 and concluding with the end of Chapter 7. However, as guidance to instructors who wish to follow a different order of presentation or a somewhat modified coverage, or to deal with situations where time might be constrained, we offer the following remarks:
The core of the first course is the study of the two transistor types, Chapters 5 and 6, in whatever order the instructor wishes, and transistor amplifiers in Chapter 7. These three chapters must be cov- ered in full.
Another important part of the first course is the study of diodes (Chapter 4). Here, however, if time does not permit, some of the applications in the later part of the chapter can be skipped.
We have found it highly motivational to cover op amps (Chapter 2) near the beginning of the course. This provides the students with the opportunity to work with a practical integrated circuit and to experiment with non-trivial circuits.
Coverage of Chapter 1, at least of the amplifier sections, should prove helpful. Here the sections on signals can be either covered in class or assigned as reading material. Section 1.6 on frequency response is needed if the frequency-response of op-amp circuits is to be studied; otherwise this section can be delayed to the second course.
Preface xxiii Finally, if the students have not taken a course on physical electronics, Chapter 3 needs to be cov-
ered. Otherwise, it can be used as review material or skipped altogether.
The Second Course
The main subject of the second course is integrated-circuit amplifiers and is based on Part II of the book, that is, Chapters 8-13. Here also, the course can be taught most simply by beginning with Chapter 8 and concluding with Chapter 13. However, this being a second course, considerable flexibil- ity in coverage is possible to satisfy particular curriculum designs and/or to deal with time constraints.
First, however, we note that the core material is presented in Chapters 8-11 and these four chapters must be covered, though not necessarily in their entirety. For instance, some of the sections near the end of a chapter and identified by the “advanced material” icon can be skipped, usually with no loss of continuity.
Beyond the required chapters, (8-11), the instructor has many possibilities for the remainder of the course. These include one or both of the two remaining chapters in Part II, namely, Output Stages and Power Amplifier (Chapter 12), and Op-Amp Circuits (Chapter 13).
Another possibility, is to include an introduction to digital integrated circuits by covering Chapter 14, and if time permits, selected topics of Chapters 15 and 16.
Yet another possibility for the remainder of the second course is selected topics from the filters chapter (17) and/or the oscillators chapter (18).
A Digitally Oriented First Course
A digitally-oriented first course can include the following: Chapter 1 (without Section 1.6), Chapter 2, Chapter 3 (if the students have not had any exposure to physical electronics), Chapter 4 (perhaps without some of the later applications sections), Chapter 5, selected topics from Chapter 7 emphasiz- ing the basics of the application of the MOSFET as an amplifier, Chapter 14, and selected topics from Chapters 15 and 16. Such a course would be particularly suited for Computer Engineering students.
Supplemental Material/Third Course
Depending on the selection of topics for the first and second courses, some material will remain and can be used for part of a third course or as supplemental material to support student design projects. These can include Chapter 12 (Output Stages and Power Amplifiers), Chapter 13 (Op-Amp Circuits), Chapter 17 (Filters) and Chapter 18 (Oscillators), which can be used to support a third course on analog circuits. These can also include Chapters 14, 15 and 16 which can be used for a portion of a senior-level course on digital IC design.
The Accompanying Laboratory
Courses in electronic circuits are usually accompanied by laboratory experiments. To support the laboratory component for courses using this book, Professor Vincent Gaudet of the University of Waterloo has, in collaboration with K.C. Smith, authored a laboratory manual. Laboratory Explorations, together with an Instructor’s Manual, is available from Oxford University Press.
Another innovative laboratory instruction system, designed to accompany this book, has been recently developed. Specifically, Illuster Technologies Inc. has developed a digitally controlled lab platform, AELabs. The platform is realized on printed circuit boards using surface mount devices. A wide variety of circuits can be configured on this platform through a custom graphical user interface. This allows students to conduct many experiments relatively quickly. More information is available from Illuster (see link on the Companion Website).
xxiv Preface
An Outline for the Reader
Part I, Devices and Basic Circuits, includes the most fundamental and essential topics for the study of electronic circuits. At the same time, it constitutes a complete package for a first course on the subject. Chapter 1. The book starts with an introduction to the basic concepts of electronics in Chapter 1. Signals, their frequency spectra, and their analog and digital forms are presented. Amplifiers are introduced as circuit building blocks and their various types and models are studied. This chapter also
establishes some of the terminology and conventions used throughout the text.
Chapter 2. Chapter 2 deals with operational amplifiers, their terminal characteristics, simple appli- cations, and practical limitations. We chose to discuss the op amp as a circuit building block at this early stage simply because it is easy to deal with and because the student can experiment with op-amp circuits that perform nontrivial tasks with relative ease and with a sense of accomplishment. We have found this approach to be highly motivating to the student. We should point out, however, that part or all of this chapter can be skipped and studied at a later stage (for instance, in conjunction with
Chapter 9, Chapter 11, and/or Chapter 13) with no loss of continuity.
Chapter 3. Chapter 3 provides an overview of semiconductor concepts at a level sufficient for under-
standing the operation of diodes and transistors in later chapters. Coverage of this material is useful in particular for students who have had no prior exposure to device physics. Even those with such a background would find a review of Chapter 3 beneficial as a refresher. The instructor can choose to cover this material in class or assign it for outside reading.
Chapter 4. The first electronic device, the diode, is studied in Chapter 4. The diode terminal character- istics, the circuit models that are used to represent it, and its circuit applications are presented. Depending on the time available in the course, some of the diode applications (e.g. Section 4.6) can be skipped. Also, the brief description of special diode types (Section 4.7) can be left for the student to read.
Chapters 5 and 6. The foundation of electronic circuits is established by the study of the two transis- tor types in use today: the MOS transistor in Chapter 5 and the bipolar transistor in Chapter 6. These two chapters have been written to be completely independent of one another and thus can be studied in either order, as desired. Furthermore, the two chapters have the same structure, making it easier and faster to study the second device, as well as to draw comparisons between the two device types.
Each of Chapters 5 and 6 begins with a study of the device structure and its physical operation, lead- ing to a description of its terminal characteristics. Then, to allow the student to become very familiar with the operation of the transistor as a circuit element, a large number of examples are presented of dc circuits utilizing the device. The last section of each of Chapters 5 and 6 deals with second-order effects that are included for completeness, but that can be skipped if time does not permit detailed coverage.
Chapter 7. The heart of a first course in electronics is the study of transistor amplifiers. Chapter 7 (new to this edition) presents a unified treatment of the subject. It begins with the basic principles that underlie the operation of a transistor, of either type, as an amplifier, and proceeds to present the important concepts of small-signal operation and modeling. This is followed by a study of the basic configurations of single-transistor amplifiers. After a presentation of dc biasing methods, the chapter concludes with practical examples of discrete-circuit amplifiers. The combined presentation emphasizes the unity of the basic principles while allowing for separate treatment of the two device types where this is warranted. Very importantly, we are able to compare the two devices and to draw conclusions about their unique areas of application.
After the study of Part I, the reader will be fully prepared to study either integrated-circuit ampli- fiers in Part II, or digital integrated circuits in Part III.
Part II, Integrated-Circuit Amplifiers, is devoted to the study of practical amplifier circuits that can be fabricated in the integrated-circuit (IC) form. Its six chapters constitute a coherent treatment of IC amplifier design and can thus serve as a second course in electronic circuits.
MOS and Bipolar. Throughout Part II, both MOS and bipolar circuits are presented side-by-side. Because the MOSFET is by far the dominant device, its circuits are presented first. Bipolar circuits are discussed to the same depth but occasionally more briefly.
Chapter 8. Beginning with a brief introduction to the philosophy of IC design, Chapter 8 presents the basic circuit building blocks that are used in the design of IC amplifiers. These include current mirrors, current sources, gain cells, and cascode amplifiers.
Chapter 9. The most important IC building block, the differential pair, is the main topic of Chapter 9. The last section of Chapter 9 is devoted to the study of multistage amplifiers.
Chapter 10. Chapter 10 presents a comprehensive treatment of the important subject of amplifier frequency response. Here, Sections 10.1, 10.2, and 10.3 contain essential material; Section 10.4 pro- vides an in-depth treatment of very useful new tools; and Sections 10.5 to 10.8 present the frequency response analysis of a variety of amplifier configurations that can be studied as and when needed. A selection of the latter sections can be made depending on the time available and the instructor’s preference.
Chapter 11. The fourth of the essential topics of Part II, feedback, is the subject of Chapter 11. Both the theory of negative feedback and its application in the design of practical feedback ampli- fiers are presented. We also discuss the stability problem in feedback amplifiers and treat frequency compensation in some detail.
Chapter 12. In Chapter 12 we switch gears from dealing with small-signal amplifiers to those that are required to handle large signals and large amounts of power. Here we study the different amplifier classes—A, B, and AB—and their realization in bipolar and CMOS technologies. We also consider power BJTs and power MOSFETs, and study representative IC power amplifiers. A brief study of the increasingly popular Class D amplifier is also presented. Depending on the availability of time, some of the later sections can be skipped in a first reading.
Chapter 13. Finally, Chapter 13 brings together all the topics of Part II in an important application; namely, the design of operational amplifier circuits. We study both CMOS and bipolar op amps. In the latter category, besides the classical and still timely 741 circuit, we present modern techniques for the design of low-voltage op amps (Section 13.4).
Part III, Digital Integrated Circuits, provides a brief but nonetheless comprehensive and sufficiently detailed study of digital IC design. Our treatment is almost self-contained, requiring for the most part only a thorough understanding of the MOSFET material presented in Chapter 5. Thus, Part III can be studied right after Chapter 5. The only exceptions to this are the last section in Chapter 15 which requires knowledge of the BJT (Chapter 6). Also, knowledge of the MOSFET internal capacitances (Section 10.2.2) will be needed.
Chapter 14. Chapter 14 is the foundation of Part III. It begins with the motivating topic of CMOS logic-gate circuits. Then, following a detailed study of digital logic inverters, we concentrate on the CMOS inverter; its static and dynamic characteristics and its design. Transistor sizing and power dissipation round out the topics of Chapter 14. The material covered in this chapter is the minimum needed to learn something meaningful about digital circuits.
Chapter 15. Chapter 15 has a modular structure and presents six topics of somewhat advanced nature. It begins with a presentation of Moore’s law and the technology scaling that has made the multi-billion-transistor chip possible. This is followed by an overview of digital IC technologies, and the design methodologies that make the design of super-complex digital ICs possible. Four different logic-circuit types are then presented. Only the last of these includes bipolar transistors.
Chapter 16. Digital circuits can be broadly divided into logic and memory circuits. The latter is the subject of Chapter 16.
Part IV, Filters and Oscillators, is intentionally oriented toward applications and systems. The two topics illustrate powerfully and dramatically the application of both negative and positive feedback.
Chapter 17. Chapter 17 deals with the design of filters, which are important building blocks of com- munication and instrumentation systems. A comprehensive, design-oriented treatment of the subject is presented. The material provided should allow the reader to perform a complete filter design, starting from specification and ending with a complete circuit realization. A wealth of design tables is included.
Chapter 18. Chapter 18 deals with circuits for the generation of signals with a variety of waveforms: sinusoidal, square, and triangular. We also present circuits for the nonlinear shaping of waveforms.
Preface xxv
xxvi Preface
Appendices. The twelve appendices contain much useful background and supplementary material. We wish to draw the reader’s attention in particular to the first two: Appendix A provides a con- cise introduction to the important topic of IC fabrication technology including IC layout. Appendix B provides SPICE device models as well as a large number of design and simulation examples in PSpice® and MultisimTM. The examples are keyed to the book chapters. These Appendices and a great deal more material on these simulation examples can be found on the Companion Website.
Ancillaries
A complete set of ancillary materials is available with this text to support your course.
For the Instructor
The Ancillary Resource Center (ARC) at www.oup-arc.com/sedrasmith is a convenient destination for all the instructor resources that accompany Microelectronic Circuits. Accessed online through individual user accounts, the ARC provides instructors with access to up-to-date ancillaries at any time while guaranteeing the security of grade-significant resources. The ARC replaces the Instructor’s Resource CD that accompanied the sixth edition. On the ARC, you will find:
• An electronic version of the Instructor’s Solutions Manual.
• PowerPoint-based figure slides that feature all the images and summary tables from the text, with
their captions, so they can easily be displayed and explained in class.
• Detailed instructor’s support for the SPICE circuit simulations in MultisimTM and PSpice®.
The Instructor’s Solutions Manual (ISBN 978-0-19-933915-0), written by Adel Sedra, contains detailed solutions to all in-text exercises and end-of-chapter problems found in Microelectronic Circuits. The Instructor’s Solutions Manual for Laboratory Explorations to Accompany Microelectronic Circuits (ISBN 978-0-19-933926-6) contains detailed solutions to all the exercises and problems found in this student’s laboratory guide.
For the Student and Instructor
A Companion Website at www.oup.com/us/sedrasmith features permanently cached versions of device datasheets, so students can design their own circuits in class. The website also contains SPICE circuit simulation examples and lessons. Bonus text topics and the Appendices are also featured on the website.
The Laboratory Explorations to Accompany Microelectronic Circuits (ISBN 978-0-19-933925-9) invites students to explore the realm of real-world engineering through practical, hands-on experi- ments. Keyed to sections in the text and taking a “learn-by-doing” approach, it presents labs that focus on the development of practical engineering skills and design practices.
Acknowledgments
Many of the changes in this seventh edition were made in response to feedback received from instruc- tors who adopted the sixth edition. We are grateful to all those who took the time to write to us. In addition, many of the reviewers provided detailed commentary on the sixth edition and suggested a number of the changes that we have incorporated in this edition. They are listed later; to all of them, we extend our sincere thanks. Adel Sedra is also grateful for the feedback received from the students who have taken his electronics courses over the past number of years at the University of Waterloo.
A number of individuals made significant contributions to this edition. Vincent Gaudet of the University of Waterloo contributed to Part III as well as co-authoring the laboratory manual. Wai- Tung Ng of the University of Toronto contributed to Chapter 12 and updated Appendix A (of which he is the original author). Muhammad Faisal of the University of Michigan updated Appendix B, which he helped create for the sixth edition; helped in obtaining the cover photo, and has over a num- ber of years been the source of many good ideas. Olivier Trescases and his students at the University of Toronto pioneered the laboratory system described elsewhere in the Preface. Jennifer Rodrigues typed all the revisions, as she did for a number of the previous editions, with tremendous skill and good humour. Chris Schroeder was of great assistance to Adel Sedra with local logistics. Laura Fujino assisted in many ways and in particular with the “Expand-Your-Perspective” notes. To all of these friends and colleagues we say thank you.
Over the recent years we have benefited greatly from discussions with a number of colleagues and friends. In particular we are very grateful to the following: James Barby, University of Waterloo; David Nairn, University of Waterloo; Anthony Chan Carusone, University of Toronto; David Johns, University of Toronto; Ken Martin, University of Toronto; Khoman Phang, University of Toronto; Gordon Roberts, McGill University; Ali Sheikholeslami, University of Toronto; and Amir Yazdani, Ryerson University.
The cover photograph shows a 3D IC system, which demonstrates the concept of wireless power delivery and communication through multiple layers of CMOS chips. The communication circuits were demonstrated in an IBM 45 nm SOI CMOS process. This technology is designed to serve a multi-Gb/s interconnect between cores spread across several IC layers for high-performance proces- sors. We are grateful to Professor David Wentzloff, Director of the Wireless Integrated Circuits Group at the University of Michigan, who allowed us to use this image, and to Muhammad Faisal, Founder of Movellus Circuits Incorporated, who edited the image.
A large number of people at Oxford University Press contributed to the development of this edition and its various ancillaries. We would like to specifically mention Marketing Manager David Jurman, Marketing Director Frank Mortimer, Higher Ed Sales Director Bill Marting, Copywriter Kristin Maffei, Art Director Michele Laseau, Production Manager Lisa Grzan, Team Leader Amy Whitmer, and Senior Production Editor Jane Lee.
We wish to extend special thanks to our Publisher at Oxford University Press, John Challice, and the Editorial Director, Patrick Lynch. Both have always shown great interest in this book and have provided considerable guidance and support throughout the process of preparing this edition. The Senior Acquisitions Editor, Nancy Blaine, and Associate Editor, Christine Mahon, have done a truly outstanding job. It has been a pleasure to work with both of them, both as professionals and as highly thoughtful individuals; we owe them much gratitude. On the production side, Barbara Mathieu, Senior Production Editor, has been superb: her attention to detail and emphasis on quality is without par.
Finally, we wish to thank our families for their support and understanding, and to thank all the students and instructors who have valued this book throughout its history.
Adel S. Sedra Kenneth C. (KC) Smith Waterloo, Ontario, Canada August 2014
Preface xxvii
xxviii Preface
Reviewers of Seventh Edition
Junseok Chae, Arizona State University, Tempe, AZ
Liang Dong, Baylor University, Waco, TX
Muhammad Faisal, University of Michigan, Ann Arbor, MI Patrick Fay, University of Notre Dame, Notre Dame, IN Vincent Gaudet, University of Waterloo, Waterloo, Canada Elmer A Grubbs, Northern Arizona University, Flagstaff, AZ Serhiy Levkov, New Jersey Institute of Technology, Newark, NJ Leda Lunardi, North Carolina State University, Raleigh, NC Phyllis R. Nelson, California State Polytechnic University,
Pomona, CA
Robert W. Newcomb, University of Maryland, College Park,
MD
Toshikazu Nishida, University of Florida, Gainesville, FL Matthew Swabey, Purdue University, West Lafayette, IN Khalid Hasan Tantawi, University of Alabama, Huntsville, AL Farid M. Tranjan, University of North Carolina, Charlotte, NC Mustapha C.E. Yagoub, University of Ottawa, Ottawa,
Canada
Justin Jackson, Weber State University, Ogden, UT John Mankowski, Texas Tech University, Lubbock, TX Chris Mi, University of Michigan, Dearborn, MI
Reviewers of Prior Editions
Maurice Aburdene, Bucknell University, Lewisburg, PA Michael Bartz, University of Memphis, TN
Elizabeth Brauer, Northern Arizona University, Flagstaff, AZ Martin Brooke, Duke University, Durham, NC
Patrick L. Chapman, University of Illinois, Urbana– Champaign, IL
Yun Chiu, University of Illinois, Urbana–Champaign, IL Roy H. Cornely, New Jersey Institute of Technology,
Newark, NJ
Norman Cox, Missouri University of Science and
Technology, Rolla, MO
Dale L. Critchlow, University of Vermont, Burlingon, VT Robert Bruce Darling, University of Washington, Seattle, WA Artice Davis, San Jose State University, CA
John Davis, University of Texas, Austin, TX
Christopher DeMarco, University of Wisconsin, Madison, WI Robert Engelken, Arkansas State University, Jonesboro, AR Ethan Farquhar, University of Tennessee, Knoxville, TN Eby G. Friedman, University of Rochester, NY
Paul M. Furth, New Mexico State University, Las Cruces, NM Rhett T. George, Jr., Duke University, Durham, NC
Roobik Gharabagi, St. Louis University, MO
George Giakos, University of Akron, OH
John Gilmer, Wilkes University, Wilkes-Barre, PA
Michael Green, University of California, Irvine, CA
Steven de Haas, California State University, Sacramento, CA Anas Hamoui, McGill University, Montreal, Canada
Reza Hashemian, Northern Illinois University, DeKalb, IL William Harrell, Clemson University, SC
Reid Harrison, University of Utah, Salt Lake City, UT
Ward J. Helms, University of Washington, Seattle, WA Richard Hornsey, York University, Toronto, Canada Timothy Horiuchi, University of Maryland, College Park, MD
Hsiung Hsu, The Ohio State University, Columbus, OH Robert Irvine, California State Polytechnic University,
Pomona, CA
Mohammed Ismail, The Ohio State University, Columbus, OH Paul Israelsen, Utah State University, Logan UT
Steve Jantzi, Broadcom, CA
Zhenhua Jiang, University of Miami, FL
Marian Kazimierczuk, Wright State University, Dayton, OH John Khoury, Columbia University, New York, NY
Jacob B. Khurgin, The Johns Hopkins University, Baltimore,
MD
Seongsin M. Kim, University of Alabama, Tuscaloosa, AL Roger King, University of Toledo, OH
Clark Kinnaird, Southern Methodist University, Dallas, TX Robert J. Krueger, University of Wisconsin, Milwaukee, WI Joy Laskar, Georgia Institute of Technology, Atlanta, GA Tsu-Jae King Liu, University of California, Berkeley, CA Yicheng Lu, Rutgers University, Piscataway, NJ
David Luke, University of New Brunswick, Fredericton,
Canada
Thomas Matthews, California State University, Sacramento, CA Un-Ku Moon, Oregon State University, Corvallis, OR Bahram Nabet, Drexel University, Philadelphia, PA Dipankar Nagchoudhuri, Indian Institute of Technology,
Delhi, India
David Nairn, University of Waterloo, Waterloo, Canada Joseph H. Nevin, University of Cincinnati, OH
Ken Noren, University of Idaho, Moscow, ID
Brita Olson, California Polytechnic University, Pomona, CA Martin Peckerar, University of Maryland, College Park, MD Khoman Phang, University of Toronto, Canada
Mahmudur Rahman, Santa Clara University, CA
Rabin Raut, Concordia University, Montreal, Canada
John A. Ringo, Washington State University, Pullman, WA Zvi S. Roth, Florida Atlantic University, Boca Raton, FL Mulukutla Sarma, Northeastern University, Boston, MA John Scalzo, Louisiana State University, Baton Rouge, LA Norman Scheinberg, City College, New York, NY
Pierre Schmidt, Florida International University, Miami, FL Richard Schreier, Analog Devices, Toronto, Canada Dipankar Sengupta, Royal Melbourne Institute of
Technology, Australia
Ali Sheikholeslami, University of Toronto, Canada
Kuang Sheng, Rutgers University, Piscataway, NJ
Michael L. Simpson, University of Tennessee, Knoxville, TN Karl A. Spuhl, Washington University in St. Louis, MO Charles Sullivan, Dartmouth College, Hanover, NH
Andrew Szeto, San Diego State University, CA
Joel Therrien, University of Massachusetts, Lowell, MA
Len Trombetta, University of Houston, TX
Daniel van der Weide, University of Delaware, Newark, DE Gregory M. Wierzba, Michigan State University, East
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Donna Yu, North Carolina State University, Raleigh, NC Jiann-Shiun Yuan, University of Central Florida, Orlando, FL Sandra Yost, University of Detroit, Mercy, MI
Alex Zaslavsky, Brown University, Providence, RI
Jianhua (David) Zhang, University of Illinois, Urbana–
Champaign, IL
Microelectronic Circuits
PART I
Devices and Basic Circuits
CHAPTER 1
SignalsandAmplifiers 4
CHAPTER 2
OperationalAmplifiers 58
CHAPTER 3
Semiconductors 134
CHAPTER 4
Diodes 174
CHAPTER 5
MOSField-EffectTransistors(MOSFETs) 246
CHAPTER 6
BipolarJunctionTransistors(BJTs) 304
CHAPTER 7
TransistorAmplifiers 366
Part I, Devices and Basic Circuits, includes the most fundamental and essential topics for the study of electronic circuits. At the same time, it constitutes a complete package for a first course on the subject.
The heart of Part I is the study of the three basic semiconductor devices: the diode (Chapter 4), the MOS transistor (Chapter 5), and the bipolar transistor (Chapter 6). In each case, we study the device operation, its characterization, and its basic circuit applications. Chapter 7 then follows with a study of the most fundamental application of the two transistor types; namely, their use in amplifier design. This side-by-side study of MOSFET and BJT amplifiers allows us to see similarities between these amplifiers and to compare them, which in turn highlights the distinct areas of applicability of each, as well as showing the unity of the basic principles that underlie the use of transistors as amplifiers.
For those who have not had a prior course on device physics, Chapter 3 provides an overview of semiconductor concepts at a level sufficient for the study of electronic circuits. A review of Chapter 3 should prove useful even for those with prior knowledge of semiconductors.
Since the purpose of electronic circuits is the processing of signals, it is essential to understand signals, their characterization in the time and frequency domains, and their analog and digital representations. The basis for such understanding is provided in Chapter1, which also introduces the most common signal-processing function, amplification, and the characterization and types of amplifiers.
Besides diodes and transistors, the basic electronic devices, the op amp is studied in Part I. Although not an electronic device in the most fundamental sense, the op amp is commercially available as an integrated circuit (IC) package and has well-defined terminal characteristics. Thus, even though the op amp’s internal circuit is complex, typically incorporating 20 or more transistors, its almost-ideal terminal behavior makes it possible to treat the op amp as a circuit element and to use it in the design of powerful circuits, as we do in Chapter 2, without any knowledge of its internal construction. We should mention, however, that the study of op amps can be delayed until a later point, and Chapter 2 can be skipped with no loss of continuity.
The foundation of this book, and of any electronics course, is the study of the two transistor types in use today: the MOS transistor in Chapter 5 and the bipolar transistor in Chapter 6. These two chapters have been written to be completely independent of each other and thus can be studied in either order, as desired.
After the study of Part I, the reader will be fully prepared to undertake the study of either integrated-circuit amplifiers in Part II or digital integrated circuits in Part III.
3
CHAPTER 1
Signals
and Amplifiers
Introduction 5
1.1 Signals 6
1.2 Frequency Spectrum of Signals
1.3 Analog and Digital Signals 12
1.4 Amplifiers 15
1.5 1.6
Circuit Models for Amplifiers 23 Frequency Response of Amplifiers 33 Summary 44
Problems 45
9
IN THIS CHAPTER YOU WILL LEARN
1. That electronic circuits process signals, and thus understanding electrical signals is essential to appreciating the material in this book.
2. The The ́ venin and Norton representations of signal sources.
3. The representation of a signal as the sum of sine waves.
4. The analog and digital representations of a signal.
5. The most basic and pervasive signal-processing function: signal amplification, and correspondingly, the signal amplifier.
6. How amplifiers are characterized (modeled) as circuit building blocks independent of their internal circuitry.
7. How the frequency response of an amplifier is measured, and how it is calculated, especially in the simple but common case of a single-time-constant (STC) type response.
Introduction
The subject of this book is modern electronics, a field that has come to be known as microelectronics. Microelectronics refers to the integrated-circuit (IC) technology that at the time of this writing is capable of producing circuits that contain billions of components in a small piece of silicon (known as a silicon chip) whose area is on the order of 100 mm2 . One such microelectronic circuit, for example, is a complete digital computer, which accordingly is known as a microcomputer or, more generally, a microprocessor. The microelectronic circuits you will learn to design in this book are used in almost every device we encounter in our daily lives: in the appliances we use in our homes; in the vehicles and transportation systems we use to travel; in the cell phones we use to communicate; in the medical equipment we need to care for our health; in the computers we use to do our work; and in the audio and video systems, the radio and TV sets, and the multitude of other digital devices we use to entertain ourselves. Indeed, it is difficult to conceive of modern life without microelectronic circuits.
In this book we shall study electronic devices that can be used singly (in the design of discrete circuits) or as components of an integrated-circuit (IC) chip. We shall study the design and analysis of interconnections of these devices, which form discrete and integrated
5
6 Chapter 1
Signals and Amplifiers
circuits of varying complexity and perform a wide variety of functions. We shall also learn about available IC chips and their application in the design of electronic systems.
The purpose of this first chapter is to introduce some basic concepts and terminol- ogy. Inparticular, we shall learn about signals and about one of the most important signal-processing functions electronic circuits are designed to perform, namely, signal ampli- fication. We shall then look at circuit representations or models for linear amplifiers. These models will be employed in subsequent chapters in the design and analysis of actual amplifier circuits.
In addition to motivating the study of electronics, this chapter serves as a bridge between the study of linear circuits and that of the subject of this book: the design and analysis of electronic circuits.
1.1 Signals
Signals contain information about a variety of things and activities in our physical world. Examples abound: Information about the weather is contained in signals that represent the air temperature, pressure, wind speed, etc. The voice of a radio announcer reading the news into a microphone provides an acoustic signal that contains information about world affairs. To monitor the status of a nuclear reactor, instruments are used to measure a multitude of relevant parameters, each instrument producing a signal.
To extract required information from a set of signals, the observer (be it a human or a machine) invariably needs to process the signals in some predetermined manner. This signal processing is usually most conveniently performed by electronic systems. For this to be possible, however, the signal must first be converted into an electrical signal, that is, a voltage or a current. This process is accomplished by devices known as transducers. A variety of transducers exist, each suitable for one of the various forms of physical signals. For instance, the sound waves generated by a human can be converted into electrical signals by using a microphone, which is in effect a pressure transducer. It is not our purpose here to study transducers; rather, we shall assume that the signals of interest already exist in the electrical domain and represent them by one of the two equivalent forms shown in Fig. 1.1. In Fig. 1.1(a) the signal is represented by a voltage source vs(t) having a source resistance Rs . In the alternate representation of Fig. 1.1(b) the signal is represented by a current source is(t) having a source resistance Rs. Although the two representations are equivalent, that in Fig. 1.1(a) (known as the The ́venin form) is preferred when Rs is low. The representation of Fig. 1.1(b) (known as the Norton form) is preferred when Rs is high. The reader will come to appreciate this point later in this chapter when we study the different types of amplifiers. For the time being, it is important to be familiar with The ́venin’s and Norton’s theorems (for a
vs(t)
Rs
is(t)
Rs
(a) (b)
Figure 1.1 Two alternative representations of a signal source: (a) the The ́venin form; (b) the Norton form.
brief review, see Appendix D) and to note that for the two representations in Fig. 1.1 to be equivalent, their parameters are related by
vs(t) = Rsis(t)
Example 1.1
The output resistance of a signal source, although inevitable, is an imperfection that limits the ability of the source to deliver its full signal strength to a load. To see this point more clearly, consider the signal source whenconnectedtoaloadresistanceRL asshowninFig.1.2.Forthecaseinwhichthesourceisrepresented by its The ́venin equivalent form, find the voltage vo that appears across RL, and hence the condition that Rs must satisfy for vo to be close to the value of vs. Repeat for the Norton-represented source; in this case finding the current io that flows through RL and hence the condition that Rs must satisfy for io to be close to the value of is.
Rs
io vsRLvois RsRL
1.1 Signals 7
(a)
Figure 1.2 Circuits for Example 1.1.
Solution
(b)
For the The ́venin-represented signal source shown in Fig. 1.2(a), the output voltage vo that appears across the load resistance RL can be found from the ratio of the voltage divider formed by Rs and RL ,
v=v RL
o s RL +Rs
From this equation we see that for
vo ≃vs thesourceresistanceRs mustbemuchlowerthantheloadresistanceRL,
Rs ≪RL
Thus, for a source represented by its The ́venin equivalent, ideally Rs = 0, and as Rs is increased, relative to the load resistance RL with which this source is intended to operate, the voltage vo that appears across the load becomes smaller, not a desirable outcome.
8
Chapter 1 Signals and Amplifiers
Example 1.1 continued
Next, we consider the Norton-represented signal source in Fig. 1.2(b). To obtain the current io that flows
throughtheloadresistanceRL,weutilizetheratioofthecurrentdividerformedbyRs andRL, i=i Rs
o s Rs +RL
From this relationship we see that for
io ≃is thesourceresistanceRs mustbemuchlargerthanRL,
Rs ≫RL
Thus for a signal source represented by its Norton equivalent, ideally Rs = ∞, and as Rs is reduced, relative to the load resistance RL with which this source is intended to operate, the current io that flows through the load becomes smaller, not a desirable outcome.
Finally, we note that although circuit designers cannot usually do much about the value of Rs, they may have to devise a circuit solution that minimizes or eliminates the loss of signal strength that results when the source is connected to the load.
EXERCISES
1.1 Forthesignal-sourcerepresentationsshowninFigs.1.1(a)and1.1(b),whataretheopen-circuitoutput voltages that would be observed? If, for each, the output terminals are short-circuited (i.e., wired together), what current would flow? For the representations to be equivalent, what must the relationship be between vs,is, and Rs?
Ans. For (a), voc = vs(t); for (b), voc = Rsis(t); for (a), isc = vs(t)/Rs; for (b), isc = is(t); for equivalency,
vs(t) = Rsis(t)
1.2 Asignalsourcehasanopen-circuitvoltageof10mVandashort-circuitcurrentof10μA.Whatisthe
source resistance?
Ans. 1 k
1.3 A signal source that is most conveniently represented by its The ́venin equivalent has vs = 10 mV and
Rs = 1 k. If the source feeds a load resistance RL , find the voltage v o that appears across the load for RL = 100 k, 10 k, 1 k, and 100 . Also, find the lowest permissible value of RL for which the output voltage is at least 80% of the source voltage.
Ans. 9.9mV;9.1mV;5mV;0.9mV;4k
1.4 A signal source that is most conveniently represented by its Norton equivalent form has is = 10 μA and Rs = 100 k. If the source feeds a load resistance RL , find the current io that flows through the load for RL = 1 k, 10 k, 100 k, and 1 M. Also, find the largest permissible value of RL for which the load current is at least 80% of the source current.
Ans. 9.9 μA; 9.1 μA; 5 μA; 0.9 μA; 25 k
Figure 1.3 An arbitrary voltage signal vs(t).
From the discussion above, it should be apparent that a signal is a time-varying quantity that can be represented by a graph such as that shown in Fig. 1.3. In fact, the information content of the signal is represented by the changes in its magnitude as time progresses; that is, the information is contained in the “wiggles” in the signal waveform. In general, such waveforms are difficult to characterize mathematically. In other words, it is not easy to describe succinctly an arbitrary-looking waveform such as that of Fig. 1.3. Of course, such a description is of great importance for the purpose of designing appropriate signal-processing circuits that perform desired functions on the given signal. An effective approach to signal characterization is studied in the next section.
1.2 Frequency Spectrum of Signals
An extremely useful characterization of a signal, and for that matter of any arbitrary function of time, is in terms of its frequency spectrum. Such a description of signals is obtained through the mathematical tools of Fourier series and Fourier transform.1 We are not interested here in the details of these transformations; suffice it to say that they provide the means for representing a voltage signal vs(t) or a current signal is(t) as the sum of sine-wave signals of different frequencies and amplitudes. This makes the sine wave a very important signal in the analysis, design, and testing of electronic circuits. Therefore, we shall briefly review the properties of the sinusoid.
Figure 1.4 shows a sine-wave voltage signal va(t),
va(t)=Va sinωt (1.1)
where Va denotes the peak value or amplitude in volts and ω denotes the angular frequency in radians per second; that is, ω = 2π f rad/s, where f is the frequency in hertz, f = 1/T Hz, and T is the period in seconds.
The sine-wave signal is completely characterized by its peak value Va , its frequency ω, and its phase with respect to an arbitrary reference time. In the case depicted in Fig. 1.4, the time
1The reader who has not yet studied these topics should not be alarmed. No detailed application of this material will be made until Chapter 10. Nevertheless, a general understanding of Section 1.2 should be very helpful in studying early parts of this book.
1.2 Frequency Spectrum of Signals 9
10 Chapter 1
Signals and Amplifiers
Figure1.5 Asymmetricalsquare-wavesignalofamplitudeV.
origin has been chosen so that the phase angle is 0. It should be mentioned that it is common to express the amplitude of a sine-wave signal in terms of its root-mean-square (rms) value,
√
of Fig. 1.4 is V / 2. For instance, when we speak of the wall power supply in our homes as
a
2 volts peak value.
Returning now to the representation of signals as the sum of sinusoids, we note that the Fourier series is utilized to accomplish this task for the special case of a signal that is a periodic function of time. On the other hand, the Fourier transform is more general and can be used to
obtain the frequency spectrum of a signal whose waveform is an arbitrary function of time. The Fourier series allows us to express a given periodic function of time as the sum of an infinite number of sinusoids whose frequencies are harmonically related. For instance, the
symmetrical square-wave signal in Fig. 1.5 can be expressed as
v(t)= 4V(sinω0t+1sin3ω0t+1sin5ω0t+···) (1.2)
where V is the amplitude of the square wave and ω0 = 2π /T (T is the period of the square wave) is called the fundamental frequency. Note that because the amplitudes of the harmonics progressively decrease, the infinite series can be truncated, with the truncated series providing an approximation to the square waveform.
The sinusoidal components in the series of Eq. (1.2) constitute the frequency spectrum of the square-wave signal. Such a spectrum can be graphically represented as in Fig. 1.6, where the horizontal axis represents the angular frequency ω in radians per second.
Figure 1.4 Sine-wave voltage signal of amplitude Va and frequency f = 1/T Hz. The angular frequency ω = 2π f rad/s.
which is equal to the peak value divided by
2. Thus the rms value of the sinusoid v (t) a
√
being 120 V, we mean that it has a sine waveform of 120
√
π35
Figure 1.6 The frequency spectrum (also known as the line spectrum) of the periodic square wave of Fig. 1.5.
Figure1.7 Thefrequencyspectrumof an arbitrary waveform such as that in Fig. 1.3.
The Fourier transform can be applied to a nonperiodic function of time, such as that depicted in Fig. 1.3, and provides its frequency spectrum as a continuous function of frequency, as indicated in Fig. 1.7. Unlike the case of periodic signals, where the spectrum consists of discrete frequencies (at ω0 and its harmonics), the spectrum of a nonperiodic signal contains in general all possible frequencies. Nevertheless, the essential parts of the spectra of practical signals are usually confined to relatively short segments of the frequency (ω) axis—an observation that is very useful in the processing of such signals. For instance, the spectrum of audible sounds such as speech and music extends from about 20 Hz to about 20 kHz—a frequency range known as the audio band. Here we should note that although some musical tones have frequencies above 20 kHz, the human ear is incapable of hearing frequencies that are much above 20 kHz. As another example, analog video signals have their spectra in the range of 0 MHz to 4.5 MHz.
We conclude this section by noting that a signal can be represented either by the manner in which its waveform varies with time, as for the voltage signal va(t) shown in Fig. 1.3, or in terms of its frequency spectrum, as in Fig. 1.7. The two alternative representations are known as the time-domain representation and the frequency-domain representation, respectively. The frequency-domain representation of va(t) will be denoted by the symbol Va(ω).
1.2 Frequency Spectrum of Signals 11
12 Chapter 1 Signals and Amplifiers
EXERCISES
1.5 Find the frequencies f and ω of a sine-wave signal with a period of 1 ms. Ans. f =1000Hz;ω=2π×103 rad/s
1.6 What is the period T of sine waveforms characterized by frequencies of (a) f = 60 Hz? (b) f = 10−3 Hz? (c)f =1MHz?
Ans. 16.7 ms; 1000 s; 1 μs
1.7 The UHF (ultra high frequency) television broadcast band begins with channel 14 and extends from
470 MHz to 806 MHz. If 6 MHz is allocated for each channel, how many channels can this band accommodate?
Ans. 56; channels 14 to 69
1.8 When the square-wave signal of Fig. 1.5, whose Fourier series is given in Eq. (1.2), is applied to a resistor, the total power dissipated may be calculated directly using the relationship P = 1/T T (v 2 /R) dt
0
or indirectly by summing the contribution of each of the harmonic components, that is, P = P1 + P3 +
P5 + . . . , which may be found directly from rms values. Verify that the two approaches are equivalent. What fraction of the energy of a square wave is in its fundamental? In its first five harmonics? In its first seven? First nine? In what number of harmonics is 90% of the energy? (Note that in counting harmonics, the fundamental at ω0 is the first, the one at 2ω0 is the second, etc.)
Ans. 0.81; 0.93; 0.95; 0.96; 3
1.3 Analog and Digital Signals
The voltage signal depicted in Fig. 1.3 is called an analog signal. The name derives from the fact that such a signal is analogous to the physical signal that it represents. The magnitude of an analog signal can take on any value; that is, the amplitude of an analog signal exhibits a continuous variation over its range of activity. The vast majority of signals in the world around us are analog. Electronic circuits that process such signals are known as analog circuits. A variety of analog circuits will be studied in this book.
An alternative form of signal representation is that of a sequence of numbers, each number representing the signal magnitude at an instant of time. The resulting signal is called a digital signal. To see how a signal can be represented in this form—that is, how signals can be converted from analog to digital form—consider Fig. 1.8(a). Here the curve represents a voltage signal, identical to that in Fig. 1.3. At equal intervals along the time axis, we have marked the time instants t0,t1,t2, and so on. At each of these time instants, the magnitude of the signal is measured, a process known as sampling. Figure 1.8(b) shows a representation of the signal of Fig. 1.8(a) in terms of its samples. The signal of Fig. 1.8(b) is defined only at the sampling instants; it no longer is a continuous function of time; rather, it is a discrete-time signal. However, since the magnitude of each sample can take any value in a continuous range, the signal in Fig. 1.8(b) is still an analog signal.
Now if we represent the magnitude of each of the signal samples in Fig. 1.8(b) by a number having a finite number of digits, then the signal amplitude will no longer be continuous; rather,
(a)
Figure 1.8 Sampling the continuous-time analog signal in (a) results in the discrete-time signal in (b).
it is said to be quantized, discretized, or digitized. The resulting digital signal then is simply a sequence of numbers that represent the magnitudes of the successive signal samples.
The choice of number system to represent the signal samples affects the type of digital signal produced and has a profound effect on the complexity of the digital circuits required to process the signals. It turns out that the binary number system results in the simplest possible digital signals and circuits. In a binary system, each digit in the number takes on one of only two possible values, denoted 0 and 1. Correspondingly, the digital signals in binary systems need have only two voltage levels, which can be labeled low and high. As an example, in some of the digital circuits studied in this book, the levels are 0 V and +5 V. Figure 1.9 shows the time variation of such a digital signal. Observe that the waveform is a pulse train with 0 V representing a 0 signal, or logic 0, and +5 V representing logic 1.
If we use N binary digits (bits) to represent each sample of the analog signal, then the digitized sample value can be expressed as
D=b020 +b121 +b222 +···+bN−12N−1 (1.3)
where b0,b1,…,bN−1, denote the N bits and have values of 0 or 1. Here bit b0 is the least significant bit (LSB), and bit bN−1 is the most significant bit (MSB). Conventionally, this binary number is written as bN−1 bN−2 …b0. We observe that such a representation quantizes theanalogsampleintooneof2N levels.Obviouslythegreaterthenumberofbits(i.e.,thelarger the N ), the closer the digital word D approximates the magnitude of the analog sample. That is, increasing the number of bits reduces the quantization error and increases the resolution of the
1.3 Analog and Digital Signals 13
14 Chapter 1
Signals and Amplifiers
v (t) (V)
5
Logic values 0 1 0 1 1 0 1 0 0 Time, t Figure 1.9 Variation of a particular binary digital signal with time.
Analog input vA
b0
b1 Digital
A/D converter
bN1
output
Figure 1.10 Block-diagram representation of the analog-to-digital converter (ADC).
analog-to-digital conversion. This improvement is, however, usually obtained at the expense of more complex and hence more costly circuit implementations. It is not our purpose here to delve into this topic any deeper; we merely want the reader to appreciate the nature of analog and digital signals. Nevertheless, it is an opportune time to introduce a very important circuit building block of modern electronic systems: the analog-to-digital converter (A/D or ADC) shown in block form in Fig. 1.10. The ADC accepts at its input the samples of an analog signal and provides for each input sample the corresponding N-bit digital representation (according to Eq. 1.3) at its N output terminals. Thus although the voltage at the input might be, say, 6.51 V, at each of the output terminals (say, at the ith terminal), the voltage will be either low (0 V) or high (5 V) if bi is supposed to be 0 or 1, respectively. The dual circuit of the ADC is the digital-to-analog converter (D/A or DAC). It converts an N -bit digital input to an analog output voltage.
Once the signal is in digital form, it can be processed using digital circuits. Of course digital circuits can deal also with signals that do not have an analog origin, such as the signals that represent the various instructions of a digital computer.
Since digital circuits deal exclusively with binary signals, their design is simpler than that of analog circuits. Furthermore, digital systems can be designed using a relatively few different kinds of digital circuit blocks. However, a large number (e.g., hundreds of thousands or even millions) of each of these blocks are usually needed. Thus the design of digital circuits poses its own set of challenges to the designer but provides reliable and economic implementations of a great variety of signal-processing functions, many of which are not possible with analog circuits. At the present time, more and more of the signal-processing functions are being performed digitally. Examples around us abound: from the digital watch and the calculator to digital audio systems, digital cameras, and digital television. Moreover, some long-standing
analog systems such as the telephone communication system are now almost entirely digital. And we should not forget the most important of all digital systems, the digital computer.
The basic building blocks of digital systems are logic circuits and memory circuits. We shall study both in this book, beginning in Chapter 14.
One final remark: Although the digital processing of signals is at present all-pervasive, there remain many signal-processing functions that are best performed by analog circuits. Indeed, many electronic systems include both analog and digital parts. It follows that a good electronics engineer must be proficient in the design of both analog and digital circuits, or mixed-signal or mixed-mode design as it is currently known. Such is the aim of this book.
EXERCISE
1.9 Considera4-bitdigitalwordD=b3b2b1b0 (seeEq.1.3)usedtorepresentananalogsignalvA thatvaries between 0 V and +15 V.
(a) GiveDcorrespondingtovA =0V,1V,2V,and15V.
(b) What change in vA causes a change from 0 to 1 in (i) b0, (ii) b1, (iii) b2, and (iv) b3?
(c) If vA = 5.2 V, what do you expect D to be? What is the resulting error in representation? Ans. (a) 0000, 0001, 0010, 1111; (b) +1 V, +2 V, +4 V, +8 V; (c) 0101, –4%
1.4 Amplifiers 15
ANALOG VS. DIGITAL CIRCUIT ENGINEERS:
1.4 Amplifiers
As digital became the preferred implementation of more and more signal-processing functions, the need arose for greater numbers of digital circuit design engineers. Yet despite predictions made periodically that the demand for analog circuit design engineers would lessen, this has not been the case. Rather, the demand for analog engineers has, if anything, increased. What is true, however, is that the skill level required of analog engineers has risen. Not only are they asked to design circuits of greater sophistication and tighter specifications, but they also have to do this using technologies that are optimized for digital (and not analog) circuits. This is dictated by economics, as digital usually constitutes the larger part of most systems.
In this section, we shall introduce the most fundamental signal-processing function, one that is employed in some form in almost every electronic system, namely, signal amplification. We shall study the amplifier as a circuit building block; that is, we shall consider its external characteristics and leave the design of its internal circuit to later chapters.
1.4.1 Signal Amplification
From a conceptual point of view the simplest signal-processing task is that of signal amplification. The need for amplification arises because transducers provide signals that
16 Chapter 1
Signals and Amplifiers
are said to be “weak,” that is, in the microvolt (μV) or millivolt (mV) range and possessing little energy. Such signals are too small for reliable processing, and processing is much easier if the signal magnitude is made larger. The functional block that accomplishes this task is the signal amplifier.
It is appropriate at this point to discuss the need for linearity in amplifiers. Care must be exercised in the amplification of a signal, so that the information contained in the signal is not changed and no new information is introduced. Thus when we feed the signal shown in Fig. 1.3 to an amplifier, we want the output signal of the amplifier to be an exact replica of that at the input, except of course for having larger magnitude. In other words, the “wiggles” in the output waveform must be identical to those in the input waveform. Any change in waveform is considered to be distortion and is obviously undesirable.
An amplifier that preserves the details of the signal waveform is characterized by the relationship
vo(t) = Avi(t) (1.4)
where vi and vo are the input and output signals, respectively, and A is a constant representing the magnitude of amplification, known as amplifier gain. Equation (1.4) is a linear relationship; hence the amplifier it describes is a linear amplifier. It should be easy to see that if the relationship between vo and vi contains higher powers of vi, then the waveform of vo will no longer be identical to that of vi. The amplifier is then said to exhibit nonlinear distortion.
The amplifiers discussed so far are primarily intended to operate on very small input signals. Their purpose is to make the signal magnitude larger, and therefore they are thought of as voltage amplifiers. The preamplifier in the home stereo system is an example of a voltage amplifier.
At this time we wish to mention another type of amplifier, namely, the power amplifier. Such an amplifier may provide only a modest amount of voltage gain but substantial current gain. Thus while absorbing little power from the input signal source to which it is connected, often a preamplifier, it delivers large amounts of power to its load. An example is found in the power amplifier of the home stereo system, whose purpose is to provide sufficient power to drive the loudspeaker, which is the amplifier load. Here we should note that the loudspeaker is the output transducer of the stereo system; it converts the electric output signal of the system into an acoustic signal. A further appreciation of the need for linearity can be acquired by reflecting on the power amplifier. A linear power amplifier causes both soft and loud music passages to be reproduced without distortion.
1.4.2 Amplifier Circuit Symbol
The signal amplifier is obviously a two-port circuit. Its function is conveniently represented by the circuit symbol of Fig. 1.11(a). This symbol clearly distinguishes the input and output ports and indicates the direction of signal flow. Thus, in subsequent diagrams it will not be necessary to label the two ports “input” and “output.” For generality we have shown the amplifier to have two input terminals that are distinct from the two output terminals. A more common situation is illustrated in Fig. 1.11(b), where a common terminal exists between the input and output ports of the amplifier. This common terminal is used as a reference point and is called the circuit ground.
1.4 Amplifiers 17
(a)
Figure 1.11 (a) Circuit symbol for amplifier. (b) An amplifier with a common terminal (ground) between the input and output ports.
(a)
Figure1.12 (a)AvoltageamplifierfedwithasignalvI(t)andconnectedtoaloadresistanceRL.(b)Transfer characteristic of a linear voltage amplifier with voltage gain Av .
1.4.3 Voltage Gain
A linear amplifier accepts an input signal vI(t) and provides at the output, across a load resistanceRL (seeFig.1.12(a)),anoutputsignalvO(t)thatisamagnifiedreplicaofvI(t).The voltage gain of the amplifier is defined by
Voltage gain (Av ) = v O (1.5) vI
Fig. 1.12(b) shows the transfer characteristic of a linear amplifier. If we apply to the input of this amplifier a sinusoidal voltage of amplitude Vˆ , we obtain at the output a sinusoid of amplitude Av Vˆ .
1.4.4 Power Gain and Current Gain
An amplifier increases the signal power, an important feature that distinguishes an amplifier from a transformer. In the case of a transformer, although the voltage delivered to the load could be greater than the voltage feeding the input side (the primary), the power delivered to the load (from the secondary side of the transformer) is less than or at most equal to the
18 Chapter 1
Signals and Amplifiers
power supplied by the signal source. On the other hand, an amplifier provides the load with power greater than that obtained from the signal source. That is, amplifiers have power gain. The power gain of the amplifier in Fig. 1.12(a) is defined as
Power gain (Ap ) ≡ load power (PL ) (1.6) input power(PI )
= vOiO (1.7) vIiI
where iO is the current that the amplifier delivers to the load (RL ), iO = v O /RL , and iI is the current the amplifier draws from the signal source. The current gain of the amplifier is defined as
Current gain (Ai ) ≡ iO iI
From Eqs. (1.5) to (1.8) we note that
Ap = Av Ai 1.4.5 Expressing Gain in Decibels
(1.8)
(1.9)
The amplifier gains defined above are ratios of similarly dimensioned quantities. Thus they will be expressed either as dimensionless numbers or, for emphasis, as V/V for the voltage gain, A/A for the current gain, and W/W for the power gain. Alternatively, for a number of reasons, some of them historic, electronics engineers express amplifier gain with a logarithmic measure. Specifically the voltage gain Av can be expressed as
Voltage gain in decibels = 20 log |Av | dB and the current gain Ai can be expressed as
Current gain in decibels = 20 log |Ai | dB
Since power is related to voltage (or current) squared, the power gain Ap can be expressed in
decibels as
Power gain in decibels = 10 log Ap dB
The absolute values of the voltage and current gains are used because in some cases Av or Ai will be a negative number. A negative gain Av simply means that there is a 180° phase difference between input and output signals; it does not imply that the amplifier is attenuating the signal. On the other hand, an amplifier whose voltage gain is, say, −20 dB is in fact attenuating the input signal by a factor of 10 (i.e., Av = 0.1 V/V).
1.4.6 The Amplifier Power Supplies
Since the power delivered to the load is greater than the power drawn from the signal source, the question arises as to the source of this additional power. The answer is found by observing that amplifiers need dc power supplies for their operation. These dc sources supply the extra power delivered to the load as well as any power that might be dissipated in the internal circuit
1.4 Amplifiers 19
ICC
IEE
(a)
VCC
VCC
ICC
IEE
VEE VEE (b)
Figure 1.13 An amplifier that requires two dc supplies (shown as batteries) for operation.
of the amplifier (such power is converted to heat). In Fig. 1.12(a) we have not explicitly shown these dc sources.
Figure 1.13(a) shows an amplifier that requires two dc sources: one positive of value VCC and one negative of value VEE. The amplifier has two terminals, labeled V+ and V−, for connection to the dc supplies. For the amplifier to operate, the terminal labeled V+ has to be connected to the positive side of a dc source whose voltage is VCC and whose negative side is connected to the circuit ground. Also, the terminal labeled V − has to be connected to the negative side of a dc source whose voltage is VEE and whose positive side is connected to the circuit ground. Now, if the current drawn from the positive supply is denoted ICC and that from the negative supply is IEE (see Fig. 1.13a), then the dc power delivered to the amplifier is
Pdc =VCCICC +VEEIEE
If the power dissipated in the amplifier circuit is denoted Pdissipated , the power-balance equation
for the amplifier can be written as
Pdc + PI = PL + Pdissipated
where PI is the power drawn from the signal source and PL is the power delivered to the load. Since the power drawn from the signal source is usually small, the amplifier power efficiency is defined as
η≡ PL ×100 (1.10) Pdc
The power efficiency is an important performance parameter for amplifiers that handle large amounts of power. Such amplifiers, called power amplifiers, are used, for example, as output amplifiers of stereo systems.
In order to simplify circuit diagrams, we shall adopt the convention illustrated in Fig. 1.13(b). Here the V + terminal is shown connected to an arrowhead pointing upward and the V − terminal to an arrowhead pointing downward. The corresponding voltage is indicated next to each arrowhead. Note that in many cases we will not explicitly show the connections
20 Chapter 1 Signals and Amplifiers
of the amplifier to the dc power sources. Finally, we note that some amplifiers require only
one power supply.
Example 1.2
Consider an amplifier operating from ±10-V power supplies. It is fed with a sinusoidal voltage having 1 V peak and delivers a sinusoidal voltage output of 9 V peak to a 1-k load. The amplifier draws a current of 9.5 mA from each of its two power supplies. The input current of the amplifier is found to be sinusoidal with 0.1 mA peak. Find the voltage gain, the current gain, the power gain, the power drawn from the dc supplies, the power dissipated in the amplifier, and the amplifier efficiency.
Solution
or
or
Av = 9 = 9 V/V 1
Av = 20log9 = 19.1 dB Iˆ o = 9 V = 9 m A
1 k
Ai=Iˆo = 9 =90A/A
or
99
PL =Vorms Iorms =√2√2=40.5mW
1 0.1
PI =Virms Iirms =√2√2=0.05mW
Ap =PL =40.5=810W/W PI 0.05
Ap = 10log810 = 29.1 dB
Pdc =10×9.5+10×9.5=190 mW
Pdissipated = Pdc + PI − PL =190+0.05−40.5=149.6 mW
η= PL ×100=21.3% Pdc
From the above example we observe that the amplifier converts some of the dc power it draws from the power supplies to signal power that it delivers to the load.
Iˆi 0.1
Ai = 20log90 = 39.1 dB
1.4.7 Amplifier Saturation
Practically speaking, the amplifier transfer characteristic remains linear over only a limited range of input and output voltages. For an amplifier operated from two power supplies the output voltage cannot exceed a specified positive limit and cannot decrease below a specified negative limit. The resulting transfer characteristic is shown in Fig. 1.14, with the positive and negative saturation levels denoted L+ and L−, respectively. Each of the two saturation levels is usually within a fraction of a volt of the voltage of the corresponding power supply.
Obviously, in order to avoid distorting the output signal waveform, the input signal swing must be kept within the linear range of operation,
L− ≤vI ≤L+ Av Av
In Fig. 1.14, which shows two input waveforms and the corresponding output waveforms, the peaks of the larger waveform have been clipped off because of amplifier saturation.
Figure 1.14 An amplifier transfer characteristic that is linear except for output saturation.
1.4 Amplifiers 21
22 Chapter 1
Signals and Amplifiers
iC
ic iC
IC
Ic
0
t
Figure 1.15 Symbol convention employed throughout the book. 1.4.8 Symbol Convention
At this point, we draw the reader’s attention to the terminology we shall employ throughout the book. To illustrate the terminology, Fig. 1.15 shows the waveform of a current iC (t) that is flowing through a branch in a particular circuit. The current iC (t) consists of a dc component IC onwhichissuperimposedasinusoidalcomponentic(t)whosepeakamplitudeisIc.Observe that at a time t, the total instantaneous current iC(t) is the sum of the dc current IC and the signal current ic(t),
where the signal current is given by
iC(t)=IC +ic(t) (1.11) ic(t)=Ic sinωt
Thus, we state some conventions: Total instantaneous quantities are denoted by a lowercase symbol with uppercase subscript(s), for example, iC(t),vDS(t). Direct-current (dc) quantities are denoted by an uppercase symbol with uppercase subscript(s), for example, IC,VDS. Incremental signal quantities are denoted by a lowercase symbol with lowercase subscript(s), for example, ic(t),vgs(t). If the signal is a sine wave, then its amplitude is denoted by an uppercase symbol with lowercase subscript(s), for example, Ic,Vgs. Finally, although not shown in Fig. 1.15, dc power supplies are denoted by an uppercase letter with a double-letter uppercase subscript, for example, VCC , VDD . A similar notation is used for the dc current drawn from the power supply, for example, ICC,IDD.
EXERCISES
1.10 An amplifier has a voltage gain of 100 V/V and a current gain of 1000 A/A. Express the voltage and current gains in decibels and find the power gain.
Ans. 40 dB; 60 dB; 50 dB
1.11 An amplifier operating from a single 15-V supply provides a 12-V peak-to-peak sine-wave signal to a 1-k load and draws negligible input current from the signal source. The dc current drawn from the 15-V supply is 8 mA. What is the power dissipated in the amplifier, and what is the amplifier efficiency?
Ans. 102 mW; 15%
1.5 Circuit Models for Amplifiers
A substantial part of this book is concerned with the design of amplifier circuits that use transistors of various types. Such circuits will vary in complexity from those using a single transistor to those with 20 or more devices. In order to be able to apply the resulting amplifier circuit as a building block in a system, one must be able to characterize, or model, its terminal behavior. In this section, we study simple but effective amplifier models. These models apply irrespective of the complexity of the internal circuit of the amplifier. The values of the model parameters can be found either by analyzing the amplifier circuit or by performing measurements at the amplifier terminals.
1.5.1 Voltage Amplifiers
Figure 1.16(a) shows a circuit model for the voltage amplifier. The model consists of a voltage-controlledvoltagesourcehavingagainfactorAvo,aninputresistanceRi thataccounts for the fact that the amplifier draws an input current from the signal source, and an output resistance Ro that accounts for the change in output voltage as the amplifier is called upon to supply output current to a load. To be specific, we show in Fig. 1.16(b) the amplifier model fed with a signal voltage source vs having a resistance Rs and connected at the output to a loadresistanceRL.ThenonzerooutputresistanceRo causesonlyafractionofAvovi toappear across the output. Using the voltage-divider rule we obtain
v=Av RL
o vo iRL+Ro
A ≡vo =A RL (1.12) v v voR+R
It follows that in order not to lose gain in coupling the amplifier output to a load, the output resistance Ro should be much smaller than the load resistance RL . In other words, for a given RL one must design the amplifier so that its Ro is much smaller than RL. Furthermore, there areapplicationsinwhichRL isknowntovaryoveracertainrange.Inordertokeeptheoutput voltage vo as constant as possible, the amplifier is designed with Ro much smaller than the lowest value of RL . An ideal voltage amplifier is one with Ro = 0. Equation (1.12) indicates also that for RL = ∞, Av = Av o . Thus Av o is the voltage gain of the unloaded amplifier, or the open-circuit voltage gain. It should also be clear that in specifying the voltage gain of an amplifier, one must also specify the value of load resistance at which this gain is measured or
1.5 Circuit Models for Amplifiers 23
Thus the voltage gain is given by
iLo
24 Chapter 1
Signals and Amplifiers
ii
(a)
(b)
io
vo
v s
vo
Figure 1.16 (a) Circuit model for the voltage amplifier. (b) The voltage amplifier with input signal source and load.
calculated. If a load resistance is not specified, it is normally assumed that the given voltage gain is the open-circuit gain Av o .
The finite input resistance Ri introduces another voltage-divider action at the input, with the result that only a fraction of the source signal vs actually reaches the input terminals of the amplifier; that is,
v =v Ri (1.13) i s Ri + Rs
It follows that in order not to lose a significant portion of the input signal in coupling the signal sourcetotheamplifierinput,theamplifiermustbedesignedtohaveaninputresistanceRi much greater than the resistance of the signal source, Ri ≫ Rs . Furthermore, there are applications in which the source resistance is known to vary over a certain range. To minimize the effect of this variation on the value of the signal that appears at the input of the amplifier, the design ensures that Ri is much greater than the largest value of Rs. An ideal voltage amplifier is one with Ri = ∞. In this ideal case both the current gain and power gain become infinite.
The overall voltage gain (vo/vs) can be found by combining Eqs. (1.12) and (1.13), vo =A Ri RL
v voR+RR+R sisLo
There are situations in which one is interested not in voltage gain but only in a significant power gain. For instance, the source signal can have a respectable voltage but a source resistance that is much greater than the load resistance. Connecting the source directly to the load would result in significant signal attenuation. In such a case, one requires an amplifier with a high input resistance (much greater than the source resistance) and a low output resistance (much smaller than the load resistance) but with a modest voltage gain (or even unity gain).
1.5 CircuitModelsforAmplifiers 25 Such an amplifier is referred to as a buffer amplifier. We shall encounter buffer amplifiers
often throughout this book.
EXERCISES
1.12 A transducer characterized by a voltage of 1 V rms and a resistance of 1 M is available to drive a 10- load. If connected directly, what voltage and power levels result at the load? If a unity-gain (i.e., Av o = 1) buffer amplifier with 1-M input resistance and 10- output resistance is interposed between source and load, what do the output voltage and power levels become? For the new arrangement, find the voltage gain from source to load, and the power gain (both expressed in decibels).
Ans. 10 μV rms; 10−11 W; 0.25 V; 6.25 mW; −12 dB; 44 dB
1.13 The output voltage of a voltage amplifier has been found to decrease by 20% when a load resistance
of 1 k is connected. What is the value of the amplifier output resistance?
Ans. 250
1.14 An amplifier with a voltage gain of +40 dB, an input resistance of 10 k, and an output resistance
of 1 k is used to drive a 1-k load. What is the value of Av o? Find the value of the power gain in decibels.
Ans. 100 V/V; 44 dB
1.5.2 Cascaded Amplifiers
To meet given amplifier specifications, we often need to design the amplifier as a cascade of two or more stages. The stages are usually not identical; rather, each is designed to serve a specific purpose. For instance, in order to provide the overall amplifier with a large input resistance, the first stage is usually required to have a large input resistance. Also, in order to equip the overall amplifier with a low output resistance, the final stage in the cascade is usually designed to have a low output resistance. To illustrate the analysis and design of cascaded amplifiers, we consider a practical example.
Example 1.3
Figure 1.17 depicts an amplifier composed of a cascade of three stages. The amplifier is fed by a signal source with a source resistance of 100 k and delivers its output into a load resistance of 100 . The first stage has a relatively high input resistance and a modest gain factor of 10. The second stage has a higher gain factor but lower input resistance. Finally, the last, or output, stage has unity gain but a low output resistance. We wish to evaluate the overall voltage gain, that is, vL/vs, the current gain, and the power gain.
26
Chapter 1 Signals and Amplifiers
Example 1.3 continued
Source
100 k
Stage 1 Stage 2
1 k
1 k
Stage 3 Load
10
1 M 10 k 100
Figure 1.17 Three-stage amplifier for Example 1.3.
Solution
The fraction of source signal appearing at the input terminals of the amplifier is obtained using the voltage-divider rule at the input, as follows:
vi1 = 1M =0.909V/V vs 1 M+100 k
The voltage gain of the first stage is obtained by considering the input resistance of the second stage to be the load of the first stage; that is,
Av1 ≡vi2 =10 100k =9.9V/V vi1 100 k+1 k
Similarly, the voltage gain of the second stage is obtained by considering the input resistance of the third stage to be the load of the second stage,
Av2 ≡vi3 =100 10k =90.9V/V vi2 10 k+1 k
Finally, the voltage gain of the output stage is as follows:
Av3≡vL =1 100 =0.909V/V
Av≡vL =Av1Av2Av3=818V/V vi1
or 58.3 dB.
Tofindthevoltagegainfromsourcetoload,wemultiplyAv bythefactorrepresentingthelossofgainat the input; that is,
vi3 100 +10
The total gain of the three stages in cascade can now be found from
vL =vL vi1 =Avi1 vvvvv
si1s s
= 818 × 0.909 = 743.6 V/V
or 57.4 dB.
The current gain is found as follows:
or 138.3 dB.
The power gain is found from
or 98.3 dB. Note that
Ap≡PL =vLio PI vi1ii
=Av Ai =818×8.18×106 =66.9×108 W/W Ap(dB)= 1[Av(dB)+Ai(dB)]
2
Ai≡io =vL/100 ii vi1/1M
=104 ×Av =8.18×106 A/A
A few comments on the cascade amplifier in the above example are in order. To avoid losing signal strength at the amplifier input where the signal is usually very small, the first stage is designed to have a relatively large input resistance (1 M), which is much larger than the source resistance. The trade-off appears to be a moderate voltage gain (10 V/V). The second stage does not need to have such a high input resistance; rather, here we need to realize the bulk of the required voltage gain. The third and final, or output, stage is not asked to provide any voltage gain; rather, it functions as a buffer amplifier, providing a relatively large input resistance and a low output resistance, much lower than RL. It is this stage that enables connecting the amplifier to the 100- load. These points can be made more concrete by solving the following exercises. In so doing, observe that in finding the gain of an amplifier stage in a cascade amplifier, the loading effect of the succeeding amplifier stage must be taken into account as we have done in the above example.
EXERCISES
1.15 What would the overall voltage gain of the cascade amplifier in Example 1.3 be without stage 3 (i.e., with the load resistance connected to the output of the second stage)?
Ans. 81.8 V/V; a decrease by a factor of 9.
1.16 For the cascade amplifier of Example 1.3, let vs be 1 mV. Find vi1,vi2,vi3, and vL. Ans. 0.91 mV; 9 mV; 818 mV; 744 mV
1.17 (a) Model the three-stage amplifier of Example 1.3 (without the source and load), using the voltage amplifier model of Fig. 1.16(a). What are the values of Ri, Avo, and Ro?
(b) IfRL variesintherange10to1000,findthecorrespondingrangeoftheoverallvoltagegain, vo/vs.
Ans. 1 M, 900 V/V, 10 ; 409 V/V to 810 V/V
1.5 Circuit Models for Amplifiers 27
28 Chapter 1
Signals and Amplifiers
1.5.3 Other Amplifier Types
In the design of an electronic system, the signal of interest—whether at the system input, at an intermediate stage, or at the output—can be either a voltage or a current. For instance, some transducers have very high output resistances and can be more appropriately modeled as current sources. Similarly, there are applications in which the output current rather than the voltage is of interest. Thus, although it is the most popular, the voltage amplifier considered above is just one of four possible amplifier types. The other three are the current amplifier, the transconductance amplifier, and the transresistance amplifier. Table 1.1 shows the four amplifier types, their circuit models, the definition of their gain parameters, and the ideal values of their input and output resistances.
1.5.4 Relationships between the Four Amplifier Models
Although for a given amplifier a particular one of the four models in Table 1.1 is most preferable, any of the four can be used to model any amplifier. In fact, simple relationships can be derived to relate the parameters of the various models. For instance, the open-circuit
Table 1.1
Type
Voltage Amplifier
Current Amplifier
Transconductance Amplifier
Transresistance Amplifier
The Four Amplifier Types
Circuit Model
Gain Parameter
Open-Circuit Voltage Gain
v
Avo≡ o (V/V)
Ideal Characteristics
Ri =∞ Ro =0
Ri =0 Ro =∞
Ri =∞ Ro =∞
Ri =0 Ro =0
vi io=0
Short-Circuit Current Gain
i
Ais≡ o (A/A)
ii vo=0
Short-Circuit Transconductance
i
Gm≡o (A/V)
Open-Circuit Transresistance
v
Rm≡ o (V/A)
ii io=0
vi vo=0
voltage gain Av o can be related to the short-circuit current gain Ais as follows: The open-circuit output voltage given by the voltage amplifier model of Table 1.1 is Av o v i . The current amplifier model in the same table gives an open-circuit output voltage of AisiiRo. Equating these two values and noting that ii = vi/Ri gives
R A=A o
(1.14)
(1.15)
(1.16) The expressions in Eqs. (1.14) to (1.16) can be used to relate any two of the gain parameters
Avo,Ais,Gm, and Rm.
1.5.5 Determining Ri and Ro
From the amplifier circuit models given in Table 1.1, we observe that the input resistance Ri of the amplifier can be determined by applying an input voltage vi and measuring (or calculating) the input current ii; that is, Ri = vi/ii. The output resistance is found as the ratio of the open-circuit output voltage to the short-circuit output current. Alternatively, the output resistance can be found by eliminating the input signal source (then ii and vi will both be zero) and applying a voltage signal vx to the output of the amplifier, as shown in Fig. 1.18. If we denote the current drawn from vx into the output terminals as ix (note that ix is opposite in direction to io ), then Ro = v x /ix . Although these techniques are conceptually correct, in actual practice more refined methods are employed in measuring Ri and Ro.
1.5.6 Unilateral Models
The amplifier models considered above are unilateral; that is, signal flow is unidirectional, from input to output. Most real amplifiers show some reverse transmission, which is usually undesirable but must nonetheless be modeled. We shall not pursue this point further at this time except to mention that more complete models for linear two-port networks are given in Appendix C. Also, in later chapters, we will find it necessary in certain cases to augment the models of Table 1.1 to take into account the nonunilateral nature of some transistor amplifiers.
ix
vx
Ro vx
ix Figure 1.18 Determining the output resistance.
1.5 Circuit Models for Amplifiers 29
Similarly, we can show that
and
vo isRi Avo =GmRo
Av o = Rm Ri
30 Chapter 1 Signals and Amplifiers
Example 1.4
The bipolar junction transistor (BJT), which will be studied in Chapter 6, is a three-terminal device that when powered up by a dc source (battery) and operated with small signals can be modeled by the linear circuit shown in Fig. 1.19(a). The three terminals are the base (B), the emitter (E), and the collector (C). The heart of the model is a transconductance amplifier represented by an input resistance between B and E (denoted rπ ), a short-circuit transconductance gm , and an output resistance ro .
BC
RsB C
vs vberp gvroRLvo
vberp ro mbe
gmvbe E
(a)
B ib
vbe rp
E
(c)
E
ro
(b)
C
bib
Figure 1.19 (a) Small-signal circuit model for a bipolar junction transistor (BJT). (b) The BJT connected as an amplifier with the emitter as a common terminal between input and output (called a common-emitter amplifier). (c) An alternative small-signal circuit model for the BJT.
(a) With the emitter used as a common terminal between input and output, Fig. 1.19(b) shows a transistor amplifier known as a common-emitter or grounded-emitter circuit. Derive an expression for the voltage gain v o /v s , and evaluate its magnitude for the case Rs = 5 k, rπ = 2.5 k, gm =40mA/V, ro =100k, and RL =5k. What would the gain value be if the effect of ro were neglected?
(b) An alternative model for the transistor in which a current amplifier rather than a transconductance amplifier is utilized is shown in Fig. 1.19(c). What must the short-circuit current gain β be? Give both an expression and a value.
Solution
(a) Refer to Fig. 1.19(b). We use the voltage-divider rule to determine the fraction of input signal that appears at the amplifier input as
v=v rπ (1.17) be s rπ +Rs
Next we determine the output voltage vo by multiplying the current (gmvbe) by the resistance (RL ∥ro),
vo = −gmvbe(RL ∥ro) (1.18)
Substituting for vbe from Eq. (1.17) yields the voltage-gain expression
vo =− rπ gm(RL∥ro) (1.19)
vs rπ +Rs
Observe that the gain is negative, indicating that this amplifier is inverting. For the given component
values,
Neglecting the effect of ro, we obtain
vo =− 2.5 ×40×(5∥100) vs 2.5+5
= −63.5 V/V
vo ≃− 2.5 ×40×5 vs 2.5+5
1.5 Circuit Models for Amplifiers 31
= −66.7 V/V
which is quite close to the value obtained including ro . This is not surprising, since ro ≫ RL .
(b) For the model in Fig. 1.19(c) to be equivalent to that in Fig. 1.19(a),
But ib = vbe/rπ ; thus,
For the values given,
βib =gmvbe
β = gm rπ
β = 40 mA/V × 2.5 k = 100 A/A
32 Chapter 1 Signals and Amplifiers
EXERCISES
1.18 ConsideracurrentamplifierhavingthemodelshowninthesecondrowofTable1.1.Lettheamplifier befedwithasignalcurrent-sourceis havingaresistanceRs,andlettheoutputbeconnectedtoaload resistance RL . Show that the overall current gain is given by
io=A Rs Ro
i is R +R R +R
1.19 Consider the transconductance amplifier whose model is shown in the third row of Table 1.1. Let a voltage signal source vs with a source resistance Rs be connected to the input and a load resistance RL be connected to the output. Show that the overall voltage gain is given by
vo =G Ri (R∥R) v mR+Ro L
1.20 Consider a transresistance amplifier having the model shown in the fourth row of Table 1.1. Let the amplifierbefedwithasignalcurrentsourceis havingaresistanceRs,andlettheoutputbeconnected to a load resistance RL . Show that the overall gain is given by
vo=RRs RL
i mR+RR+R
1.21 Find the input resistance between terminals B and G in the circuit shown in Fig. E1.21. The voltage v x is a test voltage with the input resistance Rin defined as Rin ≡ v x /ix .
ix
Rin Figure E1.21 Ans. Rin =rπ +(β+1)Re
ssioL
sis
ssiLo
1.6 Frequency Response of Amplifiers2
From Section 1.2 we know that the input signal to an amplifier can always be expressed as the sum of sinusoidal signals. It follows that an important characterization of an amplifier is in terms of its response to input sinusoids of different frequencies. Such a characterization of amplifier performance is known as the amplifier frequency response.
1.6.1 Measuring the Amplifier Frequency Response
We shall introduce the subject of amplifier frequency response by showing how it can be measured. Figure 1.20 depicts a linear voltage amplifier fed at its input with a sine-wave signal of amplitude Vi and frequency ω. As the figure indicates, the signal measured at the amplifier output also is sinusoidal with exactly the same frequency ω. This is an important point to note: Whenever a sine-wave signal is applied to a linear circuit, the resulting output is sinusoidal with the same frequency as the input. In fact, the sine wave is the only signal that does not change shape as it passes through a linear circuit. Observe, however, that the output sinusoid will in general have a different amplitude and will be shifted in phase relative to the input. The ratio of the amplitude of the output sinusoid (Vo) to the amplitude of the input sinusoid (Vi) is the magnitude of the amplifier gain (or transmission) at the test frequency ω. Also, the angle φ is the phase of the amplifier transmission at the test frequency ω. If we denote the amplifier transmission, or transfer function as it is more commonly known, by T(ω), then
|T(ω)|= Vo Vi
∠T(ω) = φ
The response of the amplifier to a sinusoid of frequency ω is completely described by |T (ω)| and ∠T(ω). Now, to obtain the complete frequency response of the amplifier we simply change the frequency of the input sinusoid and measure the new value for |T| and ∠T. The end result will be a table and/or graph of gain magnitude [|T (ω)|] versus frequency and a table and/or graph of phase angle [∠T(ω)] versus frequency. These two plots together constitute the frequency response of the amplifier; the first is known as the magnitude or amplitude
Linear amplifier
vi Vi sin t vo Vo sin (t )
Figure1.20 Measuringthefrequencyresponseofalinearamplifier:Atthetestfrequency,theamplifiergain is characterized by its magnitude (Vo/Vi) and phase φ.
2 Except for its use in the study of the frequency response of op-amp circuits in Sections 2.5 and 2.7, the material in this section will not be needed in a substantial manner until Chapter 10.
1.6 Frequency Response of Amplifiers 33
34 Chapter 1
Signals and Amplifiers
Figure 1.21 Typical magnitude response of an amplifier: |T(ω)| is the magnitude of the amplifier transfer function—that is, the ratio of the output Vo(ω) to the input Vi(ω).
response, and the second is the phase response. Finally, we should mention that it is a common practice to express the magnitude of transmission in decibels and thus plot 20 log |T(ω)| versus frequency.
1.6.2 Amplifier Bandwidth
Figure 1.21 shows the magnitude response of an amplifier. It indicates that the gain is almost constant over a wide frequency range, roughly between ω1 and ω2 . Signals whose frequencies are below ω1 or above ω2 will experience lower gain, with the gain decreasing as we move farther away from ω1 and ω2. The band of frequencies over which the gain of the amplifier is almost constant, to within a certain number of decibels (usually 3 dB), is called the amplifier bandwidth. Normally the amplifier is designed so that its bandwidth coincides with the spectrum of the signals it is required to amplify. If this were not the case, the amplifier would distort the frequency spectrum of the input signal, with different components of the input signal being amplified by different amounts.
1.6.3 Evaluating the Frequency Response of Amplifiers
Above, we described the method used to measure the frequency response of an amplifier. We now briefly discuss the method for analytically obtaining an expression for the frequency response. What we are about to say is just a preview of this important subject, whose detailed study is in Chapter 10.
To evaluate the frequency response of an amplifier, one has to analyze the amplifier equivalent circuit model, taking into account all reactive components.3 Circuit analysis proceeds in the usual fashion but with inductances and capacitances represented by their reactances. An inductance L has a reactance or impedance jωL, and a capacitance C has a reactance or impedance 1/jωC or, equivalently, a susceptance or admittance jωC. Thus in a frequency-domain analysis we deal with impedances and/or admittances. The result of the
3Note that in the models considered in previous sections no reactive components were included. These were simplified models and cannot be used alone to predict the amplifier frequency response.
analysis is the amplifier transfer function T(ω) T(ω)= Vo(ω)
Vi (ω)
where Vi(ω) and Vo(ω) denote the input and output signals, respectively. T(ω) is generally a complex function whose magnitude |T(ω)| gives the magnitude of transmission or the magnitude response of the amplifier. The phase of T(ω) gives the phase response of the amplifier.
In the analysis of a circuit to determine its frequency response, the algebraic manipulations can be considerably simplified by using the complex frequency variable s. In terms of s, the impedance of an inductance L is sL and that of a capacitance C is 1/sC. Replacing the reactive elements with their impedances and performing standard circuit analysis, we obtain the transfer function T(s) as
T(s)≡ Vo(s) Vi (s)
Subsequently, we replace s by jω to determine the transfer function for physical frequencies, T (jω). Note that T ( jω) is the same function we called T (ω) above4 ; the additional j is included in order to emphasize that T(jω) is obtained from T(s) by replacing s with jω.
1.6.4 Single-Time-Constant Networks
In analyzing amplifier circuits to determine their frequency response, one is greatly aided by knowledge of the frequency-response characteristics of single-time-constant (STC) networks. An STC network is one that is composed of, or can be reduced to, one reactive component (inductance or capacitance) and one resistance. Examples are shown in Fig. 1.22. An STC network formed of an inductance L and a resistance R has a time constant τ = L/R. The time constant τ of an STC network composed of a capacitance C and a resistance R is given by τ = CR.
Appendix E presents a study of STC networks and their responses to sinusoidal, step, and pulse inputs. Knowledge of this material will be needed at various points throughout this book, and the reader will be encouraged to refer to the appendix. At this point we need in particular the frequency-response results; we will, in fact, briefly discuss this important topic now.
1.6 Frequency Response of Amplifiers 35
R
C
Vi C Vo Vi R Vo
Figure 1.22 Two examples of STC net-
works: (a) a low-pass network and (b) a (a) (b) high-pass network.
4At this stage, we are using s simply as a shorthand for jω. We shall not require detailed knowledge of s-plane concepts until Chapter 10. A brief review of s-plane analysis is presented in Appendix F.
36 Chapter 1
Signals and Amplifiers
Most STC networks can be classified into two categories,5 low pass (LP) and high pass (HP), with each of the two categories displaying distinctly different signal responses. As an example, the STC network shown in Fig. 1.22(a) is of the low-pass type and that in Fig. 1.22(b) is of the high-pass type. To see the reasoning behind this classification, observe that the transfer function of each of these two circuits can be expressed as a voltage-divider ratio, with the divider composed of a resistor and a capacitor. Now, recalling how the impedance of a capacitor varies with frequency (Z = 1/jωC), it is easy to see that the transmission of the circuit in Fig. 1.22(a) will decrease with frequency and approach zero as ω approaches ∞. Thus the circuit of Fig. 1.22(a) acts as a low-pass filter6; it passes low-frequency, sine-wave inputs with little or no attenuation (at ω = 0, the transmission is unity) and attenuates high-frequency input sinusoids. The circuit of Fig. 1.22(b) does the opposite; its transmission is unity at ω = ∞ and decreases as ω is reduced, reaching 0 for ω = 0. The latter circuit, therefore, performs as a high-pass filter.
Table 1.2 provides a summary of the frequency-response results for STC networks of both types.7 Also, sketches of the magnitude and phase responses are given in Figs. 1.23 and 1.24. These frequency-response diagrams are known as Bode plots, and the 3-dB frequency (ω0) is also known as the corner frequency, break frequency, or pole frequency. The reader is urged to become familiar with this information and to consult Appendix E if further clarifications are needed. In particular, it is important to develop a facility for the rapid
Table 1.2 Frequency Response of STC Networks
Transfer Function T(s) Transfer Function (for physical
frequencies) T(jω) Magnitude Response |T(jω)|
Low-Pass (LP) High-Pass (HP)
K Ks 1+(s/ω0) s+ω0 KK
1+j(ω/ω0) 1−j(ω0/ω) |K| |K|
1+(ω/ω0)2 1+(ω0/ω)2 Phase Response ∠T(jω) −tan−1(ω/ω0) tan−1(ω0/ω)
Transmission at ω = 0 (dc) K Transmission at ω = ∞ 0 3-dB Frequency
0
K
ω0 = 1/τ ; τ ≡ time constant τ = CR or L/R
Bode Plots
in Fig. 1.23 in Fig. 1.24
5 An important exception is the all-pass STC network studied in Chapter 17.
6A filter is a circuit that passes signals in a specified frequency band (the filter passband) and stops or
severely attenuates (filters out) signals in another frequency band (the filter stopband). Filters will be studied in Chapter 17.
7 The transfer functions in Table 1.2 are given in general form. For the circuits of Fig. 1.22, K = 1 and ω0 = 1/CR.
1.6 Frequency Response of Amplifiers 37
(a)
(b)
Figure 1.23 (a) Magnitude and (b) phase response of STC networks of the low-pass type.
determination of the time constant τ of an STC circuit. The process is very simple: Set the independent voltage or current source to zero; “grab hold” of the two terminals of the reactive element (capacitor C or inductor L); and determine the equivalent resistance R that appears between these two terminals. The time constant is then CR or L/R.
BODE PLOTS:
In the 1930s, while working at Bell Labs, Hendrik Bode devised a simple but accurate method for using linearized asymptotic responses to graph gain and phase shift against frequency on a logarithmic scale. Such gain and phase presentations, together called Bode plots, have enormous importance in the design and analysis of the frequency-dependent behavior of systems large and small.
38 Chapter 1 Signals and Amplifiers
(b)
Figure 1.24 (a) Magnitude and (b) phase response of STC networks of the high-pass type.
(a)
Example 1.5
Figure 1.25 shows a voltage amplifier having an input resistance Ri , an input capacitance Ci , a gain factor μ,andanoutputresistanceRo.TheamplifierisfedwithavoltagesourceVs havingasourceresistanceRs, andaloadofresistanceRL isconnectedtotheoutput.
Rs Ro
Vs ViRi Ci Vi RL Vo
Figure 1.25 Circuit for Example 1.5.
(a) Derive an expression for the amplifier voltage gain Vo/Vs as a function of frequency. From this find expressions for the dc gain and the 3-dB frequency.
(b) Calculate the values of the dc gain, the 3-dB frequency, and the frequency at which the gain becomes 0dB(i.e.,unity)forthecaseRs =20k,Ri =100k,Ci =60pF,μ=144V/V,Ro =200,and RL =1k.
(c) Find vo(t) for each of the following inputs: (i) vi =0.1sin102t,V
(ii) vi =0.1sin105t,V (iii) vi =0.1sin106t,V (iv) vi =0.1sin108t,V
Solution
(a) Utilizing the voltage-divider rule, we can express Vi in terms of Vs as follows V=V Zi
i s Zi +Rs
whereZi istheamplifierinputimpedance.SinceZi iscomposedoftwoparallelelements,itisobviously easier to work in terms of Yi = 1/Zi . Toward that end we divide the numerator and denominator by Zi , thus obtaining
1.6 Frequency Response of Amplifiers 39
Thus,
V=V1
i s 1+RsYi
=V1
s 1+Rs[(1/Ri)+sCi]
Vi= 1
Vs 1+(Rs/Ri)+sCiRs
This expression can be put in the standard form for a low-pass STC network (see the top line of Table 1.2) by extracting [1 + (Rs /Ri )] from the denominator; thus we have
Vi= 1 1
Vs 1+(Rs/Ri) 1+sCi[(RsRi)/(Rs +Ri)]
At the output side of the amplifier we can use the voltage-divider rule to write
V=μV RL
o i RL +Ro
This equation can be combined with Eq. (1.20) to obtain the amplifier transfer function as
Vo=μ 1 1 1
Vs 1+(Rs/Ri) 1+(Ro/RL) 1+sCi[(RsRi)/(Rs +Ri)]
(1.20)
(1.21)
40 Chapter 1 Signals and Amplifiers
Example 1.5 continued
We note that only the last factor in this expression is new (compared with the expression derived in
the last section). This factor is a result of the input capacitance Ci , with the time constant being τ=C RsRi
i Rs +Ri = Ci(Rs ∥Ri)
(1.22)
We could have obtained this result by inspection: From Fig. 1.25 we see that the input circuit is an STC network and that its time constant can be found by reducing Vs to zero, with the result that the resistance seen by Ci is Ri in parallel with Rs . The transfer function in Eq. (1.21) is of the form K /(1 + (s/ωo )), which corresponds to a low-pass STC network. The dc gain is found as
K ≡ Vo (s = 0) = μ 1 1
Vs 1+(Rs/Ri) 1+(Ro/RL)
The 3-dB frequency ω0 can be found from
ω0 = 1 = 1
Since the frequency response of this amplifier is of the low-pass STC type, the Bode plots for the gain magnitude and phase will take the form shown in Fig. 1.23, where K is given by Eq. (1.23) and ω0 is given by Eq. (1.24).
(b) Substituting the numerical values given into Eq. (1.23) results in
K = 144 1 1 = 100 V/V
τ Ci(Rs ∥Ri)
(1.23)
(1.24)
1 + (20/100) 1 + (200/1000)
Thus the amplifier has a dc gain of 40 dB. Substituting the numerical values into Eq. (1.24) gives the
3-dB frequency
Thus,
ω0 = 1
60 pF × (20 k//100 k)
= 1
60×10−12 ×(20×100/(20+100))×103
106
f0 = 2π = 159.2 kHz
=106 rad/s
Since the gain falls off at the rate of –20 dB/decade, starting at ω0 (see Fig. 1.23a) the gain will reach 0 dB in two decades (a factor of 100); thus we have
Unity-gain frequency = 100 × ω0 = 108 rad/s or 15.92 MHz
(c) Tofindvo(t)weneedtodeterminethegainmagnitudeandphaseat102,105,106,and108 rad/s.Thiscan be done either approximately utilizing the Bode plots of Fig. 1.23 or exactly utilizing the expression for the amplifier transfer function,
T(jω) ≡ Vo (jω) = 100
V 1+j(ω/106)
s
We shall do both:
(i) For ω = 102 rad/s, which is (ω0 /104 ), the Bode plots of Fig. 1.23 suggest that |T | = K = 100 and
φ = 0°. The transfer function expression gives |T | ≃ 100 and φ = − tan−1 10−4 ≃ 0°. Thus, vo(t)=10sin102t, V
(ii) For ω = 105 rad/s, which is (ω0 /10), the Bode plots of Fig. 1.23 suggest that |T | ≃ K = 100 and φ = −5.7°. The transfer function expression gives |T | = 99.5 and φ = − tan−1 0.1 = −5.7°. Thus,
vo(t)=9.95sin(105t−5.7°), V
(iii)Forω=106 rad/s=ω0,|T|=100/√2=70.7V/Vor37dBandφ=−45°.Thus,
vo(t)=7.07sin(106t−45°), V
(iv) For ω = 108 rad/s, which is (100 ω0 ), the Bode plots suggest that |T | = 1 and φ = −90°. The
transfer function expression gives |T | ≃ 1 and φ = − tan−1 100 = −89.4°. Thus, vo(t)=0.1sin(108t−89.4°), V
1.6.5 Classification of Amplifiers Based on Frequency Response
Amplifiers can be classified based on the shape of their magnitude-response curve. Figure 1.26 shows typical frequency-response curves for various amplifier types. In Fig. 1.26(a) the gain remains constant over a wide frequency range, but falls off at low and high frequencies. This type of frequency response is common in audio amplifiers.
As will be shown in later chapters, internal capacitances in the device (a transistor) cause the falloff of gain at high frequencies, just as Ci did in the circuit of Example 1.5. On the other hand, the falloff of gain at low frequencies is usually caused by coupling capacitors used to connect one amplifier stage to another, as indicated in Fig. 1.27. This practice is usually adopted to simplify the design process of the different stages. The coupling capacitors are usually chosen quite large (a fraction of a microfarad to a few tens of microfarads) so that their reactance (impedance) is small at the frequencies of interest. Nevertheless, at sufficiently low frequencies the reactance of a coupling capacitor will become large enough to cause part of the signal being coupled to appear as a voltage drop across the coupling capacitor, thus not reaching the subsequent stage. Coupling capacitors will thus cause loss of gain at low
1.6 Frequency Response of Amplifiers 41
42 Chapter 1
Signals and Amplifiers
(b)
(c)
Figure1.26 Frequencyresponsefor(a)acapacitivelycoupledamplifier,(b)adirect-coupledamplifier,and (c) a tuned or bandpass amplifier.
s
Figure 1.27 Use of a capacitor to couple amplifier stages.
frequencies and cause the gain to be zero at dc. This is not at all surprising, since from Fig. 1.27 we observe that the coupling capacitor, acting together with the input resistance of the subsequent stage, forms a high-pass STC circuit. It is the frequency response of this high-pass circuit that accounts for the shape of the amplifier frequency response in Fig. 1.26(a) at the low-frequency end.
There are many applications in which it is important that the amplifier maintain its gain at low frequencies down to dc. Furthermore, monolithic integrated-circuit (IC) technology does not allow the fabrication of large coupling capacitors. Thus IC amplifiers are usually designed as directly coupled or dc amplifiers (as opposed to capacitively coupled, or ac amplifiers).
Figure 1.26(b) shows the frequency response of a dc amplifier. Such a frequency response characterizes what is referred to as a low-pass amplifier.
In a number of applications, such as in the design of radio and TV receivers, the need arises for an amplifier whose frequency response peaks around a certain frequency (called the center frequency) and falls off on both sides of this frequency, as shown in Fig. 1.26(c). Amplifiers with such a response are called tuned amplifiers, bandpass amplifiers, or bandpass filters. A tuned amplifier forms the heart of the front-end or tuner of a communication receiver; by adjusting its center frequency to coincide with the frequency of a desired communications channel (e.g., a radio station), the signal of this particular channel can be received while those of other channels are attenuated or filtered out.
EXERCISES
1.22 Consider a voltage amplifier having a frequency response of the low-pass STC type with a dc gain of60dBanda3-dBfrequencyof1000Hz.FindthegainindBat f =10Hz,10kHz,100kHz,and 1 MHz.
Ans. 60dB;40dB;20dB;0dB
D1.23 Consider a transconductance amplifier having the model shown in Table 1.1 with Ri = 5 k, Ro = 50k,andGm =10mA/V.IftheamplifierloadconsistsofaresistanceRL inparallelwithacapacitance CL, convince yourself that the voltage transfer function realized, Vo/Vi, is of the low-pass STC type. WhatisthelowestvaluethatRL canhavewhileadcgainofatleast40dBisobtained?Withthisvalue ofRL connected,findthehighestvaluethatCL canhavewhilea3-dBbandwidthofatleast100kHz is obtained.
Ans. 12.5 k; 159.2 pF
D1.24 ConsiderthesituationillustratedinFig.1.27.Lettheoutputresistanceofthefirstvoltageamplifierbe
1 k and the input resistance of the second voltage amplifier (including the resistor shown) be 9 k. The resulting equivalent circuit is shown in Fig. E1.24. Convince yourself that V2/Vs is a high-pass STC function. What is the smallest value for C that will ensure that the 3-dB frequency is not higher than 100 Hz?
Ans. 0.16 μF
Rs 1 k
C
1.6 FrequencyResponseofAmplifiers 43
V s R i 9 k V 2
Figure E1.24
44 Chapter 1 Signals and Amplifiers Summary
An electrical signal source can be represented in either the The ́venin form (a voltage source vs in series with a source resistance Rs ) or the Norton form (a current source is in parallel with a source resistance Rs). The The ́venin voltage vs is the open-circuit voltage between the source terminals; the Norton current is is equal to the short-circuit current between the source terminals. For the two representations to be equivalent, v s and Rs is must be equal.
A signal can be represented either by its waveform versus time or as the sum of sinusoids. The latter representation is known as the frequency spectrum of the signal.
The sine-wave signal is completely characterized by its √
peak value (or rms value, which is the peak/ 2), its frequency (ω in rad/s or f in Hz; ω=2πf and f =1/T, where T is the period in seconds), and its phase with respect to an arbitrary reference time.
Analog signals have magnitudes that can assume any value. Electronic circuits that process analog signals are called analog circuits. Sampling the magnitude of an analog signal at discrete instants of time and representing each signal sample by a number results in a digital signal. Digital signals are processed by digital circuits.
The simplest digital signals are obtained when the binary system is used. An individual digital signal then assumes one of only two possible values: low and high (say, 0 V and +5 V), corresponding to logic 0 and logic 1, respectively.
An analog-to-digital converter (ADC) provides at its output the digits of the binary number representing the analog signal sample applied to its input. The output digital signal can then be processed using digital circuits. Refer to Fig. 1.10 and Eq. (1.3).
The amplifier voltage gain can be expressed as a ratio Av in V/V or in decibels, 20 log |Av |, dB. Similarly, for current gain: Ai A/A or 20 log |Ai|, dB. For power gain: ApW/Wor10logAp,dB.
Depending on the signal to be amplified (voltage or current) and on the desired form of output signal (voltage or current), there are four basic amplifier types: voltage, current, transconductance, and transresistance amplifiers. For the circuit models and ideal characteristics of these four amplifier types, refer to Table 1.1. A given amplifier can be modeled by any one of the four models, in which case their parameters are related by the formulas in Eqs. (1.14) to (1.16).
A sinusoid is the only signal whose waveform is unchanged through a linear circuit. Sinusoidal signals are used to measure the frequency response of amplifiers.
The transfer function T (s) ≡ Vo (s)/Vi (s) of a voltage amplifier can be determined from circuit analysis. Substituting s = jω gives T ( jω), whose magnitude |T(jω)| is the magnitude response, and whose phase φ(ω) is the phase response, of the amplifier.
Amplifiers are classified according to the shape of their frequency response, |T ( jω)|. Refer to Fig. 1.26.
Single-time-constant (STC) networks are those networks that are composed of, or can be reduced to, one reactive component (L or C) and one resistance (R). The time constant τ is either L/R or CR.
STC networks can be classified into two categories: low pass (LP) and high pass (HP). LP networks pass dc and low frequencies and attenuate high frequencies. The opposite is true for HP networks.
The gain of an LP (HP) STC circuit drops by 3 dB
below the zero-frequency (infinite-frequency) value
at a frequency ω = 1/τ. At high frequencies (low 0
frequencies) the gain falls off at the rate of 6 dB/octave or 20dB/decade. Refer to Table 1.2 on page 36 and Figs. 1.23 and 1.24. Further details are given in Appendix E.
The transfer characteristic, v O versus v I , of a amplifier is a straight line with a slope equal to the voltage gain. Refer to Fig. 1.12.
Amplifiers increase the signal power and thus require dc power supplies for their operation.
linear
Circuit Basics
As a review of the basics of circuit analysis and in order for the readers to gauge their preparedness for the study of electronic circuits, this section presents a number of relevant circuit analysis problems. For a summary of The ́venin’s and Norton’s theorems, refer to Appendix D. The problems are grouped in appropriate categories.
Resistors and Ohm’s Law
1.1 Ohm’s law relates V,I, and R for a resistor. For each of the situations following, find the missing item:
(a) R=1k,V=5V
(b) V=5V,I=1mA
(c) R=10k, I=0.1mA (d) R=100,V=1V
Note: Volts, milliamps, and kilohms constitute a consistent set of units.
1.2 Measurements taken on various resistors are shown below. For each, calculate the power dissipated in the resistor and the power rating necessary for safe operation using standard components with power ratings of 1/8 W, 1/4 W, 1/2 W, 1 W, or 2 W:
organized. (Hint: In your search, first consider all parallel combinations, then consider series combinations, and then consider series-parallel combinations, of which there are two kinds.)
1.5 In the analysis and test of electronic circuits, it is often useful to connect one resistor in parallel with another to obtain a nonstandard value, one which is smaller than the smaller of the two resistors. Often, particularly during circuit testing, one resistor is already installed, in which case the second, when connected in parallel, is said to “shunt” the first. If the original resistor is 10 k, what is the value of the shunting resistor needed to reduce the combined value by 1%, 5%, 10%, and 50%? What is the result of shunting a 10-k resistor by 1 M? By 100 k? By 10 k?
Voltage Dividers
1.6 Figure P1.6(a) shows a two-resistor voltage divider. Its function is to generate a voltage VO (smaller than the power-supply voltage VDD) at its output node X. The circuit looking back at node X is equivalent to that shown in Fig. P1.6(b). Observe that this is the The ́venin equivalent of the voltage-divider circuit. Find expressions for VO and RO.
VDD
R1
X ROX
VO
R2 VO
RO
(a) (b) Figure P1.6
1.7 A two-resistor voltage divider employing a 2-k and a 3-k resistor is connected to a 5-V ground-referenced power supply to provide a 2-V voltage. Sketch the circuit. Assuming exact-valued resistors, what output voltage (measured to ground) and equivalent output resistance result? If the resistors used are not ideal but have a ±5% manufactur- ing tolerance, what are the extreme output voltages and resistances that can result?
(a) 1 k conducting 20 mA (b) 1 k conducting 40 mA (c) 100 k conducting 1 mA (d) 10 k conducting 4 mA (e) 1 k dropping 20 V
(f) 1 k dropping 11 V
1.3 Ohm’s law and the power law for a resistor relate V , I , R, and P, making only two variables independent. For each pair identified below, find the other two:
(a) R=1k, I=5mA (b) V=5V,I=1mA
(c) V=10V,P=100mW (d) I=0.1mA,P=1mW (e) R=1k, P=1W
Combining Resistors
1.4 You are given three resistors whose values are 10 k, 20 k, and 40 k. How many different resistances can you create using series and parallel combinations of these three? List them in value order, lowest first. Be thorough and
PROBLEMS
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
46 Chapter 1 Signals and Amplifiers
D 1.8 You are given three resistors, each of 10 k, and a 9-V battery whose negative terminal is connected to ground. With a voltage divider using some or all of your resistors, how many positive-voltage sources of magnitude less than 9 V can you design? List them in order, smallest first. What is the output resistance (i.e., the The ́venin resistance) of each?
D *1.9 Two resistors, with nominal values of 4.7 k and 10 k, are used in a voltage divider with a +15-V supply to create a nominal +5-V output. Assuming the resistor values to be exact, what is the actual output voltage produced? Which resistor must be shunted (paralleled) by what third resistor to create a voltage-divider output of 5.00 V? If an output resistance of exactly 3.33 k is also required, what do you suggest?
Current Dividers
1.10 Currentdividersplayanimportantroleincircuitdesign. Therefore it is important to develop a facility for dealing with current dividers in circuit analysis. Figure P1.10 shows a two-resistor current divider fed with an ideal current source I . Show that
I1= R2 I R1 +R2
I2= R1 I R1 +R2
and find the voltage V that develops across the current divider.
I1 I2 I R1 R2 V
Figure P1.10
D 1.11 Design a simple current divider that will reduce the current provided to a 10-k load to one-third of that available from the source.
D 1.12 A designer searches for a simple circuit to provide one-fifth of a signal current I to a load resistance R. Suggest a solution using one resistor. What must its value be? What is the input resistance of the resulting current divider? For a particular value R, the designer discovers that the otherwise-best-available resistor is 10% too high. Suggest two circuit topologies using one additional resistor that will solve
this problem. What is the value of the resistor required in each case? What is the input resistance of the current divider in each case?
D 1.13 A particular electronic signal source generates cur- rents in the range 0 mA to 0.5 mA under the condition that its load voltage not exceed 1 V. For loads causing more than 1 V to appear across the generator, the output current is no longer assured but will be reduced by some unknown amount. This circuit limitation, occurring, for example, at the peak of a sine-wave signal, will lead to undesirable signal distortion that must be avoided. If a 10-k load is to be connected, what must be done? What is the name of the circuit you must use? How many resistors are needed? What is (are) the(ir) value(s)? What is the range of current through the load?
The ́veninEquivalentCircuits
1.14 For the circuit in Fig. P1.14, find the The ́venin equiva- lent circuit between terminals (a) 1 and 2, (b) 2 and 3, and (c) 1 and 3.
1
1 kΩ
1.5 V 2 1 kΩ
3
Figure P1.14
1.15 Through repeated application of The ́venin’s theorem, find the The ́venin equivalent of the circuit in Fig. P1.15 between node 4 and ground, and hence find the current that flows through a load resistance of 3 k connected between node 4 and ground.
CHAPTER 1 PROBLEMS
10 V
1 20 kΩ 20 kΩ
2 20 kΩ
20 kΩ
3 20 kΩ 4
20 kΩ
Figure P1.15
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
Circuit Analysis
1.16 For the circuit shown in Fig. P1.16, find the current in each of the three resistors and the voltage (with respect to ground) at their common node using two methods:
(a) LoopEquations:DefinebranchcurrentsI1 andI2 inR1 and R2, respectively; write two equations; and solve them. (b) Node Equation: Define the node voltage V at the common
node; write a single equation; and solve it. Which method do you prefer? Why?
a much easier approach is possible: Find the The ́venin equivalent of the circuit to the left of node 1 and the The ́venin equivalent of the circuit to the right of node 2. Then solve the resulting simplified circuit.
*1.18 For the circuit in Fig. P1.18, find the equivalent resistance to ground, Req. To do this, apply a voltage Vx between terminal X and ground and find the current drawn from Vx. Note that you can use particular special properties of the circuit to get the result directly! Now, if R4 is raised to 1.2 k, what does Req become?
CHAPTER 1 PROBLEMS
10 V
R1
10 k
R3
2 k
1.17 The circuit shown in Fig. P1.17 represents the equiva- lent circuit of an unbalanced bridge. It is required to calculate the current in the detector branch (R5 ) and the voltage across it. Although this can be done by using loop and node equations,
X
R5
1 kV
5 V
R2 5 k
Figure P1.16
R1 1 kV
R2 1 kV
Req R3
1 kV
R4
1 kV
10 V
1.19 Derive an expression for vo /vs for the circuit shown in Fig. P1.19.
Problems 47
Figure P1.18
R1 1 k
R3
9.1 k
1 R5 2
Rs
2 k
R2R4vsvprp roRL 1.2 k 11 k gmvp
vo
Figure P1.17 Figure P1.19
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
48 Chapter 1 Signals and Amplifiers AC Circuits
1.20 The periodicity of recurrent waveforms, such as sine waves or square waves, can be completely specified using only one of three possible parameters: radian frequency, ω, in radians per second (rad/s); (conventional) frequency, f , in hertz(Hz); or period T, in seconds(s). As well, each of the parameters can be specified numerically in one of several ways: using letter prefixes associated with the basic units, using scientific notation, or using some com- bination of both. Thus, for example, a particular period may be specified as 100 ns, 0.1 μs, 10−1 μs, 105 ps, or 1 × 10−7 s. (For the definition of the various prefixes used in electronics, see AppendixJ.) For each of the measures listed below, express the trio of terms in scientific notation associated with the basic unit (e.g., 10−7 s rather than 10−1μs).
(a) T = 10−4 ms
(b) f = 1 GHz
(c) ω=6.28×102 rad/s (d) T=10s
(e) f = 60 Hz
(f) ω=1krad/s (g) f = 1900 MHz
1.21 Find the complex impedance, Z, of each of the following basic circuit elements at 60Hz, 100kHz, and 1 GHz:
(a) R=1k (b) C=10nF (c) C=10pF (d) L=10mH (e) L=1μH
1.22 Findthecompleximpedanceat10kHzofthefollowing networks:
(a) 1 k in series with 10 nF
(b) 10 k in parallel with 0.01 μF (c) 100 k in parallel with 100 pF (d) 100 in series with 10 mH
Section 1.1: Signals
1.23 Any given signal source provides an open-circuit voltage, voc, and a short-circuit current, isc. For the following
sources, calculate the internal resistance, Rs; the Norton current, is; and the The ́venin voltage, vs:
(a)voc =1V,isc =0.1mA (b)voc =0.1V,isc =1μA
1.24 Aparticularsignalsourceproducesanoutputof40mV when loaded by a 100-k resistor and 10 mV when loaded by a 10-k resistor. Calculate the The ́venin voltage, Norton current, and source resistance.
1.25 A temperature sensor is specified to provide 2 mV/°C. When connected to a load resistance of 5 k, the output voltage was measured to change by 10 mV, corresponding to a change in temperature of 10°C. What is the source resistance of the sensor?
1.26 RefertotheThe ́veninandNortonrepresentationsofthe signal source (Fig. 1.1). If the current supplied by the source is denoted io and the voltage appearing between the source output terminals is denoted v o , sketch and clearly label v o versusio for0≤io ≤is.
1.27 The connection of a signal source to an associated signal processor or amplifier generally involves some degree of signal loss as measured at the processor or amplifier input. Considering the two signal-source representations shown in Fig.1.1, provide two sketches showing each signal-source representation connected to the input terminals (and corresponding input resistance) of a signal processor. What signal-processor input resistance will result in 95% of the open-circuit voltage being delivered to the processor? What input resistance will result in 95% of the short-circuit signal current entering the processor?
Section 1.2: Frequency Spectrum of Signals
1.28 To familiarize yourself with typical values of angular
CHAPTER 1 PROBLEMS
frequency ω, conventional frequency f , complete the entries in the following table:
and period
T (s)
T ,
Case
a b c d e f
ω (rad/s) 2×109
6.28 × 104
f (Hz) 5×109
1 × 10−10 60
1×10−5
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
CHAPTER 1 PROBLEMS
1.29 For the following peak or rms values of some important sine waves, calculate the corresponding other value:
(a) 117Vrms,ahousehold-powervoltageinNorthAmerica
(b) 33.9 V peak, a somewhat common peak voltage in
rectifier circuits
(c) 220Vrms,ahousehold-powervoltageinpartsofEurope
(d) 220 kV rms, a high-voltage transmission-line voltage in
North America
1.30 Give expressions for the sine-wave voltage signals having:
(a) 10-V peak amplitude and 1-kHz frequency (b) 120-V rms and 60-Hz frequency
(c) 0.2-V peak-to-peak and 2000-rad/s frequency (d) 100-mV peak and 1-ms period
1.31 Using the information provided by Eq. (1.2) in
association with Fig. 1.5, characterize the signal repre-
sented by v(t) = 1/2 + 2/π(sin2000πt + 1 sin6000πt + 3
1 sin10,000πt + ···). Sketch the waveform. What is its 5
average value? Its peak-to-peak value? Its lowest value? Its highest value? Its frequency? Its period?
1.32 Measurements taken of a square-wave signal using a frequency-selective voltmeter (called a spectrum analyzer) show its spectrum to contain adjacent components (spectral lines) at 98kHz and 126kHz of amplitudes 63mV and 49mV, respectively. For this signal, what would direct measurement of the fundamental show its frequency and amplitude to be? What is the rms value of the fundamental? What are the peak-to-peak amplitude and period of the originating square wave?
1.33 Find the amplitude of a symmetrical square wave of period T that provides the same power as a sine wave of peak
Problems 49 amplitude Vˆ and the same frequency. Does this result depend
on equality of the frequencies of the two waveforms?
Section 1.3: Analog and Digital Signals
1.34 Givethebinaryrepresentationofthefollowingdecimal numbers: 0, 6, 11, 28, and 59.
1.35 Considera4-bitdigitalwordb3b2b1b0 inaformatcalled signed-magnitude, in which the most significant bit, b3, is interpreted as a sign bit—0 for positive and 1 for negative values. List the values that can be represented by this scheme. What is peculiar about the representation of zero? For a particular analog-to-digital converter (ADC), each change in b0 corresponds to a 0.5-V change in the analog input. What is the full range of the analog signal that can be represented? What signed-magnitude digital code results for an input of +2.5 V? For −3.0 V? For +2.7 V? For −2.8 V?
1.36 Consider an N-bit ADC whose analog input varies between 0 and VFS (where the subscript FS denotes “full scale”).
(a) Show that the least significant bit (LSB) corresponds to a change in the analog signal of VFS /(2N − 1). This is the resolution of the converter.
(b) Convince yourself that the maximum error in the conversion (called the quantization error) is half the resolution; that is, the quantization error = VFS /2(2N − 1).
(c) For VFS = 5 V, how many bits are required to obtain a resolution of 2 mV or better? What is the actual resolution obtained? What is the resulting quantization error?
1.37 Figure P1.37 shows the circuit of an N-bit digital-to-analog converter (DAC). Each of the N bits of the digital word to be converted controls one of the switches.
Vref
Figure P1.37
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
2R 4R 8R 2NR b1 b2 b3 bN
010101 01
iO
50 Chapter 1 Signals and Amplifiers
When the bit is 0, the switch is in the position labeled 0; when the bit is 1, the switch is in the position labeled 1. The analog output is the current iO .Vref is a constant reference voltage.
1.42 Symmetrically saturating amplifiers, operating in the so-called clipping mode, can be used to convert sine waves to pseudo-square waves. For an amplifier with a small-signal gain of 1000 and clipping levels of ±10 V, what peak value of input sinusoid is needed to produce an output whose extremes are just at the edge of clipping? Clipped 90% of the time? Clipped 99% of the time?
Section 1.5: Circuit Models for Amplifiers
1.43 Consider the voltage-amplifier circuit model shown in Fig. 1.16(b), in which Av o = 100 V/V under the following conditions:
(a) Ri =10Rs, RL =10Ro (b)Ri=Rs,RL=Ro
(c) Ri =Rs/10, RL =Ro/10
Calculatetheoverallvoltagegainvo/vs ineachcase,expressed both directly and in decibels.
1.44 An amplifier with 40 dB of small-signal, open-circuit voltage gain, an input resistance of 1 M, and an output resistance of 100 , drives a load of 500 . What voltage and power gains (expressed in dB) would you expect with the load connected? If the amplifier has a peak output-current limitation of 20 mA, what is the rms value of the largest sine-wave input for which an undistorted output is possible? What is the corresponding output power available?
1.45 A 10-mV signal source having an internal resistance of 100 k is connected to an amplifier for which the input resistance is 10 k, the open-circuit voltage gain is 1000 V/V, and the output resistance is 1 k. The amplifier is connected in turn to a 100- load. What overall voltage gain results as measured from the source internal voltage to the load? Where did all the gain go? What would the gain be if the source was connected directly to the load? What is the ratio of these two gains? This ratio is a useful measure of the benefit the amplifier brings.
1.46 A buffer amplifier with a gain of 1 V/V has an input resistance of 1 M and an output resistance of 20 . It is connected between a 1-V, 200-k source and a 100-
(a) Show that
(b) Which bit is the LSB? Which is the MSB?
(c) ForVref =10 V,R=10 k,andN =8,findthemaximum value of iO obtained. What is the change in iO resulting
from the LSB changing from 0 to 1?
1.38 In compact-disc (CD) audio technology, the audio signal is sampled at 44.1 kHz. Each sample is represented by 16 bits. What is the speed of this system in bits per second?
Section 1.4: Amplifiers
1.39 Various amplifier and load combinations are measured as listed below using rms values. For each, find the voltage, current, and power gains (Av , Ai , and Ap , respectively) both as ratios and in dB:
(a) vI =100mV,iI =100μA,vO =10V,RL =100 (b) vI =10μV,iI =100nA,vO =1V,RL =10k (c) vI =1V,iI =1mA,vO =5V,RL =10
1.40 An amplifier operating from ±3-V supplies provides a 2.2-V peak sine wave across a 100- load when provided with a 0.2-V peak input from which 1.0 mA peak is drawn. The average current in each supply is measured to be 20 mA.Find the voltage gain, current gain, and power gain expressed as ratios and in decibels as well as the supply power, amplifier dissipation, and amplifier efficiency.
1.41 Anamplifierusingbalancedpowersuppliesisknownto saturate for signals extending within 1.0 V of either supply. For linear operation, its gain is 200 V/V. What is the rms value of the largest undistorted sine-wave output available, and input needed, with ±5-V supplies? With ±10-V supplies? With ±15-V supplies?
b1 + b2 +···+ bN
iO = Vref
R2122 2N
CHAPTER 1 PROBLEMS
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
CHAPTER 1 PROBLEMS
load. What load voltage results? What are the corresponding voltage, current, and power gains (in dB)?
1.47 ConsiderthecascadeamplifierofExample1.3.Findthe overall voltage gain vo/vs obtained when the first and second stages are interchanged. Compare this value with the result in Example 1.3, and comment.
1.48 You are given two amplifiers, A and B, to connect in cascade between a 10-mV, 100-k source and a 100- load. The amplifiers have voltage gain, input resistance, and output resistance as follows: for A, 100 V/V, 100 k, 10 k, respectively; for B, 10 V/V, 10 k, 1 k, respectively. Your problem is to decide how the amplifiers should be connected. To proceed, evaluate the two possible connections between source S and load L, namely, SABL and SBAL. Find the voltage gain for each both as a ratio and in decibels. Which amplifier arrangement is best?
D *1.49 A designer has available voltage amplifiers with an input resistance of 10 k, an output resistance of 1 k, and an open-circuit voltage gain of 10. The signal source has a 10-k resistance and provides a 5-mV rms signal, and it is required to provide a signal of at least 3 V rms to a 200- load. How many amplifier stages are required? What is the output voltage actually obtained?
D *1.50 Design an amplifier that provides 0.5 W of signal power to a 100- load resistance. The signal source provides a 30-mV rms signal and has a resistance of 0.5 M. Three types of voltage-amplifier stages are available:
(a) A high-input-resistance type with Ri = 1 M, Av o = 10, andRo =10k
andRo =20
Design a suitable amplifier using a combination of these stages. Your design should utilize the minimum number of stages and should ensure that the signal level is not reduced below 10 mV at any point in the amplifier chain. Find the load voltage and power output realized.
D *1.51 It is required to design a voltage amplifier to be driven from a signal source having a 5-mV peak amplitude and a source resistance of 10 k to supply a peak output of
Ri = 10 k,
(c) A low-output-resistance type with Ri = 10 k, Av o = 1,
D 1.52 A voltage amplifier with an input resistance of 20k, an output resistance of 100 , and a gain of 1000 V/V is connected between a 100-k source with an open-circuit voltage of 10 mV and a 100- load. For this situation:
(a) What output voltage results?
(b) What is the voltage gain from source to load?
(c) What is the voltage gain from the amplifier input to the
load?
(d) If the output voltage across the load is twice that
needed and there are signs of internal amplifier overload, suggest the location and value of a single resistor that would produce the desired output. Choose an arrangement that would cause minimum disruption to an operating circuit. (Hint: Use parallel rather than series connections.)
(b) A high-gain type with Ro =1 k
Av o = 100, and
2 V
(a) (b)
(c)
(d)
(e)
across a 1-k load.
What is the required voltage gain from the source to the load?
If the peak current available from the source is 0.1 μA, what is the smallest input resistance allowed? For the design with this value of Ri , find the overall current gain and power gain.
If the amplifier power supply limits the peak value of
the output open-circuit voltage to 3 V, what is the largest
output resistance allowed?
ForthedesignwithR asin(b)andR asin(c),whatisthe i o v
required value of open-circuit voltage gain, i.e., o ,
of the amplifier?
If, as a possible design option, you are able to increase Ri tothenearestvalueoftheform1×10n andtodecrease Ro to the nearest value of the form 1 × 10m , find (i) the input resistance achievable; (ii) the output resistance achievable; and (iii) the open-circuit voltage gain now required to meet the specifications.
Problems 51
vi RL=∞
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
52 Chapter 1 Signals and Amplifiers
1.53 A voltage amplifier delivers 200 mV across a load resistance of 1 k. It was found that the output voltage decreasesby5mVwhenRL isdecreasedto780.Whatare the values of the open-circuit output voltage and the output resistance of the amplifier?
1.54 A current amplifier supplies 1 mA to a load resistance of 1 k. When the load resistance is increased to 12 k, the output current decreases to 0.5 mA. What are the values of the short-circuit output current and the output resistance of the amplifier?
1.55 A current amplifier for which Ri = 100 , Ro = 10 k, and Ais = 100 A/A is to be connected between a 100-mV source with a resistance of 10 k and a load of 1 k. What are the values of current gain io/ii, of voltage gain vo/vs, and of power gain expressed directly and in decibels?
1.56 A transconductance amplifier with Ri = 2 k, Gm = 60 mA/V, and Ro = 20 k is fed with a voltage source having a source resistance of 1 k and is loaded with a 1-k resistance. Find the voltage gain realized.
D **1.57 A designer is required to provide, across a 10-k load, the weighted sum, vO = 10v1 + 20v2, of input signals v 1 and v 2 , each having a source resistance of 10 k. She has a number of transconductance amplifiers for which the input and output resistances are both 10k and Gm = 20 mA/V, together with a selection of suitable resistors. Sketch an appropriate amplifier topology with additional resistors selected to provide the desired result. Your design should utilize the minimum number of ampli- fiers and resistors. (Hint: In your design, arrange to add currents.)
1.58 Figure P1.58 shows a transconductance amplifier whose output is fed back to its input. Find the input resistance Rin of the resulting one-port network. (Hint: Apply a test voltage vx between the two input terminals, and find the current ix drawn from the source. Then, Rin ≡ v x /ix .)
Rin
Figure P1.58
D 1.59 It is required to design an amplifier to sense the open-circuit output voltage of a transducer and to provide a proportional voltage across a load resistor. The equivalent source resistance of the transducer is specified to vary in the range of 1 k to 10 k. Also, the load resistance varies in the range of 1 k to 10 k. The change in load voltage corresponding to the specified change in Rs should be 10% at most. Similarly, the change in load voltage corresponding to the specified change in RL should be limited to 10%. Also, corresponding to a 10-mV transducer open-circuit output voltage, the amplifier should provide a minimum of 1 V across the load. What type of amplifier is required? Sketch its circuit model, and specify the values of its parameters. Specify appropriate values for Ri and Ro of the form 1×10m .
D 1.60 It is required to design an amplifier to sense the short-circuit output current of a transducer and to provide a proportional current through a load resistor. The equivalent source resistance of the transducer is specified to vary in the range of 1 k to 10 k. Similarly, the load resistance is known to vary over the range of 1 k to 10 k. The change in load current corresponding to the specified change in Rs is required to be limited to 10%. Similarly, the change in load current corresponding to the specified change in RL
CHAPTER 1 PROBLEMS
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CHAPTER 1 PROBLEMS
should be 10% at most. Also, for a nominal short-circuit output current of the transducer of 10 μA, the amplifier is required to provide a minimum of 1 mA through the load. What type of amplifier is required? Sketch the circuit model of the amplifier, and specify values for its param- eters. Select appropriate values for Ri and Ro in the form 1×10m .
D 1.61 It is required to design an amplifier to sense the open-circuit output voltage of a transducer and to provide a proportional current through a load resistor. The equivalent source resistance of the transducer is specified to vary in the range of 1 k to 10 k. Also, the load resistance is known to vary in the range of 1k to 10k. The change in the current supplied to the load corresponding to the specified change in Rs is to be 10% at most. Similarly, the change in load current corresponding to the specified change in RL is to be 10% at most. Also, for a nominal transducer open-circuit output voltage of 10 mV, the amplifier is required to provide a minimum of 1 mA current through the load. What type of amplifier is required? Sketch the amplifier circuit model, and specifyvaluesforitsparameters.ForRi andRo,specifyvalues in the form 1×10m .
D 1.62 It is required to design an amplifier to sense the short-circuit output current of a transducer and to provide a proportional voltage across a load resistor. The equivalent source resistance of the transducer is specified to vary in the range of 1 k to 10 k. Similarly, the load resistance is known to vary in the range of 1 k to 10 k. The change in load voltage corresponding to the specified change in Rs should be 10% at most. Similarly, the change in load voltage corresponding to the specified change in RL is to be limited to 10%. Also, for a nominal transducer short-circuit output current of 10 μA, the amplifier is required to provide a minimum voltage across the load of 1V. What type of amplifier is required? Sketch its circuit model, and specify the values of the model parameters. For Ri and Ro, specify appropriate values in the form 1 × 10m .
1.63 For the circuit in Fig. P1.63, show that vc −βRL
and
v =r +(β+1)R bπE
vR e=E
vb RE +[rπ/(β+1)]
BC
ib
r ib
Problems 53
vbERLvc
RE ve
Figure P1.63
1.64 An amplifier with an input resistance of 5 k, when driven by a current source of 1 μA and a source resistance of 200 k, has a short-circuit output current of 5 mA and an open-circuit output voltage of 10 V. If the amplifier is used to drive a 2-k load, give the values of the voltage gain, current gain, and power gain expressed as ratios and in decibels.
1.65 Figure P1.65(a) shows two transconductance amplifiers connected in a special configuration. Find vo in terms of v1 and v2. Let gm = 100mA/V and R = 5k. If v1 = v2 = 1 V, find the value of vo. Also, find vo for the case v1 = 1.01 V and v2 = 0.99 V. (Note: This circuit is called a differential amplifier and is given the symbol shown
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
54 Chapter 1 Signals and Amplifiers
in Fig. P1.65(b). A particular type of differential amplifier known as an operational amplifier will be studied in Chapter 2.)
to that of the voltage amplifier in Fig. 1.16(a), identify corre- sponding currents and voltages as well as the correspondence between the parameters of the amplifier equivalent circuit and the g parameters. Hence give the g parameter that corresponds to each of Ri,Avo, and Ro. Notice that there is an additional g parameter with no correspondence in the amplifier equivalent circuit. Which one? What does it signify? What assumption did we make about the amplifier that resulted in the absence of this particular g parameter from the equivalent circuit in Fig. 1.16(a)?
I1 g22 I2
CHAPTER 1 PROBLEMS
V1 g1 V2 11 g12I2 g21V1
Figure P1.66
Figure P1.65
+ –
(a)
(b)
vo
Section 1.6: Frequency Response of Amplifiers
1.67 Use the voltage-divider rule to derive the transfer functions T (s) ≡ Vo (s)/Vi (s) of the circuits shown in Fig. 1.22, and show that the transfer functions are of the form given at the top of Table 1.2.
1.68 Figure P1.68 shows a signal source connected to the input of an amplifier. Here Rs is the source resistance, and Ri and Ci are the input resistance and input capacitance, respectively, of the amplifier. Derive an expression for Vi (s)/Vs (s), and show that it is of the low-pass STC type. Find the 3-dB frequency for the case Rs = 10 k, Ri = 40 k, and Ci =5pF.
Rs
Vs Ri CiVi
Figure P1.68
1.66 Anylineartwo-portnetworkincludinglinearamplifiers can be represented by one of four possible parameter sets, given in Appendix C. For the voltage amplifier, the most convenient representation is in terms of the g parameters. If the amplifier input port is labeled as port 1 and the output port as port 2, its g-parameter representation is described by the two equations:
I1 =g11V1 +g12I2 V2 =g21V1 +g22I2
Figure P1.66 shows an equivalent circuit representation of these two equations. By comparing this equivalent circuit
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CHAPTER 1 PROBLEMS
1.69 For the circuit shown in Fig. P1.69, find the transfer function T (s) = Vo (s)/Vi (s), and arrange it in the appropriate standard form from Table 1.2. Is this a high-pass or a low-pass network? What is its transmission at very high frequencies? [Estimate this directly, as well as by letting s → ∞ in your expression for T(s).] What is the corner frequency ω0? For R1 =10k,R2 =40k,andC=1μF,findf0.Whatisthe value of |T(jωo)|?
1.71 Measurement of the frequency response of an amplifier yields the data in the following table:
Problems 55
f (Hz)
0 100 1000 104 105
| T | (dB) 40
40
37 20 0
∠T (◦ ) 0
0 −45
R1
C
Provide plausible approximate values for the missing entries. Also, sketch and clearly label the magnitude frequency response (i.e., provide a Bode plot) for this amplifier.
1.72 Measurementofthefrequencyresponseofanamplifier yields the data in the following table:
Vi R2Vo
Figure P1.69
D 1.70 It is required to couple a voltage source Vs with a resistance Rs to a load RL via a capacitor C. Derive an expression for the transfer function from source to load (i.e., Vl /Vs ), and show that it is of the high-pass STC type. For Rs = 5 k and RL = 20 k, find the smallest coupling capacitor that will result in a 3-dB frequency no greater than 100 Hz.
Vi
Figure P1.73
f (Hz) 10 102 103 104 |T|(dB) 0 20 37 40
105
106 107
37 20 0
Provide approximate plausible values for the missing table entries. Also, sketch and clearly label the magnitude fre- quency response (Bode plot) of this amplifier.
1.73 The unity-gain voltage amplifiers in the circuit of Fig. P1.73 have infinite input resistances and zero output
Vo
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56 Chapter 1 Signals and Amplifiers
resistances and thus function as perfect buffers. Furthermore, assume that their gain is frequency independent. Convince yourself that the overall gain Vo /Vi will drop by 3 dB below the value at dc at the frequency for which the gain of each RC circuit is 1.0 dB down. What is that frequency in terms of CR?
1.74 A manufacturing error causes an internal node of a high-frequency amplifier whose The ́venin-equivalent node resistance is 100 k to be accidentally shunted to ground by a capacitor (i.e., the node is connected to ground through a capacitor). If the measured 3-dB bandwidth of the amplifier is reduced from the expected 5 MHz to 100 kHz, estimate the value of the shunting capacitor. If the original cutoff frequency can be attributed to a small parasitic capacitor at the same internal node (i.e., between the node and ground), what would you estimate it to be?
D *1.75 A designer wishing to lower the overall upper 3-dB frequency of a three-stage amplifier to 10 kHz considers shunting one of two nodes: Node A, between the output of the first stage and the input of the second stage, and Node B, between the output of the second stage and the input of the third stage, to ground with a small capacitor. While measuring the overall frequency response of the amplifier, she connects a capacitor of 1 nF, first to node A and then to node B, lowering the 3-dB frequency from 3 MHz to 200 kHz and 20 kHz, respectively. If she knows that each amplifier stage has an input resistance of 100 k, what output resistance must the driving stage have at node A? At node B? What capacitor value should she connect to which node to solve her design problem most economically?
D 1.76 An amplifier with an input resistance of 100 k and an output resistance of 1 k is to be capacitor-coupled to a 10-k source and a 1-k load. Available capacitors have values only of the form 1 × 10−n F. What are the values of the smallest capacitors needed to ensure that the corner frequency associated with each is less than 100Hz? What actual corner frequencies result? For the situation in which the basic amplifier has an open-circuit voltage gain (Av o ) of 100 V/V, find an expression for T (s) = Vo (s)/Vs (s).
*1.77 A voltage amplifier has the transfer function
2
CHAPTER 1 PROBLEMS
Av =
1+j f 1+10
105 jf
1000
R1 100 k
C2 100 nF
Using the Bode plots for low-pass and high-pass STC networks (Figs. 1.23 and 1.24), sketch a Bode plot for |Av |. Give approximate values for the gain magnitude at f = 10 Hz, 102 Hz, 103 Hz, 104 Hz, 105 Hz, 106 Hz, 107 Hz, and 108 Hz. Find the bandwidth of the amplifier (defined as the frequency range over which the gain remains within 3dB of the maximum value).
*1.78 For the circuit shown in Fig. P1.78, first evaluate Ti (s) = Vi (s)/Vs (s) and the corresponding cutoff (corner) frequency. Second, evaluate To (s) = Vo (s)/Vi (s) and the corresponding cutoff frequency. Put each of the transfer functions in the standard form (see Table 1.2), and combine them to form the overall transfer function, T (s) = Ti (s) × To (s). Provide a Bode magnitude plot for |T ( jω)|. What is the bandwidth between 3-dB cutoff points?
VsC1Vi
R2 R3Vo 100 k 10 k
10 pF
GmVi
Gm 100 mAV
Figure P1.78
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D **1.79 A transconductance amplifier having the equiva- lent circuit shown in Table 1.1 is fed with a voltage source Vs having a source resistance Rs , and its output is connected to a load consisting of a resistance RL in parallel with a capacitance CL . For given values of Rs , RL , and CL , it is required to specify the values of the amplifier parameters Ri,Gm, and Ro to meet the following design constraints:
(a) At most, x% of the input signal is lost in coupling the signal source to the amplifier (i.e., Vi ≥ [1 − (x/100)]Vs ).
(b) The3-dBfrequencyoftheamplifierisequaltoorgreater
than a specified value f3 dB.
(c) The dc gain Vo/Vs is equal to or greater than a specified
value A0.
Show that these constraints can be met by selecting
100 Ri≥ x−1Rs
Ro≤ 1 2πf3dBCL −(1/RL)
G ≥ A0 /[1 − (x/100)] m (RL ∥Ro)
Find Ri,Ro, and Gm for Rs =10k, x=10%, A0 = 100V/V,RL = 10k,CL =20pF,andf3 dB =2MHz.
*1.80 Use the voltage-divider rule to find the transfer function Vo (s)/Vi (s) of the circuit in Fig. P1.80. Show that the transfer function can be made independent of frequency if the condition C1 R1 = C2 R2 applies. Under this condition
the circuit is called a compensated attenuator and is frequently employed in the design of oscilloscope probes. Find the transmission of the compensated attenuator in terms of R1 and R2.
Problems 57
CHAPTER 1 PROBLEMS
R1 C1
Vi
Figure P1.80
*1.81 An amplifier with a frequency response of the type shown in Fig. 1.21 is specified to have a phase shift of magnitude no greater than 5.7° over the amplifier bandwidth, which extends from 100 Hz to 1 kHz. It has been found that the gain falloff at the low-frequency end is determined by the response of a high-pass STC circuit and that at the high-frequency end it is determined by a low-pass STC circuit. What do you expect the corner frequencies of these two circuits to be? What is the drop in gain in decibels (relative to the maximum gain) at the two frequencies that define the amplifier bandwidth? What are the frequencies at which the drop in gain is 3 dB? (Hint: Refer to Figs. 1.23 and 1.24.)
R2 C2 Vo
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CHAPTER 2
Operational Amplifiers
Introduction 59
2.1 The Ideal Op Amp 60
2.2 The Inverting Configuration 64
2.3 The Noninverting Configuration
2.4 Difference Amplifiers 77
2.5 Integrators and Differentiators
73
87
2.6 DC Imperfections 96
2.7 Effect of Finite Open-Loop Gain and
BandwidthonCircuitPerformance 105
2.8 Large-Signal Operation of Op Amps 110
Summary 115 Problems 116
IN THIS CHAPTER YOU WILL LEARN
1. The terminal characteristics of the ideal op amp.
2. Howtoanalyzecircuitscontainingopamps,resistors,andcapacitors.
3. How to use op amps to design amplifiers having precise characteristics.
4. How to design more sophisticated op-amp circuits, including summing amplifiers, instrumentation amplifiers, integrators, and differentiators.
5. Important nonideal characteristics of op amps and how these limit the performance of basic op-amp circuits.
Introduction
Having learned basic amplifier concepts and terminology, we are now ready to undertake the study of a circuit building block of universal importance: the operational amplifier (op amp). Op amps have been in use for a long time, their initial applications being primarily in the areas of analog computation and sophisticated instrumentation. Early op amps were constructed from discrete components (vacuum tubes and then transistors, and resistors), and their cost was prohibitively high (tens of dollars). In the mid-1960s the first integrated-circuit (IC) op amp was produced. This unit (the μA 709) was made up of a relatively large number of transistors and resistors all on the same silicon chip. Although its characteristics were poor (by today’s standards) and its price was still quite high, its appearance signaled a new era in electronic circuit design. Electronics engineers started using op amps in large quantities, which caused their price to drop dramatically. They also demanded better-quality op amps. Semiconductor manufacturers responded quickly, and within the span of a few years, high-quality op amps became available at extremely low prices (tens of cents) from a large number of suppliers.
One of the reasons for the popularity of the op amp is its versatility. As we will shortly see, one can do almost anything with op amps! Equally important is the fact that the IC op amp has characteristics that closely approach the assumed ideal. This implies that it is quite easy to design circuits using the IC op amp. Also, op-amp circuits work at performance levels that are quite close to those predicted theoretically. It is for this reason that we are studying op amps at this early stage. It is expected that by the end of this chapter the reader should be able to successfully design nontrivial circuits using op amps.
As already implied, an IC op amp is made up of a large number (about 20) of transistors together with resistors, and (usually) one capacitor connected in a rather complex circuit. Since
59
60 Chapter 2
Operational Amplifiers
we have not yet studied transistor circuits, the circuit inside the op amp will not be discussed in this chapter. Rather, we will treat the op amp as a circuit building block and study its terminal characteristics and its applications. This approach is quite satisfactory in many op-amp applications. Nevertheless, for the more difficult and demanding applications it is quite useful to know what is inside the op-amp package. This topic will be studied in Chapter 13. More advanced applications of op amps will appear in later chapters.
2.1 The Ideal Op Amp 2.1.1 The Op-Amp Terminals
From a signal point of view the op amp has three terminals: two input terminals and one output terminal. Figure 2.1 shows the symbol we shall use to represent the op amp. Terminals 1 and 2 are input terminals, and terminal 3 is the output terminal. As explained in Section 1.4, amplifiers require dc power to operate. Most IC op amps require two dc power supplies, as shown in Fig. 2.2. Two terminals, 4 and 5, are brought out of the op-amp package and connectedtoapositivevoltageVCC andanegativevoltage−VEE,respectively.InFig.2.2(b)we explicitly show the two dc power supplies as batteries with a common ground. It is interesting to note that the reference grounding point in op-amp circuits is just the common terminal of the two power supplies; that is, no terminal of the op-amp package is physically connected to ground. In what follows we will not, for simplicity, explicitly show the op-amp power supplies.
VCC
Figure 2.1 Circuit symbol for the op amp.
VCC
VEE
VEE
Figure 2.2 The op amp shown connected to dc power supplies.
In addition to the three signal terminals and the two power-supply terminals, an op amp may have other terminals for specific purposes. These other terminals can include terminals for frequency compensation and terminals for offset nulling; both functions will be explained in later sections.
EXERCISE
2.1 Whatistheminimumnumberofterminalsrequiredbyasingleopamp?Whatistheminimumnumber of terminals required on an integrated-circuit package containing four op amps (called a quad op amp)? Ans. 5; 14
2.1.2 Function and Characteristics of the Ideal Op Amp
We now consider the circuit function of the op amp. The op amp is designed to sense the difference between the voltage signals applied at its two input terminals (i.e., the quantity v2 −v1), multiply this by a number A, and cause the resulting voltage A(v2 −v1) to appear at output terminal 3. Thus v3 = A(v2 − v1). Here it should be emphasized that when we talk about the voltage at a terminal we mean the voltage between that terminal and ground; thus v1 means the voltage applied between terminal 1 and ground.
The ideal op amp is not supposed to draw any input current; that is, the signal current into terminal 1 and the signal current into terminal 2 are both zero. In other words, the input impedance of an ideal op amp is supposed to be infinite.
How about the output terminal 3? This terminal is supposed to act as the output terminal of an ideal voltage source. That is, the voltage between terminal 3 and ground will always be equal to A(v2 −v1), independent of the current that may be drawn from terminal 3 into a load impedance. In other words, the output impedance of an ideal op amp is supposed to be zero.
Putting together all of the above, we arrive at the equivalent circuit model shown in Fig. 2.3. Note that the output is in phase with (has the same sign as) v2 and is out of phase with (has the opposite sign of) v1. For this reason, input terminal 1 is called the inverting input terminal and is distinguished by a “−” sign, while input terminal 2 is called the noninverting input terminal and is distinguished by a “+” sign.
As can be seen from the above description, the op amp responds only to the difference signal v2 − v1 and hence ignores any signal common to both inputs. That is, if v1 = v2 = 1 V, then the output will (ideally) be zero. We call this property common-mode rejection, and we conclude that an ideal op amp has zero common-mode gain or, equivalently, infinite common-mode rejection. We will have more to say about this point later. For the time being note that the op amp is a differential-input, single-ended-output amplifier, with the latter term referring to the fact that the output appears between terminal 3 and ground.1
1Some op amps are designed to have differential outputs. This topic will not be discussed in this book. Rather, we confine ourselves here to single-ended-output op amps, which constitute the vast majority of commercially available op amps.
2.1 The Ideal Op Amp 61
62 Chapter 2
Operational Amplifiers
Inverting input
Output
Noninverting input
Figure 2.3 Equivalent circuit of the ideal op amp.
Furthermore, gain A is called the differential gain, for obvious reasons. Perhaps not so obvious is another name that we will attach to A: the open-loop gain. The reason for this name will become obvious later on when we “close the loop” around the op amp and define another gain, the closed-loop gain.
An important characteristic of op amps is that they are direct-coupled or dc amplifiers, where dc stands for direct-coupled (it could equally well stand for direct current, since a direct-coupled amplifier is one that amplifies signals whose frequency is as low as zero). The fact that op amps are direct-coupled devices will allow us to use them in many important applications. Unfortunately, though, the direct-coupling property can cause some serious practical problems, as will be discussed in a later section.
How about bandwidth? The ideal op amp has a gain A that remains constant down to zero frequency and up to infinite frequency. That is, ideal op amps will amplify signals of any frequency with equal gain, and are thus said to have infinite bandwidth.
We have discussed all of the properties of the ideal op amp except for one, which in fact is the most important. This has to do with the value of A. The ideal op amp should have a gain A whose value is very large and ideally infinite. One may justifiably ask: If the gain A is infinite, how are we going to use the op amp? The answer is very simple: In almost all applications the op amp will not be used alone in a so-called open-loop configuration. Rather, we will use other components to apply feedback to close the loop around the op amp, as will be illustrated in detail in Section 2.2.
For future reference, Table 2.1 lists the characteristics of the ideal op amp.
Table 2.1 Characteristics of the Ideal Op Amp
1. Infinite input impedance
2. Zero output impedance
3. Zero common-mode gain or, equivalently, infinite common-mode rejection 4. Infinite open-loop gain A
5. Infinite bandwidth
2.1.3 Differential and Common-Mode Signals
The differential input signal vId is simply the difference between the two input signals v1 and v2; that is,
vId =v2 −v1 (2.1) The common-mode input signal vIcm is the average of the two input signals v1 and v2; namely,
vIcm = 1(v1 +v2) (2.2) 2
Equations (2.1) and (2.2) can be used to express the input signals v1 and v2 in terms of their differential and common-mode components as follows:
These equations can in turn lead to the pictorial representation in Fig. 2.4.
11 v1 vId2
vIcm vId2 22
v2
EXERCISES
Figure 2.4 Representation of the signal sources v1 and v2 in terms of their differential and common-mode components.
2.1 TheIdealOpAmp 63
and
v1 =vIcm −vId/2 v2 =vIcm +vId/2
(2.3)
(2.4)
2.2 Consideranopampthatisidealexceptthatitsopen-loopgainA=103.Theopampisusedinafeedback circuit, and the voltages appearing at two of its three signal terminals are measured. In each of the following cases, use the measured values to find the expected value of the voltage at the third terminal. Also give the differential and common-mode input signals in each case. (a) v2 = 0 V and v3 = 2 V; (b) v2 =+5Vandv3 =−10V;(c)v1 =1.002Vandv2 =0.998V;(d)v1 =−3.6Vandv3 =−3.6V. Ans. (a)v1 =−0.002V,vId =2mV,vIcm =−1mV;(b)v1 =+5.01V,vId =−10mV,vIcm =5.005≃ 5V;(c)v3 =−4V,vId =−4mV,vIcm =1V;(d)v2 =−3.6036V,vId =−3.6mV,vIcm ≃−3.6V
64 Chapter 2 Operational Amplifiers
2.3 The internal circuit of a particular op amp can be modeled by the circuit shown in Fig. E2.3. Express v3 asafunctionofv1 andv2.ForthecaseGm =10mA/V,R=10k,andμ=100,findthevalueof the open-loop gain A.
Ans. v3 =μGmR(v2 −v1);A=10,000V/Vor80dB
Figure E2.3
2.2 The Inverting Configuration
As mentioned above, op amps are not used alone; rather, the op amp is connected to passive components in a feedback circuit. There are two such basic circuit configurations employing an op amp and two resistors: the inverting configuration, which is studied in this section, and the noninverting configuration, which we shall study in the next section.
Figure 2.5 shows the inverting configuration. It consists of one op amp and two resistors R1 and R2. Resistor R2 is connected from the output terminal of the op amp, terminal 3, back to the inverting or negative input terminal, terminal 1. We speak of R2 as applying negative feedback; if R2 were connected between terminals 3 and 2 we would have called this positive feedback.NotealsothatR2 closesthelooparoundtheopamp.InadditiontoaddingR2,wehave grounded terminal 2 and connected a resistor R1 between terminal 1 and an input signal source
2.2 The Inverting Configuration 65
Figure 2.5 The inverting closed-loop con- figuration.
with a voltage vI . The output of the overall circuit is taken at terminal 3 (i.e., between terminal 3 and ground). Terminal 3 is, of course, a convenient point from which to take the output, since theimpedancelevelthereisideallyzero.ThusthevoltagevO willnotdependonthevalueofthe current that might be supplied to a load impedance connected between terminal 3 and ground.
2.2.1 The Closed-Loop Gain
We now wish to analyze the circuit in Fig. 2.5 to determine the closed-loop gain G, defined as G ≡ vO
vI
We will do so assuming the op amp to be ideal. Figure 2.6(a) shows the equivalent circuit, and
the analysis proceeds as follows: The gain A is very large (ideally infinite). If we assume that the circuit is “working” and producing a finite output voltage at terminal 3, then the voltage between the op-amp input terminals should be negligibly small and ideally zero. Specifically, if we call the output voltage vO, then, by definition,
v2−v1=vO =0 A
It follows that the voltage at the inverting input terminal (v1) is given by v1 = v2. That is, because the gain A approaches infinity, the voltage v1 approaches and ideally equals v2. We speak of this as the two input terminals “tracking each other in potential.” We also speak of a “virtual short circuit” that exists between the two input terminals. Here the word virtual should be emphasized, and one should not make the mistake of physically shorting terminals 1 and 2 together while analyzing a circuit. A virtual short circuit means that whatever voltage is at 2 will automatically appear at 1 because of the infinite gain A. But terminal 2 happens to be connected to ground; thus v2 = 0 and v1 = 0. We speak of terminal 1 as being a virtual ground—that is, having zero voltage but not physically connected to ground.
Now that we have determined v1 we are in a position to apply Ohm’s law and find the current i1 through R1 (see Fig. 2.6) as follows:
i1=vI−v1 =vI−0=vI
R1 R1 R1
Where will this current go? It cannot go into the op amp, since the ideal op amp has an infinite
input impedance and hence draws zero current. It follows that i1 will have to flow through R2 to the low-impedance terminal 3. We can then apply Ohm’s law to R2 and determine vO; that is,
Thus,
vO =v1 −i1R2 =0−vI R2
R1
vO =−R2 vI R1
66 Chapter 2
Operational Amplifiers
3
2
5
1
4
6
Figure 2.6 Analysis of the inverting configuration. The circled numbers indicate the order of the analysis steps.
which is the required closed-loop gain. Figure 2.6(b) illustrates these steps and indicates by the circled numbers the order in which the analysis is performed.
We thus see that the closed-loop gain is simply the ratio of the two resistances R2 and R1. The minus sign means that the closed-loop amplifier provides signal inversion. Thus if R2 /R1 = 10 and we apply at the input (v I ) a sine-wave signal of 1 V peak-to-peak, then the output vO will be a sine wave of 10 V peak-to-peak and phase-shifted 180° with respect to the input sine wave. Because of the minus sign associated with the closed-loop gain, this configuration is called the inverting configuration.
The fact that the closed-loop gain depends entirely on external passive components (resistors R1 and R2) is very significant. It means that we can make the closed-loop gain as accurate as we want by selecting passive components of appropriate accuracy. It also means that the closed-loop gain is (ideally) independent of the op-amp gain. This is a dramatic illustration of negative feedback: We started out with an amplifier having very large gain A, and through applying negative feedback we have obtained a closed-loop gain R2/R1 that is much smaller than A but is stable and predictable. That is, we are trading gain for accuracy.
2.2.2 Effect of Finite Open-Loop Gain
The points just made are more clearly illustrated by deriving an expression for the closed-loop gain under the assumption that the op-amp open-loop gain A is finite. Figure 2.7 shows the analysis. If we denote the output voltage vO, then the voltage between the two input terminals of the op amp will be vO/A. Since the positive input terminal is grounded, the voltage at the negative input terminal must be −vO/A. The current i1 through R1 can now be found from
i1 = vI −(−vO/A) = vI +vO/A R1 R1
Figure 2.7 Analysis of the inverting con- figuration taking into account the finite open-loop gain of the op amp.
The infinite input impedance of the op amp forces the current i1 to flow entirely through R2. The output voltage vO can thus be determined from
vO =−vO −i1R2 A
v v +v /A =−O−I O R2
A R1 Collecting terms, the closed-loop gain G is found as
G≡vO = −R2/R1
vI 1 + (1 + R2/R1)/A
(2.5)
2.2 The Inverting Configuration 67
We note that as A approaches ∞, G approaches the ideal value of −R2 /R1 . Also, from Fig. 2.7 we see that as A approaches ∞, the voltage at the inverting input terminal approaches zero. This is the virtual-ground assumption we used in our earlier analysis when the op amp was
68 Chapter 2 Operational Amplifiers
assumed to be ideal. Finally, note that Eq. (2.5) in fact indicates that to minimize the
dependence of the closed-loop gain G on the value of the open-loop gain A, we should make 1+R2 ≪A
R1
Example 2.1
Consider the inverting configuration with R1 = 1 k and R2 = 100 k, that is, having an ideal closed-loop gain of −100.
(a) Find the closed-loop gain for the cases A = 103 , 104 , and 105 . In each case determine the percentage errorinthemagnitudeofGrelativetotheidealvalueofR2/R1 (obtainedwithA=∞).Alsodetermine the voltage v1 that appears at the inverting input terminal when vI = 0.1 V.
(b) Iftheopen-loopgainAchangesfrom100,000to50,000(i.e.,dropsby50%),whatisthecorresponding percentage change in the magnitude of the closed-loop gain G?
Solution
(a) Substituting the given values in Eq. (2.5), we obtain the values given in the following table, where the percentage error e is defined as
e ≡ |G| − (R2 /R1 ) × 100 (R2 /R1 )
The values of v1 are obtained from v1 = −vO/A = GvI /A with vI = −0.1 V. A |G| e v1
103 90.83
104 99.00
105 99.90
−9.17% −9.08 mV −1.00% −0.99 mV −0.10% −0.10 mV
(b) UsingEq.(2.5),wefindthatforA=50,000,|G|=99.80.Thusa−50%changeintheopen-loopgain results in a change in |G| from 99.90 to 99.80, which is only −0.1%!
2.2.3 Input and Output Resistances
Assuming an ideal op amp with infinite open-loop gain, the input resistance of the closed-loop inverting amplifier of Fig. 2.5 is simply equal to R1. This can be seen from Fig. 2.6(b), where
Ri≡vI=vI =R1 i1 vI/R1
Now recall that in Section 1.5 we learned that the amplifier input resistance forms a voltage divider with the resistance of the source that feeds the amplifier. Thus, to avoid the loss of signal strength, voltage amplifiers are required to have high input resistance. In the case of the invert- ing op-amp configuration we are studying, to make Ri high we should select a high value for R1.However,iftherequiredgainR2/R1 isalsohigh,thenR2 couldbecomeimpracticallylarge
(e.g., greater than a few megohms). We may conclude that the inverting configuration suffers from a low input resistance. A solution to this problem is discussed in Example 2.2 below.
Since the output of the inverting configuration is taken at the terminals of the ideal voltage source A(v2 − v1) (see Fig. 2.6a), it follows that the output resistance of the closed-loop amplifier is zero.
Example 2.2
Assumingtheopamptobeideal,deriveanexpressionfortheclosed-loopgainvO/vI ofthecircuitshown in Fig. 2.8. Use this circuit to design an inverting amplifier with a gain of 100 and an input resistance of 1 M. Assume that for practical reasons it is required not to use resistors greater than 1 M. Compare your design with that based on the inverting configuration of Fig. 2.5.
2.2 The Inverting Configuration 69
4
1
5 vx
7
x
6
2
3
Figure 2.8 Circuit for Example 2.2. The circled numbers indicate the sequence of the steps in the analysis. Solution
The analysis begins at the inverting input terminal of the op amp, where the voltage is v1=−vO =−vO =0
v1, we can determine the current i1 as follows:
i1=vI−v1 =vI−0=vI
R1 R1 R1
Since zero current flows into the inverting input terminal, all of i1 will flow through R2, and thus
i2 =i1 = vI R1
vx =v1 −i2R2 =0− vI R2 =−R2 vI R1 R1
8
A∞
Here we have assumed that the circuit is “working” and producing a finite output voltage vO. Knowing
Now we can determine the voltage at node x:
70 Chapter 2 Operational Amplifiers
Example 2.2 continued
This in turn enables us to find the current i3:
Next, a node equation at x yields i4: Finally, we can determine vO from
i3=0−vx=R2 vI R3 R1R3
i4=i2+i3=vI + R2 vI R1 R1R3
vO=vx−i4R4
=−R2vI− vI + R2 vI R4
Thus the voltage gain is given by
which can be written in the form
R1 R1 R1R3
v R R R
O=−2+41+2 vI R1 R1 R3
vRRR O=−21+4+4 vI R1 R2 R3
Now, since an input resistance of 1 M is required, we select R1 = 1 M. Then, with the limitation of using resistors no greater than 1 M, the maximum value possible for the first factor in the gain expression is 1 and is obtained by selecting R2 = 1 M. To obtain a gain of −100, R3 and R4 must be selected so that the second factor in the gain expression is 100. If we select the maximum allowed (in this example) value of 1 M for R4, then the required value of R3 can be calculated to be 10.2 k. Thus this circuit utilizes three 1-M resistors and a 10.2-k resistor. In comparison, if the inverting configuration were used with R1 = 1 M we would have required a feedback resistor of 100 M, an impractically large value!
Before leaving this example it is insightful to inquire into the mechanism by which the circuit is able to realize a large voltage gain without using large resistances in the feedback path. Toward that end, observe that because of the virtual ground at the inverting input terminal of the op amp, R2 and R3 are in effect in parallel. Thus, by making R3 lower than R2 by, say, a factor k (i.e., where k > 1), R3 is forced to carry a currentk-timesthatinR2.Thus,whilei2 =i1,i3 =ki1 andi4 =(k+1)i1.Itisthecurrentmultiplicationbya factorof(k+1)thatenablesalargevoltagedroptodevelopacrossR4 andhencealargevO withoutusing a large value for R4. Notice also that the current through R4 is independent of the value of R4. It follows that the circuit can be used as a current amplifier as shown in Fig. 2.9.
i2 iI
v1 0
iI
i4 R4 R3
i3R2 iI R3
R2
Figure 2.9 A current amplifier based on the circuit
of Fig. 2.8. The amplifier delivers its output current
to R4. It has a current gain of (1+R2/R3), a zero input
resistance, and an infinite output resistance. The load
(R ), however, must be floating (i.e., neither of its 4R3I 4
two terminals can be connected to ground).
R i1 2i
2.2 TheInvertingConfiguration 71
EXERCISES
D2.4 UsethecircuitofFig.2.5todesignaninvertingamplifierhavingagainof−10andaninputresistance of100k.GivethevaluesofR1 andR2.
Ans. R1 =100k;R2 =1M
2.5 The circuit shown in Fig. E2.5(a) can be used to implement a transresistance amplifier (see Table 1.1 in Section 1.5). Find the value of the input resistance Ri, the transresistance Rm, and the output resistance Ro of the transresistance amplifier. If the signal source shown in Fig. E2.5(b) is connected to the input of the transresistance amplifier, find the amplifier output voltage.
Ans. Ri =0;Rm =−10k;Ro =0;vO =−5V
Figure E2.5
2.6 For the circuit in Fig. E2.6 determine the values of v1,i1,i2,vO,iL, and iO. Also determine the voltage gain vO/vI, current gain iL/iI, and power gain PO/PI.
Ans. 0V;1mA;1mA;−10V;−10mA;−11mA;−10V/V(20dB),−10A/A(20dB); 100 W/W (20 dB)
i2 10 k
i1
1 vO 1 V i L
1 k
1 k
v iO
Figure E2.6
2.2.4 An Important Application—The Weighted Summer
A very important application of the inverting configuration is the weighted-summer circuit shown in Fig. 2.10. Here we have a resistance Rf in the negative-feedback path (as before), but we have a number of input signals v1,v2,…,vn each applied to a corresponding resistor
72 Chapter 2
Operational Amplifiers
R1 , R2 , . . . , Rn , which are connected to the inverting terminal of the op amp. From our previous discussion, the ideal op amp will have a virtual ground appearing at its negative input terminal. Ohm’s law then tells us that the currents i1,i2,…,in are given by
i1=v1, i2=v2, …, in=vn R1 R2 Rn
0
Figure 2.10 A weighted summer.
All these currents sum together to produce the current i,
i=i1 +i2 +···+in
(2.6)
which will be forced to flow through Rf (since no current flows into the input terminals of an ideal op amp). The output voltage vO may now be determined by another application of Ohm’s law,
Thus,
vO =0−iRf =−iRf
RRR vO=− fv1+ fv2+···+ fvn
R1 R2 Rn
(2.7)
That is, the output voltage is a weighted sum of the input signals v1,v2,…,vn. This circuit is therefore called a weighted summer. Note that each summing coefficient may be independently adjusted by adjusting the corresponding “feed-in” resistor (R1 to Rn). This nice property, which greatly simplifies circuit adjustment, is a direct consequence of the virtual ground that exists at the inverting op-amp terminal. As the reader will soon come to appreciate, virtual grounds are extremely “handy.” In the weighted summer of Fig. 2.10 all the summing coefficients must be of the same sign. The need occasionally arises for summing signals with opposite signs. Such a function can be implemented, however, using two op amps as shown in Fig. 2.11. Assuming ideal op amps, it can be easily shown that the output voltage is given by
R R R R R R
v=v a c +v a c −v c −v c (2.8)
O1RR2RR3R4R 1b2b34
Weighted summers are utilized in a variety of applications including in the design of audio systems, where they can be used in mixing signals originating from different musical instruments.
Ra Rc
R1
v1 Rb
R2 v2R3 vO
v3 R4
v4
Figure 2.11 A weighted summer capable of implementing summing coefficients of both signs.
EXERCISES
D2.7 Design an inverting op-amp circuit to form the weighted sum vO of two inputs v1 and v2. It is required thatvO =−(v1 +5v2).ChoosevaluesforR1,R2,andRf sothatforamaximumoutputvoltageof10V the current in the feedback resistor will not exceed 1 mA.
Ans. Apossiblechoice:R1 =10k,R2 =2k,andRf =10k
D2.8 Use the idea presented in Fig. 2.11 to design a weighted summer that provides vO =2v1 +v2 −4v3
Ans. A possible choice: R1 = 5k, R2 = 10k, Ra = 10k, Rb = 10k, R3 = 2.5k, Rc =10k
2.3 The Noninverting Configuration
The second closed-loop configuration we shall study is shown in Fig. 2.12. Here the input signalvI isapplieddirectlytothepositiveinputterminaloftheopampwhileoneterminalof R1 is connected to ground.
2.3.1 The Closed-Loop Gain
Analysis of the noninverting circuit to determine its closed-loop gain (vO/vI) is illustrated in Fig. 2.13. Again the order of the steps in the analysis is indicated by circled numbers. Assuming that the op amp is ideal with infinite gain, a virtual short circuit exists between its two input terminals. Hence the difference input signal is
vId =vO =0 forA=∞ A
Thus the voltage at the inverting input terminal will be equal to that at the noninverting input terminal, which is the applied voltage vI . The current through R1 can then be determined as v I /R1 . Because of the infinite input impedance of the op amp, this current will flow through R2, as shown in Fig. 2.13. Now the output voltage can be determined from
v
vO =vI + I R2 R1
2.3 The Noninverting Configuration 73
74 Chapter 2
Operational Amplifiers
5 vI R1
R2
Figure 2.12 The noninverting configuration.
vI R2 vOvI RR2vI 1R 6
3 vI R1
R1 2v
I11
0 1 vId 0 V 4
vI
vO
Figure 2.13 Analysis of the noninverting circuit. The sequence of the steps in the analysis is indicated by the circled numbers.
which yields
vO =1+RI (2.9) vI R2
Further insight into the operation of the noninverting configuration can be obtained by considering the following: Since the current into the op-amp inverting input is zero, the circuit composed of R1 and R2 acts in effect as a voltage divider feeding a fraction of the output voltage back to the inverting input terminal of the op amp; that is,
R
v =v 1 (2.10)
Then the infinite op-amp gain and the resulting virtual short circuit between the two input terminals of the op amp forces this voltage to be equal to that applied at the positive input
terminal; thus,
which yields the gain expression given in Eq. (2.9).
This is an appropriate point to reflect further on the action of the negative feedback present
in the noninverting circuit of Fig. 2.12. Let vI increase. Such a change in vI will cause vId to increase, and vO will correspondingly increase as a result of the high (ideally infinite) gain of the op amp. However, a fraction of the increase in vO will be fed back to the inverting input terminal of the op amp through the (R1,R2) voltage divider. The result of this feedback will betocounteracttheincreaseinvId,drivingvId backtozero,albeitatahighervalueofvO that corresponds to the increased value of vI . This degenerative action of negative feedback gives it the alternative name degenerative feedback. Finally, note that the argument above applies equallywellifvI decreases.AformalanddetailedstudyoffeedbackispresentedinChapter11.
1 O R1 +R2
R v1=v
OR+RI 12
2.3.2 Effect of Finite Open-Loop Gain
As we have done for the inverting configuration, we now consider the effect of the finite op-amp open-loop gain A on the gain of the noninverting configuration. Assuming the op amp to be ideal except for having a finite open-loop gain A, it can be shown that the closed-loop gain of the noninverting amplifier circuit of Fig. 2.12 is given by
G≡vO = 1+(R2/R1) (2.11) vI 1+ 1+(R2/R1)
A
Observe that the denominator is identical to that for the case of the inverting configuration (Eq. 2.5). This is no coincidence; it is a result of the fact that both the inverting and the noninverting configurations have the same feedback loop, which can be readily seen if the input signal source is eliminated (i.e., short-circuited). The numerators, however, are different, for the numerator gives the ideal or nominal closed-loop gain (−R2/R1 for the invertingconfiguration,and1+R2/R1 forthenoninvertingconfiguration).Finally,wenote (with reassurance) that the gain expression in Eq. (2.11) reduces to the ideal value for A = ∞. In fact, it approximates the ideal value for
A ≫ 1 + R2 R1
This is the same condition as in the inverting configuration, except that here the quantity on the right-hand side is the nominal closed-loop gain. The expressions for the actual and ideal values of the closed-loop gain G in Eqs. (2.11) and (2.9), respectively, can be used to determine the percentage error in G resulting from the finite op-amp gain A as
Percent gain error = − 1 + (R2 /R1 ) × 100 (2.12) A+1+(R2/R1)
Thus, as an example, if an op amp with an open-loop gain of 1000 is used to design a noninverting amplifier with a nominal closed-loop gain of 10, we would expect the closed-loop gain to be about 1% below the nominal value.
2.3.3 Input and Output Resistance
The gain of the noninverting configuration is positive—hence the name noninverting. The input impedance of this closed-loop amplifier is ideally infinite, since no current flows into the positive input terminal of the op amp. The output of the noninverting amplifier is taken at the terminals of the ideal voltage source A(v2 −v1) (see the op-amp equivalent circuit in Fig. 2.3), and thus the output resistance of the noninverting configuration is zero.
2.3.4 The Voltage Follower
The property of high input impedance is a very desirable feature of the noninverting configuration. It enables using this circuit as a buffer amplifier to connect a source with a high impedance to a low-impedance load. We discussed the need for buffer amplifiers in Section 1.5. In many applications the buffer amplifier is not required to provide any voltage gain; rather, it is used mainly as an impedance transformer or a power amplifier. In such cases we may make R2 = 0 and R1 = ∞ to obtain the unity-gain amplifier shown in Fig. 2.14(a). This circuit is commonly referred to as a voltage follower, since the output “follows” the input. In the ideal case, v O = v I , Rin = ∞, Rout = 0, and the follower has the equivalent circuit shown in Fig. 2.14(b).
2.3 The Noninverting Configuration 75
76 Chapter 2
Operational Amplifiers
vI 1vI
vO
vO vI
vI
Figure 2.14 (a) The unity-gain buffer or follower amplifier. (b) Its equivalent circuit model.
(a) (b)
Since in the voltage-follower circuit the entire output is fed back to the inverting input, the circuit is said to have 100% negative feedback. The infinite gain of the op amp then acts to make vId = 0 and hence vO = vI . Observe that the circuit is elegant in its simplicity!
Since the noninverting configuration has a gain greater than or equal to unity, depending on the choice of R2/R1, some prefer to call it “a follower with gain.”
EXERCISES
2.9 Use the superposition principle to find the output voltage of the circuit shown in Fig. E2.9. Ans. vO =6v1 +4v2
Figure E2.9
2.10 If in the circuit of Fig. E2.9 the 1-k resistor is disconnected from ground and connected to a third signal source v3, use superposition to determine vO in terms of v1,v2, and v3.
Ans. vO =6v1 +4v2 −9v3
D2.11 Designanoninvertingamplifierwithagainof2.Atthemaximumoutputvoltageof10Vthecurrent in the voltage divider is to be 10 μA.
Ans. R1 =R2 =0.5M
2.12 (a) Show that if the op amp in the circuit of Fig. 2.12 has a finite open-loop gain A, then the closed-loop gain is given by Eq. (2.11). (b) For R1 = 1 k and R2 = 9 k find the percentage deviation e of the closed-loop gain from the ideal value of (1 + R2 /R1 ) for the cases A = 103 , 104 , and 105. For vI = 1 V, find in each case the voltage between the two input terminals of the op amp. Ans. e=−1%,−0.1%,−0.01%;v2 −v1 =9.9mV,1mV,0.1mV
2.13 For the circuit in Fig. E2.13 find the values of iI, v1, i1, i2, vO, iL, and iO. Also find the voltage gain vO/vI, the current gain iL/iI, and the power gain PL/PI.
Ans. 0;1V;1mA;1mA;10V;10mA;11mA;10V/V(20dB);∞;∞
i2
9 k
2.4 Difference Amplifiers 77
i1 1k
iI
v I 1 V
iO v1
vO iL
1 k
Figure E2.13
2.14 It is required to connect a transducer having an open-circuit voltage of 1 V and a source resistance of 1 M to a load of 1-k resistance. Find the load voltage if the connection is done (a) directly, and (b) through a unity-gain voltage follower.
Ans. (a)1mV;(b)1V
2.4 Difference Amplifiers
Having studied the two basic configurations of op-amp circuits together with some of their direct applications, we are now ready to consider a somewhat more involved but very important application. Specifically, we shall study the use of op amps to design difference or differential amplifiers.2 A difference amplifier is one that responds to the difference between the two signals applied at its input and ideally rejects signals that are common to the two inputs. The representation of signals in terms of their differential and common-mode components was given in Fig. 2.4. It is repeated here in Fig. 2.15 with slightly different symbols to serve as the input signals for the difference amplifiers we are about to design. Although ideally the difference amplifier will amplify only the differential input signal vId and reject completely the common-mode input signal vIcm, practical circuits will have an output voltage vO given by
vO =AdvId +AcmvIcm (2.13)
where Ad denotes the amplifier differential gain and Acm denotes its common-mode gain (ideally zero). The efficacy of a differential amplifier is measured by the degree of its rejection of common-mode signals in preference to differential signals. This is usually quantified by a measure known as the common-mode rejection ratio (CMRR), defined as
CMRR = 20 log |Ad | (2.14) |Acm |
2The terms difference and differential are usually used to describe somewhat different amplifier types. For our purposes at this point, the distinction is not sufficiently significant. We will be more precise near the end of this section.
78 Chapter 2
Operational Amplifiers
vI1 vIcm vId2 vId2
vIcm vId2
vId vI2 vI1
vIcm 12 (vI1 vI2)
vI2 vIcm vId2
Figure2.15 Representingtheinputsignalstoa differential amplifier in terms of their differential and common-mode components.
The need for difference amplifiers arises frequently in the design of electronic systems, especially those employed in instrumentation. As a common example, consider a transducer providing a small (e.g., 1 mV) signal between its two output terminals while each of the two wires leading from the transducer terminals to the measuring instrument may have a large interference signal (e.g., 1 V) relative to the circuit ground. The instrument front end obviously needs a difference amplifier.
Before we proceed any further we should address a question that the reader might have: The op amp is itself a difference amplifier; why not just use an op amp? The answer is that the very high (ideally infinite) gain of the op amp makes it impossible to use by itself. Rather, as we did before, we have to devise an appropriate feedback network to connect to the op amp to create a circuit whose closed-loop gain is finite, predictable, and stable.
2.4.1 A Single-Op-Amp Difference Amplifier
Our first attempt at designing a difference amplifier is motivated by the observation that the gain of the noninverting amplifier configuration is positive, (1 + R2 /R1 ), while that of the inverting configuration is negative, (−R2/R1). Combining the two configurations together is then a step in the right direction—namely, getting the difference between two input signals. Of course, we have to make the two gain magnitudes equal in order to reject common-mode signals. This, however, can be easily achieved by attenuating the positive input signal to reduce the gain of the positive path from (1 + R2 /R1 ) to (R2 /R1 ). The resulting circuit would then look like that shown in Fig. 2.16, where the attenuation in the positive input path is achieved by the voltage divider (R3,R4). The proper ratio of this voltage divider can be determined from
which can be put in the form
RRR 41+2=2 R4 +R3 R1 R1
R4 = R2 R4 +R3 R2 +R1
This condition is satisfied by selecting
R4 = R2 R3 R1
(2.15)
vI1 vI2
2.4 Difference Amplifiers 79
This completes our work. However, we have perhaps proceeded a little too fast! Let’s step back and verify that the circuit in Fig. 2.16 with R3 and R4 selected according to Eq. (2.15) does in fact function as a difference amplifier. Specifically, we wish to determine the output voltage vO in terms of vI1 and vI2. Toward that end, we observe that the circuit is linear, and thus we can use superposition.
To apply superposition, we first reduce vI2 to zero—that is, ground the terminal to which vI2 is applied—and then find the corresponding output voltage, which will be due entirely to vI1. We denote this output voltage vO1. Its value may be found from the circuit in Fig. 2.17(a), which we recognize as that of the inverting configuration. The existence of R3 and R4 does not affect the gain expression, since no current flows through either of them. Thus,
vO1 =−R2vI1 R1
Next, we reduce vI1 to zero and evaluate the corresponding output voltage vO2. The circuit will now take the form shown in Fig. 2.17(b), which we recognize as the noninverting configuration withanadditionalvoltagedivider,madeupofR3 andR4,connectedtotheinputvI2.Theoutput voltage vO2 is therefore given by
Figure 2.16 A difference amplifier.
RRR
v=v41+2=2v O2 I2R+R R RI2
3411
where we have utilized Eq. (2.15).
The superposition principle tells us that the output voltage vO is equal to the sum of vO1
and vO2. Thus we have
vO = R2 (vI2 −vI1)= R2 vId (2.16) R1 R1
Thus,asexpected,thecircuitactsasadifferenceamplifierwithadifferentialgainAd of
Ad = R2 (2.17)
R1
Of course this is predicated on the op amp being ideal and furthermore on the selection of R3 and R4 so that their ratio matches that of R1 and R2 (Eq. 2.15). To make this matching requirement a little easier to satisfy, we usually select
R3 =R1 and R4 =R2
80 Chapter 2
Operational Amplifiers
vI1
Figure 2.17 Application of superposition to the analysis of the circuit of Fig. 2.16.
Let’s next consider the circuit with only a common-mode signal applied at the input, as shown in Fig. 2.18. The figure also shows some of the analysis steps. Thus,
(2.18)
1R i1 = vIcm − 4 vIcm
vI2
R1 R4 +R3 =v R3 1
IcmR4+R3 R1 The output voltage can now be found from
vO = R4 vIcm −i2R2 R4 +R3
Substituting i2 = i1 and for i1 from Eq. (2.18),
vO = R4 vIcm − R2 R3 vIcm
Thus,
R4 +R3 R1 R4 +R3
RRR =4 1−23vIcm
R4 +R3 R1 R4
v R RR Acm≡O= 4 1−23 vIcm R4 +R3 R1 R4
(2.19)
For the design with the resistor ratios selected according to Eq. (2.15), we obtain Acm =0
as expected. Note, however, that any mismatch in the resistance ratios can make Acm nonzero, and hence CMRR finite.
In addition to rejecting common-mode signals, a difference amplifier is usually required to have a high input resistance. To find the input resistance between the two input terminals
i2
R2
2.4 Difference Amplifiers 81
i1
vIcm
R4
R1
R3
vO
R4 vIcm
R4 R3
Figure 2.18 Analysis of the difference amplifier to determine its common-mode gain Acm ≡ vO/vIcm.
(i.e., the resistance seen by v Id ), called the differential input resistance Rid , consider Fig. 2.19. Here we have assumed that the resistors are selected so that
Now
R3 =R1 and R4 =R2 Rid ≡ vId
iI
Since the two input terminals of the op amp track each other in potential, we may write a loop equation and obtain
Thus,
vId =R1iI +0+R1iI
Rid =2R1 (2.20)
Note that if the amplifier is required to have a large differential gain (R2/R1), then R1 of necessity will be relatively small and the input resistance will be correspondingly low, a drawback of this circuit. Another drawback of the circuit is that it is not easy to vary the differential gain of the amplifier. Both of these drawbacks are overcome in the instrumentation amplifier discussed next.
vId
I
I
Rid
Figure 2.19 Finding the input resis- tance of the difference amplifier for the caseR3 =R1 andR4 =R2.
82 Chapter 2 Operational Amplifiers
EXERCISES
2.15 Consider the difference-amplifier circuit of Fig. 2.16 for the case R1 = R3 = 2 k and R2 = R4 = 200 k. (a) Find the value of the differential gain Ad . (b) Find the value of the differential input resistance Rid andtheoutputresistanceRo.(c)Iftheresistorshave1%tolerance(i.e.,eachcanbewithin±1% of its nominal value), use Eq. (2.19) to find the worst-case common-mode gain Acm and hence the corresponding value of CMRR.
Ans. (a)100V/V(40dB);(b)4k,0;(c)0.04V/V,68dB
D2.16 Find values for the resistances in the circuit of Fig. 2.16 so that the circuit behaves as a difference
amplifier with an input resistance of 20 k and a gain of 10. Ans. R1 =R3 =10k;R2 =R4 =100k
2.4.2 A Superior Circuit—The Instrumentation Amplifier
The low-input-resistance problem of the difference amplifier of Fig. 2.16 can be solved by using voltage followers to buffer the two input terminals; that is, a voltage follower of the type in Fig. 2.14 is connected between each input terminal and the corresponding input terminal of the difference amplifier. However, if we are going to use two additional op amps, we should ask the question: Can we get more from them than just impedance buffering? An obvious answer would be that we should try to get some voltage gain. It is especially interesting that
1R vI1 v R2
I1
1
A1
R2
R4
R1
R3
X A3
R1
R3
R2 RvO
4
A2
1R vI2
vI2
R2 1
(a)
Figure 2.20 A popular circuit for an instrumentation amplifier. (a) Initial approach to the circuit. (b) The circuit in (a) with the connection between node X and ground removed and the two resistors R1 and R1 lumped together. This simple wiring change dramatically improves performance. (c) Analysis of the circuit in (b) assuming ideal op amps.
2.4 Difference Amplifiers 83
vI1
vI2
vI1 0 V
A1
R R4
2
R3
2R1
R3
A3
R2 RvO
A2
vO1
4
A1
(b)
R R4 v02
I1
v /2R R3
Id1
I2 I1 2R1 Id vId 12R A3 vId2R11
(vv)v 2R2
v/2R
Id 1 R3 R4 R2
R vOR 1R vId
vI2
2
0R431
0 V A2 vI2
Figure 2.20 continued
vO 2
(c)
we can achieve this without compromising the high input resistance simply by using followers with gain rather than unity-gain followers. Achieving some or indeed the bulk of the required gain in this new first stage of the differential amplifier eases the burden on the difference amplifier in the second stage, leaving it to its main task of implementing the differencing function and thus rejecting common-mode signals.
The resulting circuit is shown in Fig. 2.20(a). It consists of two stages in cascade. The first stage is formed by op amps A1 and A2 and their associated resistors, and the second stage is the by-now-familiar difference amplifier formed by op amp A3 and its four associated resistors. Observe that as we set out to do, each of A1 and A2 is connected in the noninverting configu- ration and thus realizes a gain of (1+R2/R1). It follows that each of vI1 and vI2 is amplified by this factor, and the resulting amplified signals appear at the outputs of A1 and A2 , respectively.
The difference amplifier in the second stage operates on the difference signal (1+R2/R1)(vI2−vI1)=(1+R2/R1)vId andprovidesatitsoutput
R R vO=4 1+2 vId
R3 R1
84 Chapter 2
Operational Amplifiers
Thus the differential gain realized is
Ad=4 1+2 (2.21)
R R R3 R1
The common-mode gain will be zero because of the differencing action of the second-stage amplifier.
The circuit in Fig. 2.20(a) has the advantage of very high (ideally infinite) input resistance and high differential gain. Also, provided A1 and A2 and their corresponding resistors are matched, the two signal paths are symmetric—a definite advantage in the design of a differential amplifier. The circuit, however, has three major disadvantages:
1. The input common-mode signal vIcm is amplified in the first stage by a gain equal to that experienced by the differential signal v Id . This is a very serious issue, for it could result in the signals at the outputs of A1 and A3 being of such large magnitudes that the op amps saturate (more on op-amp saturation in Section 2.8). But even if the op amps do not saturate, the difference amplifier of the second stage will now have to deal with much larger common-mode signals, with the result that the CMRR of the overall amplifier will inevitably be reduced.
2. The two amplifier channels in the first stage have to be perfectly matched, otherwise a spurious signal may appear between their two outputs. Such a signal would get amplified by the difference amplifier in the second stage.
3. To vary the differential gain Ad , two resistors have to be varied simultaneously, say the two resistors labeled R1 . At each gain setting the two resistors have to be perfectly matched: a difficult task.
All three problems can be solved with a very simple wiring change: Simply disconnect the node between the two resistors labeled R1, node X, from ground. The circuit with this small but functionally profound change is redrawn in Fig. 2.20(b), where we have lumped the two resistors (R1 and R1) together into a single resistor (2R1).
Analysis of the circuit in Fig. 2.20(b), assuming ideal op amps, is straightforward, as is illustrated in Fig. 2.20(c). The key point is that the virtual short circuits at the inputs of op amps A1 and A2 cause the input voltages vI1 and vI2 to appear at the two terminals of resistor (2R1 ). Thus the differential input voltage v I 2 − v I 1 ≡ v Id appears across 2R1 and causes a currenti=vId/2R1 toflowthrough2R1 andthetworesistorslabeledR2.Thiscurrentinturn produces a voltage difference between the output terminals of A1 and A2 given by
2R vO2−vO1= 1+ 2 vId
2R1
The difference amplifier formed by op amp A3 and its associated resistors senses the voltage
difference (vO2 −vO1) and provides a proportional output voltage vO: vO = R4 (vO2 −vO1)
R3
R R
= 4 1+ 2 vId R3 R1
Thus the overall differential voltage-gain is given by
vId R3 R1
Observe that proper differential operation does not depend on the matching of the two resistors
labeled R2 . Indeed, if one of the two is of different value, say R2′ , the expression for Ad becomes R R +R′
Ad=4 1+2 2 (2.23) R3 2R1
Consider next what happens when the two input terminals are connected together to a common-mode input voltage v Icm . It is easy to see that an equal voltage appears at the negative input terminals of A1 and A2, causing the current through 2R1 to be zero. Thus there will be no current flowing in the R2 resistors, and the voltages at the output terminals of A1 and A2 will be equal to the input (i.e., vIcm). Thus the first stage no longer amplifies vIcm; it simply propagates vIcm to its two output terminals, where they are subtracted to produce a zero common-mode output by A3. The difference amplifier in the second stage, however, now has a much improved situation at its input: The difference signal has been amplified by (1 + R2 /R1 ) while the common-mode voltage remained unchanged.
Finally, we observe from the expression in Eq. (2.22) that the gain can be varied by changing only one resistor, 2R1. We conclude that this is an excellent differential amplifier circuit and is widely employed as an instrumentation amplifier, that is, as the input amplifier used in a variety of electronic instruments.
vRR
Ad≡O=4 1+2 (2.22)
2.4 Difference Amplifiers 85
INTEGRATED INSTRUMENTATION AMPLIFIERS:
Example 2.3
The conventional combination of three op amps and a number of precision resistors to form an instrumentation amplifier is an extremely powerful tool for the design of instruments for many applications. While the earliest applications used separate op amps and discrete resistors, fully integrated versions incorporating most required components in a single integrated-circuit package are increasingly available from many manufacturers. Low-power versions of these units are extremely important in the design of portable, wearable, and implantable medical monitoring devices, such as wristband activity monitors.
Design the instrumentation amplifier circuit in Fig. 2.20(b) to provide a gain that can be varied over the range of 2 to 1000 utilizing a 100-k variable resistance (a potentiometer, or “pot” for short).
Solution
It is usually preferable to obtain all the required gain in the first stage, leaving the second stage to perform the task of taking the difference between the outputs of the first stage and thereby rejecting the common-mode signal. In other words, the second stage is usually designed for a gain of 1. Adopting this approach, we select
86 Chapter 2 Operational Amplifiers
Example 2.3 continued
all the second-stage resistors to be equal to a practically convenient value, say 10 k. The problem then reduces to designing the first stage to realize a gain adjustable over the range of 2 to 1000. Implementing 2R1 as the series combination of a fixed resistor R1f and the variable resistor R1v obtained using the 100-k pot (Fig. 2.21), we can write
1 +
2R2 = 2 to 1000 R1f +R1v
1+2R2 =1000 R1f
1+ 2R2 =2 R1f +100k
Thus,
and
These two equations yield R1f = 100.2 and R2 = 50.050 k. Other practical values may be selected; for instance, R1f = 100 and R2 = 49.9 k (both values are available as standard 1%-tolerance metal-film resistors; see Appendix J) results in a gain covering approximately the required range.
2R1
R1f
100 k R1v
pot
Figure 2.21 To make the gain of the circuit in Fig. 2.20(b) variable, 2R1 is implemented as the series combination of a fixed resistor R1f and a variable resistor R1v . Resistor R1f ensures that the maximum available gain is limited.
EXERCISE
2.17 Consider the instrumentation amplifier of Fig. 2.20(b) with a common-mode input voltage of +5 V (dc) and a differential input signal of 10-mV-peak sine wave. Let (2R1) = 1 k, R2 = 0.5 M, and R3 = R4 = 10 k. Find the voltage at every node in the circuit.
Ans. vI1 =5−0.005sinωt;vI2 =5+0.005sinωt;v–(op amp A1)=5−0.005sinωt;v–(op amp A2)=5+ 0.005sinωt;vO1 =5−5.005sinωt;vO2 =5+5.005sinωt;v– (A3)=v+(A3)=2.5+2.5025sinωt;vO = 10.01 sin ωt (all in volts)
2.5 Integrators and Differentiators
The op-amp circuit applications we have studied thus far utilized resistors in the op-amp feedback path and in connecting the signal source to the circuit, that is, in the feed-in path. As a result, circuit operation has been (ideally) independent of frequency. By allowing the use of capacitors together with resistors in the feedback and feed-in paths of op-amp circuits, we open the door to a very wide range of useful and exciting applications of the op amp. We begin our study of op-amp–RC circuits by considering two basic applications, namely, signal integrators and differentiators.3
2.5.1 The Inverting Configuration with General Impedances
To begin with, consider the inverting closed-loop configuration with impedances Z1(s) and Z2(s) replacing resistors R1 and R2, respectively. The resulting circuit is shown in Fig. 2.22 and, for an ideal op amp, has the closed-loop gain or, more appropriately, the closed-loop transfer function
Vo(s) =−Z2(s) (2.24) Vi (s) Z1 (s)
As explained in Section 1.6, replacing s by jω provides the transfer function for physical frequencies ω, that is, the transmission magnitude and phase for a sinusoidal input signal of frequency ω.
2.5 Integrators and Differentiators 87
Figure 2.22 The inverting configura- tion with general impedances in the feedback and the feed-in paths.
3At this point, a review of Section 1.6 would be helpful. Also, an important fact to remember: Passing a constant current I through a capacitor C for a time t causes a change of It to accumulate on the capacitor. Thus the capacitor voltage changes by △V = △Q/C = It/C; that is, the capacitor voltage increases linearly with time.
88 Chapter 2 Operational Amplifiers
EARLY OP AMPS AND ANALOG COMPUTATION:
In 1941, Karl D. Swartzel Jr. of Bell Labs patented “the summing amplifier,”
a high-gain dc inverting amplifier, intended to be used with negative feedback. This precursor of the op amp used three vacuum tubes (the predecessor of the transistor) and ±350-V power supplies to achieve a gain of 90 dB. Though lacking a differential input, it provided the usual applications of summation, integration, and general filtering using convenient passive resistive and capacitive components.
Soon after (1942), Loebe Julie, working with Professor John R. Regazzini at Columbia University, created a differential version, still using vacuum tubes. During World War II, these units were used extensively to provide analog computational functions in association with radar-directed antiaircraft firing control involving aircraft speed projection.
In the early 1950s, driven by the demonstrated wartime success of op-amp-based computation, general-purpose commercial systems called “analog computers” began to appear. They consisted of a few dozen op amps and associated passive components, including potentiometers; the interconnections required for programming were achieved with plug boards. These computers were used to solve differential equations.
Example 2.4
For the circuit in Fig. 2.23, derive an expression for the transfer function Vo (s)/Vi (s). Show that the transfer function is that of a low-pass STC circuit. By expressing the transfer function in the standard form shown in Table 1.2 on page 36, find the dc gain and the 3-dB frequency. Design the circuit to obtain a dc gain of 40 dB, a 3-dB frequency of 1 kHz, and an input resistance of 1 k. At what frequency does the magnitude of transmission become unity? What is the phase angle at this frequency?
Figure 2.23 Circuit for Example 2.4.
Solution
To obtain the transfer function of the circuit in Fig.2.23, we substitute in Eq. (2.24), Z1=R1 and Z2=R2∥(1/sC2).SinceZ2 istheparallelconnectionoftwocomponents,itismoreconvenienttoworkin terms of Y2; that is, we use the following alternative form of the transfer function:
Vo(s) =− 1
Vi (s) Z1 (s)Y2 (s)
andsubstituteZ1 =R1 andY2(s)=(1/R2)+sC2 toobtain Vo(s) =− 1
Vi(s) R1 +sC R
21
R2
This transfer function is of first order, has a finite dc gain (at s = 0, Vo /Vi = −R2 /R1 ), and has zero gain at infinite frequency. Thus it is the transfer function of a low-pass STC network and can be expressed in the standard form of Table 1.2 as follows:
2.5 Integrators and Differentiators 89
from which we find the dc gain K to be
and the 3-dB frequency ω0 as
Vo(s) = −R2/R1 Vi(s) 1+sC2R2
K = − R2 R1
ω0= 1 C2 R2
We could have found all this from the circuit in Fig. 2.23 by inspection. Specifically, note that the capacitor behaves as an open circuit at dc; thus at dc the gain is simply (−R2/R1). Furthermore, because there is a virtual ground at the inverting input terminal, the resistance seen by the capacitor is R2, and thus the time constant of the STC network is C2R2.
Now to obtain a dc gain of 40 dB, that is, 100 V/V, we select R2 /R1 = 100. For an input resistance of 1 k, we select R1 = 1 k, and thus R2 = 100 k. Finally, for a 3-dB frequency f0 = 1 kHz, we select C2 from
2π×1×103 = 1
C ×100×103
2
which yields C2 = 1.59 nF.
The circuit has gain and phase Bode plots of the standard form in Fig. 1.23. As the gain falls off at the
rate of –20 dB/decade, it will reach 0 dB in two decades, that is, at f = 100f0 = 100 kHz. As Fig. 1.23(b) indicates, at such a frequency, which is much greater than f0, the phase is approximately −90°. To this, however, we must add the 180° arising from the inverting nature of the amplifier (i.e., the negative sign in the transfer function expression). Thus at 100 kHz, the total phase shift will be −270° or, equivalently, +90°.
2.5.2 The Inverting Integrator
By placing a capacitor in the feedback path (i.e., in place of Z2 in Fig. 2.22) and a resistor at the input (in place of Z1), we obtain the circuit of Fig. 2.24(a). We shall now show that this circuit realizes the mathematical operation of integration. Let the input be a time-varying function vI (t). The virtual ground at the inverting op-amp input causes vI (t) to appear in effect
90 Chapter 2
Operational Amplifiers
across R, and thus the current i1(t) will be vI(t)/R. This current flows through the capacitor
C, causing charge to accumulate on C. If we assume that the circuit begins operation at time
t = 0, then at an arbitrary time t the current i (t) will have deposited on C a charge equal to t1t
i (t)dt. Thus the capacitor voltage v (t) will change by 1 i (t)dt. If the initial voltage on 01CC01
C (at t = 0) is denoted VC , then
vC(t)=VC +C Now the output voltage vO(t) = −vC(t); thus,
1t vO(t)=−CR vI(t)dt−VC
0
Thus the circuit provides an output voltage that is proportional to the time integral of the input,withVC beingtheinitialconditionofintegrationandCRtheintegratortimeconstant. Note that, as expected, there is a negative sign attached to the output voltage, and thus this integrator circuit is said to be an inverting integrator. It is also known as a Miller integrator after an early worker in this field.
The operation of the integrator circuit can be described alternatively in the frequency domain by substituting Z1 (s) = R and Z2 (s) = 1/sC in Eq. (2.24) to obtain the transfer function
For physical frequencies, s = jω and
Vo(s)=− 1 (2.26) Vi (s) sCR
Vo(jω)=− 1 (2.27) Vi ( jω) jωCR
1t
0
i1(t)dt
(2.25)
Thus the integrator transfer function has magnitude V 1
and phase
o=
Vi ωCR
(2.28)
φ = +90° (2.29)
The Bode plot for the integrator magnitude response can be obtained by noting from Eq. (2.28) that as ω doubles (increases by an octave) the magnitude is halved (decreased by 6 dB). Thus the Bode plot is a straight line of slope –6 dB/octave (or, equivalently, –20 dB/ decade). This line (shown in Fig. 2.24b) intercepts the 0-dB line at the frequency that makes |Vo/Vi| = 1, which from Eq. (2.28) is
ωint = 1 (2.30) CR
The frequency ωint is known as the integrator frequency and is simply the inverse of the integrator time constant.
Comparison of the frequency response of the integrator to that of an STC low-pass network indicates that the integrator behaves as a low-pass filter with a corner frequency of zero. Observe also that at ω = 0, the magnitude of the integrator transfer function is infinite. This
vC
i1 1 t
i1 R 0 C vO(t) CR vI(t) dtVC
0
2.5 Integrators and Differentiators 91
0V vI(t)
Vo1 vO (t) Vi sCR
(a)
(b)
Figure 2.24 (a) The Miller or inverting integrator. (b) Frequency response of the integrator.
indicates that at dc the op amp is operating with an open loop. This should also be obvious from the integrator circuit itself. Reference to Fig. 2.24(a) shows that the feedback element is a capacitor, and thus at dc, where the capacitor behaves as an open circuit, there is no negative feedback! This is a very significant observation and one that indicates a source of problems with the integrator circuit: Any tiny dc component in the input signal will theoretically produce an infinite output. Of course, no infinite output voltage results in practice; rather, the output of the amplifier saturates at a voltage close to the op-amp positive or negative power supply (L+ or L−), depending on the polarity of the input dc signal.
The dc problem of the integrator circuit can be alleviated by connecting a resistor RF across the integrator capacitor C, as shown in Fig. 2.25, and thus the gain at dc will be –RF /R rather than infinite. Such a resistor provides a dc feedback path. Unfortunately, however, the integration is no longer ideal, and the lower the value of RF , the less ideal the integrator circuit becomes. This is because RF causes the frequency of the integrator pole to move from its ideal location at ω = 0 to one determined by the corner frequency of the STC network (RF , C ). Specifically, the integrator transfer function becomes
Vo(s)=− RF/R Vi (s) 1 + sCRF
92 Chapter 2
Operational Amplifiers
R
vI (t)
RF
C
vO (t)
Figure 2.25 The Miller integrator with a large resistance RF connectedinparallelwithCinordertoprovidenegative feedback and hence finite gain at dc.
as opposed to the ideal function of −1/sCR. The lower the value we select for RF , the higher the corner frequency (1/CRF ) will be and the more nonideal the integrator becomes. Thus selecting a value for RF presents the designer with a trade-off between dc performance and signal performance. The effect of RF on integrator performance is investigated further in Example 2.5.
Example 2.5
Find the output produced by a Miller integrator in response to an input pulse of 1-V height and 1-ms width [Fig. 2.26(a)]. Let R = 10 k and C = 10 nF. If the integrator capacitor is shunted by a 1-M resistor, how will the response be modified? The op amp is specified to saturate at ±13 V.
Solution
In response to a 1-V, 1-ms input pulse, the integrator output will be
1t
vO(t) = −CR
where we have assumed that the initial voltage on the integrator capacitor is 0. For C = 10 nF and R = 10 k,
CR = 0.1 ms, and
vO(t) = −10t, 0 ≤ t ≤ 1 ms
which is the linear ramp shown in Fig. 2.26(b). It reaches a magnitude of −10 V at t = 1 ms and remains constant thereafter.
That the output is a linear ramp should also be obvious from the fact that the 1-V input pulse produces a constant current through the capacitor of 1 V/10 k = 0.1 mA. This constant current I = 0.1 mA supplies the capacitor with a charge It, and thus the capacitor voltage changes linearly as (It/C), resulting in vO = −(I/C)t. It is worth remembering that charging a capacitor with a constant current produces a linear voltage across it.
0
1dt, 0 ≤ t ≤ 1 ms
vI (t)
1V 0
vO(t)
10 V
vO(t)
9.5 V
0
1 ms (a)
1 ms
(b)
1 ms
t
t
2.5 Integrators and Differentiators 93
0
0
t
(c)
Figure2.26 WaveformsforExample2.5:(a)Inputpulse.(b)Outputlinearrampofidealintegratorwithtimeconstant of0.1ms.(c)OutputexponentialrampwithresistorRF connectedacrossintegratorcapacitor.
Next consider the situation with resistor RF = 1 M connected across C. As before, the 1-V pulse will provide a constant current I = 0.1 mA. Now, however, this current is supplied to an STC network composedofRF inparallelwithC.Thus,theoutputwillbeanexponentialheadingtoward−100Vwith
to 0 V
Exponentials with time constant of 10 ms
to 100 V
94 Chapter 2 Operational Amplifiers
Example 2.5 continued
atimeconstantofCRF =10×10−9 ×1×106 =10ms,
vO(t) = −100(1 − e−t/10), 0 ≤ t ≤ 1 ms
Of course, the exponential will be interrupted at the end of the pulse, that is, at t = 1 ms, and the output
will reach the value
vO(1 ms) = −100(1 − e−1/10) = −9.5 V
The output waveform is shown in Fig. 2.26(c), from which we see that including RF causes the ramp to be slightly rounded such that the output reaches only −9.5 V, 0.5 V short of the ideal value of −10 V. Furthermore, for t > 1 ms, the capacitor discharges through RF with the relatively long time constant of 10 ms. Finally, we note that op-amp saturation, specified to occur at ±13 V, has no effect on the operation of this circuit.
The preceding example hints at an important application of integrators, namely, their use in providing triangular waveforms in response to square-wave inputs. This application is explored in Exercise 2.18. Integrators have many other applications, including their use in the design of filters (Chapter 17).
2.5.3 The Op-Amp Differentiator
Interchanging the location of the capacitor and the resistor of the integrator circuit results in the circuit in Fig. 2.27(a), which performs the mathematical function of differentiation. To see how this comes about, let the input be the time-varying function vI (t), and note that the virtual ground at the inverting input terminal of the op amp causes vI (t) to appear in effect across the capacitor C. Thus the current through C will be C(dvI /dt), and this current flows through the feedback resistor R providing at the op-amp output a voltage vO(t),
vO(t)=−CRdvI(t) (2.31) dt
The frequency-domain transfer function of the differentiator circuit can be found by substituting in Eq. (2.24), Z1 (s) = 1/sC and Z2 (s) = R to obtain
Vo(s) = −sCR Vi (s)
(2.32)
(2.33)
(2.34)
which for physical frequencies s = jω yields
Vo(jω) =−jωCR
Vi(jω) Thus the transfer function has magnitude
V
o=ωCR
Vi
and phase
φ = −90°
(2.35)
The Bode plot of the magnitude response can be found from Eq. (2.34) by noting that for an octave increase in ω, the magnitude doubles (increases by 6 dB). Thus the plot is simply a straight line of slope +6 dB/octave (or, equivalently, +20 dB/decade) intersecting the 0-dB line (where |Vo/Vi| = 1) at ω = 1/CR, where CR is the differentiator time constant [see Fig. 2.27(b)].
The frequency response of the differentiator can be thought of as the response of an STC high-pass filter with a corner frequency at infinity (refer to Fig. 1.24). Finally, we should note that the very nature of a differentiator circuit causes it to be a “noise magnifier.” This is due to the spike introduced at the output every time there is a sharp change in vI (t); such a change could be interference coupled electromagnetically (“picked up”) from adjacent signal sources. For this reason and because they suffer from stability problems (Chapter 11), differentiator circuits are generally avoided in practice. When the circuit of Fig. 2.27(a) is used, it is usually necessary to connect a small-valued resistor in series with the capacitor. This modification, unfortunately, turns the circuit into a nonideal differentiator.
2.5 Integrators and Differentiators 95
i
C 0
iR
i(t) C dvI(t)
dt dvI(t)
vO(t)CR dt vO(t) Vo sCR
vI(t)
Vi
0V
Vo (dB) Vi
(a)
6 dB/octave
0
(log scale)
1
CR
Figure 2.27 (a) A differentiator. (b) Frequency response of a differentiator with a time constant CR.
(b)
96 Chapter 2 Operational Amplifiers
EXERCISES
2.18 Consider a symmetrical square wave of 20-V peak-to-peak, 0 average, and 2-ms period applied to a Miller integrator. Find the value of the time constant CR such that the triangular waveform at the output has a 20-V peak-to-peak amplitude.
Ans. 0.5 ms
D2.19 Use an ideal op amp to design an inverting integrator with an input resistance of 10 k and an integration time constant of 10−3 s. What is the gain magnitude and phase angle of this circuit at 10 rad/s and at 1 rad/s? What is the frequency at which the gain magnitude is unity?
Ans. R=10k,C=0.1μF;atω=10rad/s:|Vo/Vi|=100V/Vandφ=+90°;atω=1rad/s: |Vo /Vi | = 1000 V/V and φ = +90°; 1000 rad/s
D2.20 Design a differentiator to have a time constant of 10−2 s and an input capacitance of 0.01 μF. What is the gain magnitude and phase of this circuit at 10 rad/s, and at 103 rad/s? In order to limit the high-frequency gain of the differentiator circuit to 100, a resistor is added in series with the capacitor. Find the required resistor value.
Ans. C=0.01μF;R=1M;atω=10rad/s:|Vo/Vi|=0.1V/Vandφ=−90°;atω=1000rad/s: |Vo /Vi | = 10 V/V and φ = −90°; 10 k
2.6 DC Imperfections
Thus far we have considered the op amp to be ideal. The only exception has been a brief discussion of the effect of the op-amp finite gain A on the closed-loop gain of the inverting and noninverting configurations. Although in many applications the assumption of an ideal op amp is not a bad one, a circuit designer has to be thoroughly familiar with the characteristics of practical op amps and the effects of such characteristics on the performance of op-amp circuits. Only then will the designer be able to use the op amp intelligently, especially if the application at hand is not a straightforward one. The nonideal properties of op amps will, of course, limit the range of operation of the circuits analyzed in the previous examples.
In this and the two sections that follow, we consider some of the important nonideal properties of the op amp.4 We do this by treating one nonideality at a time, beginning in this section with the dc problems to which op amps are susceptible.
2.6.1 Offset Voltage
Because op amps are direct-coupled devices with large gains at dc, they are prone to dc problems. The first such problem is the dc offset voltage. To understand this problem consider
4We should note that real op amps have nonideal effects additional to those discussed in this chapter. These include finite (nonzero) common-mode gain or, equivalently, noninfinite CMRR, noninfinite input resistance, and nonzero output resistance. The effect of these, however, on the performance of most of the closed-loop circuits studied here is not very significant, and their study will be postponed to later chapters (in particular, Chapters 9, 10, and 13).
the following conceptual experiment: If the two input terminals of the op amp are tied together and connected to ground, it will be found that despite the fact that vId = 0, a finite dc voltage exists at the output. In fact, if the op amp has a high dc gain, the output will be at either the positive or negative saturation level. The op-amp output can be brought back to its ideal value of 0 V by connecting a dc voltage source of appropriate polarity and magnitude between the two input terminals of the op amp. This external source balances out the input offset voltage of the op amp. It follows that the input offset voltage (VOS ) must be of equal magnitude and of opposite polarity to the voltage we applied externally.
The input offset voltage arises as a result of the unavoidable mismatches present in the input differential stage inside the op amp. In later chapters (in particular Chapters 9 and 13) we shall study this topic in detail. Here, however, our concern is to investigate the effect of VOS on the operation of closed-loop op-amp circuits. Toward that end, we note thatgeneral-purposeopampsexhibitVOS intherangeof1mVto5mV.Also,thevalueofVOS depends on temperature. The op-amp data sheets usually specify typical and maximum values for VOS at room temperature as well as the temperature coefficient of VOS (usually in μV/°C). They do not, however, specify the polarity of VOS because the component mismatches that giverisetoVOS areobviouslynotknownapriori;differentunitsofthesameop-amptypemay exhibit either a positive or a negative VOS .
To analyze the effect of VOS on the operation of op-amp circuits, we need a circuit model for the op amp with input offset voltage. Such a model is shown in Fig. 2.28. It consists of a dc source of value VOS placed in series with the positive input lead of an offset-free op amp. The justification for this model follows from the description above.
2.6 DCImperfections 97
Figure2.28 Circuitmodelforanopampwithinput offset voltage VOS .
EXERCISE
2.21 UsethemodelofFig.2.28tosketchthetransfercharacteristicvO versusvId(vO ≡v3 andvId ≡v2 −v1) of an op amp having an open-loop dc gain A0 = 104 V/V, output saturation levels of ±10 V, and VOS of +5 mV.
Ans. See Fig. E2.21. Observe that true to its name, the input offset voltage causes an offset in the voltage-transfer characteristic; rather than passing through the origin it is now shifted to the left by VOS .
98 Chapter 2 Operational Amplifiers
Figure E2.21 Transfer characteristic of an op amp with VOS = 5 mV.
Analysisofop-ampcircuitstodeterminetheeffectoftheop-ampVOS ontheirperformance is straightforward: The input voltage signal source is short-circuited and the op amp is replaced with the model of Fig. 2.28. (Eliminating the input signal, done to simplify matters, is based on the principle of superposition.) Following this procedure, we find that both the inverting and the noninverting amplifier configurations result in the same circuit, that shown in Fig. 2.29, from which the output dc voltage due to VOS is found to be
R
VO=VOS 1+ 2 (2.36)
R1
This output dc voltage can have a large magnitude. For instance, a noninverting amplifier with a closed-loop gain of 1000, when constructed from an op amp with a 5-mV input offset voltage, will have a dc output voltage of +5 V or −5 V (depending on the polarity of VOS) rather than the ideal value of 0 V. Now, when an input signal is applied to the amplifier, the corresponding signal output will be superimposed on the 5-V dc. Obviously then, the
R1
R2
VV 1R2 O OS R1
VO VOS
Offset-free op amp
Figure2.29 Evaluatingtheoutputdcoff- set voltage due to VOS in a closed-loop amplifier.
V
2.6 DC Imperfections 99
To rest of circuit
Figure 2.30 The output dc offset voltage of an op amp can be trimmed to zero by connecting a potentiometer to the two offset-nulling terminals. The wiper of the potentiometer is connected to the negative supply of the op amp.
Offset-nulling terminals
V
R2
VOS
(a)
VO VOS Offset free
(b)
Figure2.31 (a)Acapacitivelycoupledinvertingamplifier.(b)Theequivalentcircuitfordeterminingitsdc output offset voltage VO.
allowable signal swing at the output will be reduced. Even worse, if the signal to be amplified is dc, we would not know whether the output is due to VOS or to the signal!
Some op amps are provided with two additional terminals to which a specified circuit can be connected to trim to zero the output dc voltage due to VOS. Figure 2.30 shows such an arrangement that is typically used with general-purpose op amps. A potentiometer is connected between the offset-nulling terminals with the wiper of the potentiometer connected to the op-amp negative supply. Moving the potentiometer wiper introduces an imbalance that counteracts the asymmetry present in the internal op-amp circuitry and that gives rise to VOS . We shall return to this point in the context of our study of the internal circuitry of op amps in Chapter 13. It should be noted, however, that even though the dc output offset can be trimmed to zero, the problem remains of the variation (or drift) of VOS with temperature.
One way to overcome the dc offset problem is by capacitively coupling the amplifier. This, however, will be possible only in applications where the closed-loop amplifier is not required to amplify dc or very-low-frequency signals. Figure 2.31(a) shows a capacitively coupled amplifier. Because of its infinite impedance at dc, the coupling capacitor will cause the gain to be zero at dc. As a result, the equivalent circuit for determining the dc output voltageresultingfromtheop-ampinputoffsetvoltageVOS willbethatshowninFig.2.31(b). Thus VOS sees in effect a unity-gain voltage follower, and the dc output voltage VO will be equal to VOS rather than VOS(1+R2/R1), which is the case without the coupling capacitor. As far as input signals are concerned, the coupling capacitor C forms together with R1 an STC high-pass circuit with a corner frequency of ω0 = 1/CR1. Thus the gain of the capacitively
100 Chapter 2 Operational Amplifiers
coupled amplifier will fall off at the low-frequency end [from a magnitude of (1 + R2 /R1 ) at
high frequencies] and will be 3 dB down at ω0.
EXERCISES
2.22 Consideraninvertingamplifierwithanominalgainof1000constructedfromanopampwithaninput offset voltage of 3 mV and with output saturation levels of ±10 V. (a) What is (approximately) the peaksine-waveinputsignalthatcanbeappliedwithoutoutputclipping?(b)IftheeffectofVOS isnulled at room temperature (25°C), how large an input can one now apply if: (i) the circuit is to operate at a constant temperature? (ii) the circuit is to operate at a temperature in the range 0°C to 75°C and the temperaturecoefficientofVOS is10μV/°C?
Ans. (a) 7 mV; (b) 10 mV, 9.5 mV
2.23 Consider the same amplifier as in Exercise 2.22—that is, an inverting amplifier with a nominal gain
of 1000 constructed from an op amp with an input offset voltage of 3 mV and with output saturation levels of ±10 V—except here let the amplifier be capacitively coupled as in Fig. 2.31(a). (a) What is the dc offset voltage at the output, and what (approximately) is the peak sine-wave signal that can be applied at the input without output clipping? Is there a need for offset trimming? (b) If R1 = 1 k and R2 = 1 M, find the value of the coupling capacitor C1 that will ensure that the gain will be greater than 57 dB down to 100 Hz.
Ans. (a) 3 mV, 10 mV, no need for offset trimming; (b) 1.6 μF
2.6.2 Input Bias and Offset Currents
The second dc problem encountered in op amps is illustrated in Fig. 2.32. In order for the op amp to operate, its two input terminals have to be supplied with dc currents, termed the input bias currents.5 In Fig. 2.32 these two currents are represented by two current sources, IB1 and IB2, connected to the two input terminals. It should be emphasized that the input bias currents are independent of the fact that a real op amp has finite (though large) input resistance (not shown in Fig. 2.32). The op-amp manufacturer usually specifies the average value of IB1 and IB2 as well as their expected difference. The average value IB is called the input bias current,
IB = IB1 +IB2 2
and the difference is called the input offset current and is given by IOS =|IB1 −IB2|
Typical values for general-purpose op amps that use bipolar transistors are IB = 100 nA and IOS =10nA.
5This is the case for op amps constructed using bipolar junction transistors (BJTs). Those using MOSFETs in the first (input) stage do not draw an appreciable input bias current; nevertheless, the input terminals should have continuous dc paths to ground. More on this in later chapters.
2.6 DC Imperfections 101
Figure 2.32 The op-amp input bias currents represented by two current sources IB1 and IB2.
Figure 2.33 Analysis of the closed-loop amplifier, taking into account the input bias currents.
We now wish to find the dc output voltage of the closed-loop amplifier due to the input bias currents. To do this we ground the signal source and obtain the circuit shown in Fig. 2.33 for both the inverting and noninverting configurations. As shown in Fig. 2.33, the output dc voltage is given by
VO = IB1R2 ≃ IBR2 (2.37)
102 Chapter 2
Operational Amplifiers
Figure 2.34 Reducing the effect of the input bias currents by introducing a resistor R3.
This obviously places an upper limit on the value of R2. Fortunately, however, a technique exists for reducing the value of the output dc voltage due to the input bias currents. The method consists of introducing a resistance R3 in series with the noninverting input lead, as shown in Fig. 2.34. From a signal point of view, R3 has a negligible effect (ideally no effect). The appropriate value for R3 can be determined by analyzing the circuit in Fig. 2.34, where analysis details are shown, and the output voltage is given by
VO = −IB2R3 + R2(IB1 − IB2R3/R1) Consider first the case IB1 = IB2 = IB , which results in
VO = IB[R2 − R3(1 + R2/R1)] Thus we can reduce VO to zero by selecting R3 such that
R3= R2 = R1R2 1+R2/R1 R1 +R2
(2.38)
(2.39)
That is, R3 should be made equal to the parallel equivalent of R1 and R2.
Having selected R3 as above, let us evaluate the effect of a finite offset current IOS. Let
IB1 = IB + IOS /2 and IB2 = IB − IOS /2, and substitute in Eq. (2.38). The result is
VO =IOSR2 (2.40)
which is usually about an order of magnitude smaller than the value obtained without R3 (Eq. 2.37). We conclude that to minimize the effect of the input bias currents, one should place in the positive lead a resistance equal to the equivalant dc resistance seen by the inverting terminal. We emphasize the word dc in the last statement; note that if the amplifier is ac-coupled, we should select R3 = R2 , as shown in Fig. 2.35.
2.6 DC Imperfections 103
R2
Figure 2.35 In an ac-coupled amplifier the dc resis- tance seen by the inverting terminal is R2; hence R3 is chosen equal to R2.
Figure 2.36 Illustrating the need for a continuous dc path for each of the op-amp input terminals. Specifically, note that the amplifier will not work without resistor R3.
While we are on the subject of ac-coupled amplifiers, we should note that one must always provide a continuous dc path between each of the input terminals of the op amp and ground. ThisisthecasenomatterhowsmallIB is.Forthisreasontheac-couplednoninvertingamplifier of Fig. 2.36 will not work without the resistance R3 to ground. Unfortunately, including R3 lowers considerably the input resistance of the closed-loop amplifier.
EXERCISE
2.24 Consider an inverting amplifier circuit designed using an op amp and two resistors, R1 = 10 k and R2 = 1 M. If the op amp is specified to have an input bias current of 100 nA and an input offset current of 10 nA, find the output dc offset voltage resulting and the value of a resistor R3 to be placed in series with the positive input lead in order to minimize the output offset voltage. What is the new value of VO?
Ans. 0.1 V; 9.9 k (≃ 10 k); 0.01 V
2.6.3 Effect of VOS and IOS on the Operation of the Inverting Integrator
Our discussion of the inverting integrator circuit in Section 2.5.2 mentioned the susceptibility of this circuit to saturation in the presence of small dc voltages or currents. It behooves us therefore to consider the effect of the op-amp dc offsets on its operation. As will be seen, these effects can be quite dramatic.
104 Chapter 2
Operational Amplifiers
t
Figure 2.37 Determining the effect of the op-amp input offset voltage VOS on the Miller integrator circuit. Note that since the output rises with time, the op amp eventually saturates.
To see the effect of the input dc offset voltage VOS, consider the integrator circuit in Fig. 2.37, where for simplicity we have short-circuited the input signal source. Analysis of the circuit is straightforward and is shown in Fig. 2.37. Assuming for simplicity that at time t = 0 the voltage across the capacitor is zero, the output voltage as a function of time is given by
vO = VOS + VOS t (2.41) CR
Thus vO increases linearly with time until the op amp saturates—clearly an unacceptable situation! As should be expected, the dc input offset current IOS produces a similar problem. Figure 2.38 illustrates the situation. Observe that we have added a resistance R in the op-amp positive-input lead in order to keep the input bias current IB from flowing through C. Nevertheless, the offset current IOS will flow through C and cause vO to ramp linearly with time until the op amp saturates.
As mentioned in Section 2.5.2 the dc problem of the integrator circuit can be alleviated by connecting a resistor RF across the integrator capacitor C, as shown in Fig. 2.25. Such a resistorprovidesadcpaththroughwhichthedccurrents(VOS/R)andIOS canflow(assuming a resistance equal to R∥RF is connected in the positive op-amp lead), with the result that vO will now have a dc component [VOS (1 + RF /R) + IOS RF ] instead of rising linearly. To keep the dc offset at the output small, one would select a low value for RF . Unfortunately, however, the lower the value of RF , the less ideal the integrator circuit becomes.
IB2R R IB2
C
(IB1 IB2) IOS R IB1
vO
R I vO IB2RIOSt
B2 C IB2R
Figure 2.38 Effect of the op-amp input bias and offset currents on the performance of the Miller integrator circuit.
2.7 Effect of Finite Open-Loop Gain and Bandwidth on Circuit Performance 105
EXERCISE
2.25 Consider a Miller integrator with a time constant of 1 ms and an input resistance of 10 k. Let the op amp have VOS = 2 mV and output saturation voltages of ±12 V. (a) Assuming that when the power supply is turned on the capacitor voltage is zero, how long does it take for the amplifier to saturate? (b) Select the largest possible value for a feedback resistor RF so that at least ±10 V of output signal swing remains available. What is the corner frequency of the resulting STC network?
Ans. (a) 6 s; (b) 10 M, 0.16 Hz
2.7 Effect of Finite Open-Loop Gain and Bandwidth on Circuit Performance
2.7.1 Frequency Dependence of the Open-Loop Gain
The differential open-loop gain A of an op amp is not infinite; rather, it is finite and decreases with frequency. Figure 2.39 shows a plot for |A|, with the numbers typical of some commercially available general-purpose op amps (such as the popular 741-type op amp, available from many semiconductor manufacturers; its internal circuit is studied in Chapter 13).
Figure 2.39 Open-loop gain of a typical general-purpose, internally compensated op amp.
106 Chapter 2
Operational Amplifiers
Note that although the gain is quite high at dc and low frequencies, it starts to fall off at a rather low frequency (10 Hz in our example). The uniform –20-dB/decade gain rolloff shown is typical of internally compensated op amps. These are units that have a network (usually a single capacitor) included within the same IC chip whose function is to cause the op-amp gain to have the single-time-constant (STC) low-pass response shown. This process of modifying the open-loop gain is termed frequency compensation, and its purpose is to ensure that op-amp circuits will be stable (as opposed to oscillatory). The subject of stability of op-amp circuits—or, more generally, of feedback amplifiers—will be studied in Chapter 11.
By analogy to the response of low-pass STC circuits (see Section 1.6 and, for more detail, Appendix E), the gain A(s) of an internally compensated op amp may be expressed as
A(s) = A0 1+s/ωb
which for physical frequencies, s = jω, becomes A(jω)= A0
1 + jω/ωb
(2.42)
(2.43)
where A0 denotes the dc gain and ωb is the 3-dB frequency (corner frequency or “break” frequency). For the example shown in Fig. 2.39, A0 = 105 and ωb = 2π × 10 rad/s. For frequencies ω ≫ ωb (about 10 times and higher) Eq. (2.43) may be approximated by
Thus,
A(jω)≃ A0ωb jω
|A(jω)|= A0ωb ω
(2.44)
(2.45)
from which it can be seen that the gain |A| reaches unity (0 dB) at a frequency denoted by ωt and given by
Substituting in Eq. (2.44) gives
ωt =A0ωb (2.46)
A(jω) ≃ ωt (2.47) jω
The frequency ft = ωt /2π is usually specified on the data sheets of commercially available op amps and is known as the unity-gain bandwidth.6 Also note that for ω ≫ ωb the open-loop gain in Eq. (2.42) becomes
A(s) ≃ ωt (2.48) s
6 Since ft is the product of the dc gain A0 and the 3-dB bandwidth fb (where fb = ωb /2π ), it is also known as the gain–bandwidth product (GB). The reader is cautioned, however, that in some amplifiers (those that do not have an STC response), the unity-gain frequency and the gain–bandwidth product are not equal.
2.7 Effect of Finite Open-Loop Gain and Bandwidth on Circuit Performance 107 The gain magnitude can be obtained from Eq. (2.47) as
|A(jω)| ≃ ωt = ft (2.49) ωf
Thus if ft is known (106 Hz in our example), one can easily determine the magnitude of the op-amp gain at a given frequency f . Furthermore, observe that this relationship correlates with the Bode plot in Fig. 2.39. Specifically, for f ≫ fb, doubling f (an octave increase) results in halving the gain (a 6-dB reduction). Similarly, increasing f by a factor of 10 (a decade increase) results in reducing |A| by a factor of 10 (20 dB).
As a matter of practical importance, we note that the production spread in the value of ft between op-amp units of the same type is usually much smaller than that observed for A0 and fb. For this reason ft is preferred as a specification parameter. Finally, it should be mentioned that an op amp having this uniform –6-dB/octave (or equivalently –20-dB/decade) gain rolloff is said to have a single-pole model. Also, since this single pole dominates the amplifier frequency response, it is called a dominant pole. For more on poles (and zeros), the reader may wish to consult Appendix F.
EXERCISE
2.26 Aninternallycompensatedopampisspecifiedtohaveanopen-loopdcgainof106dBandaunity-gain bandwidthof3MHz.Findfb andtheopen-loopgain(indB)atfb,300Hz,3kHz,12kHz,and60kHz. Ans. 15Hz;103dB;80dB;60dB;48dB;34dB
2.7.2 Frequency Response of Closed-Loop Amplifiers
We next consider the effect of limited op-amp gain and bandwidth on the closed-loop transfer functions of the two basic configurations: the inverting circuit of Fig. 2.5 and the noninverting circuit of Fig. 2.12. The closed-loop gain of the inverting amplifier, assuming a finite op-amp open-loop gain A, was derived in Section 2.2 and given in Eq. (2.5), which we repeat here as
Vo = −R2/R1
Vi 1 + (1 + R2/R1)/A
(2.50)
(2.51)
(2.52)
Substituting for A from Eq. (2.42) and using Eq. (2.46) gives Vo (s) −R2 /R1
V (s) = 1 R i1+1+2+s
A0 R1 ωt/(1+R2/R1) ForA0 ≫1+R2/R1,whichisusuallythecase,
Vo(s) ≃ −R2/R1
Vi(s) 1+ s ωt/(1+R2/R1)
108 Chapter 2
Operational Amplifiers
which is of the same form as that for a low-pass STC network (see Table 1.2, page 36). Thus the inverting amplifier has an STC low-pass response with a dc gain of magnitude equal to R2 /R1 . The closed-loop gain rolls off at a uniform –20-dB/decade slope with a corner frequency (3-dB frequency) given by
ω3dB = ωt (2.53) 1 + R2/R1
Similarly, analysis of the noninverting amplifier of Fig. 2.12, assuming a finite open-loop gain A, yields the closed-loop transfer function
Vo = 1+R2/R1 (2.54) Vi 1 + (1 + R2/R1)/A
Substituting for A from Eq. (2.42) and making the approximation A0 ≫ 1 + R2 /R1 results in Vo(s) ≃ 1+R2/R1 (2.55)
Vi(s) 1+ s ωt/(1+R2/R1)
Thus the noninverting amplifier has an STC low-pass response with a dc gain of (1 + R2 /R1 ) and a 3-dB frequency given also by Eq. (2.53).
Example 2.6
Consider an op amp with ft = 1 MHz. Find the 3-dB frequency of closed-loop amplifiers with nominal gains of +1000, +100, +10, +1, −1, −10, −100, and −1000. Sketch the magnitude frequency response for the amplifiers with closed-loop gains of +10 and −10.
Solution
We use Eq. (2.53) to obtain the results given in the following table.
Closed-Loop Gain R2/R1
+1000 999 +100 99 +10 9 + 1 0 − 1 1 −10 10 −100 100 −1000 1000
f3 dB =ft/(1 +R2/R1)
1 kHz 10 kHz 100 kHz 1 MHz 0.5 MHz 90.9 kHz 9.9 kHz ≃ 1 kHz
Figure 2.40 shows the frequency response for the amplifier whose nominal dc gain is +10 (20 dB), and Fig. 2.41 shows the frequency response for the –10 (also 20 dB) case. An interesting observation follows
2.7 Effect of Finite Open-Loop Gain and Bandwidth on Circuit Performance 109
fromthetableabove:Theunity-gaininvertingamplifierhasa3-dBfrequencyofft/2ascomparedtoft for the unity-gain noninverting amplifier (the unity-gain voltage follower).
Figure 2.40 Frequency response of an amplifier with a nominal gain of +10 V/V.
Figure 2.41 Frequency response of an amplifier with a nominal gain of −10 V/V.
The table in Example 2.6 above clearly illustrates the trade-off between gain and bandwidth: For a given op amp, the lower the closed-loop gain required, the wider the bandwidth achieved. Indeed, the noninverting configuration exhibits a constant gain–bandwidth product equal to ft of the op amp. An interpretation of these results in terms of feedback theory will be given in Chapter 11.
110 Chapter 2 Operational Amplifiers
EXERCISES
2.27 An internally compensated op amp has a dc open-loop gain of 106 V/V and an open-loop gain of 40 dB at 10 kHz. Estimate its 3-dB frequency, its unity-gain frequency, its gain–bandwidth product, and its expected gain at 1 kHz.
Ans. 1Hz;1MHz;1MHz;60dB
2.28 An op amp having a 106-dB gain at dc and a single-pole frequency response with ft = 2 MHz is used to design a noninverting amplifier with nominal dc gain of 100. Find the 3-dB frequency of the closed-loop gain.
Ans. 20 kHz
2.8 Large-Signal Operation of Op Amps
In this section, we study the limitations on the performance of op-amp circuits when large output signals are present.
2.8.1 Output Voltage Saturation
Similar to all other amplifiers, op amps operate linearly over a limited range of output voltages. Specifically, the op-amp output saturates in the manner shown in Fig. 1.14 with L+ and L− within 1 V or so of the positive and negative power supplies, respectively. Thus, an op amp that is operating from ±15-V supplies will saturate when the output voltage reaches about +13 V in the positive direction and –13 V in the negative direction. For this particular op amp the rated output voltage is said to be ±13 V. To avoid clipping off the peaks of the output waveform, and the resulting waveform distortion, the input signal must be kept correspondingly small.
2.8.2 Output Current Limits
Another limitation on the operation of op amps is that their output current is limited to a specified maximum. For instance, the popular 741 op amp is specified to have a maximum output current of ±20 mA. Thus, in designing closed-loop circuits utilizing the 741, the designer has to ensure that under no condition will the op amp be required to supply an output current, in either direction, exceeding 20 mA. This, of course, has to include both the current in the feedback circuit as well as the current supplied to a load resistor. If the circuit requires a larger current, the op-amp output voltage will saturate at the level corresponding to the maximum allowed output current.
2.8 Large-Signal Operation of Op Amps 111
Example 2.7
Consider the noninverting amplifier circuit shown in Fig. 2.42. As shown, the circuit is designed for a nominal gain (1 + R2 /R1 ) = 10 V/V. It is fed with a low-frequency sine-wave signal of peak voltage Vp and is connected to a load resistor RL . The op amp is specified to have output saturation voltages of ±13 V and output current limits of ±20 mA.
(a) For Vp = 1 V and RL = 1 k, specify the signal resulting at the output of the amplifier.
(b) For Vp = 1.5 V and RL = 1 k, specify the signal resulting at the output of the amplifier.
(c) For RL = 1 k, what is the maximum value of Vp for which an undistorted sine-wave output is
obtained?
(d) For Vp = 1 V, what is the lowest value of RL for which an undistorted sine-wave output is obtained?
R2 9 k
iO iF
vO
vO 0
15 V 13 V
1 k
R1
t
iL
Vp RL
(a)
0 t vI
13 V 15 V
Figure 2.42 (a) A noninverting amplifier with a nominal gain of 10 V/V designed using an op amp that saturates at ±13-V output voltage and has ±20-mA output current limits. (b) When the input sine wave has a peak of 1.5 V, the output is clipped off at ±13 V.
Solution
(a) For Vp =1V and RL =1k, the output will be a sine wave with peak value of 10 V. This is lower than output saturation levels of ±13 V, and thus the amplifier is not limited that way. Also, when the output is at its peak (10 V), the current in the load will be 10 V/1 k = 10 mA, and the current in the feedback network will be 10 V/(9 + 1) k = 1 mA, for a total op-amp output current of 11 mA, well under its limit of 20 mA.
(b) Now if Vp is increased to 1.5 V, ideally the output would be a sine wave of 15-V peak. The op amp, however, will saturate at ±13 V, thus clipping the sine-wave output at these levels. Let’s next check on the op-amp output current: At 13-V output and RL = 1 k, iL = 13 mA and iF = 1.3 mA; thus iO = 14.3 mA, again under the 20-mA limit. Thus the output will be a sine wave with its peaks clipped off at ±13 V, as shown in Fig. 2.42(b).
(c) For RL = 1 k, the maximum value of Vp for undistorted sine-wave output is 1.3 V. The output will be a 13-V peak sine wave, and the op-amp output current at the peaks will be 14.3 mA.
(b)
112
Chapter 2 Operational Amplifiers
Example 2.7 continued
(d) For Vp = 1 V and RL reduced, the lowest value possible for RL while the output is remaining an
undistorted sine wave of 10-V peak can be found from iOmax =20mA=10V+
10V
9 k + 1 k
which results in
2.8.3 Slew Rate
RLmin RLmin = 526
Another phenomenon that can cause nonlinear distortion when large output signals are present is slew-rate limiting. The name refers to the fact that there is a specific maximum rate of change possible at the output of a real op amp. This maximum is known as the slew rate (SR) of the op amp and is defined as
dv
SR = O (2.56)
dt max
and is usually specified on the op-amp data sheet in units of V/μs. It follows that if the input signal applied to an op-amp circuit is such that it demands an output response that is faster than the specified value of SR, the op amp will not comply. Rather, its output will change at the maximum possible rate, which is equal to its SR. As an example, consider an op amp connected in the unity-gain voltage-follower configuration shown in Fig. 2.43(a), and let the input signal be the step voltage shown in Fig. 2.43(b). The output of the op amp will not be able to rise instantaneously to the ideal value V; rather, the output will be the linear ramp of slope equal to SR, shown in Fig. 2.43(c). The amplifier is then said to be slewing, and its output is slew-rate limited.
In order to understand the origin of the slew-rate phenomenon, we need to know about the internal circuit of the op amp, and we will study it in Chapter 13. For the time being, however, it is sufficient to know about the phenomenon and to note that it is distinct from the finite op-amp bandwidth that limits the frequency response of the closed-loop amplifiers, studied in the previous section. The limited bandwidth is a linear phenomenon and does not result in a change in the shape of an input sinusoid; that is, it does not lead to nonlinear distortion. The slew-rate limitation, on the other hand, can cause nonlinear distortion to an input sinusoidal signal when its frequency and amplitude are such that the corresponding ideal output would require vO to change at a rate greater than SR. This is the origin of another related op-amp specification, its full-power bandwidth, to be explained later.
Before leaving the example in Fig. 2.43, however, we should point out that if the step input voltage V is sufficiently small, the output can be the exponentially rising ramp shown
v1
vO Slope SR
vO
V
2.8 Large-Signal Operation of Op Amps 113
0t (b)
V 0t
(c)
Slope tV SR
V
Figure2.43 (a)Unity-gainfollower.(b)Inputstepwaveform.(c)Linearlyrisingoutputwaveformobtained when the amplifier is slew-rate limited. (d) Exponentially rising output waveform obtained when V is sufficiently small so that the initial slope (ωt V ) is smaller than or equal to SR.
in Fig. 2.43(d). Such an output would be expected from the follower if the only limitation on its dynamic performance were the finite op-amp bandwidth. Specifically, the transfer function of the follower can be found by substituting R1 = ∞ and R2 = 0 in Eq. (2.55) to obtain
Vo = 1 (2.57) Vi 1 + s/ωt
which is a low-pass STC response with a time constant 1/ωt . Its step response would therefore be (see Appendix E)
vO(t)=V(1−e−ωtt) (2.58)
The initial slope of this exponentially rising function is (ωt V ). Thus, as long as V is sufficiently small so that ωt V ≤ SR, the output will be as in Fig. 2.43(d).
0t (d)
114 Chapter 2 Operational Amplifiers
EXERCISE
2.29 An op amp that has a slew rate of 1 V/μs and a unity-gain bandwidth ft of 1 MHz is connected in the unity-gain follower configuration. Find the largest possible input voltage step for which the output waveform will still be given by the exponential ramp of Eq. (2.58). For this input voltage, what is the 10% to 90% rise time of the output waveform? If an input step 10 times as large is applied, find the 10% to 90% rise time of the output waveform.
Ans. 0.16 V; 0.35 μs; 1.28 μs
2.8.4 Full-Power Bandwidth
Op-amp slew-rate limiting can cause nonlinear distortion in sinusoidal waveforms. Consider once more the unity-gain follower with a sine-wave input given by
vI =Vˆisinωt The rate of change of this waveform is given by
dvI =ωVˆicosωt dt
with a maximum value of ωVˆ i . This maximum occurs at the zero crossings of the input sinusoid. Now if ωVˆi exceeds the slew rate of the op amp, the output waveform will be distorted in the manner shown in Fig. 2.44. Observe that the output cannot keep up with the large rate of change of the sinusoid at its zero crossings, and the op amp slews.
Theop-ampdatasheetsusuallyspecifyafrequencyfM calledthefull-powerbandwidth. It is the frequency at which an output sinusoid with amplitude equal to the rated output voltage of the op amp begins to show distortion due to slew-rate limiting. If we denote the rated output
Figure 2.44 Effect of slew-rate limiting on output sinusoidal waveforms.
voltage Vomax, then fM is related to SR as follows: ωMVomax =SR
Thus,
fM = SR (2.59) 2π Vo max
ItshouldbeobviousthatoutputsinusoidsofamplitudessmallerthanVomax willshowslew-rate distortion at frequencies higher than ωM . In fact, at a frequency ω higher than ωM , the maximum amplitude of the undistorted output sinusoid is given by
ωM
Vo =Vomax ω (2.60)
EXERCISE
2.30 An op amp has a rated output voltage of ±10 V and a slew rate of 1 V/μs. What is its full-power bandwidth?Ifaninputsinusoidwithfrequencyf=5fM isappliedtoaunity-gainfollowerconstructed using this op amp, what is the maximum possible amplitude that can be accommodated at the output without incurring SR distortion?
Summary 115
Ans. 15.9 kHz; 2 V (peak)
Summary
The IC op amp is a versatile circuit building block. It is easy to apply, and the performance of op-amp circuits closely matches theoretical predictions.
The op-amp terminals are the inverting input terminal (1), the noninverting input terminal (2), the output terminal (3), the positive-supply terminal (4) to be connected to the positive power supply (VCC ), and the negative-supply terminal (5) to be connected to the negative supply (−VEE ). The common terminal of the two supplies is the circuit ground.
The ideal op amp responds only to the difference input signal, that is, (v2 −v1); it provides at the output, between terminal 3 and ground, a signal A(v 2 − v 1 ), where A, the open-loop gain, is very large (104 to 106) and ideally infinite; and it has an infinite input resistance and a zero output resistance. (See Table 2.1.)
Negative feedback is applied to an op amp by connecting a passive component between its output terminal and its inverting (negative) input terminal. Negative feedback
causes the voltage between the two input terminals to become very small and ideally zero. Correspondingly, a virtual short circuit is said to exist between the two input terminals. If the positive input terminal is connected to ground, a virtual ground appears on the negative input terminal.
The two most important assumptions in the analy- sis of op-amp circuits, presuming negative feedback exists and the op amps are ideal, are as follows: the two input terminals of the op amp are at the same voltage, and zero current flows into the op-amp input terminals.
With negative feedback applied and the loop closed, the closed-loop gain is almost entirely determined by external components: For the inverting configuration, Vo /Vi = −R2 /R1 ; and for the noninverting configuration, Vo/Vi =1+R2/R1.
The noninverting closed-loop configuration features a very high input resistance. A special case is the unity-gain
116 Chapter 2 Operational Amplifiers
follower, frequently employed as a buffer amplifier to
connect a high-resistance source to a low-resistance load.
The difference amplifier of Fig. 2.16 is designed with
R4/R3 =R2/R1,resultinginvO =(R2/R1)(vI2 −vI1).
The instrumentation amplifier of Fig. 2.20(b) is a
very popular circuit. It provides v O = (1 + R2 /R1 )(R4 /R3 ) (vI2 −vI1). It is usually designed with R3 =R4, and R1 and R2 selected to provide the required gain. If an adjustable gain is needed, part of R1 can be made variable.
The inverting Miller integrator of Fig. 2.24(a) is a popular circuit, frequently employed in analog signal-processing functions such as filters (Chapter 17) and oscillators (Chapter 18).
The input offset voltage, VOS, is the magnitude of dc voltage that when applied between the op-amp input terminals, with appropriate polarity, reduces the dc offset voltage at the output to zero.
The effect of VOS on performance can be evaluated by including in the analysis a dc source VOS in series with the op-amp positive input lead. For both the inverting and thenoninvertingconfigurations,VOS resultsinadcoffset voltage at the output of VOS (1 + R2 /R1 ).
Capacitively coupling an op amp reduces the dc offset voltage at the output considerably.
The average of the two dc currents, IB1 and IB2, that flow in the input terminals of the op amp, is called the
PROBLEMS
Computer Simulation Problems
Problems identified by the Multisim/PSpice icon are intended to demonstrate the value of using SPICE simulation to verify hand analysis and design, and to investigate important issues such as allowable signal swing and amplifier nonlinear distortion. Instructions to assist in setting up PSPice and Multisim simulations for all the indicated problems can be found in the corresponding files on the website. Note that if a particular parameter value is not specified
input bias current, IB. In a closed-loop amplifier, IB gives rise to a dc offset voltage at the output of magnitude IBR2. This voltage can be reduced to IOSR2 by connecting a resistance in series with the positive input terminal equal to the total dc resistance seen by the negative input terminal. IOS is the input offset current; that is, IOS = |IB1 − IB2 |.
Connecting a large resistance in parallel with the capacitor of an op-amp inverting integrator prevents op-amp saturation (due to the effect of VOS and IB).
For most internally compensated op amps, the open-loop gain falls off with frequency at a rate of −20 dB/decade, reaching unity at a frequency ft (the unity-gain band- width). Frequency ft is also known as the gain–bandwidth product of the op amp: ft = A0 fb, where A0 is the dc gain, and fb is the 3-dB frequency of the open-loop gain. At any frequencyf(f ≫fb),theop-ampgain|A|≃ft/f.
For both the inverting and the noninverting closed- loop configurations, the 3-dB frequency is equal to ft/(1+R2/R1).
The maximum rate at which the op-amp output voltage can change is called the slew rate. The slew rate, SR, is usually specified in V/μs. Op-amp slewing can result in nonlinear distortion of output signal waveforms.
The full-power bandwidth, fM , is the maximum frequency at which an output sinusoid with an amplitude equal to the op-amp rated output voltage (Vo max ) can be produced without distortion: fM = SR/2π Vo max .
in the problem statement, you are to make a reasonable assumption.
Section 2.1: The Ideal Op Amp
2.1 What is the minimum number of pins required for a so-called dual-op-amp IC package, one containing two op amps? What is the number of pins required for a so-called quad-op-amp package, one containing four op-amps?
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CHAPTER 2 PROBLEMS
2.2 The circuit of Fig. P2.2 uses an op amp that is ideal except for having a finite gain A. Measurements indicate vO = 4.0 V when vI = 1.0 V. What is the op-amp gain A?
Figure P2.2
2.3 Measurementofacircuitincorporatingwhatisthoughtto be an ideal op amp shows the voltage at the op-amp output to be −2.000 V and that at the negative input to be −1.000 V. For the amplifier to be ideal, what would you expect the voltage at the positive input to be? If the measured voltage at the positive input is −1.005 V, what is likely to be the actual gain of the amplifier?
2.4 A set of experiments is run on an op amp that is ideal except for having a finite gain A. The results are tabulated below. Are the results consistent? If not, are they reasonable, in view of the possibility of experimental error? What do they show the gain to be? Using this value, predict values of the measurements that were accidentally omitted (the blank entries).
For equal transconductances Gm and a transresistance Rm , find an expression for the open-loop gain A. For Gm = 40 mA/V andRm=1×106,whatvalueofAresults?
2.6 The two wires leading from the output terminals of a transducer pick up an interference signal that is a 60-Hz, 2-V sinusoid. The output signal of the transducer is sinusoidal of 5-mV amplitude and 1000-Hz frequency. Give expressions for vcm,vd, and the total signal between each wire and the system ground.
2.7 Nonideal (i.e., real) operational amplifiers respond to both the differential and common-mode components of their input signals (refer to Fig. 2.4 for signal representation). Thus the output voltage of the op amp can be expressed as
vO =AdvId +AcmvIcm
where Ad is the differential gain (referred to simply as A in the text) and Acm is the common-mode gain (assumed to be zero in the text). The op amp’s effectiveness in rejecting common-mode signals is measured by its CMRR, defined as
A CMRR=20log d
Acm
Consider an op amp whose internal structure is of the type shown in Fig. E2.3 except for a mismatch Gm between the transconductances of the two channels; that is,
Gm1 = Gm − 1 Gm 2
G =G +1G m2 m 2 m
Problems 117
Experiment # v1
1 0.00
2 1.00
3 1.00 1.00
expressions
for Ad , Acm , and CMRR. What
is the
4 1.00 5 2.01 6 1.99 7 5.10
1.10 10.1
2.5 Refer to Exercise 2.3. This problem explores an alter- native internal structure for the op amp. In particular, we wish to model the internal structure of a particular op amp using two transconductance amplifiers and one transresistance amplifier. Suggest an appropriate topology.
v2
vO
0.00 0.00 1.00 0.00
2.00 2.00
−0.99 1.00 −5.10
Find
maximum permitted percentage mismatch between the two Gm values if a minimum CMRR of 60 dB is required?
Section 2.2: The Inverting Configuration
2.8 Assuming ideal op amps, find the voltage gain v o /v i and input resistance Rin of each of the circuits in Fig. P2.8.
2.9 A particular inverting circuit uses an ideal op amp and two 10-k resistors. What closed-loop gain would you expect? If a dc voltage of +1.00 V is applied at the input, what outputs result? If the 10-k resistors are said to be “1% resistors,” having values somewhere in the range (1 ± 0.01) times the nominal value, what range of outputs would you expect to actually measure for an input of precisely 1.00 V?
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118 Chapter 2 Operational Amplifiers
20 k
20 k
(a)
(c)
(b)
20 k
CHAPTER 2 PROBLEMS
20 k 20 k
Figure P2.8
20 k
2.10 You are provided with an ideal op amp and three 10-k resistors. Using series and parallel resistor combinations, how many different inverting-amplifier circuit topologies are possible? What is the largest (noninfinite) available voltage gain magnitude? What is the smallest (nonzero) available gain magnitude? What are the input resistances in these two cases?
2.11 For ideal op amps operating with the following feedback networks in the inverting configuration, what closed-loop gain results?
(a) R1 =10k,R2 =10k (b) R1 =10k,R2 =100k (c) R1 =10k,R2 =1k (d) R1 =100k,R2 =10M (e) R1 =100k,R2 =1M
D 2.12 Given an ideal op amp, what are the values of the resistors R1 and R2 to be used to design amplifiers with the closed-loop gains listed below? In your designs, use at least one 10-k resistor and another equal or larger resistor.
(a) −1 V/V (b) −2 V/V
D2.13 Designaninvertingop-ampcircuitforwhichthegain is −10 V/V and the total resistance used is 110 k.
D2.14 UsingthecircuitofFig.2.5andassuminganidealop amp, design an inverting amplifier with a gain of 46 dB having the largest possible input resistance under the constraint of having to use resistors no larger than 1 M. What is the input resistance of your design?
2.15 AnidealopampisconnectedasshowninFig.2.5with R1 = 10 k and R2 = 100 k. A symmetrical square-wave signal with levels of 0 V and −1 V is applied at the input. Sketch and clearly label the waveform of the resulting output voltage. What is its average value? What is its highest value? What is its lowest value?
2.16 ForthecircuitinFig.P2.16,assuminganidealopamp, find the currents through all branches and the voltages at all nodes. Since the current supplied by the op amp is greater than the current drawn from the input signal source, where does the additional current come from?
20 k
(c) −5 V/V (d) −100 V/V
(d)
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Problems 119
CHAPTER 2 PROBLEMS
1 k
10 k
voltage ranges from −10 V to +10 V, what is the maximum voltage by which the “virtual ground node” departs from its ideal value?
2.22 The circuit in Fig. P2.22 is frequently used to provide an output voltage v o proportional to an input signal current ii .
vi
Figure P2.22
Derive expressions for the transresistance Rm ≡ vo/ii and the input resistance Ri ≡ v i /ii for the following cases:
(a) A is infinite. (b) A is finite.
2.23 Showthatfortheinvertingamplifieriftheop-ampgain is A, the input resistance is given by
R2 Rin = R1 + A + 1
2.24 For an inverting amplifier with nominal closed-loop gain R2 /R1 , find the minimum value that the op-amp open-loop gain A must have (in terms of R2 /R1 ) so that the gain error (due to the finite A) is limited to 0.1%, 1%, and 10%. In each case find the value of a resistor RIa such that when it is placed in shunt with R1, the gain is restored to its nominal value.
*2.25 Figure P2.25 shows an op amp that is ideal except for having a finite open-loop gain and is used to realize an inverting amplifier whose gain has a nominal magnitude G = R2/R1. To compensate for the gain reduction due to
1 V Figure P2.16
2 k
2.17 An inverting op-amp circuit is fabricated with the resistorsR1 andR2 havingx%tolerance(i.e.,thevalueofeach resistance can deviate from the nominal value by as much as ±x%). What is the tolerance on the realized closed-loop gain? Assume the op amp to be ideal. If the nominal closed-loop gain is −100 V/V and x = 1, what is the range of gain values expected from such a circuit?
2.18 Anidealopampwith5-kand15-kresistorsisused to create a +5-V supply from a −15-V reference. Sketch the circuit. What are the voltages at the ends of the 5-k resistor? If these resistors are so-called 1% resistors, whose actual values are the range bounded by the nominal value ±1%, what are the limits of the output voltage produced? If the −15-V supply can also vary by ±1%, what is the range of the output voltages that might be found?
2.19 Aninvertingop-ampcircuitforwhichtherequiredgain is −50 V/V uses an op amp whose open-loop gain is only 500 V/V. If the larger resistor used is 100 k, to what must the smaller be adjusted? With what resistor must a 2-k resistor connected to the input be shunted to achieve this goal? (Note that a resistor Ra is said to be shunted by resistor Rb when Rb is placed in parallel with Ra.)
v
o
D 2.20 (a) Design an inverting amplifier with a closed-loop
gain of −200 V/V and an input resistance of 1 k.
(b) If the op amp is known to have an open-loop gain of 5000
V/V, what do you expect the closed-loop gain of your circuit Rc to be (assuming the resistors have precise values)?
R2
(c) Give the value of a resistor you can place in parallel
(shunt) with R1 to restore the closed-loop gain to its R1
nominal value. Use the closest standard 1% resistor value (see Appendix J).
2.21 Anopampwithanopen-loopgainof5000V/Visused
in the inverting configuration. If in this application the output Figure P2.25
Vi
Vo
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
120 Chapter 2 Operational Amplifiers
the finite A, a resistor Rc is shunted across R1. Show that perfect compensation is achieved when Rc is selected according to
Rc =A−G R1 1+G
D *2.26 (a) Use Eq. (2.5) to obtain the amplifier open-loop gain A required to realize a specified closed-loop gain (Gnominal = −R2 /R1 ) within a specified gain error e,
G − G e ≡ nominal
Gnominal
(b) Design an inverting amplifer for a nominal closed-loop gain of −100, an input resistance of 1 k, and a gain error of ≤10%. Specify R1, R2, and the minimum A required.
*2.27 (a) Use Eq. (2.5) to show that a reduction A in the op-amp gain A gives rise to a reduction |G| in the magnitude of the closed-loop gain G with |G| and A related by
|G|/|G| ≃ 1+R2/R1 A/A A
R A Assume that 1 + 2 ≪ A and ≪ 1.
D 2.29 An inverting op-amp circuit using an ideal op amp must be designed to have a gain of −500 V/V using resistors no larger than 100 k.
(a) For the simple two-resistor circuit, what input resistance would result?
(b) If the circuit in Fig. 2.8 is used with three resistors of maximum value, what input resistance results? What is the value of the smallest resistor needed?
2.30 The inverting circuit with the T network in the feedback is redrawn in Fig. P2.30 in a way that emphasizes the observation that R2 and R3 in effect are in parallel (because the ideal op amp forces a virtual ground at the inverting input terminal). Use this observation to derive an expression for the gain (vO/vI ) by first finding (vX /vI ) and (vO/vX ). For the latter usethevoltage-dividerruleappliedtoR4 and(R2∥R3).
CHAPTER 2 PROBLEMS
R2 vX R4 R3
iI
v
Figure P2.30
R1 A I
(b) If in a closed-loop amplifier with a nominal gain (i.e., R2/R1) of 100, A decreases by 10%, what is the minimum nominal A required to limit the percentage change in |G| to 0.1%?
2.28 Consider the circuit in Fig. 2.8 with R1 = R2 = R4 = 1 M, and assume the op amp to be ideal. Find values for R3 to obtain the following gains:
R1 0 V
vO
(a) −100 V/V (b) −10 V/V (c) −2 V/V
*2.31 The circuit in Fig. P2.31 can be considered to be an extension of the circuit in Fig. 2.8.
(a) Find the resistances looking into node 1, R1; node 2, R2; node 3, R3; and node 4, R4.
R/2 4
R1 R
I1 I2 I3 I4
2
0V
1
Ideal
R 1
R/2 2
R/2 3
I
Figure P2.31
R2 R
R3 R R4
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CHAPTER 2 PROBLEMS
(b) Find the currents I1, I2, I3, and I4, in terms of the input current I.
(c) Find the voltages at nodes 1, 2, 3, and 4, that is, V1, V2, V3, and V4 in terms of (IR).
2.32 The circuit in Fig. P2.32 utilizes an ideal op amp.
iL RL
R
10 kV
2 1
Figure P2.34
D 2.35 Design the circuit shown in Fig. P2.35 to have an input resistance of 100 k and a gain that can be varied from −1 V/V to −100 V/V using the 100-k potentiometer R4. What voltage gain results when the potentiometer is set exactly at its middle value?
Problems 121
iI
(a) Find I1, I2, I3, IL, and Vx.
(b) If VO is not to be lower than −13 V, find the maximum
allowed value for RL .
(c) IfRL isvariedintherange100to1k,whatisthe
vO
corresponding change in IL and in VO?
I2 10kV VX RL IL
100 V
I1 10 kV
1V
Figure P2.32
I3 2
1
VO
R3
vO
R2
R4
D 2.33 Use the circuit in Fig. P2.32 as an inspiration to design a circuit that supplies a constant current IL of 3.1 mA to a variable resistance RL. Assume the availability of a 1.5-V battery and design so that the current drawn from the battery is 0.1 mA. For the smallest resistance in the circuit, use 500 . If the op amp saturates at ±10 V, what is the maximum value that RL can have while the current source supplying it operates properly?
D 2.34 Assuming the op amp to be ideal, it is required to design the circuit shown in Fig. P2.34 to implement a current amplifierwithgainiL/iI =11A/A.
(a) Find the required value for R.
(b) Whataretheinputandtheoutputresistanceofthiscurrent
amplifier?
(c) If RL = 1 k and the op amp operates in an ideal manner
aslongasvO isintherange±12V,whatrangeofiI is
possible?
(d) If the amplifier is fed with a current source having a
R1
vI 2
1
Figure P2.35
2.36 A weighted summer circuit using an ideal op amp has three inputs using 10-k resistors and a feedback resistor of 50 k. A signal v1 is connected to two of the inputs while a signal v2 is connected to the third. Express vO in terms of v1 andv2.Ifv1 =1Vandv2 =−1V,whatisvO?
D 2.37 Design an op-amp circuit to provide an output v O = −[2v 1 + (v 2 /2)]. Choose relatively low values of resistors but ones for which the input current (from each input signal source) does not exceed 50 μA for 1-V input signals.
D 2.38 Use the scheme illustrated in Fig. 2.10 to design an op-amp circuit with inputs v1, v2, and v3, whose output is
current of 0.2 mA and a source resistance of 10 k, find iL .
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122 Chapter 2 Operational Amplifiers
vO = −(2v1+ 4v2+ 8v3) using small resistors but no smaller
than 1 k.
D2.39 Anidealopampisconnectedintheweightedsummer configurationofFig.2.10.ThefeedbackresistorRf =100k, and six 100-k resistors are connected to the inverting input terminal of the op amp. Show, by sketching the various circuit configurations, how this basic circuit can be used to implement the following functions:
(a) vO =–(v1 +2v2 +3v3)
(b) vO =–(v1 +v2 +2v3 +2v4) (c) vO =–(v1 +5v2)
(d) vO =–6v1
In each case find the input resistance seen by each of the signal sources supplying v1, v2, v3, and v4. Suggest at least two additional summing functions that you can realize with this circuit. How would you realize a summing coefficient that is 0.5?
D2.40 Giveacircuit,completewithcomponentvalues,fora weighted summer that shifts the dc level of a sine-wave signal of 3 sin(ωt) V from zero to −3 V. Assume that in addition to the sine-wave signal you have a dc reference voltage of 1.5 V available. Sketch the output signal waveform.
D2.41 Usetwoidealopampsandresistorstoimplementthe summing function
vO =v1 +2v2 –3v3 –5v4
D 2.42 In an instrumentation system, there is a need to take the difference between two signals, one of v1 = 2 sin(2π × 60t) + 0.01 sin(2π × 1000t) volts and another of v2 = 2 sin(2π × 60t) − 0.01 sin(2π × 1000t) volts. Draw a circuit that finds the required difference using two op amps and mainly 100-k resistors. Since it is desirable to amplify the 1000-Hz component in the process, arrange to provide an overall gain of 100 as well. The op amps available are ideal except that their output voltage swing is limited to ±10 V.
*2.43 Figure P2.43 shows a circuit for a digital-to-analog converter (DAC). The circuit accepts a 4-bit input binary word a3a2a1a0, where a0, a1, a2, and a3 take the values of 0 or 1, and it provides an analog output voltage vO proportional to the value of the digital input. Each of the bits of the input word controls the correspondingly numbered switch. For instance, if a2 is 0 then switch S2 connects the 20-k resistor to ground, while if a2 is 1 then S2 connects the 20-k resistor to the +5-V
power supply. Show that vO is given by
vO =−Rf [20a0 +21a1 +22a2 +23a3]
16
is in kilohms. Find the value of R so that v ranges
where R
from 0 to −12 volts.
ffO
CHAPTER 2 PROBLEMS
Figure P2.43
Section 2.3: The Noninverting Configuration
D 2.44 Given an ideal op amp to implement designs for the following closed-loop gains, what values of resistors (R1, R2) should be used? Where possible, use at least one 10-k resistor as the smallest resistor in your design.
(a) +1 V/V (b) +2 V/V (c) +21 V/V (d) +100 V/V
D 2.45 Design a circuit based on the topology of the noninverting amplifier to obtain a gain of +1.5 V/V, using only 10-k resistors. Note that there are two possibilities. Which of these can be easily converted to have a gain of
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Problems 123
CHAPTER 2 PROBLEMS
either +1.0 V/V or +2.0 V/V simply by short-circuiting a single resistor in each case?
D 2.46 Figure P2.46 shows a circuit for an analog voltmeter of very high input resistance that uses an inexpensive moving-coil meter. The voltmeter measures the voltage V applied between the op amp’s positive-input terminal and ground. Assuming that the moving coil produces full-scale deflection when the current passing through it is 100 μA, find the value of R such that a full-scale reading is obtained when V is +10 V. Does the meter resistance shown affect the voltmeter calibration?
RP0
Figure P2.47
Figure P2.46
R2
vO
V
D *2.48 Design a circuit, using one ideal op amp, whose outputisvO =vI1 +2vI2 −9vI3 +4vI4.(Hint:Useastructure similar to that shown in general form in Fig. P2.47.)
2.49 Derive an expression for the voltage gain, vO/vI , of the circuit in Fig. P2.49.
R1
D *2.47 (a) Use superposition to show that the output of the circuit in Fig. P2.47 is given by
R3 RRR vR4
f v + f v +···+ f v N1 N2 Nn
I
Figure P2.49
v =
ORN1RN2 RNn
RRR R +1+ f PvP1+ PvP2+···+ PvPn
RNRP1RP2 RPn whereRN =RN1∥RN2∥···∥RNn, and
RP = RP1 ∥RP2 ∥ ··· ∥RPn ∥RP0
(b) Design a circuit to obtain
vO =–4vN1 +vP1 +3vP2
findvO.
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The smallest resistor used should be 10 k.
2.50 For the circuit in Fig. P2.50, use superposition to find v in terms of the input voltages v and v . Assume an ideal
O12 op amp. For
v1 =10sin(2π×60t)−0.1sin(2π×1000t), volts v2 =10sin(2π×60t)+0.1sin(2π×1000t), volts
124 Chapter 2
Operational Amplifiers
10R
10R
In each case find the load current and the current supplied by the source. Where does the load current come from in case (b)?
2.54 Deriveanexpressionforthegainofthevoltagefollower of Fig. 2.14, assuming the op amp to be ideal except for having a finite gain A. Calculate the value of the closed-loop gain for A = 1000, 100, and 10. In each case find the percentage error in gain magnitude from the nominal value of unity.
2.55 Complete the following table for feedback amplifiers created using one ideal op amp. Note that Rin signifies input resistance and R1 and R2 are feedback-network resistors as labeled in the inverting and noninverting configurations.
CHAPTER 2 PROBLEMS
Figure P2.50
D 2.51 The circuit shown in Fig. P2.51 utilizes a 10-k potentiometer to realize an adjustable-gain amplifier. Derive an expression for the gain as a function of the potentiometer setting x. Assume the op amp to be ideal. What is the range of gains obtained? Show how to add a fixed resistor so that the gain range can be 1 to 11 V/V. What should the resistor value be?
Figure P2.51
D 2.52 Given the availability of resistors of value 1 k and 10 k only, design a circuit based on the noninverting configuration to realize a gain of +10 V/V. What is the input resistance of your amplifier?
2.53 It is required to connect a 10-V source with a source resistance of 1 M to a 1-k load. Find the voltage that will appear across the load if:
(a) The source is connected directly to the load.
(b) A unity-gain op-amp buffer is inserted between the source
and the load.
Case
a b c d e f g
Gain
−10 V/V −1 V/V −2 V/V +1 V/V +2 V/V +11 V/V −0.5 V/V
Rin 10 k
∞
20 k
R1 R2 100 k
200 k 100 k
100 k
D 2.56 A noninverting op-amp circuit with nominal gain of 10 V/V uses an op amp with open-loop gain of 100 V/V and a lowest-value resistor of 10k. What closed-loop gain actually results? With what value resistor can which resistor be shunted to achieve the nominal gain? If in the manufacturing process, an op amp of gain 200 V/V were used, what closed-loop gain would result in each case (the uncompensated one, and the compensated one)?
2.57 Use Eq. (2.11) to show that if the reduction in the closed-loop gain G from the nominal value G0 = 1 + R2 /R1 is to be kept less than x% of G0, then the open-loop gain of the opampmustexceedG0 byatleastafactorF=(100/x)−1≃ 100/x. Find the required F for x = 0.01, 0.1, 1, and 10. Utilize these results to find for each value of x the minimum required open-loop gain to obtain closed-loop gains of 1, 10, 102, 103, and 104 V/V.
2.58 For each of the following combinations of op-amp open-loop gain A and nominal closed-loop gain G0 , calculate the actual closed-loop gain G that is achieved. Also, calculate the percentage by which |G| falls short of the nominal gain magnitude |G0 |.
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Problems 125
CHAPTER 2 PROBLEMS
Case G0 (V/V) A (V/V)
a −1 10
b +1 10
c −1 100
d +10 10
e −10 100
f −10 1000
g +12
2.59 Figure P2.59 shows a circuit that provides an output voltage vO whose value can be varied by turning the wiper of the 100-k potentiometer. Find the range over which vO can be varied. If the potentiometer is a “20-turn” device, find the change in vO corresponding to each turn of the pot.
25
25
Figure P2.59
Section 2.4: Difference Amplifiers
2.60 Find the voltage gain vO/vId for the difference amplifier
of Fig. 2.16 for the case R1 =R3 =5k and R2 =R4 =
100 k. What is the differential input resistance Rid ? If the
two key resistance ratios (R /R ) and (R /R ) are different 21 43
from each other by 1%, what do you expect the common-mode gain Acm to be? Also, find the CMRR in this case. Neglect the effect of the ratio mismatch on the value of Ad .
D 2.61 Using the difference amplifier configuration of Fig. 2.16 and assuming an ideal op amp, design the circuit to provide the following differential gains. In each case, the differential input resistance should be 20 k.
(a) 1 V/V (b) 5 V/V (c) 100 V/V (d) 0.5 V/V
2.62 For the circuit shown in Fig. P2.62, express vO as a function of v 1 and v 2 . What is the input resistance seen by v 1 alone? By v2 alone? By a source connected between the two input terminals? By a source connected to both input terminals simultaneously?
Figure P2.62
2.63 Consider the difference amplifier of Fig. 2.16 with the two input terminals connected together to an input common-mode signal source. For R2/R1 = R4/R3, show that the input common-mode resistance is (R3 + R4 ) ∥ (R1 + R2 ).
2.64 Consider the circuit of Fig. 2.16, and let each of the v I 1 and v I 2 signal sources have a series resistance Rs . What condition must apply in addition to the condition in Eq. (2.15) in order for the amplifier to function as an ideal difference amplifier?
*2.65 For the difference amplifier shown in Fig. P2.62, let all the resistors be 10 k ± x%. Find an expression for the worst-case common-mode gain that results. Evaluate this for x = 0.1, 1, and 5. Also, evaluate the resulting CMRR in each case. Neglect the effect of resistor tolerances on Ad .
2.66 For the difference amplifier of Fig. 2.16, show that if each resistor has a tolerance of ±100e% (i.e., for, say, a 5% resistor, e = 0.05) then the worst-case CMRR is given approximately by
K+1 CMRR ≃ 20 log 4e
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126 Chapter 2 Operational Amplifiers
where K is the nominal (ideal) value of the ratios (R2 /R1 ) and (R4/R3). Calculate the value of worst-case CMRR for an amplifier designed to have a differential gain of ideally 100 V/V, assuming that the op amp is ideal and that 1% resistors are used. What resistor tolerance is needed if a CMRR of 80 dB is required?
D *2.67 Design the difference amplifier circuit of Fig. 2.16
to realize a differential gain of 1000, a differential input
resistance of 2 k, and a minimum CMRR of 88 dB. Assume and R6, such that (R5 + R6) ≤ R/100. the op amp to be ideal. Specify both the resistor values and
their required tolerance (e.g., better than x%).
β ≃ R6 |(R5 + R6 ). Show that the differential gain is given by Ad≡vO= 1
vId 1−β
Design the circuit to obtain a differential gain of 10 V/V and
(Hint: Use superposition.)
differential input resistance of 2 M. Select values for R, R5,
v1
vId
RR
CHAPTER 2 PROBLEMS
*2.68 (a) Find Ad and Acm for the difference amplifier circuit shown in Fig. P2.68.
(b) If the op amp is specified to operate properly as long
as the common-mode voltage at its positive and negative inputs falls in the range ±2.5 V, what is the corresponding limitation on the range of the input common-mode signal v Icm ?
(This is known as the common-mode range of the differential v2 amplifier.)
R5
R6
vO bvO
RR
(c) The circuit is modified by connecting a 10-k resistor between node A and ground, and another 10-k resistor between node B and ground. What will now be the values of Ad , Acm , and the input common-mode range?
100 k
Figure P2.69
100 k
vI1
*2.70 Figure P2.70 shows a modified version of the differ- ence amplifier. The modified circuit includes a resistor RG, which can be used to vary the gain. Show that the differential voltage gain is given by
vO =−2R2 1+R2 vId R1 RG
(Hint: The virtual short circuit at the op-amp input causes the current through the R1 resistors to be vId/2R1).
vId
Figure P2.70
A vO vI2 B
100 k
100 k
Figure P2.68
D *2.69 To obtain a high-gain, high-input-resistance differ- ence amplifier, the circuit in Fig. P2.69 employs positive feedback, in addition to the negative feedback provided by the resistor R connected from the output to the negative input of the op amp. Specifically, a voltage divider (R5 , R6 ) connected across the output feeds a fraction β of the output, that is, a voltage βvO, back to the positive-input terminal of the op amp through a resistor R. Assume that R5 and R6 are much smaller than R so that the current through R is much lower than the current in the voltage divider, with the result that
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CHAPTER 2 PROBLEMS
D *2.71 The circuit shown in Fig. P2.71 is a representation of a versatile, commercially available IC, the INA105, manu- factured by Burr-Brown and known as a differential amplifier module. It consists of an op amp and precision, laser-trimmed, metal-film resistors. The circuit can be configured for a variety of applications by the appropriate connection of terminals A, B, C, D, and O.
(a) Show how the circuit can be used to implement a difference amplifier of unity gain.
(b) Show how the circuit can be used to implement single-ended amplifiers with gains:
(i) −1 V/V (ii) +1 V/V (iii) +2 V/V
(iv) +1/2 V/V
Avoid leaving a terminal open-circuited, for such a terminal may act as an “antenna,” picking up interference and noise through capacitive coupling. Rather, find a convenient node to connect such a terminal in a redundant way. When more than one circuit implementation is possible, comment on the rel- ative merits of each, taking into account such considerations as dependence on component matching and input resistance.
25 k 25 k AC
2.74 (a) Expressing v I 1 and v I 2 in terms of differential and
common-mode components, find v O1 and v O2 in the circuit
in Fig. 2.20(a) and hence find their differential component
v − v and their common-mode component 1 (v + v ). O2 O1 2 O1 O2
Now find the differential gain and the common-mode gain of the first stage of this instrumentation amplifier and hence the CMRR.
(b) Repeat for the circuit in Fig. 2.20(b), and comment on the difference between the two circuits.
*2.75 For an instrumentation amplifier of the type shown in Fig. 2.20(b), a designer proposes to make R2 = R3 = R4 = 100 k, and 2R1 = 10 k. For ideal components, what difference-mode gain, common-mode gain, and CMRR result? Reevaluate the worst-case values for these for the situation in which all resistors are specified as ±1% units. Repeat the latter analysis for the case in which 2R1 is reduced to 1 k. What do you conclude about the effect of the gain of the first stage on CMRR? (Hint: Eq. (2.19) can be used to evaluate Acm of the second stage.)
D 2.76 Design the instrumentation-amplifier circuit of Fig. 2.20(b) to realize a differential gain, variable in the range 2 to 100, utilizing a 100-k pot as variable resistor.
*2.77 The circuit shown in Fig. P2.77 is intended to supply a voltage to floating loads (those for which both terminals are ungrounded) while making greatest possible use of the available power supply.
Problems 127
O
BD 25 k 25 k
Figure P2.71
2.72 Consider the instrumentation amplifier of Fig. 2.20(b) with a common-mode input voltage of +3 V (dc) and a differential input signal of 100-mV peak sine wave. Let 2R1 =2k,R2 =50k,R3 =R4 =10k.Findthevoltage at every node in the circuit.
2.73 (a) Consider the instrumentation amplifier circuit of Fig. 2.20(a). If the op amps are ideal except that their outputs saturate at ±12 V, in the manner shown in Fig. 1.14, find the maximum allowed input common-mode signal for the case R1 =1kandR2 =100k.
(b) Repeat (a) for the circuit in Fig. 2.20(b), and comment on the difference between the two circuits.
20 k
30 k
Figure P2.77
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128 Chapter 2 Operational Amplifiers
(a) Assuming ideal op amps, sketch the voltage waveforms at nodes B and C for a 1-V peak-to-peak sine wave applied at A. Also sketch v O .
(b) What is the voltage gain vO/vI ?
(c) Assuming that the op amps operate from ±15-V power
supplies and that their output saturates at ±14 V (in the manner shown in Fig. 1.14), what is the largest sine-wave output that can be accommodated? Specify both its peak-to-peak and rms values.
*2.78 ThetwocircuitsinFig.P2.78areintendedtofunction as voltage-to-current converters; that is, they supply the load impedance ZL with a current proportional to vI and independent of the value of ZL . Show that this is indeed the case,andfindforeachcircuitiO asafunctionofvI.Comment on the differences between the two circuits.
Section 2.5: Integrators and Differentiators
2.79 A Miller integrator incorporates an ideal op amp, a resistor R of 10 k, and a capacitor C of 1 nF. A sine-wave signal is applied to its input.
(a) At what frequency (in Hz) are the input and output signals equal in amplitude?
(b) At that frequency, how does the phase of the output sine wave relate to that of the input?
(c) If the frequency is lowered by a factor of 10 from that found in (a), by what factor does the output voltage change, and in what direction (smaller or larger)?
(d) What is the phase relation between the input and output in situation (c)?
D2.80 DesignaMillerintegratorwithatimeconstantof1s and an input resistance of 100 k. A dc voltage of −1 volt is applied at the input at time 0, at which moment vO = −10 V. How long does it take the output to reach 0 V? +10 V?
2.81 An op-amp-based inverting integrator is measured at 10 kHz to have a voltage gain of −100 V/V. At what frequency is its gain reduced to −1 V/V? What is the integrator time constant?
D 2.82 Design a Miller integrator that has a unity-gain frequency of 10 krad/s and an input resistance of 100 k. Sketch the output you would expect for the situation in which, with output initially at 0 V, a 2-V, 100-μs pulse is applied to the input. Characterize the output that results when a sine wave 2 sin 104 t is applied to the input.
D 2.83 Design a Miller integrator whose input resistance is 10 k and unity-gain frequency is 100 kHz. What components are needed? For long-term stability, a feedback resistor is introduced across the capacitor to limit the dc gain
CHAPTER 2 PROBLEMS
R1
R1
ZL vI
vR iO
I R1R1
R
(a) (b)
Figure P2.78
Z iO L
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CHAPTER 2 PROBLEMS
to 40 dB. What is its value? What is the associated lower 3-dB frequency? Sketch and label the output that results with a 10-μs, 1-V positive-input pulse (initially at 0 V) with (a) no dc stabilization (but with the output initially at 0 V) and (b) the feedback resistor connected.
*2.84 A Miller integrator whose input and output voltages are initially zero and whose time constant is 1 ms is driven by the signal shown in Fig. P2.84. Sketch and label the output waveform that results. Indicate what happens if the input levels are ±2 V, with the time constant the same (1 ms) and with the time constant raised to 2 ms.
Figure P2.84
2.85 Consider a Miller integrator having a time constant of 1 ms and an output that is initially zero, when fed with a string of pulses of 10-μs duration and 1-V amplitude rising from 0 V (see Fig. P2.85). Sketch and label the output waveform resulting. How many pulses are required for an output voltage change of 1 V?
Problems 129 low-pass active filter. Derive the transfer function and
show that the dc gain is (−R2 /R1 ) and the 3-dB frequency ω0 = 1/CR2 . Design the circuit to obtain an input resistance of 10k,adcgainof40dB,anda3-dBfrequencyof1kHz.At what frequency does the magnitude of the transfer function reduce to unity?
Vo
Figure P2.86
*2.87 Show that a Miller integrator implemented with an op amp with open-loop gain A0 has a low-pass STC transfer function. What is the pole frequency of the STC function? How does this compare with the pole frequency of the ideal integrator? If an ideal Miller integrator is fed with a −1-V pulse signal with a width T = CR, what will the output voltage beatt=T?Assumethatatt=0,vO =0.Repeatforan integrator with an op amp having A0 = 1000.
2.88 A differentiator utilizes an ideal op amp, a 10-k resistor, and a 1-nF capacitor. What is the frequency f0 (in Hz) at which its input and output sine-wave signals have equal magnitude? What is the output signal for a 1-V peak-to-peak sine-wave input with frequency equal to 10f0?
2.89 An op-amp differentiator with 1-ms time constant is driven by the rate-controlled step shown in Fig. P2.89. Assuming vO to be zero initially, sketch and label its waveform.
0.2
Figure P2.89
Figure P2.85
D2.86 FigureP2.86showsacircuitthatperformsalow-pass STC function. Such a circuit is known as a first-order,
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130 Chapter 2 Operational Amplifiers
2.90 An op-amp differentiator, employing the circuit shown in Fig. 2.27(a), has R = 20k and C = 0.1μF. When a triangle wave of ±1-V peak amplitude at 1 kHz is applied to the input, what form of output results? What is its frequency? What is its peak amplitude? What is its average value? What value of R is needed to cause the output to have a 12-V peak amplitude?
2.91 Use an ideal op amp to design a differentiation circuit for which the time constant is 10−3 s using a 10-nF capacitor. What are the gains and phase shifts found for this circuit at one-tenth and 10 times the unity-gain frequency? A series input resistor is added to limit the gain magnitude at high frequencies to 100 V/V. What is the associated 3-dB frequency? What gain and phase shift result at 10 times the unity-gain frequency?
D 2.92 Figure P2.92 shows a circuit that performs the high-pass, single-time-constant function. Such a circuit is known as a first-order high-pass active filter. Derive the transfer function and show that the high-frequency gain is (−R2/R1) and the 3-dB frequency ω0 = 1/CR1. Design the circuit to obtain a high-frequency input resistance of 1 k, a high-frequency gain of 40 dB, and a 3-dB frequency of 2 kHz. At what frequency does the magnitude of the transfer function reduce to unity?
Vo
Figure P2.92
D **2.93 Derive the transfer function of the circuit in Fig. P2.93 (for an ideal op amp) and show that it can be written in the form
for the transfer function in the following frequency regions:
(a) ω≪ω1
(b) ω1 ≪ω≪ω2 (c) ω≫ω2
CHAPTER 2 PROBLEMS
Figure P2.93
Vo
Vo = Vi
−R2/R1
[1 + (ω1 /jω)][1 + j(ω/ω2 )]
Use these approximations to sketch a Bode plot for the magnitude response. Observe that the circuit performs as an amplifier whose gain rolls off at the low-frequency end in the manner of a high-pass STC network, and at the high-frequency end in the manner of a low-pass STC network. Design the circuit to provide a gain of 40 dB in the “middle-frequency range,” a low-frequency 3-dB point at 200 Hz, a high-frequency 3-dB point at 200 kHz, and an input resistance (at ω ≫ ω1) of 2 k.
Section 2.6: DC Imperfections
2.94 An op amp wired in the inverting configuration with the input grounded, having R2 = 100 k and R1 = 2 k, has an output dc voltage of −0.2 V. If the input bias current is known to be very small, find the input offset voltage.
2.95 A noninverting amplifier with a gain of 100 uses an op amp having an input offset voltage of ±2 mV. Find the output when the input is 0.01 sin ωt, volts.
2.96 A noninverting amplifier with a closed-loop gain of 1000 is designed using an op amp having an input offset voltage of 3 mV and output saturation levels of ±12 V. What is the maximum amplitude of the sine wave that can be applied at the input without the output clipping? If the amplifier is
where ω1 = 1/C1 R1 and ω2 = 1/C2 R2 . Assuming that the circuit is designed such that ω2 ≫ ω1 , find approximate expressions
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CHAPTER 2 PROBLEMS
capacitively coupled in the manner indicated in Fig. 2.36, what would the maximum possible amplitude be?
2.97 An op amp connected in a closed-loop inverting configuration having a gain of 1000 V/V and using relatively small-valued resistors is measured with input grounded to have a dc output voltage of −1.8 V. What is its input offset voltage? Prepare an offset-voltage-source sketch resembling that in Fig. 2.28. Be careful of polarities.
2.98 A particular inverting amplifier with nominal gain of −100 V/V uses an imperfect op amp in conjunction with 100-k and 10-M resistors. The output voltage is found to be +5.3 V when measured with the input open and +5 V with the input grounded.
(a) What is the bias current of this amplifier? In what direction does it flow?
(b) Estimate the value of the input offset voltage.
(c) A10-Mresistorisconnectedbetweenthepositive-input terminal and ground. With the input left floating (discon- nected), the output dc voltage is measured to be −0.6 V.
Estimate the input offset current.
D *2.99 A noninverting amplifier with a gain of +10 V/V using 100 k as the feedback resistor operates from a 5-k source. For an amplifier offset voltage of 0 mV, but with a bias current of 2 μA and an offset current of 0.2 μA, what range of outputs would you expect? Indicate where you would add an additional resistor to compensate for the bias currents. What does the range of possible outputs then become? A designer wishes to use this amplifier with a 15-k source. In order to compensate for the bias current in this case, what resistor would you use? And where?
D 2.100 The circuit of Fig. 2.36 is used to create an ac-coupled noninverting amplifier with a gain of 100 V/V using resistors no larger than 100 k. What values of R1, R2, and R3 should be used? For a break frequency due to C1 at 100 Hz, and that due to C2 at 10 Hz, what values of C1 and C2 are needed?
*2.101 Consider the difference amplifier circuit in Fig. 2.16. LetR1 =R3 =10kandR2 =R4 =1M.Iftheopamphas VOS =5mV,IB =1μA,andIOS =0.2μA,findtheworst-case (largest) dc offset voltage at the output.
*2.102 The circuit shown in Fig. P2.102 uses an op amp having a ±3-mV offset. What is its output offset voltage? What does the output offset become with the input ac coupled
through a capacitor C? If, instead, a large capacitor is placed in series with a 1-k resistor, what does the output offset become?
Figure P2.102
2.103 Usingoffset-nullingfacilitiesprovidedfortheopamp, a closed-loop amplifier with gain of +1000 is adjusted at 25°C to produce zero output with the input grounded. If the input offset-voltage drift is specified to be 20 μV/°C, what output would you expect at 0°C and at 100°C? While nothing can be said separately about the polarity of the output offset at either 0 or 75°C, what would you expect their relative polarities to be?
2.104 An op amp is connected in a closed loop with gain of +100 utilizing a feedback resistor of 1 M.
(a) If the input bias current is 200 nA, what output voltage results with the input grounded?
(b) If the input offset voltage is ±2 mV and the input bias current as in (a), what is the largest possible output that can be observed with the input grounded?
(c) Ifbias-currentcompensationisused,whatisthevalueof the required resistor? If the offset current is no more than one-tenth the bias current, what is the resulting output offset voltage (due to offset current alone)?
(d) With bias-current compensation as in (c) in place, what is the largest dc voltage at the output due to the combined effect of offset voltage and offset current?
*2.105 Anopampintendedforoperationwithaclosed-loop gain of –100 V/V uses resistors of 10 k and 1 M with a bias-current-compensation resistor R3 . What should the value of R3 be? With input grounded, the output offset voltage is found to be +0.30 V. Estimate the input offset current assuming zero input offset voltage. If the input offset voltage
Problems 131
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132 Chapter 2 Operational Amplifiers
can be as large as 1 mV of unknown polarity, what range of
offset current is possible?
2.106 A Miller integrator with R = 10 k and C = 10 nF is implemented by using an op amp with VOS = 2 mV, IB = 0.1 μA, and IOS = 20 nA. To provide a finite dc gain, a 1-M resistor is connected across the capacitor.
(a) TocompensatefortheeffectofIB,aresistorisconnected in series with the positive-input terminal of the op amp. What should its value be?
(b) With the resistor of (a) in place, find the worst-case dc output voltage of the integrator when the input is grounded.
Section 2.7: Effect of Finite Open-Loop Gain and Bandwidth on Circuit Performance
2.107 The data in the following table apply to internally compensated op amps. Fill in the blank entries.
2.111 An inverting amplifier with nominal gain of −50 V/V employs an op amp having a dc gain of 104 and a unity-gain frequency of 106 Hz. What is the 3-dB frequency f3dB of the closed-loopamplifier?Whatisitsgainat0.1f3dB andat10f3dB?
2.112A particular op amp, characterized by a gain–bandwidth product of 20MHz, is operated with a closed-loop gain of +100 V/V. What 3-dB bandwidth results? At what frequency does the closed-loop amplifier exhibit a −6° phase shift? A −84° phase shift?
2.113 Find the ft required for internally compensated op amps to be used in the implementation of closed-loop amplifiers with the following nominal dc gains and 3-dB bandwidths:
(a) −50 V/V; 100 kHz (b) +50 V/V; 100 kHz (c) +2 V/V; 5 MHz
(d) −2 V/V; 5 MHz
(e) −1000 V/V; 10 kHz
(f) +1 V/V; 1 MHz (g) −1 V/V; 1 MHz
2.114 A noninverting op-amp circuit with a gain of 96 V/V is found to have a 3-dB frequency of 8 kHz. For a particular system application, a bandwidth of 32 kHz is required. What is the highest gain available under these conditions?
2.115 Consider a unity-gain follower utilizing an internally compensated op amp with ft = 2 MHz. What is the 3-dB frequency of the follower? At what frequency is the gain of the follower 1% below its low-frequency magnitude? If the input to the follower is a 1-V step, find the 10% to 90% rise time of the output voltage. (Note: The step response of STC low-pass networks is discussed in Appendix E. Specifically, note that the 10%–90% rise time of a low-pass STC circuit with a time constant τ is 2.2τ .)
D *2.116 It is required to design a noninverting amplifier with a dc gain of 10. When a step voltage of 100 mV is applied at the input, it is required that the output be within 1% of its finalvalueof1Vinatmost200ns.Whatmusttheft oftheop amp be? (Note: The step response of STC low-pass networks is discussed in Appendix E.)
D *2.117 This problem illustrates the use of cascaded closed-loop amplifiers to obtain an overall bandwidth greater than can be achieved using a single-stage amplifier with the same overall gain.
CHAPTER 2 PROBLEMS
fb (Hz) 102
106
2×105 10
ft (Hz) 106
108 106
A0 105
103 10−1
2.108 A measurement of the open-loop gain of an internally compensated op amp at very low frequencies shows it to be 98 dB; at 100 kHz, this shows it is 40 dB. Estimate values for A0, fb, and ft.
2.109 Measurementsoftheopen-loopgainofacompensated op amp intended for high-frequency operation indicate that the gainis4×103 at100kHzand20×103 at10kHz.Estimate its 3-dB frequency, its unity-gain frequency, and its dc gain.
2.110 Measurements made on the internally compensated amplifiers listed below provide the dc gain and the frequency at which the gain has dropped by 20 dB. For each, what are the 3 dB and unity-gain frequencies?
(a) 2×105 V/Vand5×102 Hz (b) 20×105 V/Vand10Hz
(c) 1800 V/V and 0.1 MHz
(d) 100 V/V and 0.1 GHz
(e) 25 V/mV and 250 kHz
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CHAPTER 2 PROBLEMS
(a) Show that cascading two identical amplifier stages, each having a low-pass STC frequency response with a 3-dB frequency f1, results in an overall amplifier with a 3-dB frequency given by √
f3dB =
is connected from the output to ground, and a low-frequency sine-wave signal of peak amplitude Vp is applied to the input. Let the op amp be ideal except that its output voltage saturates at ±10 V and its output current is limited to the range ±20 mA.
(a) For RL = 1 k, what is the maximum possible value of Vp while an undistorted output sinusoid is obtained?
(b) Repeat (a) for RL = 200 .
(c) If it is desired to obtain an output sinusoid of 10-V peak
amplitude, what minimum value of RL is allowed?
2.123 Anopamphavingaslewrateof10V/μsistobeused in the unity-gain follower configuration, with input pulses that rise from 0 to 2 V. What is the shortest pulse that can be used while ensuring full-amplitude output? For such a pulse, describe the output resulting.
2.124 For operation with 10-V output pulses with the requirement that the sum of the rise and fall times represent only 20% of the pulse width (at half-amplitude), what is the slew-rate requirement for an op amp to handle pulses 2 μs wide? (Note: The rise and fall times of a pulse signal are usually measured between the 10%- and 90%-height points.)
2.125 What is the highest frequency of a triangle wave of 10-V peak-to-peak amplitude that can be reproduced by an op amp whose slew rate is 20 V/μs? For a sine wave of the same frequency, what is the maximum amplitude of output signal that remains undistorted?
2.126 For an amplifier having a slew rate of 40 V/μs, what is the highest frequency at which a 20-V peak-to-peak sine wave can be produced at the output?
D *2.127 In designing with op amps one has to check the limitations on the voltage and frequency ranges of operation of the closed-loop amplifier, imposed by the op-amp finite bandwidth (ft), slew rate (SR), and output saturation (Vomax). This problem illustrates the point by considering the use of an op amp with ft = 20 MHz, SR=10 V/μs, and Vomax = 10 V in the design of a noninverting amplifier with a nominal gain of 10. Assume a sine-wave input with peak amplitude Vi .
(a) If Vi = 0.5 V, what is the maximum frequency before the output distorts?
(b) If f = 200 kHz, what is the maximum value of Vi before the output distorts?
(c) If Vi = 50 mV, what is the useful frequency range of operation?
Problems 133
(b) It is required to design a noninverting amplifier with a dc gain of 40 dB utilizing a single internally compensated op amp with ft = 2 MHz. What is the 3-dB frequency obtained?
(c) Redesign the amplifier of (b) by cascading two identical noninverting amplifiers each with a dc gain of 20 dB. What is the 3-dB frequency of the overall amplifier? Compare this to the value obtained in (b) above.
D **2.118 A designer, wanting to achieve a stable gain of 100 V/V at 5 MHz, considers her choice of amplifier topologies. What unity-gain frequency would a single operational amplifier require to satisfy her need? Unfortunately, the best available amplifier has an ft of 40 MHz. How many such amplifiers connected in a cascade of identical noninverting stages would she need to achieve her goal? What is the 3-dB frequency of each stage she can use? What is the overall 3-dB frequency?
2.119 Consider the use of an op amp with a unity-gain frequencyft intherealizationof:
(a) An inverting amplifier with dc gain of magnitude K. (b) A noninverting amplifier with a dc gain of K.
In each case find the 3-dB frequency and the gain–bandwidth product (GBP ≡ |Gain| × f3dB). Comment on the results.
*2.120 ConsideraninvertingsummerwithtwoinputsV1 and V2 and with Vo = −(V1+ 3V2). Find the 3-dB frequency of each of the gain functions Vo/V1 and Vo/V2 in terms of the op amp ft . (Hint: In each case, the other input to the summer can be set to zero—an application of superposition.)
Section 2.8: Large-Signal Operation of Op Amps
2.121 A particular op amp using ±15-V supplies operates linearly for outputs in the range −14 V to +14 V. If used in an inverting amplifier configuration of gain −100, what is the rms value of the largest possible sine wave that can be applied at the input without output clipping?
2.122 Consider an op amp connected in the inverting configuration to realize a closed-loop gain of −100 V/V utilizing resistors of 1 k and 100 k. A load resistance RL
2–1f1
(d) If f = 50 kHz, what is the useful input voltage range? = Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
CHAPTER 3
Semiconductors
Introduction 135
3.1 Intrinsic Semiconductors 136
3.2 Doped Semiconductors 139
3.3 Current Flow in Semiconductors
3.4 The pn Junction 148
142
3.5 The pn Junction with an Applied Voltage 155
3.6 Capacitive Effects in the pn Junction 164 Summary 168
Problems 171
IN THIS CHAPTER YOU WILL LEARN
1. The basic properties of semiconductors and in particular silicon, which is the material used to make most of today’s electronic circuits.
2. How doping a pure silicon crystal dramatically changes its electrical conductivity, which is the fundamental idea underlying the use of semiconductors in the implementation of electronic devices.
3. The two mechanisms by which current flows in semiconductors: drift and diffusion of charge carriers.
4. The structure and operation of the pn junction; a basic semiconductor structure that implements the diode and plays a dominant role in transistors.
Introduction
Thus far we have dealt with electronic circuits, and notably amplifiers, as system building blocks. For instance, in Chapter 2 we learned how to use op amps to design interesting and useful circuits, taking advantage of the terminal characteristics of the op amp and without any knowledge of what is inside the op-amp package. Though interesting and motivating, this approach has its limitations. Indeed, to achieve our goal of preparing the reader to become a proficient circuit designer, we have to go beyond this black-box or system-level abstraction and learn about the basic devices from which electronic circuits are assembled, namely, diodes (Chapter 4) and transistors (Chapters 5 and 6). These solid-state devices are made using semiconductor materials, predominantly silicon.
In this chapter, we briefly introduce the properties and physics of semiconductors. The objective is to provide a basis for understanding the physical operation of diodes and transistors in order to enable their effective use in the design of circuits. Although many of the concepts studied in this chapter apply to semiconductor materials in general, our treatment is heavily biased toward silicon, simply because it is the material used in the vast majority of microelectronic circuits. To complement the material presented here, Appendix A provides a description of the integrated-circuit fabrication process. As discussed in Appendix A, whether our circuit consists of a single transistor or is an integrated circuit containing more than 2 billion transistors, it is fabricated in a single silicon crystal, which gives rise to the name monolithic circuit. This chapter therefore begins with a study of the crystal structure of semiconductors and introduces the two types of charge carriers available for current conduction: electrons and holes. The most significant property of semiconductors is that their conductivity can be varied over a very wide range through the introduction of
135
136 Chapter 3
Semiconductors
controlled amounts of impurity atoms into the semiconductor crystal in a process called doping. Doped semiconductors are discussed in Section 3.2. This is followed by the study in Section 3.3 of the two mechanisms for current flow in semiconductors, namely, carrier drift and carrier diffusion.
Armed with these basic semiconductor concepts, we spend the remainder of the chapter on the study of an important semiconductor structure: the pn junction. In addition to being essen- tially a diode, the pn junction is the basic element of the bipolar junction transistor (BJT, Chap- ter 6) and plays an important role in the operation of field-effect transistors (FETs, Chapter 5).
3.1 Intrinsic Semiconductors
As their name implies, semiconductors are materials whose conductivity lies between that of conductors, such as copper, and insulators, such as glass. There are two kinds of semiconduc- tors: single-element semiconductors, such as germanium and silicon, which are in group IV in the periodic table; and compound semiconductors, such as gallium-arsenide, which are formed by combining elements from groups III and V or groups II and VI. Compound semiconductors are useful in special electronic circuit applications as well as in applications that involve light, such as light-emitting diodes (LEDs). Of the two elemental semiconductors, germanium was used in the fabrication of very early transistors (late 1940s, early 1950s). It was quickly supplanted, however, with silicon, on which today’s integrated-circuit technology is almost entirely based. For this reason, we will deal mostly with silicon devices throughout this book.1
A silicon atom has four valence electrons, and thus it requires another four to complete its outermost shell. This is achieved by sharing one of its valence electrons with each of its four neighboring atoms. Each pair of shared electrons forms a covalent bond. The result is that a crystal of pure or intrinsic silicon has a regular lattice structure, where the atoms are held in their position by the covalent bonds. Figure 3.1 shows a two-dimensional representation of such a structure.
At sufficiently low temperatures, approaching absolute zero (0 K), all the covalent bonds are intact and no electrons are available to conduct electric current. Thus, at such low temperatures, the intrinsic silicon crystal behaves as an insulator.
At room temperature, sufficient thermal energy exists to break some of the covalent bonds, a process known as thermal generation. As shown in Fig. 3.2, when a covalent bond is broken, an electron is freed. The free electron can wander away from its parent atom, and it becomes available to conduct electric current if an electric field is applied to the crystal. As the electron leaves its parent atom, it leaves behind a net positive charge, equal to the magnitude of the electron charge. Thus, an electron from a neighboring atom may be attracted to this positive charge, and leaves its parent atom. This action fills up the “hole” that existed in the ionized atom but creates a new hole in the other atom. This process may repeat itself, with the result that we effectively have a positively charged carrier, or hole, moving through the silicon crystal structure and being available to conduct electric current. The charge of a hole is equal in magnitude to the charge of an electron. We can thus see that as temperature increases, more covalent bonds are broken and electron–hole pairs are generated. The increase in the numbers of free electrons and holes results in an increase in the conductivity of silicon.
1 An exception is the subject of gallium arsenide (GaAs) circuits, which though not covered in this edition of the book, is studied in some detail in material provided on the text website.
Valence Covalent electrons bonds
4 4 4
4 4 4
4 4 4
Silicon atoms
3.1 Intrinsic Semiconductors 137
Figure 3.1 Two-dimensional representation of the silicon crystal. The circles represent the inner core of silicon atoms, with +4 indicating its positive charge of +4q, which is neutralized by the charge of the four valence electrons. Observe how the covalent bonds are formed by sharing of the valence electrons. At 0 K, all bonds are intact and no free electrons are available for current conduction.
Broken covalent bond
Covalent bond
Valence Free electrons electron
4 4 4
4
4 4 4
Hole
Silicon atoms
0
4
4
Figure3.2 Atroomtemperature,someofthecovalentbondsarebrokenbythermalgeneration.Eachbroken bond gives rise to a free electron and a hole, both of which become available for current conduction.
Thermal generation results in free electrons and holes in equal numbers and hence equal concentrations, where concentration refers to the number of charge carriers per unit volume (cm3). The free electrons and holes move randomly through the silicon crystal structure, and in the process some electrons may fill some of the holes. This process, called recombination, results in the disappearance of free electrons and holes. The recombination rate is
138 Chapter 3
Semiconductors
proportional to the number of free electrons and holes, which in turn is determined by the thermal generation rate. The latter is a strong function of temperature. In thermal equilibrium, the recombination rate is equal to the generation rate, and one can conclude that the concentration of free electrons n is equal to the concentration of holes p,
n=p=ni (3.1) where ni denotes the number of free electrons and holes in a unit volume (cm3) of intrinsic
silicon at a given temperature. Results from semiconductor physics gives ni as
n = BT3/2e−Eg /2kT (3.2)
i
where B is a material-dependent parameter that is 7.3×1015cm−3K−3/2 for silicon; T is the temperature in K; Eg, a parameter known as the bandgap energy, is 1.12 electron volt (eV) for silicon2 ; and k is Boltzmann’s constant (8.62 × 10−5 eV/K). It is interesting to know that the bandgap energy Eg is the minimum energy required to break a covalent bond and thus generate an electron-hole pair.
Example 3.1
Calculate the value of ni for silicon at room temperature (T ≃ 300 K).
Solution
Substituting the values given above in Eq. (3.2) provides
ni =7.3×1015(300)3/2e−1.12/(2×8.62×10−5×300)
= 1.5 × 1010 carriers/cm3
Althoughthisnumberseemslarge,toplaceitintocontextnotethatsiliconhas5×1022 atoms/cm3.Thus at room temperature only one in about 5 × 1012 atoms is ionized and contributing a free electron and a hole!
Finally, it is useful for future purposes to express the product of the hole and free-electron concentration as
pn=ni2 (3.3) where for silicon at room temperature, ni ≃ 1.5 × 1010/cm3. As will be seen shortly, this
relationship extends to extrinsic or doped silicon as well.
2Notethat1eV=1.6×10−19 J.
3.2 Doped Semiconductors 139
LCDs, THE FACE OF ELECTRONICS:
The existence of liquid crystals whose color could be changed by means of an external heat source was first reported in 1888 by an Austrian botanical physiologist. The LC idea lay dormant until the late 1940s, however. Subsequent developments in the field of solid-state electronics provided the technology to harness the technique in display media, with the first LCDs being demonstrated by RCA beginning in 1962. Today, LCDs are an essential component in every mobile device as the interface to the world of electronics within. At the other end of the scale, large LCDs are used in flat-panel TVs, and very large LCDs are appearing as “dynamic” wallpaper in museum display settings.
EXERCISE
3.1 Calculate the intrinsic carrier density ni for silicon at T = 50 K and 350 K. Ans. 9.6×10−39/cm3;4.15×1011/cm3
3.2 Doped Semiconductors
The intrinsic silicon crystal described above has equal concentrations of free electrons and holes, generated by thermal generation. These concentrations are far too small for silicon to conduct appreciable current at room temperature. Also, the carrier concentrations and hence the conductivity are strong functions of temperature, not a desirable property in an electronic device. Fortunately, a method was developed to change the carrier concentration in a semiconductor crystal substantially and in a precisely controlled manner. This process is known as doping, and the resulting silicon is referred to as doped silicon.
Doping involves introducing impurity atoms into the silicon crystal in sufficient numbers to substantially increase the concentration of either free electrons or holes but with little or no change in the crystal properties of silicon. To increase the concentration of free electrons, n, silicon is doped with an element with a valence of 5, such as phosphorus. The resulting doped silicon is then said to be of n type. To increase the concentration of holes, p, silicon is doped with an element having a valence of 3, such as boron, and the resulting doped silicon is said to be of p type.
Figure 3.3 shows a silicon crystal doped with phosphorus impurity. The dopant (phosphorus) atoms replace some of the silicon atoms in the crystal structure. Since the phosphorus atom has five electrons in its outer shell, four of these electrons form covalent bonds with the neighboring atoms, and the fifth electron becomes a free electron. Thus each phosphorus atom donates a free electron to the silicon crystal, and the phosphorus impurity is called a donor. It should be clear, though, that no holes are generated by this process. The net positive charge associated with the phosphorus atom is a bound charge that does not move through the crystal.
If the concentration of donor atoms is ND, where ND is usually much greater than ni, the concentration of free electrons in the n-type silicon will be
nn ≃ND (3.4)
140 Chapter 3
Semiconductors
Valence electrons
Covalent bonds
4 4 4
4 5
4 4 4
Free electron donated by impurity atom
Pentavalent impurity atom (donor)
Silicon atoms
4
Figure 3.3 A silicon crystal doped by a pentavalent element. Each dopant atom donates a free electron and is thus called a donor. The doped semiconductor becomes n type.
wherethesubscriptndenotesn-typesilicon.Thusnn isdeterminedbythedopingconcentration and not by temperature. This is not the case, however, for the hole concentration. All the holes in the n-type silicon are those generated by thermal ionization. Their concentration pn can be found by noting that the relationship in Eq. (3.3) applies equally well for doped silicon, provided thermal equilibrium is achieved. Thus for n-type silicon
p n n n = n i2 Substituting for nn from Eq. (3.4), we obtain for pn
pn ≃ N
ni2
(3.5)
Thus pn will have the same dependence on temperature as that of ni2. Finally, we note that in n-type silicon the concentration of free electrons nn will be much larger than that of holes. Hence electrons are said to be the majority charge carriers and holes the minority charge carriers in n-type silicon.
To obtain p-type silicon in which holes are the majority charge carriers, a trivalent impurity such as boron is used. Figure 3.4 shows a silicon crystal doped with boron. Note that the boron atoms replace some of the silicon atoms in the silicon crystal structure. Since each boron atom has three electrons in its outer shell, it accepts an electron from a neighboring atom, thus forming covalent bonds. The result is a hole in the neighboring atom and a bound negative charge at the acceptor (boron) atom. It follows that each acceptor atom provides a hole. If the acceptor doping concentration is NA , where NA ≫ ni , the hole concentration becomes
pp ≃NA (3.6)
where the subscript p denotes p-type silicon. Thus, here the majority carriers are holes and their concentration is determined by NA . The concentration of minority electrons can be found
D
Valence electrons
Covalent bonds
3.2 Doped Semiconductors 141
4 4 4
4 3 4
0
4 4 4
Silicon atom
Trivalent impurity atom (acceptor)
Electron accepted from this atom, thus creating a hole
Figure 3.4 A silicon crystal doped with boron, a trivalent impurity. Each dopant atom gives rise to a hole, and the semiconductor becomes p type.
by using the relationship
p p n p = n i2 and substituting for pp from Eq. (3.6),
np ≃ N
ni2
(3.7)
A
Thus, the concentration of the minority electrons will have the same temperature dependence as that of ni2.
It should be emphasized that a piece of n-type or p-type silicon is electrically neutral; the charge of the majority free carriers (electrons in the n-type and holes in the p-type silicon) are neutralized by the bound charges associated with the impurity atoms.
Example 3.2
Consider an n-type silicon for which the dopant concentration ND = 1017/cm3. Find the electron and hole concentrations at T = 300 K.
Solution
The concentration of the majority electrons is
nn ≃ND =1017/cm3
142
Chapter 3 Semiconductors
Example 3.2 continued
The concentration of the minority holes is
pn ≃ ni2 ND
InExample3.1wefoundthatatT=300K,ni =1.5×1010/cm3.Thus, 2
1.5 × 1010 pn = 1017
=2.25×103/cm3 Observe that nn ≫ ni and that nn is vastly higher than pn .
EXERCISES
3.2 For the situation in Example 3.2, find the electron and hole concentrations at 350 K. You may use the value of ni at T = 350 K found in Exercise 3.1.
Ans. nn =1017/cm3,pn =1.72×106/cm3
3.3 For a silicon crystal doped with boron, what must NA be if at T = 300 K the electron concentration drops below the intrinsic level by a factor of 106?
Ans. NA =1.5×1016/cm3
3.3 Current Flow in Semiconductors
There are two distinctly different mechanisms for the movement of charge carriers and hence for current flow in semiconductors: drift and diffusion.
3.3.1 Drift Current
When an electrical field E is established in a semiconductor crystal, holes are accelerated in the direction of E, and free electrons are accelerated in the direction opposite to that of E. This situation is illustrated in Fig. 3.5. The holes acquire a velocity νp-drift given by
νp-drift = μpE (3.8)
where μp is a constant called the hole mobility: It represents the degree of ease by which holes move through the silicon crystal in response to the electrical field E. Since velocity has the units of centimeters per second and E has the units of volts per centimeter, we see from Eq. (3.8) that the mobility μp must have the units of centimeters squared per volt-second (cm2/V·s).Forintrinsicsiliconμp =480cm2/V·s.
E
V
where the result is negative because the electrons move in the direction opposite to E. Here μn istheelectronmobility,whichforintrinsicsiliconisabout1350cm2/V·s.Notethatμn is about 2.5 times μp, signifying that electrons move with much greater ease through the silicon crystal than do holes.
Let’s now return to the single-crystal silicon bar shown in Fig. 3.5. Let the concentration of holes be p and that of free electrons n. We wish to calculate the current component due to the flow of holes. Consider a plane perpendicular to the x direction. In one second, the hole charge that crosses that plane will be (Aqpνp-drift) coulombs, where A is the cross-sectional area of the silicon bar and q is the magnitude of electron charge. This then must be the hole component of the drift current flowing through the bar,
Ip = Aqpνp-drift (3.10) Substitutingforνp-drift fromEq.(3.8),weobtain
Ip =AqpμpE
We are usually interested in the current density Jp, which is the current per unit cross-
sectional area,
Jp=Ip =qpμpE (3.11) A
The current component due to the drift of free electrons can be found in a similar manner. Note, however, that electrons drifting from right to left result in a current component from left to right. This is because of the convention of taking the direction of current flow as the direction of flow of positive charge and opposite to the direction of flow of negative charge. Thus,
In =−Aqnνn-drift
Substituting for νn-drift from Eq. (3.9), we obtain the current density Jn = In /A as
Jn = qnμnE (3.12) The total drift current density can now be found by summing Jp and Jn from Eqs. (3.11) and
3.3 Current Flow in Semiconductors 143
(3.12),
Holes
Electrons
x Figure 3.5 An electric field E established in a bar of silicon causes the holes to drift in the direction of E and the free electrons to drift in the opposite direction. Both the hole and electron drift currents
are in the direction of E. The free electrons acquire a drift velocity νn-drift given by
νn-drift =−μnE (3.9)
J =Jp +Jn =q pμp +nμn E (3.13) This relationship can be written as
J=σE (3.14)
144 Chapter 3
Semiconductors
or
where the conductivity σ is given by
J = E/ρ
(3.15) (3.16)
(3.17)
(3.18)
and the resistivity ρ is given by
σ =q pμp +nμn ρ≡1= 1
σ q pμp +nμn
Observe that Eq. (3.15) is a form of Ohm’s law and can be written alternately as
ρ = E J
Thus the units of ρ are obtained from: V/cm = · cm. A/cm2
Example 3.3
Find the resistivity of (a) intrinsic silicon and (b) p-type silicon with NA = 1016/cm3. Use ni = 1.5 × 1010 /cm3 , and assume that for intrinsic silicon μn = 1350 cm2 /V · s and μp = 480 cm2 /V · s, and for the doped silicon μn = 1110 cm2 /V · s and μp = 400 cm2 /V · s. (Note that doping results in reduced carrier mobilities.)
Solution
(a) For intrinsic silicon,
Thus,
p=n=ni =1.5×1010/cm3
ρ=1 q pμp +nμn
ρ=1 1.6×10−19 1.5×1010 ×480+1.5×1010 ×1350
=2.28×105 ·cm
pp ≃NA =1016/cm3
n2 1.5 × 1010 2 np ≃ i = 16
NA 10
(b) For the p-type silicon
=2.25×104/cm3
Thus,
ρ=1 q pμp +nμn
=1 1.6×10−19 1016 ×400+2.25×104 ×1110
≃ 1 =1.56·cm 1.6×10−19 ×1016 ×400
Observe that the resistivity of the p-type silicon is determined almost entirely by the doping concentration. Also observe that doping the silicon reduces its resistivity by a factor of about 104, a truly remarkable change.
EXERCISE
3.4 A uniform bar of n-type silicon of 2-μm length has a voltage of 1 V applied across it. If ND = 1016 /cm3 and μn = 1350 cm2 /V · s, find (a) the electron drift velocity, (b) the time it takes an electron to cross the 2-μm length, (c) the drift-current density, and (d) the drift current in the case that the silicon bar has a cross-sectional area of 0.25 μm2.
Ans. 6.75×106 cm/s;30ps;1.08×104 A/cm2;27μA
3.3.2 Diffusion Current
Carrier diffusion occurs when the density of charge carriers in a piece of semiconductor is not uniform. For instance, if by some mechanism the concentration of, say, holes, is made higher in one part of a piece of silicon than in another, then holes will diffuse from the region of high concentration to the region of low concentration. Such a diffusion process is like that observed if one drops a few ink drops in a water-filled tank. The diffusion of charge carriers gives rise to a net flow of charge, or diffusion current.
As an example, consider the bar of silicon shown in Fig. 3.6(a): By some unspecified process, we have arranged to inject holes into its left side. This continuous hole injection gives rise to and maintains a hole concentration profile such as that shown in Fig. 3.6(b). This profile in turn causes holes to diffuse from left to right along the silicon bar, resulting in a hole current in the x direction. The magnitude of the current at any point is proportional to the slope of the concentration profile, or the concentration gradient, at that point,
J =−qD dp(x) (3.19) p pdx
3.3 Current Flow in Semiconductors 145
146 Chapter 3
Semiconductors
Hole injection
(a)
x
Hole diffusion
Hole current
0
x direction.
0
x
(b)
Figure 3.6 A bar of silicon (a) into which holes are injected, thus creating the hole concentration profile along the x axis, shown in (b). The holes diffuse in the positive direction of x and give rise to a hole diffusion current in the same direction. Note that we are not showing the circuit to which the silicon bar is connected.
Electron diffusion Electron current
where Jp is the hole-current density (A/cm2), q is the magnitude of electron charge, Dp is a constant called the diffusion constant or diffusivity of holes; and p(x) is the hole concentration at point x. Note that the gradient (dp/dx) is negative, resulting in a positive current in the x direction, as should be expected.
In the case of electron diffusion resulting from an electron concentration gradient (see Fig. 3.7), a similar relationship applies, giving the electron-current density,
J =qD dn(x) (3.20) n ndx
where Dn is the diffusion constant or diffusivity of electrons. Observe that a negative (dn/dx) gives rise to a negative current, a result of the convention that the positive direction of current is taken to be that of the flow of positive charge (and opposite to that of the flow of negative
Figure 3.7 If the electron concentration pro- file shown is established in a bar of silicon, electrons diffuse in the x direction, giving rise to an electron diffusion current in the negative-x
Electron concentration, n
Hole concentration, p
charge). For holes and electrons diffusing in intrinsic silicon, typical values for the diffusion constants are Dp = 12 cm2/s and Dn = 35 cm2/s.
At this point the reader is probably wondering where the diffusion current in the silicon bar in Fig. 3.6(a) goes. A good question, as we are not showing how the right-side end of the bar is connected to the rest of the circuit. We will address this and related questions in detail in our discussion of the pn junction in later sections.
Example 3.4
Consider a bar of silicon in which a hole concentration profile described by
p(x)=p e−x/Lp 0
is established. Find the hole-current density at x = 0. Let p0 = 1016/cm3, Lp = 1 μm, and Dp = 12 cm2/s. If the cross-sectional area of the bar is 100 μm2, find the current Ip.
Thus, Jp(0)=qDp p0 Lp
The current Ip can be found from
EXERCISE
L0 p
=1.6×10−19 × 12 1×10−4
= 192 A/cm2
Ip = Jp × A =192×100×10−8 = 192 μA
×1016
3.3 Current Flow in Semiconductors 147
Solution
J =−qD dp(x) p pdx
d −x/L =−qD pe p
pdx 0 =qDp p e−x/Lp
3.5 The linear electron-concentration profile shown in Fig. E3.5 has been established in a piece of silicon. If n0 = 1017/cm3 and W = 1 μm, find the electron-current density in microamperes per micron squared (μA/μm2). If a diffusion current of 1 mA is required, what must the cross-sectional area (in a direction perpendicular to the page) be? Recall that Dn = 35 cm2 /s.
148 Chapter 3 Semiconductors
n(x) n0
0
W x FigureE3.5
Ans. 56 μA/μm2; 18 μm2
3.3.3 Relationship between D and μ
A simple but powerful relationship ties the diffusion constant with the mobility,
Dn =Dp =VT μn μp
(3.21)
where VT = kT /q. The parameter VT is known as the thermal voltage. At room temperature, T ≃ 300 K and VT = 25.9 mV. We will encounter VT repeatedly throughout this book. The relationship in Eq. (3.21) is known as the Einstein relationship.
EXERCISE
3.6 Use the Einstein relationship to find Dn and Dp for intrinsic silicon using μn = 1350 cm2/V·s and μp =480cm2/V·s.
Ans. 35 cm2/s; 12.4 cm2/s
3.4 The pn Junction
Having learned important semiconductor concepts, we are now ready to consider our first practical semiconductor structure—the pn junction. As mentioned previously, the pn junction implements the diode (Chapter 4) and plays the dominant role in the structure and operation of the bipolar junction transistor (BJT, Chapter 6). As well, understanding pn junctions is very important to the study of the MOSFET operation (Chapter 5).
Metal contact Metal contact
Anode Cathode
Figure 3.8 Simplified physical structure of the pn junction. (Actual geometries are given in Appendix A.) As the pn junction implements the junction diode, its terminals are labeled anode and cathode.
3.4.1 Physical Structure
Figure 3.8 shows a simplified physical structure of the pn junction. It consists of a p-type semiconductor (e.g., silicon) brought into close contact with an n-type semiconductor material (also silicon). In actual practice, both the p and n regions are part of the same silicon crystal; that is, the pn junction is formed within a single silicon crystal by creating regions of different dopings (p and n regions). Appendix A provides a description of the fabrication process of integrated circuits including pn junctions. As indicated in Fig. 3.8, external wire connections are made to the p and n regions through metal (aluminum) contacts. If the pn junction is used as a diode, these constitute the diode terminals and are therefore labeled “anode” and “cathode” in keeping with diode terminology.3
3.4.2 Operation with Open-Circuit Terminals
Figure 3.9 shows a pn junction under open-circuit conditions—that is, the external terminals are left open. The “+” signs in the p-type material denote the majority holes. The charge of these holes is neutralized by an equal amount of bound negative charge associated with the acceptor atoms. For simplicity, these bound charges are not shown in the diagram. Also not shown are the minority electrons generated in the p-type material by thermal ionization.
In the n-type material the majority electrons are indicated by “–” signs. Here also, the bound positive charge, which neutralizes the charge of the majority electrons, is not shown in order to keep the diagram simple. The n-type material also contains minority holes generated by thermal ionization but not shown in the diagram.
The Diffusion Current ID Because the concentration of holes is high in the p region and low in the n region, holes diffuse across the junction from the p side to the n side. Similarly, electrons diffuse across the junction from the n side to the p side. These two current components add together to form the diffusion current ID, whose direction is from the p side to the n side, as indicated in Fig. 3.9.
The Depletion Region The holes that diffuse across the junction into the n region quickly recombine with some of the majority electrons present there and thus disappear from the scene. This recombination process results also in the disappearance of some free electrons from the
3This terminology in fact is a carryover from that used with vacuum-tube technology, which was the technology for making diodes and other electronic devices until the invention of the transistor in 1947. This event ushered in the era of solid-state electronics, which changed not only electronics, communications, and computers but indeed the world!
3.4 The pn Junction 149
p-type silicon
n-type silicon
150 Chapter 3
Semiconductors
E
(b)
Figure 3.9 (a) The pn junction with no applied voltage (open-circuited terminals). (b) The potential distribution along an axis perpendicular to the junction.
n-type material. Thus some of the bound positive charge will no longer be neutralized by free electrons, and this charge is said to have been uncovered. Since recombination takes place close to the junction, there will be a region close to the junction that is depleted of free electrons and contains uncovered bound positive charge, as indicated in Fig. 3.9.
The electrons that diffuse across the junction into the p region quickly recombine with some of the majority holes there, and thus disappear from the scene. This results also in the disappearance of some majority holes, causing some of the bound negative charge to be uncovered (i.e., no longer neutralized by holes). Thus, in the p material close to the junction, there will be a region depleted of holes and containing uncovered bound negative charge, as indicated in Fig. 3.9.
From the above it follows that a carrier-depletion region will exist on both sides of the junction, with the n side of this region positively charged and the p side negatively charged. This carrier-depletion region—or, simply, depletion region—is also called the space-charge region. The charges on both sides of the depletion region cause an electric field E to be established across the region in the direction indicated in Fig. 3.9. Hence a potential difference results across the depletion region, with the n side at a positive voltage relative to the p side, as shown in Fig. 3.9(b). Thus the resulting electric field opposes the diffusion of holes into the n region and electrons into the p region. In fact, the voltage drop across the depletion region acts as a barrier that has to be overcome for holes to diffuse into the n region and electrons to diffuse into the p region. The larger the barrier voltage, the smaller the number of carriers that will be able to overcome the barrier, and hence the lower the magnitude of diffusion current. Thus it is the appearance of the barrier voltage V0 that limits the carrier diffusion process. It follows that the diffusion current ID depends strongly on the voltage drop V0 across the depletion region.
The Drift Current IS and Equilibrium In addition to the current component ID due to majority-carrier diffusion, a component due to minority-carrier drift exists across the junction. Specifically, some of the thermally generated holes in the n material move toward the junction and reach the edge of the depletion region. There, they experience the electric field in the depletion region, which sweeps them across that region into the p side. Similarly, some of the minority thermally generated electrons in the p material move to the edge of the depletion region and get swept by the electric field in the depletion region across that region into the n side. These two current components—electrons moved by drift from p to n and holes moved by drift from n to p—add together to form the drift current IS , whose direction is from the n side to the p side of the junction, as indicated in Fig. 3.9. Since the current IS is carried by thermally generated minority carriers, its value is strongly dependent on temperature; however, it is independent of the value of the depletion-layer voltage V0. This is due to the fact that the drift current is determined by the number of minority carriers that make it to the edge of the depletion region; any minority carriers that manage to get to the edge of the depletion region will be swept across by E irrespective of the value of E or, correspondingly, of V0.
Under open-circuit conditions (Fig. 3.9) no external current exists; thus the two opposite currents across the junction must be equal in magnitude:
ID =IS
This equilibrium condition4 is maintained by the barrier voltage V0. Thus, if for some reason ID exceeds IS, then more bound charge will be uncovered on both sides of the junction, the depletion layer will widen, and the voltage across it (V0) will increase. This in turn causes ID to decrease until equilibrium is achieved with ID = IS . On the other hand, if IS exceeds ID , then the amount of uncovered charge will decrease, the depletion layer will narrow, and the voltage across it (V0) will decrease. This causes ID to increase until equilibrium is achieved withID =IS.
The Junction Built-in Voltage With no external voltage applied, the barrier voltage V0 across the pn junction can be shown to be given by5
N N
V0 = VT ln A D (3.22)
ni2
where NA and ND are the doping concentrations of the p side and n side of the junction, respectively. Thus V0 depends both on doping concentrations and on temperature. It is known as the junction built-in voltage. Typically, for silicon at room temperature, V0 is in the range of 0.6 V to 0.9 V.
When the pn junction terminals are left open-circuited, the voltage measured between them will be zero. That is, the voltage V0 across the depletion region does not appear between the junction terminals. This is because of the contact voltages existing at the metal–semiconductor junctions at the terminals, which counter and exactly balance the barrier voltage. If this were not the case, we would have been able to draw energy from the isolated pn junction, which would clearly violate the principle of conservation of energy.
Width of and Charge Stored in the Depletion Region Figure 3.10 provides further illustration of the situation that obtains in the pn junction when the junction is in equilibrium.
4 In fact, in equilibrum the equality of drift and diffusion currents applies not just to the total currents but also to their individual components. That is, the hole drift current must equal the hole diffusion current and, similarly, the electron drift current must equal the electron diffusion current.
5The derivation of this formula and of a number of others in this chapter can be found in textbooks dealing with devices, such as that by Streetman and Bannerjee (see the reading list in Appendix I).
3.4 The pn Junction 151
152 Chapter 3
Semiconductors
p
n
pp NA
np0 ni2 NA
ID
IS
xp 0 xn E
(a)
W
nn ND
pn0 ni2 ND
x
xp 0 xn (b)
Q Aq NAxp
Q Aq ND xn
xp xn x
W
(c)
xp 0 xn (d)
VO
Figure 3.10 (a) A pn junction with the terminals open-circuited. (b) Carrier concentrations; note that N > N . (c) The charge stored in both sides of the depletion region; Q = Q = Q . (d) The built-in
AD J+− voltage V0.
Charge Voltage density
Carrier concentration
In Fig. 3.10(a) we show a junction in which NA > ND , a typical situation in practice. This is borne out by the carrier concentration on both sides of the junction, as shown in Fig. 3.10(b). Note that we have denoted the minority-carrier concentrations in both sides by np0 and pn0, with the additional subscript “0” signifying equilibrium (i.e., before external voltages are applied, as will be seen in the next section). Observe that the depletion region extends in both the p and n materials and that equal amounts of charge exist on both sides (Q+ and Q− in Fig. 3.10c). However, since usually unequal dopings NA and ND are used, as in the case illustrated in Fig. 3.10, the width of the depletion layer will not be the same on the two sides. Rather, to uncover the same amount of charge, the depletion layer will extend deeper into the more lightly doped material. Specifically, if we denote the width of the depletion region in the p side by xp and in the n side by xn, we can express the magnitude of the charge on the n side of the junction as
Q = qAx N (3.23) +nD
and that on the p side of the junction asQ = qAx N (3.24)
−pA
where A is the cross-sectional area of the junction in the plane perpendicular to the page. The
charge equality condition can now be written as
which can be rearranged to yield
qAxnND = qAxpNA
xn = NA (3.25)
xp ND
In actual practice, it is usual for one side of the junction to be much more heavily doped than the other, with the result that the depletion region exists almost entirely on one side (the lightly doped side).
The width W of the depletion layer can be shown to be given by
3.4 The pn Junction 153
W = xn + xp = 2es 1 + 1 V0 (3.26) q NA ND
where es is the electrical permittivity of silicon = 11.7e0 = 11.7 × 8.85 × 10−14 F/cm = 1.04 × 10−12 F/cm. Typically W is in the range 0.1 μm to 1 μm. Eqs. (3.25) and (3.26) can be used to obtain xn and xp in terms of W as
xn =W NA (3.27) NA +ND
xp =W ND (3.28) NA +ND
The charge stored on either side of the depletion region can be expressed in terms of W by utilizing Eqs. (3.23) and (3.27) to obtain
QJ=Q+ =Q−
NN QJ =Aq A D W
Finally, we can substitute for W from Eq. (3.26) to obtain NN
QJ=A2esq AD V0 NA +ND
(3.29)
(3.30)
NA +ND
TheseexpressionsforQJ willproveusefulinsubsequentsections.
154 Chapter 3 Semiconductors
Example 3.5
Consider a pn junction in equilibrium at room temperature (T = 300 K) for which the dop- ing concentrations are NA = 1018/cm3 and ND = 1016/cm3 and the cross-sectional area A = 10−4 cm2. Calculate pp, np0, nn, pn0, V0, W, xn, xp, and QJ . Use ni = 1.5 × 1010/cm3.
Solution
To find V0 we use Eq. (3.22),
where
Thus,
pp ≃NA =1018 cm−3
n2 n2 (1.5×1010)2 np0= i ≃ i = 18
ppNA 10 nn ≃ND =1016 cm−3
n2 n2 (1.5 × 1010 )2
=2.25×102cm−3
pn0= i ≃ i = nnND 10
16
=2.25×104cm−3
V =V ln NAND O T ni2
VT = kT = 8.62 × 10−5 × 300 (eV) q q(e)
=25.9×10−3 V
V =25.9×10−3 ln 0
1018 ×1016 2.25 × 1020
= 0.814 V
To determine W we use Eq. (3.26):
W = 1.6×10−19 1018 + 1016 ×0.814
2×1.04×10−12 1 1 =3.27×10−5 cm=0.327μm
To determine xn and xp we use Eqs. (3.27) and (3.28), respectively: xn=W NA
= 0.327 1018 + 1016 = 0.324 μm xp=W ND
NA +ND 1018
NA +ND 1016
= 0.327 1018 + 1016 = 0.003 μm
Finally, to determine the charge stored on either side of the depletion region, we use Eq. (3.29):
1018 ×1016
Q =10−4 ×1.6×10−19 ×0.327×10−4
J 1018 +1016 =5.18×10−12 C=5.18pC
3.5 The pn Junction with an Applied Voltage 155
EXERCISES
3.7 Show that
V0=1q NAND W2 2 es NA+ND
3.8 Showthatforapnjunctioninwhichthepsideismuchmoreheavilydopedthanthenside(i.e.,NA ≫ND), referred to as a p+n diode, Eqs. (3.26), (3.27), (3.28), (3.29), and (3.30) can be simplified as follows:
W≃ 2es V0 qND
(3.26′)
(3.27′) (3.28′) (3.29′) (3.30′)
xn ≃W
x ≃W/N /N
pAD QJ ≃AqNDW
QJ ≃A2esqNDV0
3.9 If in the fabrication of the pn junction in Example 3.5, it is required to increase the minority-carrier concentration in the n region by a factor of 2, what must be done?
Ans. Lower ND by a factor of 2.
3.5 The pn Junction with an Applied Voltage
Having studied the open-circuited pn junction in detail, we are now ready to apply a dc voltage between its two terminals to find its electrical conduction properties. If the voltage is applied so that the p side is made more positive than the n side, it is referred to as a forward-bias6 voltage. Conversely, if our applied dc voltage is such that it makes the n side more positive than the p side, it is said to be a reverse-bias voltage. As will be seen, the pn junction exhibits vastly different conduction properties in its forward and reverse directions.
Our plan is as follows. We begin by a simple qualitative description in Section 3.5.1 and then consider an analytical description of the i–v characteristic of the junction in Section 3.5.2.
3.5.1 Qualitative Description of Junction Operation
Figure 3.11 shows the pn junction under three different conditions: (a) the open-circuit or equilibrium condition studied in the previous section; (b) the reverse-bias condition, where a dc voltage VR is applied; and (c) the forward-bias condition, where a dc voltage VF is applied.
6 For the time being, we take the term bias to refer simply to the application of a dc voltage. We will see in later chapters that it has a deeper meaning in the design of electronic circuits.
156 Chapter 3 Semiconductors
VR VF ID ID ID
IS IS IS
pnpnpn
V0 (V0 VR) (V0 VF)
(a) Open-circuit (b) Reverse bias (c) Forward bias (equilibrium)
Figure3.11 Thepnjunctionin:(a)equilibrium;(b)reversebias;(c)forwardbias.
Observe that in the open-circuit case, a barrier voltage V0 develops, making n more positive than p, and limiting the diffusion current ID to a value exactly equal to the drift current IS, thus resulting in a zero current at the junction terminals, as should be the case, since the terminals are open-circuited. Also, as mentioned previously, the barrier voltage V0, though it establishes the current equilibrium across the junction, does not in fact appear between the junction terminals.
Consider now the reverse-bias case in (b). The externally applied reverse-bias voltage VR is in the direction to add to the barrier voltage, and it does, thus increasing the effective barrier voltage to (V0 + VR ) as shown. This reduces the number of holes that diffuse into the n region and the number of electrons that diffuse into the p region. The end result is that the diffusion current ID is dramatically reduced. As will be seen shortly, a reverse-bias voltage of a volt or so is sufficient to cause ID ≃ 0, and the current across the junction and through the external circuit will be equal to IS . Recalling that IS is the current due to the drift across the depletion region of the thermally generated minority carriers, we expect IS to be very small and to be strongly dependent on temperature. We will show this to be the case very shortly. We thus conclude that in the reverse direction, the pn junction conducts a very small and almost-constant current equal to IS .
Before leaving the reverse-bias case, observe that the increase in barrier voltage will be accompanied by a corresponding increase in the stored uncovered charge on both sides of the depletion region. This in turn means a wider depletion region, needed to uncover the additional charge required to support the larger barrier voltage (V0 + VR ). Analytically, these results can be obtained easily by a simple extension of the results of the equilibrium case. Thus the width of the depletion region can be obtained by replacing V0 in Eq. (3.26) by (V0 + VR ),
W=xn+xp= 2es 1+1 (V0+VR) (3.31)
q NA ND
and the magnitude of the charge stored on either side of the depletion region can be determined byreplacingV0 inEq.(3.30)by(V0+VR),
NN
QJ =A 2esq A D (V0+VR) (3.32)
NA +ND
Wenextconsidertheforward-biascaseshowninFig.3.11(c).HeretheappliedvoltageVF is in the direction that subtracts from the built-in voltage V0 , resulting in a reduced barrier voltage (V0 − VF ) across the depletion region. This reduced barrier voltage will be accompanied by reduced depletion-region charge and correspondingly narrower depletion-region width W. Most importantly, the lowering of the barrier voltage will enable more holes to diffuse from p to n and more electrons to diffuse from n to p. Thus the diffusion current ID increases substantially and, as will be seen shortly, can become many orders of magnitude larger than the driftcurrentIS.ThecurrentIintheexternalcircuitisofcoursethedifferencebetweenID andIS,
I = ID − IS
and it flows in the forward direction of the junction, from p to n. We thus conclude that the pn junction can conduct a substantial current in the forward-bias region and that current is mostly a diffusion current whose value is determined by the forward-bias voltage VF .
3.5 The pn Junction with an Applied Voltage 157
158 Chapter 3
Semiconductors
3.5.2 The Current–Voltage Relationship of the Junction
We are now ready to find an analytical expression that describes the current–voltage relationship of the pn junction. In the following we consider a junction operating with a forward applied voltage V and derive an expression for the current I that flows in the forward direction (from p to n). However, our derivation is general and will be seen to yield the reverse current when the applied voltage V is made negative.
From the qualitative description above we know that a forward-bias voltage V subtracts from the built-in voltage V0, thus resulting in a lower barrier voltage (V0 −V). The lowered barrier in turn makes it possible for a greater number of holes to overcome the barrier and diffuse into the n region. A similar statement can be made about electrons from the n region diffusing into the p region.
Let us now consider the holes injected into the n region. The concentration of holes in the n region at the edge of the depletion region will increase considerably. In fact, an important result from device physics shows that the steady-state concentration at the edge of the depletion region will be
pn (xn ) = pn0 eV/VT (3.33)
That is, the concentration of the minority holes increases from the equilibrium value of pn0 (see Fig. 3.10) to the much larger value determined by the value of V, given by Eq. (3.33).
We describe this situation as follows: The forward-bias voltage V results in an excess concentration of minority holes at x = xn , given by
Excess concentration = pn0 eV/VT − pn0
= p eV/VT − 1 (3.34)
n0
The increase in minority-carrier concentration in Eqs. (3.33) and (3.34) occurs at the edge of the depletion region (x = xn ). As the injected holes diffuse into the n material, some will recombine with the majority electrons and disappear. Thus, the excess hole concentration will decay exponentially with distance. As a result, the total hole concentration in the n material will be given by
p (x) = p + (Excess concentration)e−(x−xn )/Lp n n0
Substituting for the “Excess concentration” from Eq. (3.34) gives p (x) = p + p eV/VT − 1e−(x−xn )/Lp
n n0 n0
(3.35)
The exponential decay is characterized by the constant Lp , which is called the diffusion length of holes in the n material. The smaller the value of Lp , the faster the injected holes will recombine with the majority electrons, resulting in a steeper decay of minority-carrier concentration.
Figure 3.12 shows the steady-state minority-carrier concentration profiles on both sides of a pn junction in which NA ≫ ND . Let’s stay a little longer with the diffusion of holes into the n region. Note that the shaded region under the exponential represents the excess minority carriers (holes). From our study of diffusion in Section 3.3, we know that the establishment of a carrier concentration profile such as that in Fig. 3.12 is essential to support a steady-state diffusion current. In fact, we can now find the value of the hole–diffusion current density by applying Eq. (3.19),
J (x) = −qD dpn(x) p pdx
pn, np Depletion
region
pn0
xp 0
Figure 3.12 Minority-carrier distribution in a forward-biased pn junction. It is assumed that the p region is
3.5
The pn Junction with an Applied Voltage 159
p region
np(x)
pn(xn)
n region
Excess concentration
pn(x)
np(xp)
more heavily doped than the n region; NA ≫ ND . Substituting for pn(x) from Eq. (3.35) gives
np0
Thermal equilibrium value
xn
D ( n)p Jp(x)=q p pn0 eV/VT −1 e− x−x /L
Lp As expected, Jp(x) is highest at x = xn,
D Jp(xn)=q p pn0 eV/VT −1
Lp
x
(3.36)
(3.37)
and decays exponentially for x > xn, as the minority holes recombine with the majority electrons. This recombination, however, means that the majority electrons will have to be replenished by a current that injects electrons from the external circuit into the n region of the junction. This latter current component has the same direction as the hole current (because electrons moving from right to left give rise to current in the direction from left to right). It follows that as Jp(x) decreases, the electron current component increases by exactly the same amount, making the total current in the n material constant at the value given by Eq. (3.37).
An exactly parallel development can be applied to the electrons that are injected from the n to the p region, resulting in an electron diffusion current given by a simple adaptation of Eq. (3.37),
D
Jn −xp =q n np0 eV/VT −1 (3.38)
Ln
Now, although the currents in Eqs. (3.37) and (3.38) are found at the two edges of the depletion region, their values do not change in the depletion region. Thus we can drop the location
descriptors (xn), −xp , add the two current densities, and multiply by the junction area A to
160 Chapter 3
Semiconductors
obtain the total current I as
I = A Jp + Jn
D D I = Aq p pn0 + n np0 eV/VT − 1
Lp Ln Substituting for pn0 = ni2/ND and for np0 = ni2/NA gives
D D
I=Aqni2 p + n eV/VT −1 (3.39)
Lp ND Ln NA
From this equation we note that for a negative V (reverse bias) with a magnitude of a few timesVT (25.9mV),theexponentialtermbecomesessentiallyzero,andthecurrentacrossthe junction becomes negative and constant. From our qualitative description in Section 3.5.1, we know that this current must be IS . Thus,
where
I=IeV/VT −1 S
DD IS =Aqni2 p + n
Lp ND Ln NA
(3.40)
(3.41)
Figure 3.13 shows the I–V characteristic of the pn junction (Eq. 3.40). Observe that in the reverse direction the current saturates at a value equal to –IS . For this reason, IS is given the name saturation current. From Eq. (3.41) we see that IS is directly proportional to the cross-sectional area A of the junction. Thus, another name for IS , one we prefer to use in this book, is the junction scale current. Typical values for IS , for junctions of various areas, range from 10−18 A to 10−12 A.
Besides being proportional to the junction area A, the expression for IS in Eq. (3.41) indicates that IS is proportional to ni2, which is a very strong function of temperature (see Eq. 3.2).
I
0
V
IS
Figure3.13 ThepnjunctionI–Vcharacteristic.
3.5 The pn Junction with an Applied Voltage 161
Example 3.6
For the pn junction considered in Example 3.5 for which NA = 1018 /cm3 , ND = 1016 /cm3 , A = 10−4 cm2 , and ni =1.5×1010/cm3, let Lp =5 μm, Ln =10 μm, Dp (in the n region) =10 cm2/V·s, and Dn (in the p region) = 18 cm2 /V· s. The pn junction is forward biased and conducting a current I = 0.1 mA. Calculate: (a) IS ; (b) the forward-bias voltage V; and (c) the component of the current I due to hole injection and that due to electron injection across the junction.
Solution
(a)UsingEq.(3.41),wefindIS as
IS =10−4 ×1.6×10−19 × 1.5×1010
(b) In the forward direction,
Thus,
ForI =0.1mA,
2
× 10 + 18 5×10−4 ×1016 10×10−4 ×1018
=7.3×10−15A
I=IeV/VT −1
S
≃ I eV/VT S
V=VTln I IS
(c) The hole-injection component of I can be found using Eq. (3.37) I =AqDpp eV/VT −1
=AqDp ni2 eV/VT −1 Lp ND
Similarly, In can be found using Eq. (3.39),
I =AqDn ni2 eV/VT −1
V =25.9×10−3 ln = 0.605 V
0.1×10−3 7.3 × 10−15
p Ln0 p
Thus,
For our case,
n
Ln NA
I D L N
p=pnA In Dn Lp ND
I 10 10 1018
p = × × 16 =1.11×102 =111
In 18 5 10
162
Chapter 3 Semiconductors
Example 3.6 continued
Thus most of the current is conducted by holes injected into the n region. Specifically,
Ip =111×0.1=0.0991mA 112
In = 1 ×0.1=0.0009mA 112
This stands to reason, since the p material has a doping concentration 100 times that of the n material.
EXERCISES
3.10 ShowthatifNA ≫ND,
IS≃Aqni2 Dp Lp ND
3.11 ForthepnjunctioninExample3.6,findthevalueofIS andthatofthecurrentIatV=0.605V(same voltage found in Example 3.6 at a current I = 0.1 mA) if ND is reduced by a factor of 2.
Ans. 1.46×10−14 A;0.2mA
3.12 For the pn junction considered in Examples 3.5 and 3.6, find the width of the depletion region W corresponding to the forward-bias voltage found in Example 3.6. (Hint: Use the formula in Eq. (3.31) withVR replacedwith−VF.)
Ans. 0.166 μm
3.13 ForthepnjunctionconsideredinExamples3.5and3.6,findthewidthofthedepletionregionWand the charge stored in the depletion region QJ when a 2-V reverse bias is applied. Also find the value of the reverse current I.
Ans. 0.608 μm; 9.63 pC; 7.3 × 10−15 A
3.5.3 Reverse Breakdown
The description of the operation of the pn junction in the reverse direction, and the I−V relationship of the junction in Eq. (3.40), indicate that at a reverse-bias voltage –V, with V ≫ VT , the reverse current that flows across the junction is approximately equal to IS and thus is very small. However, as the magnitude of the reverse-bias voltage V is increased, a value is reached at which a very large reverse current flows as shown in Fig. 3.14. Observe that as V reaches the value VZ , the dramatic increase in reverse current is accompanied by a very small increase in the reverse voltage; that is, the reverse voltage across the junction
3.5 The pn Junction with an Applied Voltage 163
VZ
I
0
remains very close to the value VZ . The phenomenon that occurs at V = VZ is known as junction breakdown. It is not a destructive phenomenon. That is, the pn junction can be repeatedly operated in the breakdown region without a permanent effect on its characteristics. This, however, is predicated on the assumption that the magnitude of the reverse-breakdown current is limited by the external circuit to a “safe” value. The “safe” value is one that results in the limitation of the power dissipated in the junction to a safe, allowable level.
There are two possible mechanisms for pn junction breakdown: the zener effect7 and the avalanche effect. If a pn junction breaks down with a breakdown voltage VZ < 5 V, the breakdown mechanism is usually the zener effect. Avalanche breakdown occurs when VZ is greater than approximately 7 V. For junctions that break down between 5 V and 7 V, the breakdown mechanism can be either the zener or the avalanche effect or a combination of the two.
Zener breakdown occurs when the electric field in the depletion layer increases to the point of breaking covalent bonds and generating electron–hole pairs. The electrons generated in this way will be swept by the electric field into the n side and the holes into the p side. Thus these electrons and holes constitute a reverse current across the junction. Once the zener effect starts, a large number of carriers can be generated, with a negligible increase in the junction voltage. Thus the reverse current in the breakdown region will be large and its value must be determined by the external circuit, while the reverse voltage appearing between the diode terminals will remain close to the specified breakdown voltage VZ .
The other breakdown mechanism, avalanche breakdown, occurs when the minority carriers that cross the depletion region under the influence of the electric field gain sufficient kinetic energy to be able to break covalent bonds in atoms with which they collide. The carriers liberated by this process may have sufficiently high energy to be able to cause other carriers to be liberated in another ionizing collision. This process keeps repeating in the fashion of an avalanche, with the result that many carriers are created that are able to support any value of
7Namedafteranearlyworkerinthearea.NotethatthesubscriptZinVZ denoteszener.WewilluseVZ to denote the breakdown voltage whether the breakdown mechanism is the zener effect or the avalanche effect.
V
Figure3.14 TheI–Vcharacteristicofthepn junction showing the rapid increase in reverse current in the breakdown region.
164 Chapter 3
Semiconductors
reverse current, as determined by the external circuit, with a negligible change in the voltage drop across the junction.
As will be seen in Chapter 4, some pn junction diodes are fabricated to operate specifically in the breakdown region, where use is made of the nearly constant voltage VZ .
3.6 Capacitive Effects in the pn Junction
There are two charge-storage mechanisms in the pn junction. One is associated with the charge stored in the depletion region, and the other is associated with the minority-carrier charge stored in the n and p materials as a result of the concentration profiles established by carrier injection. While the first is easier to see when the pn junction is reverse biased, the second is in effect only when the junction is forward biased.
3.6.1 Depletion or Junction Capacitance
When a pn junction is reverse biased with a voltage VR, the charge stored on either side of the depletion region is given by Eq. (3.32),
QJ=A2esqNAND (V0+VR) NA +ND
QJ=α V0+VR
it difficult to define a capacitance that accounts for the need to change QJ whenever VR is
Thus, for a given pn junction,
where α is given by
(3.42)
α = A 2esq NAND NA +ND
(3.43) ThusQJ isnonlinearlyrelatedtoVR,asshowninFig.3.15.Thisnonlinearrelationshipmakes
Slope CJ
Q
Bias point
0
VQ
Reverse voltage,VR
Figure 3.15 The charge stored on either side of the depletion layer as a function of the reverse voltage VR .
Charge stored in depletion layer, QJ
changed. We can, however, assume that the junction is operating at a point such as Q, as indicated in Fig. 3.15, and define a capacitance Cj that relates the change in the charge QJ to a change in the voltage VR,
dQ
Cj = J (3.44)
dVR VR =VQ
This incremental-capacitance approach turns out to be quite useful in electronic circuit design, as we shall see throughout this book.
3.6 Capacitive Effects in the pn Junction 165
Using Eq. (3.44) together with Eq. (3.42) yields
Cj = α
2 V0+VR
The value of Cj at zero reverse bias can be obtained from Eq. (3.45) as α
which enables us to express Cj as
Cj = Cj0
1 + VR
V0
where Cj0 is given by Eq. (3.46) or alternatively if we substitute for α from Eq. (3.43) by
eqNN 1
Cj0=A s A D (3.48)
Before leaving the subject of depletion-region or junction capacitance we point out that in the pn junction we have been studying, the doping concentration is made to change abruptly at the junction boundary. Such a junction is known as an abrupt junction. There is another type of pn junction in which the carrier concentration is made to change gradually from one side of the junction to the other. To allow for such a graded junction, the formula for the junction capacitance (Eq. 3.47) can be written in the more general form
Cj = Cj0 m (3.49) 1 + VR
V0
where m is a constant called the grading coefficient, whose value ranges from 1/3 to 1/2 depending on the manner in which the concentration changes from the p to the n side.
Cj0 =
2 V0
(3.45)
(3.46)
(3.47)
2 NA +ND V0
166 Chapter 3 Semiconductors
EXERCISE
3.14 For the pn junction considered in Examples 3.5 and 3.6, find Cj0 and Cj at VR = 2 V. Recall that V0 = 0.814 V, NA = 1018/cm3, ND = 1016/cm3, and A = 10−4 cm2.
Ans. 3.2 pF; 1.7 pF
3.6.2 Diffusion Capacitance
Consider a forward-biased pn junction. In steady state, minority-carrier distributions in the p and n materials are established, as shown in Fig. 3.12. Thus a certain amount of excess minority-carrier charge is stored in each of the p and n bulk regions (outside the depletion region). If the terminal voltage V changes, this charge will have to change before a new steady state is achieved. This charge-storage phenomenon gives rise to another capacitive effect, distinctly different from that due to charge storage in the depletion region.
To calculate the excess minority-carrier charge, refer to Fig. 3.12. The excess hole charge stored in the n region can be found from the shaded area under the exponential as follows:8
Qp = Aq × shaded area under the pn (x)curve =Aq[pn(xn)−pn0]Lp
Substitutingforpn(xn)fromEq.(3.33)andusingEq.(3.37)enablesustoexpressQp as
Lp2
Qp = D Ip (3.50)
p
ThefactorL2/DthatrelatesQ toI isausefuldeviceparameterthathasthedimensionof pppp
time (s) and is denoted τp
Thus,
Lp2
τp = D Qp = τpIp
(3.51)
(3.52)
The time constant τp is known as the excess minority-carrier (hole) lifetime. It is the average time it takes for a hole injected into the n region to recombine with a majority electron. This definition of τp implies that the entire charge Qp disappears and has to be replenished every τp seconds. The current that accomplishes the replenishing is Ip = Qp/τp. This is an alternate derivation for Eq. (3.52).
8Recall that the area under an exponential curve Ae−x/B is equal to AB.
p
3.6 Capacitive Effects in the pn Junction 167 A relationship similar to that in Eq. (3.52) can be developed for the electron charge stored
in the p region,
Qn =τnIn (3.53) where τn is the electron lifetime in the p region. The total excess minority-carrier charge can
be obtained by adding together Qp and Qn,
Q=τpIp +τnIn (3.54)
This charge can be expressed in terms of the diode current I = Ip + In as
Q = τT I (3.55)
where τT is called the mean transit time of the junction. Obviously, τT is related to τp and τn . Furthermore, for most practical devices, one side of the junction is much more heavily doped thantheother.Forinstance,ifNA ≫ND,onecanshowthatIp ≫In,I≃Ip,Qp ≫Qn,Q≃Qp, andthusτT ≃τp.
For small changes around a bias point, we can define an incremental diffusion capacitanceCd as
and can show that
Cd = dQ dV
τ Cd = T I
VT
(3.56)
(3.57)
whereIistheforward-biascurrent.NotethatCd isdirectlyproportionaltotheforwardcurrent Iandthusisnegligiblysmallwhenthediodeisreversebiased.AlsonotethattokeepCd small, the transit time τT must be made small, an important requirement for a pn junction intended for high-speed or high-frequency operation.
EXERCISES
3.15 Use the definition of Cd in Eq. (3.56) to derive the expression in Eq. (3.57) by means of Eqs. (3.55) and (3.40).
3.16 For the pn junction considered in Examples 3.5 and 3.6 for which Dp = 10 cm2 /V · s, and Lp = 5 μm, find τp and Cd at a forward-bias current of 0.1 mA. Recall that for this junction, Ip ≃ I .
Ans. 25 ns; 96.5 pF
168 Chapter 3 Semiconductors Summary
Today’s microelectronics technology is almost entirely based on the semiconductor material silicon. If a circuit is to be fabricated as a monolithic integrated circuit (IC) it is made using a single silicon crystal, no matter how large the circuit is (a recent chip contains 4.31 billion transistors).
In a crystal of intrinsic or pure silicon, the atoms are held in position by covalent bonds. At very low temperatures, all the bonds are intact, and no charge carriers are available to conduct electrical current. Thus, at such low temperatures, silicon behaves as an insulator.
At room temperature, thermal energy causes some of the covalent bonds to break, thus generating free electrons and holes that become available for current conduction.
Current in semiconductors is carried by free electrons and holes. Their numbers are equal and relatively small in intrinsic silicon.
The conductivity of silicon can be increased dramatically by introducing small amounts of appropriate impurity materials into the silicon crystal in a process called doping.
There are two kinds of doped semiconductor: n-type, in which electrons are abundant, and p-type, in which holes are abundant.
There are two mechanisms for the transport of charge carriers in semiconductors: drift and diffusion.
Carrier drift results when an electric field E is applied across a piece of silicon. The electric field accelerates the holes in the direction of E and the electrons in the direction opposite to E. These two current components add together to produce a drift current in the direction of E.
Carrier diffusion occurs when the concentration of charge carriers is made higher in one part of the silicon crystal than in other parts. To establish a steady-state diffusion current, a carrier concentration gradient must be maintained in the silicon crystal.
A basic semiconductor structure is the pn junction. It is fabricated in a silicon crystal by creating a p region in close proximity to an n region. The pn junction is a diode and plays a dominant role in the structure and operation of transistors.
When the terminals of the pn junction are left open, no current flows externally. However, two equal and
opposite currents, ID and IS, flow across the junction, and equilibrium is maintained by a built-in voltage V0 that develops across the junction, with the n side positive relative to the p side. Note, however, that the voltage across an open junction is 0 V, since V0 is canceled by potentials appearing at the metal-to-semiconductor connection interfaces.
The voltage V0 appears across the depletion region, which extends on both sides of the junction.
The diffusion current ID is carried by holes diffusing from p to n and electrons diffusing from n to p. ID flows from p to n, which is the forward direction of the junction. Its value depends on V0 .
The drift current IS is carried by thermally generated minority electrons in the p material that are swept across the depletion layer into the n side, and by thermally generated minority holes in the n side that are swept across the depletion region into the p side. IS flows from n to p, in the reverse direction of the junction, and its value is a strong function of temperature but independent of V0.
Forward biasing the pn junction, that is, applying an external voltage V that makes p more positive than n, reduces the barrier voltage to V0 − V and results in an exponential increase in ID while IS remains unchanged. The net result is a substantial current I = ID − IS that flows across the junction and through the external circuit.
Applying a negative V reverse biases the junction and increases the barrier voltage, with the result that ID is reduced to almost zero and the net current across the junction becomes the very small reverse current IS .
If the reverse voltage is increased in magnitude to a value VZ specific to the particular junction, the junction breaks down, and a large reverse current flows. The value of the reverse current must be limited by the external circuit.
Whenever the voltage across a pn junction is changed, some time has to pass before steady state is reached. This is due to the charge-storage effects in the junction, which are modeled by two capacitances: the junction capacitance Cj andthediffusioncapacitanceCd.
For future reference, we present in Table 3.1 a summary of pertinent relationships and the values of physical constants.
Summary 169
Table 3.1 Summary of Important Equations
Quantity
Carrier concentration in intrinsic silicon (cm−3)
Diffusion current density (A/cm2)
Drift current density (A/cm2 )
Resistivity ( · cm)
Relationship between mobility and diffusivity
Carrier concentration in n-type silicon (cm−3 )
Carrier concentration in p-type silicon (cm−3)
Junction built-in voltage (V)
Width of depletion region (cm)
Relationship
n =BT3/2e−Eg/2kT i
J =−qD dp p p dx
J =qD dn
Values of Constants and Parameters (for Intrinsic Si at T = 300 K)
B=7.3×1015 cm−3K−3/2 Eg = 1.12 eV
k=8.62×10−5 eV/K ni = 1.5 × 1010 /cm3
J
=qpμ +nμ E p n
μ =480cm2/V·s p
μn = 1350 cm2 /V · s
μp and μn decrease with the increase in
doping concentration
VT =kT/q≃25.9mV
q=1.60×10−19 coulomb D =12cm2/s
n
drift
n dx
p Dn=34cm2/s
ρ = 1/ q pμp + nμn
Dn =Dp =VT
μn nn0
pn0 pp0
n p 0
μp ≃ND
=ni2/ND ≃NA
= n i2 / N A NN
V=Vln AD 0 T ni2
xn = NA
xp ND W=xn+xp
es = 11.7e0
e =8.854×10−14 F/cm 0
=2es 1+1V+V qNN0R
AD
170 Chapter 3 Semiconductors
Table 3.1 continued Quantity
Charge stored in depletion layer (coulomb)
Forward current (A)
Saturation current (A)
I–V relationship
Minority-carrier lifetime (s)
Minority-carrier charge storage (coulomb)
Depletion capacitance (F)
Diffusion capacitance (F)
Relationship
QJ=qNAND AW NA +ND
Values of Constants and Parameters (for Intrinsic Si at T = 300 K)
I =Ip+In
2 Dp V/V
Ip=AqniLN eT−1 pD
D In=Aqni2 n eV/VT −1
Ln NA
IS=Aqni2 Dp+Dn
Lp ND Ln NA
I=ISeV/VT−1
τp =Lp2/Dp τn =Ln2/Dn
Qp=τpIp Qn=τnIn Q=Qp +Qn =τTI
Lp,Ln =1μmto100μm τp,τn =1nsto104 ns
eqNN 1 Cj0=A s A D
2 NA +ND V0 Vm
Cj=Cj0 1+R V0
τ
Cd= T I VT
1 1 m = 3 to 2
If in the following problems the need arises for the values of particular parameters or physical constants that are not stated, please consult Table 3.1.
Section 3.1: Intrinsic Semiconductors
3.1 Find values of the intrinsic carrier concentration ni for silicon at −55°C, 0°C, 20°C, 75°C, and 125°C. At each temperature, what fraction of the atoms is ionized?
Recall that a silicon crystal has approximately 5 × 1022 3
3.2 Calculate the value of ni for gallium arsenide (GaAs) at T = 300 K. The constant B = 3.56 × 1014 cm−3 K−3/2 and the bandgap voltage Eg = 1.42 eV.
Section 3.2: Doped Semiconductors
3.3 For a p-type silicon in which the dopant concentration NA =5×1018/cm3,findtheholeandelectronconcentrations at T = 300 K.
3.4 For a silicon crystal doped with phosphorus, what must
of 3 V is imposed. Let μn = 1350 cm2/V·s and μp = 480cm2/V·s·
3.8 Find the current that flows in a silicon bar of 10-μm length having a 5-μm × 4-μm cross-section and having free-electron and hole densities of 104 /cm3 and 1016 /cm3 , respectively, when a 1 V is applied end-to-end. Use μn = 1200cm2/V·sandμp =500cm2/V·s.
3.9 In a 10-μm-long bar of donor-doped silicon, what donor concentration is needed to realize a current density of 2 mA/μm2 in response to an applied voltage of 1 V? (Note: Although the carrier mobilities change with doping concentration, as a first approximation you may assume μn to be constant and use 1350 cm2 /V · s, the value for intrinsic silicon.)
3.10 Holesarebeingsteadilyinjectedintoaregionofn-type
silicon (connected to other devices, the details of which
are not important for this question). In the steady state, the
excess-hole concentration profile shown in Fig. P3.10 is
established in the n-type silicon region. Here “excess” means
over and above the thermal-equilibrium concentration (in the
absence of hole injection), denoted pn0. If ND = 1016/cm3,
n =1.5×1010/cm3,D =12cm2/s,andW=50nm,findthe ip
density of the current that will flow in the x direction.
atoms/cm .
be if at T = 300 K the hole concentration drops below the intrinsic level by a factor of 108?
3.5 In a phosphorus-doped silicon layer with impurity concentration of 1017/cm3, find the hole and electron con- centrations at 27°C and 125°C.
Section 3.3: Current Flow in Semiconductors
3.6 A young designer, aiming to develop intuition concern- ing conducting paths within an integrated circuit, examines the end-to-end resistance of a connecting bar 10-μm long, 3-μm wide, and 1 μm thick, made of various materials. The designer considers:
(a) intrinsic silicon
(b) n-dopedsiliconwithND =5×1016/cm3 (c) n-dopedsiliconwithND =5×1018/cm3 (d) p-dopedsiliconwithNA =5×1016/cm3 (e) aluminum with resistivity of 2.8 μ· cm
Find the resistance in each case. For intrinsic silicon, use the data in Table 3.1. For doped silicon, assume μn = 3μp = 1200 cm2/V · s. (Recall that R = ρL/A.)
3.7 Contrast the electron and hole drift velocities through a 10-μm layer of intrinsic silicon across which a voltage
N
D
PROBLEMS
108 p n0
pn0
pn(x)
n region
0Wx Figure P3.10
3.11 Boththecarriermobilityandthediffusivitydecreaseas the doping concentration of silicon is increased. Table P3.11 provides a few data points for μn and μp versus doping concentration. Use the Einstein relationship to obtain the corresponding values for Dn and Dp .
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
172 Chapter 3 Semiconductors Table P3.11
Doping Concentration
(carriers/cm3) μn (cm2/V·s)
Intrinsic 1350 1016 1200 1017 750 1018 380
Section 3.4: The pn Junction
3.12 Calculatethebuilt-involtageofajunctioninwhichthe
pandnregionsaredopedequallywith5×1016 atoms/cm3.
μp (cm2/V · s)
480
400
260
160
Dn (cm2/s)
Dp (cm2/s)
CHAPTER 3 PROBLEMS
Assumen =1.5×1010/cm3.Withtheterminalsleftopen, i0
charge stored on either side of the junction, QJ, can be expressed as
W=W 1+VR V0
what is the width of the depletion region, and how far does it extend into the p and n regions? If the cross-sectional area of the junction is 20 μm2, find the magnitude of the charge stored on either side of the junction.
3.13 If, for a particular junction, the acceptor concentration is 1017 /cm3 and the donor concentration is 1016 /cm3 , find the junctionbuilt-involtage.Assumeni =1.5×1010/cm3.Also, find the width of the depletion region (W) and its extent in each of the p and n regions when the junction terminals are left open. Calculate the magnitude of the charge stored on either side of the junction. Assume that the junction area is 100 μm2 .
3.14 Estimate the total charge stored in a 0.1-μm depletion
QJ =QJ0
are the values in equilibrium.
3.19 In a forward-biased pn junction show that the ratio of the current component due to hole injection across the junction to the component due to electron injection is given by
Ip = Dp Ln NA In Dn Lp ND
1+VR V0
layer on one side of a 10-μm × 10-μm junction. The doping
183 AD
concentration on that side of the junction is 10 /cm .
Evaluate this ratio for the case N = 1018 /cm3 , N = 1016/cm3, Lp =5 μm, Ln =10 μm, Dp =10 cm2/s, and Dn = 20 cm2 /s, and hence find Ip and In for the case in which the pn junction is conducting a forward current I=100μA.
3.20 Calculate IS and the current I for V = 750 mV for a pn junction for which NA = 1017 /cm3 , ND = 1016 /cm3 , A=100μm2,ni =1.5×1010/cm3,Lp =5μm,Ln =10μm, Dp = 10 cm2/s, and Dn = 18 cm2/s.
3.21 Assuming that the temperature dependence of IS arises mostlybecauseIS isproportionaltoni2,usetheexpressionfor ni in Eq. (3.2) to determine the factor by which ni2 changes as T changes from 300 K to 305 K. This will be approximately the same factor by which IS changes for a 5°C rise in temperature. What is the factor?
3.15 In a pn junction for which NA ≫ ND , and the depletion layer exists mostly on the shallowly doped side with W = 0.2 μm, find V0 if ND = 1016/cm3. Also calculate QJ for the case A = 10 μm2 .
3.16 By how much does V0 change if NA or ND is increased by a factor of 10?
Section 3.5: The pn Junction with an Applied Voltage
3.17 If a 3-V reverse-bias voltage is applied across the junction specified in Problem 3.13, find W and QJ .
3.18 Show that for a pn junction reverse-biased with a voltage VR, the depletion-layer width W and the
where W
0 J0
and Q
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
3.22 A p+ n junction is one in which the doping concentration in the p region is much greater than that in the n region. In such a junction, the forward current is mostly due to hole injection across the junction. Show that
Problems 173 to have at I = 0.1 mA? What is the mean transit time for this
junction?
3.28 For the p+n junction specified in Problem 3.22, find τp and calculate the excess minority-carrier charge and the value of the diffusion capacitance at I = 0.1 mA.
*3.29 A short-base diode is one where the widths of the p and n regions are much smaller than Ln and Lp, respectively. As a result, the excess minority-carrier distribution in each region is a straight line rather than the exponentials shown in Fig. 3.12.
CHAPTER 3 PROBLEMS
2 Dp V/V I≃I =Aqn e T −1
p i LpND
For the specific case in which ND = 1017 /cm3 , Dp = 10 cm2 /s, Lp =10 μm, and A=104 μm2, find IS and the voltage V obtained when I = 1 mA. Assume operation at 300 K where ni =1.5×1010/cm3.
3.23 A pn junction for which the breakdown voltage is 12 V has a rated (i.e., maximum allowable) power dissipation of 0.25 W. What continuous current in the breakdown region will raise the dissipation to half the rated value? If breakdown occurs for only 10 ms in every 20 ms, what average breakdown current is allowed?
Section 3.6: Capacitive Effects in the pn Junction
3.24 For the pn junction specified in Problem 3.13, find Cj0 andCj atVR =3V.
3.25 For a particular junction for which Cj0 = 0.4 pF, V0 = 0.75 V, and m = 1/3, find C at reverse-bias voltages of 1 V
j
and 10 V.
3.26 The junction capacitance Cj can be thought of as that of a parallel-plate capacitor and thus given by
(a) (b)
For the short-base diode, sketch a figure corresponding to Fig. 3.12 and assume as in Fig. 3.12 that NA ≫ ND . Following a derivation similar to that given in Section 3.5.2, show that if the widths of the p and n regions are denoted Wp and Wn then
I=Aqn2 i
and
Dp + Dn eV/VT −1
Wn−xn ND Wp−xp NA
2 Q =1 Wn−xn I
p2Dp p
1 W n2
≃2D Ip,forWn≫xn
p
C = eA
jW VT
Show that this approach leads to a formula identical to that obtained by combining Eqs. (3.43) and (3.45) [or equivalently, by combining Eqs. (3.47) and (3.48)].
3.27 Apnjunctionoperatingintheforward-biasregionwith a current I of 1 mA is found to have a diffusion capacitance of 5 pF. What diffusion capacitance do you expect this junction
Also, assuming Q ≃ Qp, I ≃ Ip, show that Cd = τT I
where
τ T = 1 W n2 2 Dp
(d) IfadesignerwishestolimitCd to8pFatI=1mA,what should Wn be? Assume Dp = 10 cm2 /s.
(c)
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
CHAPTER 4
Diodes
Introduction 175
4.1 The Ideal Diode 176
4.2 Terminal Characteristics of Junction Diodes 184
4.3 Modeling the Diode Forward Characteristic 190
4.4 Operation in the Reverse Breakdown Region—ZenerDiodes 202
4.5 Rectifier Circuits 207
4.6 Limiting and Clamping Circuits 221 4.7 Special Diode Types 227
Summary 229 Problems 230
IN THIS CHAPTER YOU WILL LEARN
1. The characteristics of the ideal diode and how to analyze and design circuits containing multiple ideal diodes together with resistors and dc sources to realize useful and interesting nonlinear functions.
2. The details of the i–v characteristic of the junction diode (which was derived in Chapter 3) and how to use it to analyze diode circuits operating in the various bias regions: forward, reverse, and breakdown.
3. A simple but effective model of the diode i–v characteristic in the forward direction: the constant-voltage-drop model.
4. A powerful technique for the application and modeling of the diode (and in later chapters, transistors): dc-biasing the diode and modeling its operation for small signals around the dc operating point by means of the small-signal model.
5. The use of a string of forward-biased diodes and of diodes operating in the breakdown region (zener diodes), to provide constant dc voltages (voltage regulators).
6. Application of the diode in the design of rectifier circuits, which convert ac voltages to dc as needed for powering electronic equipment.
7. A number of other practical and important applications of diodes.
Introduction
In Chapters 1 and 2 we dealt almost entirely with linear circuits; any nonlinearity, such as that introduced by amplifier output saturation, was treated as a problem to be solved by the circuit designer. However, there are many other signal-processing functions that can be implemented only by nonlinear circuits. Examples include the generation of dc voltages from the ac power supply, and the generation of signals of various waveforms (e.g., sinusoids, square waves, pulses). Also, digital logic and memory circuits constitute a special class of nonlinear circuits.
The simplest and most fundamental nonlinear circuit element is the diode. Just like a resistor, the diode has two terminals; but unlike the resistor, which has a linear (straight-line) relationship between the current flowing through it and the voltage appearing across it, the diode has a nonlinear i–v characteristic.
This chapter is concerned with the study of diodes. In order to understand the essence of the diode function, we begin with a fictitious element, the ideal diode. We then introduce the silicon junction diode, explain its terminal characteristics, and provide techniques for the
175
176 Chapter 4
Diodes
analysis of diode circuits. The latter task involves the important subject of device modeling. Our study of modeling the diode characteristics will lay the foundation for our study of modeling transistor operation in the next three chapters.
Of the many applications of diodes, their use in the design of rectifiers (which convert ac to dc) is the most common. Therefore we shall study rectifier circuits in some detail and briefly look at a number of other diode applications. Further nonlinear circuits that utilize diodes and other devices will be found throughout the book, but particularly in Chapter 18.
The junction diode is nothing more than the pn junction we studied in Chapter 3, and most of this chapter is concerned with the study of silicon pn-junction diodes. In the last section, however, we briefly consider some specialized diode types, including the photodiode and the light-emitting diode.
4.1 The Ideal Diode
4.1.1 Current–Voltage Characteristic
The ideal diode may be considered to be the most fundamental nonlinear circuit element. It is a two-terminal device having the circuit symbol of Fig. 4.1(a) and the i–v characteristic shown in Fig. 4.1(b). The terminal characteristic of the ideal diode can be interpreted as follows: If a negative voltage (relative to the reference direction indicated in Fig. 4.1a) is applied to the diode, no current flows and the diode behaves as an open circuit (Fig. 4.1c). Diodes operated in this mode are said to be reverse biased, or operated in the reverse direction. An ideal diode has zero current when operated in the reverse direction and is said to be cut off, or simply off.
On the other hand, if a positive current (relative to the reference direction indicated in Fig. 4.1(a) is applied to the ideal diode, zero voltage drop appears across the diode. In other words, the ideal diode behaves as a short circuit in the forward direction (Fig. 4.1d); it passes any current with zero voltage drop. A forward-biased diode is said to be turned on, or simply on.
From the above description it should be noted that the external circuit must be designed to limit the forward current through a conducting diode, and the reverse voltage across a cutoff diode, to predetermined values. Figure 4.2 shows two diode circuits that illustrate this point. In the circuit of Fig. 4.2(a) the diode is obviously conducting. Thus its voltage drop will be zero, and the current through it will be determined by the +10-V supply and the 1-k resistor as 10 mA. The diode in the circuit of Fig. 4.2(b) is obviously cut off, and thus its current will be zero, which in turn means that the entire 10-V supply will appear as reverse bias across the diode.
The positive terminal of the diode is called the anode and the negative terminal the cathode, a carryover from the days of vacuum-tube diodes. The i–v characteristic of the ideal diode (conducting in one direction and not in the other) should explain the choice of its arrow-like circuit symbol.
As should be evident from the preceding description, the i–v characteristic of the ideal diode is highly nonlinear; although it consists of two straight-line segments, they are at 90° to one another. A nonlinear curve that consists of straight-line segments is said to be piecewise linear. If a device having a piecewise-linear characteristic is used in a particular application in such a way that the signal across its terminals swings along only one of the linear segments, then the device can be considered a linear circuit element as far as that particular circuit
4.1 The Ideal Diode 177
i
v
Figure 4.1 The ideal diode: (a) diode circuit symbol; (b) i–v characteristic; (c) equivalent circuit in the reverse direction; (d) equivalent circuit in the forward direction.
Figure 4.2 The two modes of operation of ideal diodes and the
use of an external circuit to limit (a) the forward current and (b) the (a) (b) reverse voltage.
application is concerned. On the other hand, if signals swing past one or more of the break points in the characteristic, linear analysis is no longer possible.
4.1.2 A Simple Application: The Rectifier
A fundamental application of the diode, one that makes use of its severely nonlinear i–v curve, is the rectifier circuit shown in Fig. 4.3(a). The circuit consists of the series connection of a diode D and a resistor R. Let the input voltage vI be the sinusoid shown in Fig. 4.3(b), and assume the diode to be ideal. During the positive half-cycles of the input sinusoid, the positive
178 Chapter 4
Diodes
vI will cause current to flow through the diode in its forward direction. It follows that the diode voltage vD will be very small—ideally zero. Thus the circuit will have the equivalent shown in Fig. 4.3(c), and the output voltage vO will be equal to the input voltage vI . On the other hand, during the negative half-cycles of vI , the diode will not conduct. Thus the circuit will have the equivalent shown in Fig. 4.3(d), and vO will be zero. Thus the output voltage willhavethewaveformshowninFig.4.3(e).NotethatwhilevI alternatesinpolarityandhas a zero average value, vO is unidirectional and has a finite average value or a dc component. Thus the circuit of Fig. 4.3(a) rectifies the signal and hence is called a rectifier. It can be used to generate dc from ac. We will study rectifier circuits in Section 4.5.
D
(a) (b)
vI 0
(c) (e)
vI 0 (d)
Figure 4.3 (a) Rectifier circuit. (b) Input waveform. (c) Equivalent circuit when vI ≥ 0. (d) Equivalent circuit when vI ≤ 0. (e) Output waveform.
4.1 The Ideal Diode 179
EXERCISES
4.1 ForthecircuitinFig.4.3(a),sketchthetransfercharacteristicvO versusvI. Ans. See Fig. E4.1
Figure E4.1
4.2 For the circuit in Fig. 4.3(a), sketch the waveform of vD. Ans. vD =vI −vO,resultinginthewaveforminFig.E4.2
vD
0
–Vp
Figure E4.2
t
4.3 In the circuit of Fig. 4.3(a), let vI have a peak value of 10 V and R = 1 k. Find the peak value of iD and the dc component of vO. (Hint: The average value of half-sine waves is Vp/π.)
Ans. 10 mA; 3.18 V
180 Chapter 4 Diodes
Example 4.1
Figure 4.4(a) shows a circuit for charging a 12-V battery. If vS is a sinusoid with 24-V peak amplitude, find the fraction of each cycle during which the diode conducts. Also, find the peak value of the diode current and the maximum reverse-bias voltage that appears across the diode.
(a) (b)
Figure 4.4 Circuit and waveforms for Example 4.1. Solution
ThediodeconductswhenvS exceeds12V,asshowninFig.4.4(b).Theconductionangleis2θ,whereθ is given by
24 cos θ = 12
Thus θ = 60° and the conduction angle is 120°, or one-third of a cycle.
The peak value of the diode current is given by
Id = 24−12 =0.12A
100
The maximum reverse voltage across the diode occurs when vS is at its negative peak and is equal to
24+12=36V.
4.1.3 Another Application: Diode Logic Gates
Diodes together with resistors can be used to implement digital logic functions. Figure 4.5 shows two diode logic gates. To see how these circuits function, consider a positive-logic system in which voltage values close to 0 V correspond to logic 0 (or low) and voltage values close to +5 V correspond to logic 1 (or high). The circuit in Fig. 4.5(a) has three inputs, vA, vB, and vC. It is easy to see that diodes connected to +5-V inputs will conduct, thus clamping theoutputvY toavalueequalto+5V.Thispositivevoltageattheoutputwillkeepthediodes whose inputs are low (around 0 V) cut off. Thus the output will be high if one or more of the inputs are high. The circuit therefore implements the logic OR function, which in Boolean
4.1 The Ideal Diode 181
(a) (b)
Figure4.5 Diodelogicgates:(a)ORgate;(b)ANDgate(inapositive-logicsystem). notation is expressed as
Y =A+B+C
Similarly, the reader is encouraged to show that using the same logic system mentioned
above, the circuit of Fig. 4.5(b) implements the logic AND function, Y =A·B·C
Example 4.2
Assuming the diodes to be ideal, find the values of I and V in the circuits of Fig. 4.6.
D
DD
(a) (b)
D
Figure 4.6 Circuits for Example 4.2.
182
Chapter 4 Diodes
Example 4.2 continued Solution
In these circuits it might not be obvious at first sight whether none, one, or both diodes are conducting. In such a case, we make a plausible assumption, proceed with the analysis, and then check whether we end up with a consistent solution. For the circuit in Fig. 4.6(a), we shall assume that both diodes are conducting. It follows that VB = 0 and V = 0. The current through D2 can now be determined from
Writing a node equation at B,
ID2 =10−0=1mA 10
I + 1 = 0 − (−10) 5
results in I = 1 mA. Thus D1 is conducting as originally assumed, and the final result is I = 1 mA and V = 0 V.
For the circuit in Fig. 4.6(b), if we assume that both diodes are conducting, then VB = 0 and V = 0. The current in D2 is obtained from
The node equation at B is
ID2 =10−0=2mA 5
I + 2 = 0 − (−10) 10
which yields I = −1 mA. Since this is not possible, our original assumption is not correct. We start again, assuming that D1 is off and D2 is on. The current ID2 is given by
ID2 = 10−(−10) =1.33mA 15
and the voltage at node B is
VB =−10+10×1.33=+3.3V
Thus D1 is reverse biased as assumed, and the final result is I = 0 and V = 3.3 V.
4.1
The Ideal Diode 183
EXERCISES
4.4 Find the values of I and V in the circuits shown in Fig. E4.4.
(a) (b) (c)
(d)
Figure E4.4
(e) (f)
Ans. (a)2mA,0V;(b)0mA,5V;(c)0mA,5V;(d)2mA,0V;(e)3mA,+3V;(f)4mA,+1V 4.5 Figure E4.5 shows a circuit for an ac voltmeter. It utilizes a moving-coil meter that gives a full-scale reading when the average current flowing through it is 1 mA. The moving-coil meter has a 50-
resistance.
184 Chapter 4 Diodes
Moving-coil meter
Figure E4.5
Find the value of R that results in the meter indicating a full-scale reading when the input sine-wave voltage vI is 20 V peak-to-peak. (Hint: The average value of half-sine waves is Vp/π.)
Ans. 3.133 k
4.2 Terminal Characteristics of Junction Diodes
The most common implementation of the diode utilizes a pn junction. We have studied the physics of the pn junction and derived its i–v characteristic in Chapter 3. That the pn junction is used to implement the diode function should come as no surprise: the pn junction can conduct substantial current in the forward direction and almost no current in the reverse direction. In this section we study the i–v characteristic of the pn junction diode in detail in order to prepare ourselves for diode circuit applications.
Figure 4.7 shows the i–v characteristic of a silicon junction diode. The same characteristic is shown in Fig. 4.8 with some scales expanded and others compressed to reveal details. Note that the scale changes have resulted in the apparent discontinuity at the origin.
As indicated, the characteristic curve consists of three distinct regions:
1. The forward-bias region, determined by v > 0
2. The reverse-bias region, determined by v < 0
3. The breakdown region, determined by v < −VZK
These three regions of operation are described in the following sections.
4.2.1 The Forward-Bias Region
The forward-bias—or simply forward—region of operation is entered when the terminal voltage v is positive. In the forward region the i–v relationship is closely approximated by
i=Iev/VT −1 (4.1) S
In this equation1 IS is a constant for a given diode at a given temperature. A formula for IS in terms of the diode’s physical parameters and temperature was given in Eq. (3.41). The current
1 Equation (4.1), the diode equation, is sometimes written to include a constant n in the exponential, i=I(ev/nVT −1)
S
with n having a value between 1 and 2, depending on the material and the physical structure of the
diode. Diodes using the standard integrated-circuit fabrication process exhibit n = 1 when operated under normal conditions. For simplicity, we shall use n = 1 throughout this book, unless otherwise specified.
Figure 4.7 The i–v characteristic of a silicon junction diode.
Figure 4.8 The diode i–v relationship with some scales expanded and others compressed in order to reveal details.
4.2 Terminal Characteristics of Junction Diodes 185
186 Chapter 4
Diodes
IS is usually called the saturation current (for reasons that will become apparent shortly). Another name for IS , and one that we will occasionally use, is the scale current. This name arises from the fact that IS is directly proportional to the cross-sectional area of the diode. Thus doubling of the junction area results in a diode with double the value of IS and, as the diode equation indicates, double the value of current i for a given forward voltage v. For “small-signal” diodes, which are small-size diodes intended for low-power applications, IS is on the order of 10−15 A. The value of IS is, however, a very strong function of temperature. As a rule of thumb, IS doubles in value for every 5°C rise in temperature.
where
ThevoltageVT inEq.(4.1)isaconstantcalledthethermalvoltageandisgivenby VT = kT
k = Boltzmann’s constant = 8.62 × 10−5 eV/K = 1.38 × 10−23 joules/kelvin T = the absolute temperature in kelvins = 273 + temperature in °C
q=themagnitudeofelectroniccharge=1.60×10−19 coulomb Substituting k = 8.62 × 10−5 eV/K into Eq. (4.2) gives
VT =0.0862T,mV
Thus, at room temperature (20°C) the value of VT is 25.3 mV. In rapid approximate circuit analysis we shall use VT ≃ 25 mV at room temperature.2
For appreciable current i in the forward direction, specifically for i ≫ IS , Eq. (4.1) can be approximated by the exponential relationship
i≃ISev/VT (4.3) This relationship can be expressed alternatively in the logarithmic form
v = VT ln i (4.4) IS
where ln denotes the natural (base e) logarithm.
The exponential relationship of the current i to the voltage v holds over many decades
of current (a span of as many as seven decades—i.e., a factor of 107—can be found). This is quite a remarkable property of junction diodes, one that is also found in bipolar junction transistors and that has been exploited in many interesting applications.
Let us consider the forward i–v relationship in Eq. (4.3) and evaluate the current I1 corresponding to a diode voltage V1:
I1 =ISeV1/VT Similarly, if the voltage is V2, the diode current I2 will be
I2 =ISeV2/VT
2A slightly higher ambient temperature (25°C or so) is usually assumed for electronic equipment operatinginsideacabinet.Atthistemperature,VT ≃25.8mV.Nevertheless,forthesakeofsimplicityand to promote rapid circuit analysis, we shall use the more arithmetically convenient value of VT ≃ 25 mV throughout this book.
q
(4.2)
(4.2a)
These two equations can be combined to produce
I2 =e(V2−V1)/VT
4.2
Terminal Characteristics of Junction Diodes 187
which can be rewritten as
or, in terms of base-10 logarithms,
I1
V2 − V1 = VT ln I2
I1
V2−V1=2.3VT logI2 I1
(4.5)
This equation simply states that for a decade (factor of 10) change in current, the diode voltage drop changes by 2.3VT , which is approximately 60 mV. This also suggests that the diode i–v relationship is most conveniently plotted on semilog paper. Using the vertical, linear axis for v and the horizontal, log axis for i, one obtains a straight line with a slope of 60 mV per decade of current.
A glance at the i–v characteristic in the forward region (Fig. 4.8) reveals that the current is negligibly small for v smaller than about 0.5 V. This value is usually referred to as the cut-in voltage. It should be emphasized, however, that this apparent threshold in the characteristic is simply a consequence of the exponential relationship. Another consequence of this relationship is the rapid increase of i. Thus, for a “fully conducting” diode, the voltage drop lies in a narrow range, approximately 0.6 V to 0.8 V. This gives rise to a simple “model” for the diode where it is assumed that a conducting diode has approximately a 0.7-V drop across it. Diodes with different current ratings (i.e., different areas and correspondingly different IS ) will exhibit the 0.7-V drop at different currents. For instance, a small-signal diode may be considered to have a 0.7-V drop at i = 1 mA, while a higher-power diode may have a 0.7-V drop at i = 1 A. We will study the topics of diode-circuit analysis and diode models in the next section.
Example 4.3
A silicon diode said to be a 1-mA device displays a forward voltage of 0.7 V at a current of 1 mA. Evaluate the junction scaling constant IS . What scaling constants would apply for a 1-A diode of the same manufacture that conducts 1 A at 0.7 V?
Solution
Since
then
i=I ev/VT S
I =ie−v/VT S
188
Chapter 4 Diodes
Example 4.3 continued For the 1-mA diode:
IS =10−3e−700/25 =6.9×10−16 A
The diode conducting 1 A at 0.7 V corresponds to one-thousand 1-mA diodes in parallel with a total
junctionarea1000timesgreater.ThusIS isalso1000timesgreater, IS =6.9×10−13 A
Since both IS and VT are functions of temperature, the forward i–v characteristic varies with temperature, as illustrated in Fig. 4.9. At a given constant diode current, the voltage drop across the diode decreases by approximately 2 mV for every 1°C increase in temperature. The change in diode voltage with temperature has been exploited in the design of electronic thermometers.
2 mV°C
Figure 4.9 Temperature dependence of the diode forward characteristic. At a constant current, the voltage drop decreases by approx- imately 2 mV for every 1°C increase in temperature.
4.6 Find the change in diode voltage if the current changes from 0.1 mA to 10 mA. Ans. 120 mV
4.7 Asiliconjunctiondiodehasv=0.7Vati=1mA.Findthevoltagedropati=0.1mAandi=10mA. Ans. 0.64 V; 0.76 V
4.8 Using the fact that a silicon diode has IS = 10−14 A at 25°C and that IS increases by 15% per °C rise in temperature,findthevalueofIS at125°C.
Ans. 1.17 × 10−8 A
EXERCISES
4.2.2 The Reverse-Bias Region
The reverse-bias region of operation is entered when the diode voltage v is made negative. Equation (4.1) predicts that if v is negative and a few times larger than VT (25 mV) in magnitude, the exponential term becomes negligibly small compared to unity, and the diode current becomes
i≃−IS
That is, the current in the reverse direction is constant and equal to IS . This constancy is the reason behind the term saturation current.
Real diodes exhibit reverse currents that, though quite small, are much larger than IS. For instance, a small-signal diode whose IS is on the order of 10−14 A to 10−15 A could show a reverse current on the order of 1 nA. The reverse current also increases somewhat with the increase in magnitude of the reverse voltage. Note that because of the very small magnitude of the current, these details are not clearly evident on the diode i–v characteristic of Fig. 4.8.
A large part of the reverse current is due to leakage effects. These leakage currents are proportional to the junction area, just as IS is. Their dependence on temperature, however, is different from that of IS. Thus, whereas IS doubles for every 5°C rise in temperature, the corresponding rule of thumb for the temperature dependence of the reverse current is that it doubles for every 10°C rise in temperature.
EXERCISE
4.9 ThediodeinthecircuitofFig.E4.9isalargehigh-currentdevicewhosereverseleakageisreasonably independent of voltage. If V = 1 V at 20°C, find the value of V at 40°C and at 0°C.
4.2 Terminal Characteristics of Junction Diodes 189
Ans. 4 V; 0.25 V
Figure E4.9
190 Chapter 4
Diodes
4.2.3 The Breakdown Region
The third distinct region of diode operation is the breakdown region, which can be easily identified on the diode i–v characteristic in Fig. 4.8. The breakdown region is entered when the magnitude of the reverse voltage exceeds a threshold value that is specific to the particular diode, called the breakdown voltage. This is the voltage at the “knee” of the i–v curve in Fig. 4.8 and is denoted VZK , where the subscript Z stands for zener (see Section 3.5.3) and K denotes knee.
As can be seen from Fig. 4.8, in the breakdown region the reverse current increases rapidly, with the associated increase in voltage drop being very small. Diode breakdown is normally not destructive, provided the power dissipated in the diode is limited by external circuitry to a “safe” level. This safe value is normally specified on the device data sheets. It therefore is necessary to limit the reverse current in the breakdown region to a value consistent with the permissible power dissipation.
The fact that the diode i–v characteristic in breakdown is almost a vertical line enables it to be used in voltage regulation. This subject will be studied in Section 4.5.
4.3 Modeling the Diode Forward Characteristic
Having studied the diode terminal characteristics we are now ready to consider the analysis of circuits employing forward-conducting diodes. Figure 4.10 shows such a circuit. It consists of adcsourceVDD,aresistorR,andadiode.Wewishtoanalyzethiscircuittodeterminethediode voltage VD and current ID . To aid in our analysis, we need to represent the diode with a model. There are a variety of diode models, of which we now know two: the ideal-diode model and the exponential model. In the following discussion we shall assess the suitability of these two models in various analysis situations. Also, we shall develop and comment on other models. This material, besides being useful in the analysis and design of diode circuits, establishes a foundation for the modeling of transistor operation that we will study in the next three chapters.
4.3.1 The Exponential Model
The most accurate description of the diode operation in the forward region is provided by the exponential model. Unfortunately, however, its severely nonlinear nature makes this model the most difficult to use. To illustrate, let’s analyze the circuit in Fig. 4.10 using the exponential diode model.
Assuming that VDD is greater than 0.5 V or so, the diode current will be much greater than IS, and we can represent the diode i–v characteristic by the exponential relationship,
ID
+
VD
–
Figure 4.10 A simple circuit used to illustrate the analysis of circuits in which the diode is forward conducting.
resulting in
ID =ISeVD/VT
The other equation that governs circuit operation is obtained by writing a Kirchhoff loop
equation, resulting in
ID = VDD −VD (4.7) R
Assuming that the diode parameter IS is known, Eqs. (4.6) and (4.7) are two equations in the two unknown quantities ID and VD. Two alternative ways for obtaining the solution are graphical analysis and iterative analysis.
4.3.2 Graphical Analysis Using the Exponential Model
Graphical analysis is performed by plotting the relationships of Eqs. (4.6) and (4.7) on the i–v plane. The solution can then be obtained as the coordinates of the point of intersection of the two graphs. A sketch of the graphical construction is shown in Fig. 4.11. The curve represents the exponential diode equation (Eq. 4.6), and the straight line represents Eq. (4.7). Such a straight line is known as the load line, a name that will become more meaningful in later chapters. The load line intersects the diode curve at point Q, which represents the operating point of the circuit. Its coordinates give the values of ID and VD.
Graphical analysis aids in the visualization of circuit operation. However, the effort involved in performing such an analysis, particularly for complex circuits, is too great to be justified in practice.
Figure 4.11 Graphical analysis of the circuit in Fig. 4.10 using the exponential diode model. 4.3.3 Iterative Analysis Using the Exponential Model
Equations (4.6) and (4.7) can be solved using a simple iterative procedure, as illustrated in the following example.
4.3 Modeling the Diode Forward Characteristic 191
(4.6)
192 Chapter 4 Diodes
Example 4.4
Determine the current ID and the diode voltage VD for the circuit in Fig. 4.10 with VDD = 5 V and R = 1 k. Assume that the diode has a current of 1 mA at a voltage of 0.7 V.
Solution
To begin the iteration, we assume that VD = 0.7 V and use Eq. (4.7) to determine the current, ID = VDD −VD
R
= 5−0.7 =4.3mA 1
We then use the diode equation to obtain a better estimate for VD . This can be done by employing Eq. (4.5), namely,
Substituting2.3VT =60mV,wehave
V2 − V1 = 2.3VT log I2 I1
V2 = V1 + 0.06 log I2 I1
Substituting V1 = 0.7 V, I1 = 1 mA, and I2 = 4.3 mA results in V2 = 0.738 V. Thus the results of the first iteration are ID = 4.3 mA and VD = 0.738 V. The second iteration proceeds in a similar manner:
ID = 5−0.738 =4.262mA
1
V2 = 0.738 + 0.06 log 4.262 4.3
= 0.738 V
Thus the second iteration yields ID = 4.262 mA and VD = 0.738 V. Since these values are very close to the values obtained after the first iteration, no further iterations are necessary, and the solution is ID = 4.262 mA and VD = 0.738 V.
4.3.4 The Need for Rapid Analysis
The iterative analysis procedure utilized in the example above is simple and yields accurate results after two or three iterations. Nevertheless, there are situations in which the effort and time required are still greater than can be justified. Specifically, if one is doing a pencil-and-paper design of a relatively complex circuit, rapid circuit analysis is a necessity.
Through quick analysis, the designer is able to evaluate various possibilities before deciding on a suitable circuit design. To speed up the analysis process, one must be content with less precise results. This, however, is seldom a problem, because the more accurate analysis can be postponed until a final or almost-final design is obtained. Accurate analysis of the almost-final design can be performed with the aid of a computer circuit-analysis program such as SPICE (see Appendix B and the website). The results of such an analysis can then be used to further refine or “fine-tune” the design.
To speed up the analysis process, we must find a simpler model for the diode forward characteristic.
4.3.5 The Constant-Voltage-Drop Model
The simplest and most widely used diode model is the constant-voltage-drop model. This model is based on the observation that a forward-conducting diode has a voltage drop that varies in a relatively narrow range, say, 0.6 to 0.8 V. The model assumes this voltage to be constant at a value, say, 0.7 V. This development is illustrated in Fig. 4.12.
The constant-voltage-drop model is the one most frequently employed in the initial phases of analysis and design. This is especially true if at these stages one does not have detailed information about the diode characteristics, which is often the case.
ii
4.3 Modeling the Diode Forward Characteristic 193
(a)
0.7 V v
i
i 0, vD 0.7 V (c)
0 0.7 V v (b)
vD
Figure 4.12 Development of the diode constant-voltage-drop model: (a) the exponential characteristic; (b) approximating the exponential characteristic by a constant voltage, usually about 0.7 Vi ; (c) the resulting model of the forward-conducting diodes.
194 Chapter 4
Diodes
Finally, note that if we employ the constant-voltage-drop model to solve the problem in Example 4.4, we obtain
and
VD =0.7V
ID = VDD −0.7 R
= 5−0.7 =4.3mA 1
which are not very different from the values obtained before with the more elaborate exponential model.
4.3.6 The Ideal-Diode Model
In applications that involve voltages much greater than the diode voltage drop (0.6 V–0.8 V), we may neglect the diode voltage drop altogether while calculating the diode current. The result is the ideal-diode model, which we studied in Section 4.1. For the circuit in Example 4.4 (i.e., Fig. 4.10 with VDD = 5 V and R = 1 k), utilization of the ideal-diode model leads to
VD = 0 V
ID = 5 − 0 = 5 mA
1
which for a very quick analysis would not be bad as a gross estimate. However, with almost no additional work, the 0.7-V-drop model yields much more realistic results. We note, however, that the greatest utility of the ideal-diode model is in determining which diodes are on and which are off in a multidiode circuit, such as those considered in Section 4.1.
EXERCISES
4.10 For the circuit in Fig. 4.10, find ID and VD for the case VDD = 5 V and R = 10 k. Assume that the diode has a voltage of 0.7 V at 1-mA current. Use (a) iteration and (b) the constant-voltage-drop model with VD = 0.7 V.
Ans. (a) 0.43 mA, 0.68 V; (b) 0.43 mA, 0.7 V
D4.11 Design the circuit in Fig. E4.11 to provide an output voltage of 2.4 V. Assume that the diodes available have 0.7-V drop at 1 mA.
Figure E4.11
Ans. R=139
4.12 Repeat Exercise 4.4 using the 0.7-V-drop model to obtain better estimates of I and V than those
found in Exercise 4.4 (using the ideal-diode model).
Ans. (a) 1.72mA, 0.7V; (b) 0mA, 5V; (c) 0mA, 5V; (d) 1.72mA, 0.7V; (e) 2.3mA, +2.3V; (f) 3.3 mA, +1.7 V
4.3.7 The Small-Signal Model
Consider the situation in Fig. 4.13(a), where a dc voltage VDD establishes a dc current ID through the series combination of a resistance R and a diode D. The resulting diode voltage is denoted VD. As mentioned above, values of ID and VD can be obtained by solving the circuit using the diode exponential characteristic or, much more quickly, approximate values can be found using the diode constant-voltage-drop model.
Next, consider the situation of VDD undergoing a small change △VDD, as shown in Fig. 4.13(b). As indicated, the current ID changes by an increment △ID , and the diode voltage VD changes by an increment △VD. We wish to find a quick way to determine the values of these incremental changes. Toward that end, we develop a “small-signal” model for the diode.
R ID R ID+ID
V DVVDD DV+V DD D DD
VDD
(a) (b)
4.3 Modeling the Diode Forward Characteristic 195
Figure 4.13 (a) A simple diode circuit; (b) the situation when VDD changes by VDD .
196 Chapter 4
Diodes
Figure 4.14 Development of the diode small-signal model.
Here the word signal emphasizes that in general, △VDD can be a time-varying quantity. The qualifier “small” indicates that this diode model applies only when △VD is kept sufficiently small, with “sufficiently” to be quantified shortly.
To develop the diode small-signal model, refer to Fig. 4.14. We express the voltage across the diode as the sum of the dc voltage VD and the time-varying signal vd (t),
vD(t)=VD +vd(t) (4.8) Correspondingly, the total instantaneous diode current iD(t) will be
iD(t)=ISevD/VT (4.9) Substituting for vD from Eq. (4.8) gives
which can be rewritten
i D ( t ) = I S e ( VD + v d ) / VT
iD(t)=ISeVD/VT evd/VT (4.10)
4.3 Modeling the Diode Forward Characteristic 197 In the absence of the signal vd(t), the diode voltage is equal to VD, and the diode current is ID,
given by
ID =ISeVD/VT Thus, iD(t) in Eq. (4.10) can be expressed as
iD(t) = IDevd /VT
Now if the amplitude of the signal vd(t) is kept sufficiently small such that
vd ≪1 VT
(4.11)
(4.12)
(4.13)
then we may expand the exponential of Eq. (4.12) in a series and truncate the series after the first two terms to obtain the approximate expression
v
iD(t)≃ID 1+ d (4.14)
VT
This is the small-signal approximation. It is valid for signals whose amplitudes are smaller than about 5 mV (see Eq. 4.13, and recall that VT = 25 mV).3
From Eq. (4.14) we have
iD(t) = ID + ID vd (4.15) VT
Thus, superimposed on the dc current ID, we have a signal current component directly proportional to the signal voltage v d . That is,
where
iD = ID + id (4.16)
id = ID vd (4.17) VT
The quantity relating the signal current id to the signal voltage vd has the dimensions of conductance, mhos (), and is called the diode small-signal conductance. The inverse of this parameter is the diode small-signal resistance, or incremental resistance, rd ,
rd = VT (4.18) ID
Notethatthevalueofrd isinverselyproportionaltothebiascurrentID.
3 For v d = 5 mV, v d /VT = 0.2. Thus the next term in the series expansion of the exponential will be
1 × 0.22 = 0.02, a factor of 10 lower than the linear term we kept. 2
198 Chapter 4
Diodes
Additional insight into the small-signal approximation and the small-signal diode model can be obtained by considering again the graphical construction in Fig. 4.14. Here the diode is seen to be operating at a dc bias point Q characterized by the dc voltage VD and the correspondingdccurrentID.SuperimposedonVD wehaveasignalvd(t),assumed(arbitrarily) to have a triangular waveform.
It is easy to see that using the small-signal approximation is equivalent to assuming that the signal amplitude is sufficiently small such that the excursion along the i–v curve is limited to a short almost-linear segment. The slope of this segment, which is equal to the slope of the tangent to the i–v curve at the operating point Q, is equal to the small-signal conductance. The reader is encouraged to prove that the slope of the i–v curve at i = ID is equal to ID/VT , which is 1/rd ; that is,
∂i
rd =1 D (4.19)
From the preceding we conclude that superimposed on the quantities VD and ID that define the dc bias point, or quiescent point, of the diode will be the small-signal quantities vd(t) and id(t), which are related by the diode small-signal resistance rd evaluated at the bias point (Eq. 4.18). Thus the small-signal analysis can be performed separately from the dc bias analysis, a great convenience that results from the linearization of the diode characteristics inherent in the small-signal approximation. Specifically, after the dc analysis is performed, the small-signal equivalent circuit is obtained by eliminating all dc sources (i.e., short-circuiting dc voltage sources and open-circuiting dc current sources) and replacing the diode by its small-signal resistance. Thus, for the circuit in Fig. 4.13(b), the dc analysis is obtained by using the circuit in Fig. 4.13(a), while the incremental quantities ID and VD can be determined by using the small-signal equivalent circuit shown in Fig. 4.15. The following example should further illustrate the application of the small-signal model.
R
ID
∂vD iD=ID
V DD
V Figure 4.15 Circuit for determining the incremental
r D quantities I and V for the circuit in Figure 4.13(b). dDD
Example 4.5
Note that replacing the diode with its small-signal resistancerd resultsinalinearcircuit.
Consider the circuit shown in Fig. 4.16(a) for the case in which R = 10 k. The power supply V + has a dc value of 10 V on which is superimposed a 60-Hz sinusoid of 1-V peak amplitude. (This “signal” component of the power-supply voltage is an imperfection in the power-supply design. It is known as the power-supply ripple. More on this later.) Calculate both the dc voltage of the diode and the amplitude of the sine-wave signal appearing across it. Assume the diode to have a 0.7-V drop at 1-mA current.
4.3 ModelingtheDiodeForwardCharacteristic 199
10 V
ID
R
R
VD vs rd vd
(b) (c)
Figure4.16 (a)Circuit for Example4.5. (b)Circuit for calculating the dc operating point. (c)Small-signal
equivalent circuit.
Solution
Considering dc quantities only, we assume VD ≃ 0.7 V and calculate the diode dc current ID = 10−0.7 =0.93mA
10
Since this value is very close to 1 mA, the diode voltage will be very close to the assumed value of 0.7 V.
Atthisoperatingpoint,thediodeincrementalresistancerd is
rd = VT = 25 = 26.9
ID 0.93
The signal voltage across the diode can be found from the small-signal equivalent circuit in Fig. 4.16(c). Here vs denotes the 60-Hz 1-V peak sinusoidal component of V+, and vd is the corresponding signal across thediode.Usingthevoltagedividerruleprovidesthepeakamplitudeofvd asfollows:
v(peak)=Vˆ rd
d s R+rd
= 1 0.0269 = 2.68 mV 10 + 0.0269
Finally, we note that since this value is quite small, our use of the small-signal model of the diode is justified.
From the above we see that for a diode circuit that involves both dc and signal quantities, a small-signal equivalent circuit can be obtained by eliminating the dc sources and replacing each diode with its small-signal resistance rd . Such a circuit is linear and can be solved using linear circuit analysis.
Finally, we note that while rd models the small-signal operation of the diode at low frequencies, its dynamic operation is modeled by the capacitances Cj and Cd, which we
(a)
200 Chapter 4
Diodes
studied in Section 3.6 and which also are small-signal parameters. A complete model of the diodeincludesCj andCd inparallelwithrd.
4.3.8 Use of the Diode Forward Drop in Voltage Regulation
A further application of the diode small-signal model is found in a popular diode application, namely, the use of diodes to create a regulated voltage. A voltage regulator is a circuit whose purpose is to provide a constant dc voltage between its output terminals. The output voltage is required to remain as constant as possible in spite of (a) changes in the load current drawn from the regulator output terminal and (b) changes in the dc power-supply voltage that feeds the regulator circuit. Since the forward-voltage drop of the diode remains almost constant at approximately 0.7 V while the current through it varies by relatively large amounts, a forward-biased diode can make a simple voltage regulator. For instance, we have seen in Example 4.5 that while the 10-V dc supply voltage had a ripple of 2 V peak-to-peak (a ±10% variation), the corresponding ripple in the diode voltage was only about ±2.7 mV (a ±0.4% variation). Regulated voltages greater than 0.7 V can be obtained by connecting a number of diodes in series. For example, the use of three forward-biased diodes in series provides a voltage of about 2 V. One such circuit is investigated in the following example, which utilizes the diode small-signal model to quantify the efficacy of the voltage regulator that is realized.
Example 4.6
Consider the circuit shown in Fig. 4.17. A string of three diodes is used to provide a constant voltage of about 2.1 V. We want to calculate the percentage change in this regulated voltage caused by (a) a ±10% change in the power-supply voltage, and (b) connection of a 1-k load resistance.
10 1 V
R = 1 k
RL = 1 k vO
Solution
Figure 4.17 Circuit for Example 4.6.
With no load, the nominal value of the current in the diode string is given by
I = 10 − 2.1 = 7.9 mA 1
Thus each diode will have an incremental resistance of
Thus,
rd = VT I
rd = 25 =3.2 7.9
The three diodes in series will have a total incremental resistance of r=3rd =9.6
This resistance, along with the resistance R, forms a voltage divider whose ratio can be used to calculate the change in output voltage due to a ±10% (i.e., ±1-V) change in supply voltage. Thus the peak-to-peak change in output voltage will be
vO = 2 r = 2 0.0096 = 19 mV peak-to-peak r+R 0.0096+1
That is, corresponding to the ±1-V (±10%) change in supply voltage, the output voltage will change by ±9.5 mV or ±0.5%. Since this implies a change of about ±3.2 mV per diode, our use of the small-signal model is justified.
When a load resistance of 1 k is connected across the diode string, it draws a current of approximately 2.1 mA. Thus the current in the diodes decreases by 2.1 mA, resulting in a decrease in voltage across the diode string given by
vO =−2.1×r=−2.1×9.6=−20mV
Since this implies that the voltage across each diode decreases by about 6.7 mV, our use of the small-signal model is not entirely justified. Nevertheless, a detailed calculation of the voltage change using the exponential model results in vO = − 23 mV, which is not too different from the approximate value obtained using the incremental model.
EXERCISES
4.13 Findthevalueofthediodesmall-signalresistancerd atbiascurrentsof0.1mA,1mA,and10mA. Ans. 250 ; 25 ; 2.5
4.14 Consider a diode biased at 1 mA. Find the change in current as a result of changing the voltage by (a) –10 mV, (b) –5 mV, (c) +5 mV, and (d) +10 mV. In each case, do the calculations (i) using the small-signal model and (ii) using the exponential model.
Ans. (a) –0.40, –0.33 mA; (b) –0.20, –0.18 mA; (c) +0.20, +0.22 mA; (d) +0.40, +0.49 mA
D4.15 DesignthecircuitofFig.E4.15sothatVO =3VwhenIL =0,andVO changesby20mVper1mA of load current.
(a) Use the small-signal model of the diode to find the value of R. (b) Specify the value of IS of each of the diodes.
4.3 ModelingtheDiodeForwardCharacteristic 201
202 Chapter 4 Diodes
(c) For this design, use the diode exponential model to determine the actual change in VO when a current IL = 1 mA is drawn from the regulator.
15 V
R
VO IL
Figure E4.15
Ans. (a)R=2.4k;(b)IS =4.7×10−16 A;(c)–23mV
4.4 Operation in the Reverse Breakdown Region—Zener Diodes
The very steep i–v curve that the diode exhibits in the breakdown region (Fig. 4.8) and the almost-constant voltage drop that this indicates suggest that diodes operating in the breakdown region can be used in the design of voltage regulators. From the previous section, the reader will recall that voltage regulators are circuits that provide a constant dc output voltage in the face of changes in their load current and in the system power-supply voltage. This in fact turns out to be an important application of diodes operating in the reverse breakdown region, and special diodes are manufactured to operate specifically in the breakdown region. Such diodes are called breakdown diodes or, more commonly, as noted earlier, zener diodes.
Figure 4.18 shows the circuit symbol of the zener diode. In normal applications of zener diodes, current flows into the cathode, and the cathode is positive with respect to the anode. ThusIZ andVZ inFig.4.18havepositivevalues.
IZ
VZ
Figure 4.18 Circuit symbol for a zener diode.
4.4 Operation in the Reverse Breakdown Region—Zener Diodes 203 4.4.1 Specifying and Modeling the Zener Diode
Figure 4.19 shows details of the diode i–v characteristic in the breakdown region. We observe that for currents greater than the knee current IZK (specified on the data sheet of the zener diode), the i–v characteristic is almost a straight line. The manufacturer usually specifies thevoltageacrossthezenerdiodeVZ ataspecifiedtestcurrent,IZT.Wehaveindicatedthese parameters in Fig. 4.19 as the coordinates of the point labeled Q. Thus a 6.8-V zener diode will exhibit a 6.8-V drop at a specified test current of, say, 10 mA. As the current through the zener deviates from IZT , the voltage across it will change, though only slightly. Figure 4.19 shows that corresponding to current change I the zener voltage changes by V, which is related to I by
V =rzI
where rz is the inverse of the slope of the almost-linear i–v curve at point Q. Resistance rz is the incremental resistance of the zener diode at operating point Q. It is also known as the dynamic resistance of the zener, and its value is specified on the device data sheet. Typically, rz is in the range of a few ohms to a few tens of ohms. Obviously, the lower the value of rz is, the more constant the zener voltage remains as its current varies, and thus the more ideal its performance becomes in the design of voltage regulators. In this regard, we observe from Fig. 4.19 that while rz remains low and almost constant over a wide range of current, its value increases considerably in the vicinity of the knee. Therefore, as a general design guideline, one should avoid operating the zener in this low-current region.
ZenerdiodesarefabricatedwithvoltagesVZ intherangeofafewvoltstoafewhundred volts. In addition to specifying VZ (at a particular current IZT ), rz , and IZK , the manufacturer
V VZ0 V
Z ZK
Slope 1 rz
V
i
0v IZK
IZT (test current)
Q
I
V I rz
Figure 4.19 The diode i–v characteristic with the breakdown region shown in some detail.
204 Chapter 4
Diodes
Figure 4.20 Model for the zener diode.
also specifies the maximum power that the device can safely dissipate. Thus a 0.5-W, 6.8-V zener diode can operate safely at currents up to a maximum of about 70 mA.
The almost-linear i–v characteristic of the zener diode suggests that the device can be modeled as indicated in Fig. 4.20. Here VZ0 denotes the point at which the straight line of slope 1/rz intersects the voltage axis (refer to Fig. 4.19). Although VZ0 is shown in Fig. 4.19 to be slightly different from the knee voltage VZK , in practice their values are almost equal. The equivalent circuit model of Fig. 4.20 can be analytically described by
VZ =VZ0+rzIZ (4.20) and it applies for IZ > IZK and, obviously, VZ > VZ0.
4.4.2 Use of the Zener as a Shunt Regulator
We now illustrate, by way of an example, the use of zener diodes in the design of shunt regulators, so named because the regulator circuit appears in parallel (shunt) with the load.
Example 4.7
The 6.8-V zener diode in the circuit of Fig. 4.21(a) is specified to have VZ = 6.8 V at IZ = 5 mA, rz = 20 , and IZK = 0.2 mA. The supply voltage V + is nominally 10 V but can vary by ±1 V.
(a) Find VO with no load and with V+ at its nominal value.
(b) Find the change in VO resulting from the ±1-V change in V + . Note that VO /V + , usually expressed
in mV/V, is known as line regulation.
(c) Find the change in V resulting from connecting a load resistance R that draws a current I = 1 mA,
OLL and hence find the load regulation VO/IL in mV/mA.
(d) Find the change in VO when RL = 2 k.
(e) Find the value of VO when RL = 0.5 k.
(f) What is the minimum value of RL for which the diode still operates in the breakdown region?
4.4
Operation in the Reverse Breakdown Region—Zener Diodes 205
1 V)
I
IZ
VO
(b)
IL
(a)
Figure 4.21 (a) Circuit for Example 4.7. (b) The circuit with the zener diode replaced with its equivalent circuit model.
Solution
FirstwemustdeterminethevalueoftheparameterVZ0 ofthezenerdiodemodel.SubstitutingVZ =6.8V, IZ = 5 mA, and rz = 20 in Eq. (4.20) yields VZ 0 = 6.7 V. Figure 4.21(b) shows the circuit with the zener diode replaced with its model.
(a) With no load connected, the current through the zener is given by
Thus,
IZ =I=V+−VZ0 R+rz
= 10−6.7 =6.35mA 0.5 + 0.02
VO =VZ0 +IZrz =6.7+6.35×0.02=6.83V
(b) For a ±1-V change in V+, the change in output voltage can be found from VO =V+ rz
R+rz
=±1× 20 =±38.5mV
Thus,
500+20
Line regulation = 38.5 mV/V
206
Chapter 4 Diodes
Example 4.7 continued
(c) When a load resistance RL that draws a load current IL = 1 mA is connected, the zener current will
decrease by 1 mA. The corresponding change in zener voltage can be found from
Thus the load regulation is
VO =rzIZ
= 20 × −1 = −20 mV
Load regulation ≡ VO = −20 mV/mA IL
(d) When a load resistance of 2 k is connected, the load current will be approximately 6.8 V/2 k = 3.4 mA. Thus the change in zener current will be IZ = −3.4 mA, and the corresponding change in zener voltage (output voltage) will thus be
VO =rzIZ =20×−3.4=−68mV
ThisvaluecouldhavebeenobtainedbymultiplyingtheloadregulationbythevalueofIL (3.4mA).
(e) An RL of 0.5 k would draw a load current of 6.8/0.5 = 13.6 mA. This is not possible, because the current I supplied through R is only 6.4 mA (for V + = 10 V). Therefore, the zener must be cut off. If this is indeed the case, then VO is determined by the voltage divider formed by RL and R (Fig. 4.21a),
VO =V+ RL R+RL
=10 0.5 =5V 0.5 + 0.5
Since this voltage is lower than the breakdown voltage of the zener, the diode is indeed no longer operating in the breakdown region.
(f) For the zener to be at the edge of the breakdown region, IZ =IZK =0.2mA and VZ ≃VZK ≃6.7V. At this point the lowest (worst-case) current supplied through R is (9 − 6.7)/0.5 = 4.6 mA, and thus the load currentis4.6−0.2=4.4mA.ThecorrespondingvalueofRL is
RL = 6.7 ≃1.5k 4.4
4.4.3 Temperature Effects
ThedependenceofthezenervoltageVZ ontemperatureisspecifiedintermsofitstemperature coefficient TC, or temco as it is commonly known, which is usually expressed in mV/°C. The value of TC depends on the zener voltage, and for a given diode the TC varies with the operatingcurrent.ZenerdiodeswhoseVZ arelowerthanabout5VexhibitanegativeTC.On the other hand, zeners with higher voltages exhibit a positive TC. The TC of a zener diode withaVZ ofabout5Vcanbemadezerobyoperatingthediodeataspecifiedcurrent.Another commonly used technique for obtaining a reference voltage with low temperature coefficient
is to connect a zener diode with a positive temperature coefficient of about 2 mV/°C in series with a forward-conducting diode. Since the forward-conducting diode has a voltage drop of ≃0.7 V and a TC of about –2 mV/°C, the series combination will provide a voltage of (VZ + 0.7) with a TC of about zero.
EXERCISES
4.16 A zener diode whose nominal voltage is 10 V at 10 mA has an incremental resistance of 50 . What voltage do you expect if the diode current is halved? Doubled? What is the value of VZ0 in the zener model?
Ans. 9.75 V; 10.5 V; 9.5 V
4.17 Azenerdiodeexhibitsaconstantvoltageof5.6Vforcurrentsgreaterthanfivetimesthekneecurrent. IZK isspecifiedtobe1mA.Thezeneristobeusedinthedesignofashuntregulatorfedfroma15-V supply. The load current varies over the range of 0 mA to 15 mA. Find a suitable value for the resistor R. What is the maximum power dissipation of the zener diode?
Ans. 470 ; 112 mW
4.18 A shunt regulator utilizes a zener diode whose voltage is 5.1 V at a current of 50 mA and whose
incremental resistance is 7 . The diode is fed from a supply of 15-V nominal voltage through a 200- resistor. What is the output voltage at no load? Find the line regulation and the load regulation. Ans. 5.1 V; 33.8 mV/V; –7 mV/mA
4.4.4 A Final Remark
Though simple and useful, zener diodes have lost a great deal of their popularity in recent years. They have been virtually replaced in voltage-regulator design by specially designed integrated circuits (ICs) that perform the voltage-regulation function much more effectively and with greater flexibility than zener diodes.
4.5 Rectifier Circuits
One of the most important applications of diodes is in the design of rectifier circuits. A diode rectifier forms an essential building block of the dc power supplies required to power electronic equipment. A block diagram of such a power supply is shown in Fig. 4.22. As indicated, the power supply is fed from the 120-V (rms) 60-Hz ac line, and it delivers a dc voltage VO (usually in the range of 4 V to 20 V) to an electronic circuit represented by the load block. The dc voltage VO is required to be as constant as possible in spite of variations in the ac line voltage and in the current drawn by the load.
The first block in a dc power supply is the power transformer. It consists of two separate coils wound around an iron core that magnetically couples the two windings. The primary winding, having N1 turns, is connected to the 120-V ac supply, and the secondary winding, having N2 turns, is connected to the circuit of the dc power supply. Thus an ac voltage vS of 120(N2/N1) V (rms) develops between the two terminals of the secondary winding. By
4.5 Rectifier Circuits 207
208 Chapter 4
Diodes
selecting an appropriate turns ratio (N1/N2) for the transformer, the designer can step the line voltage down to the value required to yield the particular dc voltage output of the supply. For instance, a secondary voltage of 8-V rms may be appropriate for a dc output of 5 V. This can be achieved with a 15:1 turns ratio.
In addition to providing the appropriate sinusoidal amplitude for the dc power supply, the power transformer provides electrical isolation between the electronic equipment and the power-line circuit. This isolation minimizes the risk of electric shock to the equipment user.
ThedioderectifierconvertstheinputsinusoidvS toaunipolaroutput,whichcanhavethe pulsating waveform indicated in Fig. 4.22. Although this waveform has a nonzero average or a dc component, its pulsating nature makes it unsuitable as a dc source for electronic circuits, hence the need for a filter. The variations in the magnitude of the rectifier output are considerably reduced by the filter block in Fig. 4.22. In this section we shall study a number of rectifier circuits and a simple implementation of the output filter.
The output of the rectifier filter, though much more constant than without the filter, still contains a time-dependent component, known as ripple. To reduce the ripple and to stabilize the magnitude of the dc output voltage against variations caused by changes in load current, a voltage regulator is employed. Such a regulator can be implemented using the zener shunt regulator configuration studied in Section 4.4. Alternatively, and much more commonly at present, an integrated-circuit regulator can be used.
4.5.1 The Half-Wave Rectifier
The half-wave rectifier utilizes alternate half-cycles of the input sinusoid. Figure 4.23(a) shows the circuit of a half-wave rectifier. This circuit was analyzed in Section 4.1 (see Fig. 4.3) assuming an ideal diode. Using the more realistic constant-voltage-drop diode model, we obtain
vO = 0, vS < VD (4.21a) vO =vS −VD, vS ≥VD (4.21b)
The transfer characteristic represented by these equations is sketched in Fig. 4.23(b), where VD = 0.7 V or 0.8 V. Figure 4.23(c) shows the output voltage obtained when the input vS is a sinusoid.
In selecting diodes for rectifier design, two important parameters must be specified: the current-handling capability required of the diode, determined by the largest current the diode is expected to conduct, and the peak inverse voltage (PIV) that the diode must be able to
t
Figure 4.22 Block diagram of a dc power supply.
D
vS RvO
vO
4.5 Rectifier Circuits 209
Slope 1
0 VD (b)
vS
(a)
v
Vs
VD
VD
vS
vO
(c)
Figure 4.23 (a) Half-wave rectifier. (b) Transfer characteristic of the rectifier circuit. (c) Input and output waveforms.
withstand without breakdown, determined by the largest reverse voltage that is expected to appear across the diode. In the rectifier circuit of Fig. 4.23(a), we observe that when vS is negative the diode will be cut off and vO will be zero. It follows that the PIV is equal to the peak of vS,
PIV = Vs (4.22)
It is usually prudent, however, to select a diode that has a reverse breakdown voltage at least 50% greater than the expected PIV.
Before leaving the half-wave rectifier, the reader should note two points. First, it is possible to use the diode exponential characteristic to determine the exact transfer characteristic of the rectifier (see Problem 4.68). However, the amount of work involved is usually too great to be justified in practice. Of course, such an analysis can be easily done using a computer circuit-analysis program such as SPICE.
Second, whether we analyze the circuit accurately or not, it should be obvious that this circuit does not function properly when the input signal is small. For instance, this circuit cannot be used to rectify an input sinusoid of 100-mV amplitude. For such an application one
t
210 Chapter 4 Diodes
resorts to a so-called precision rectifier, a circuit utilizing diodes in conjunction with op amps.
One such circuit is presented in Section 4.5.5.
EXERCISE
Ds
a total conduction angle of (π – 2θ ). (b) The average value (dc component) of v is V ≃ (1/π )V − V /2.
4.19 For the half-wave rectifier circuit in Fig. 4.23(a), show the following: (a) For the half-cycles during which the diode conducts, conduction begins at an angle θ = sin−1 V /V and terminates at (π – θ ), for
OO sD
(c) The peak diode current is Vs − VD /R.
Find numerical values for these quantities for the case of 12-V (rms) sinusoidal input, VD ≃ 0.7 V, and R = 100 . Also, give the value for PIV.
Ans. (a) θ = 2.4°, conduction angle = 175°; (b) 5.05 V; (c) 163 mA; 17 V
4.5.2 The Full-Wave Rectifier
The full-wave rectifier utilizes both halves of the input sinusoid. To provide a unipolar output, it inverts the negative halves of the sine wave. One possible implementation is shown in Fig. 4.24(a). Here the transformer secondary winding is center-tapped to provide two equal voltagesvS acrossthetwohalvesofthesecondarywindingwiththepolaritiesindicated.Note that when the input line voltage (feeding the primary) is positive, both of the signals labeled vS will be positive. In this case D1 will conduct and D2 will be reverse biased. The current through D1 will flow through R and back to the center tap of the secondary. The circuit then behaves like a half-wave rectifier, and the output during the positive half-cycles when D1 conducts will be identical to that produced by the half-wave rectifier.
Now, during the negative half-cycle of the ac line voltage, both of the voltages labeled vS will be negative. Thus D1 will be cut off while D2 will conduct. The current conducted by D2 will flow through R and back to the center tap. It follows that during the negative half-cycles while D2 conducts, the circuit behaves again as a half-wave rectifier. The important point, however, is that the current through R always flows in the same direction, and thus vO will be unipolar, as indicated in Fig. 4.24(c). The output waveform shown is obtained by assuming that a conducting diode has a constant voltage drop VD. Thus the transfer characteristic of the full-wave rectifier takes the shape shown in Fig. 4.24(b).
The full-wave rectifier obviously produces a more “energetic” waveform than that prov- ided by the half-wave rectifier. In almost all rectifier applications, one opts for a full-wave type of some kind.
To find the PIV of the diodes in the full-wave rectifier circuit, consider the situation during the positive half-cycles. Diode D1 is conducting, and D2 is cut off. The voltage at the cathode of D2 is vO, and that at its anode is –vS. Thus the reverse voltage across D2 will be (vO +vS), which will reach its maximum when vO is at its peak value of (Vs – VD), and vS is at its peak value of Vs; thus,
PIV = 2Vs − VD
which is approximately twice that for the case of the half-wave rectifier.
D1
Center vS tap R vO ac
vO
VD 0VD (b)
vS
vO
4.5
Rectifier Circuits 211
line
voltage
vS
Slope 1
Slope 1
vS
v
Vs
VD
vS
D2 (a)
Figure 4.24 Full-wave rectifier utilizing a transformer with a center-tapped secondary winding: (a) circuit; (b) transfer characteristic assuming a constant-voltage-drop model for the diodes; (c) input and output waveforms.
EXERCISE
(c)
t
4.20 For the full-wave rectifier circuit in Fig. 4.24(a), show the following: (a) The output is zero for an angle of 2 sin− 1 V /V centered around the zero-crossing points of the sine-wave input. (b) The
Ds
average value (dc component) of v is V ≃ (2/π )V − V . (c) The peak current through each diode is
OO sD
Vs −VD /R.Findthefraction(percentage)ofeachcycleduringwhichvO >0,thevalueofVO,thepeak
diode current, and the value of PIV, all for the case in which vS is a 12-V (rms) sinusoid, VD ≃ 0.7 V, and R = 100 .
Ans. 97.4%; 10.1 V; 163 mA; 33.2 V
212 Chapter 4
Diodes
4.5.3 The Bridge Rectifier
An alternative implementation of the full-wave rectifier is shown in Fig. 4.25(a). This circuit, known as the bridge rectifier because of the similarity of its configuration to that of the Wheatstone bridge, does not require a center-tapped transformer, a distinct advantage over the full-wave rectifier circuit of Fig. 4.24. The bridge rectifier, however, requires four diodes as compared to two in the previous circuit. This is not much of a disadvantage, because diodes are inexpensive and one can buy a diode bridge in one package.
The bridge-rectifier circuit operates as follows: During the positive half-cycles of the input voltage, vS is positive, and thus current is conducted through diode D1, resistor R, and diode D2. Meanwhile, diodes D3 and D4 will be reverse biased. Observe that there are two diodes in series in the conduction path, and thus vO will be lower than vS by two diode drops (compared to one drop in the circuit previously discussed). This is somewhat of a disadvantage of the bridge rectifier.
Next, consider the situation during the negative half-cycles of the input voltage. The secondaryvoltagevS willbenegative,andthus−vS willbepositive,forcingcurrentthrough D3, R, and D4. Meanwhile, diodes D1 and D2 will be reverse biased. The important point to note, though, is that during both half-cycles, current flows through R in the same direction (from right to left), and thus vO will always be positive, as indicated in Fig. 4.25(b).
To determine the peak inverse voltage (PIV) of each diode, consider the circuit during the positive half-cycles. The reverse voltage across D3 can be determined from the loop formed
D4 D1
ac
line vS
voltage
v
Vs
vO
D2
R
D3
vS vS
(a)
2 VD
vO
Figure 4.25 The bridge rectifier: (a) circuit; (b) input and output waveforms.
(b)
t
byD3,R,andD2 as
vD3(reverse) = vO + vD2(forward)
Thus the maximum value of vD3 occurs at the peak of vO and is given by
PIV=Vs −2VD +VD =Vs −VD
Observe that here the PIV is about half the value for the full-wave rectifier with a center-tapped transformer. This is another advantage of the bridge rectifier.
Yet one more advantage of the bridge-rectifier circuit over that utilizing a center-tapped transformer is that only about half as many turns are required for the secondary winding of the transformer. Another way of looking at this point can be obtained by observing that each half of the secondary winding of the center-tapped transformer is utilized for only half the time. These advantages have made the bridge rectifier the most popular rectifier circuit configuration.
EXERCISE
4.21 Forthebridge-rectifiercircuitofFig.4.25(a),usetheconstant-voltage-dropdiodemodeltoshowthat (a) the average (or dc component) of the output voltage is VO ≃ (2/π )Vs − 2VD and (b) the peak diode current is (Vs − 2VD )/R. Find numerical values for the quantities in (a) and (b) and the PIV for the case inwhichvS isa12-V(rms)sinusoid,VD ≃0.7V,andR=100.
Ans. 9.4 V; 156 mA; 16.3 V
4.5.4 The Rectifier with a Filter Capacitor—The Peak Rectifier
The pulsating nature of the output voltage produced by the rectifier circuits discussed above makes it unsuitable as a dc supply for electronic circuits. A simple way to reduce the variation of the output voltage is to place a capacitor across the load resistor. It will be shown that this filter capacitor serves to reduce substantially the variations in the rectifier output voltage.
To see how the rectifier circuit with a filter capacitor works, consider first the simple circuit shown in Fig. 4.26. Let the input vI be a sinusoid with a peak value Vp, and assume thediodetobeideal.AsvI goespositive,thediodeconductsandthecapacitorischargedso that vO = vI . This situation continues until vI reaches its peak value Vp. Beyond the peak, as vI decreases, the diode becomes reverse biased and the output voltage remains constant at the value Vp. In fact, theoretically speaking, the capacitor will retain its charge and hence its voltage indefinitely, because there is no way for the capacitor to discharge. Thus the circuit provides a dc voltage output equal to the peak of the input sine wave. This is a very encouraging result in view of our desire to produce a dc output.
Next, we consider the more practical situation where a load resistance R is connected across the capacitor C, as depicted in Fig. 4.27(a). However, we will continue to assume the diode to be ideal. As before, for a sinusoidal input, the capacitor charges to the peak of the input Vp. Then the diode cuts off, and the capacitor discharges through the load resistance R. The capacitor discharge will continue for almost the entire cycle, until the time at which vI
4.5 Rectifier Circuits 213
214 Chapter 4
Diodes
D
(a)
0
iL =vO/R and of the diode current (when it is conducting)
iD = iC + iL =CdvI +iL
dt
are shown in Fig. 4.27(c). The following observations are in order:
(4.23)
(4.24)
(4.25)
(b)
Figure 4.26 (a) A simple circuit used to illustrate the effect of a filter capacitor. (b) Input and output waveforms assuming an ideal diode. Note that the circuit provides a dc voltage equal to the peak of the input sine wave. The circuit is therefore known as a peak rectifier or a peak detector.
exceeds the capacitor voltage. Then the diode turns on again and charges the capacitor up to the peak of vI , and the process repeats itself. Observe that to keep the output voltage from decreasing too much during capacitor discharge, one selects a value for C so that the time constant CR is much greater than the discharge interval.
We are now ready to analyze the circuit in detail. Figure 4.27(b) shows the steady-state input and output voltage waveforms under the assumption that CR ≫ T , where T is the period of the input sinusoid. The waveforms of the load current
1. The diode conducts for a brief interval, t, near the peak of the input sinusoid and supplies the capacitor with charge equal to that lost during the much longer discharge interval. The latter is approximately equal to the period T.
iD
4.5 Rectifier Circuits 215
T
vO Vr
vI
(b)
DiC iL
vI CRvO
(a)
Vp
vI
t
t1 t2 Conduction
interval t
t
t
iD
iL
(c)
t
Figure4.27 Voltageandcurrentwaveformsinthepeak-rectifiercircuitwithCR≫T.Thediodeisassumed ideal.
2. Assuming an ideal diode, the diode conduction begins at time t1, at which the input v I equals the exponentially decaying output v O . Conduction stops at t2 shortly after the peak of vI ; the exact value of t2 can be determined by setting iD = 0 in Eq. (4.25).
3. During the diode-off interval, the capacitor C discharges through R, and thus vO decays exponentially with a time constant CR. The discharge interval begins just past the peak of vI . At the end of the discharge interval, which lasts for almost the entire period T, v O = Vp – Vr , where Vr is the peak-to-peak ripple voltage. When CR ≫ T , thevalueofVr issmall.
216 Chapter 4
Diodes
4. When Vr is small, vO is almost constant and equal to the peak value of vI . Thus the dc output voltage is approximately equal to Vp. Similarly, the current iL is almost constant, and its dc component IL is given by
IL = Vp (4.26) R
If desired, a more accurate expression for the output dc voltage can be obtained by taking the average of the extreme values of vO,
VO = Vp − 1 Vr (4.27) 2
With these observations in hand, we now derive expressions for Vr and for the average and peak values of the diode current. During the diode-off interval, vO can be expressed as
vO =Vpe−t/CR At the end of the discharge interval we have
Vp −Vr ≃Vpe−T/CR
Now, since CR ≫ T , we can use the approximation e−T /CR ≃ 1 − T /CR to obtain
voltageVr inEq.(4.28)canbeexpressedintermsofthefrequencyf=1/Tas Vr = Vp
fCR UsingEq.(4.26)wecanexpressVr bythealternateexpression
Vr = IL fC
V≃V T r p CR
(4.28) WeobservethattokeepVr smallwemustselectacapacitanceCsothatCR≫T.Theripple
(4.29a)
(4.29b)
Note that an alternative interpretation of the approximation made above is that the capacitor discharges by means of a constant current IL = Vp/R. This approximation is valid as long as Vr ≪Vp.
Assuming that diode conduction ceases almost at the peak of vI , we can determine the conduction interval t from
Vp cos(ωt) = Vp − Vr
where ω = 2πf = 2π/T is the angular frequency of vI . Since (ωt) is a small angle, we can
employtheapproximationcos(ωt)≃1−1(ωt)2 toobtain 2
ωt ≃ 2Vr /Vp (4.30)
We note that when Vr ≪ Vp, the conduction angle ωt will be small, as assumed.
To determine the average diode current during conduction, iDav, we equate the charge that
the diode supplies to the capacitor,
Qsupplied = iCavt
where from Eq. (4.24),
to the charge that the capacitor loses during the discharge interval,
to obtain, using Eqs. (4.30) and (4.29a),
iDav =IL 1+π 2Vp/Vr
iCav =iDav −IL Qlost =CVr
Observe that when Vr ≪ Vp , the average diode current during conduction is much greater than the dc load current. This is not surprising, since the diode conducts for a very short interval and must replenish the charge lost by the capacitor during the much longer interval in which it is discharged by IL .
The peak value of the diode current, iDmax , can be determined by evaluating the expression
in Eq. (4.25) at the onset of diode conduction—that is, at t = t1 = −t (where t = 0 is at the
peak). Assuming that iL is almost constant at the value given by Eq. (4.26), we obtain
iDmax =IL 1+2π 2Vp/Vr (4.32) From Eqs. (4.31) and (4.32), we see that for Vr ≪ Vp , iDmax ≃ 2iDav , which correlates with the
fact that the waveform of iD is almost a right-angle triangle (see Fig. 4.27c).
Example 4.8
Consider a peak rectifier fed by a 60-Hz sinusoid having a peak value Vp = 100 V. Let the load resistance R = 10 k. Find the value of the capacitance C that will result in a peak-to-peak ripple of 2 V. Also, calculate the fraction of the cycle during which the diode is conducting and the average and peak values of the diode current.
Solution
From Eq. (4.29a) we obtain the value of C as
C = Vp = 100 = 83.3 μF
The conduction angle ωt is found from Eq. (4.30) as √
ωt= 2×2/100=0.2rad
Thus the diode conducts for (0.2/2π ) × 100 = 3.18% of the cycle. The average diode current is obtained
from Eq. (4.31), where IL = 100/10 = 10 mA, as √
iDav =10 1+π 2×100/2 =324mA
The peak diode current is found using Eq. (4.32),
√
iDmax =10 1+2π 2×100/2 =638mA
4.5 RectifierCircuits 217
(4.31)
Vr fR 2×60×10×103
218 Chapter 4
Diodes
Figure 4.28 Waveforms in the full-wave peak rectifier.
The circuit of Fig. 4.27(a) is known as a half-wave peak rectifier. The full-wave rectifier circuits of Figs. 4.24(a) and 4.25(a) can be converted to peak rectifiers by including a capacitor across the load resistor. As in the half-wave case, the output dc voltage will be almost equal to the peak value of the input sine wave (Fig. 4.28). The ripple frequency, however, will be twice that of the input. The peak-to-peak ripple voltage, for this case, can be derived using a procedure identical to that above but with the discharge period T replaced by T/2, resulting in
Vr= Vp (4.33) 2 fCR
While the diode conduction interval, t, will still be given by Eq. (4.30), the average and peak currents in each of the diodes will be given by
iDav =IL 1+π Vp/2Vr (4.34)
iDmax = IL 1 + 2π Vp/2Vr (4.35)
Comparing these expressions with the corresponding ones for the half-wave case, we note that for the same values of Vp, f, R, and Vr (and thus the same IL), we need a capacitor half the size of that required in the half-wave rectifier. Also, the current in each diode in the full-wave rectifier is approximately half that which flows in the diode of the half-wave circuit.
The analysis above assumed ideal diodes. The accuracy of the results can be improved by taking the diode voltage drop into account. This can be easily done by replacing the peak voltage Vp to which the capacitor charges with (Vp –VD) for the half-wave circuit and the full-wave circuit using a center-tapped transformer and with (Vp – 2VD) for the bridge-rectifier case.
We conclude this section by noting that peak-rectifier circuits find application in signal-processing systems where it is required to detect the peak of an input signal. In such a case, the circuit is referred to as a peak detector. A particularly popular application of the peak detector is in the design of a demodulator for amplitude-modulated (AM) signals. We shall not discuss this application further here.
4.5 Rectifier Circuits 219
EXERCISES
4.22 Derive the expressions in Eqs. (4.33), (4.34), and (4.35).
4.23 Consider a bridge-rectifier circuit with a filter capacitor C placed across the load resistor R for the
case in which the transformer secondary delivers a sinusoid of 12 V (rms) having a 60-Hz frequency and assuming VD = 0.8 V and a load resistance R = 100 . Find the value of C that results in a ripple voltage no larger than 1 V peak-to-peak. What is the dc voltage at the output? Find the load current. Find the diodes’ conduction angle. Provide the average and peak diode currents. What is the peak reverse voltage across each diode? Specify the diode in terms of its peak current and its PIV.
Ans. 1281 μF; 15.4 V or (a better estimate) 14.9 V; 0.15 A; 0.36 rad (20.7°); 1.45 A; 2.74 A; 16.2 V. Thus select a diode with 3.5-A to 4-A peak current and a 20-V PIV rating.
THE EARLIEST SEMICONDUCTOR DIODE:
The cat’s whisker or crystal detector was the first electronic diode to be commercialized as an envelope detector for the radio-frequency signals used in radio telephony. The earliest diode, invented in Germany by Karl Ferdinand Braun, consisted of a small slab of galena (lead sulfide) to which contact was made by sharpened spring wire, which could be adjusted. For this and other contributions to early radios, Braun received the Nobel Prize in Physics in 1909. The silicon-based point-contact diode, later refined and packaged, was an important solid-state component of radar equipment during World War II.
4.5.5 Precision Half-Wave Rectifier—The Superdiode4
The rectifier circuits studied thus far suffer from having one or two diode drops in the signal paths. Thus these circuits work well only when the signal to be rectified is much larger than the voltage drop of a conducting diode (0.7 V or so). In such a case, the details of the diode forward characteristics or the exact value of the diode voltage do not play a prominent role in determining circuit performance. This is indeed the case in the application of rectifier circuits in power-supply design. There are other applications, however, where the signal to be rectified is small (e.g., on the order of 100 mV or so) and thus clearly insufficient to turn on a diode. Also, in instrumentation applications, the need arises for rectifier circuits with very precise and predictable transfer characteristics. For these applications, a class of circuits has been developed utilizing op amps (Chapter 2) together with diodes to provide precision rectification. In the following discussion, we study one such circuit. A comprehensive study of op amp–diode circuits is available on the website.
4 This section requires knowledge of operational amplifiers (Chapter 2).
220 Chapter 4
Diodes
(a) (b)
Figure4.29 (a)The“superdiode”precisionhalf-waverectifierand(b)itsalmost-idealtransfercharacteristic. Note that when vI > 0 and the diode conducts, the op amp supplies the load current, and the source is conveniently buffered, an added advantage. Not shown are the op-amp power supplies.
Figure 4.29(a) shows a precision half-wave rectifier circuit consisting of a diode placed in the negative-feedback path of an op amp, with R being the rectifier load resistance. The op amp, of course, needs power supplies for its operation. For simplicity, these are not shown in the circuit diagram. The circuit works as follows: If vI goes positive, the output voltage vA of the op amp will go positive and the diode will conduct, thus establishing a closed feedback path between the op amp’s output terminal and the negative input terminal. This negative-feedback path will cause a virtual short circuit to appear between the two input terminals of the op amp. Thus the voltage at the negative input terminal, which is also the output voltage vO, will equal (to within a few millivolts) that at the positive input terminal, which is the input voltage vI ,
vO =vI vI ≥0
Note that the offset voltage (≃ 0.7 V) exhibited in the simple half-wave rectifier circuit of Fig.4.23 is no longer present. For the op-amp circuit to start operation, vI has to exceed only a negligibly small voltage equal to the diode drop divided by the op amp’s open-loop gain. In other words, the straight-line transfer characteristic vO–vI almost passes through the origin. This makes this circuit suitable for applications involving very small signals.
Consider now the case when vI goes negative. The op amp’s output voltage vA will tend to follow and go negative. This will reverse-bias the diode, and no current will flow through resistance R, causing vO to remain equal to 0 V. Thus, for vI < 0, vO = 0. Since in this case the diode is off, the op amp will be operating in an open-loop fashion, and its output will be at its negative saturation level.
The transfer characteristic of this circuit will be that shown in Fig. 4.29(b), which is almost identical to the ideal characteristic of a half-wave rectifier. The nonideal diode characteristics have been almost completely masked by placing the diode in the negative-feedback path of an op amp. This is another dramatic application of negative feedback, a subject we will study formally in Chapter 11. The combination of diode and op amp, shown in the dashed box in Fig. 4.29(a), is appropriately referred to as a “superdiode.”
4.6 Limiting and Clamping Circuits 221
EXERCISES
4.24 Consider the operational rectifier or superdiode circuit of Fig. 4.29(a), with R=1 k. For vI = 10 mV, 1 V, and –1 V, what are the voltages that result at the rectifier output and at the output of the op amp? Assume that the op amp is ideal and that its output saturates at ±12 V. The diode has a 0.7-V drop at 1-mA current.
Ans. 10mV,0.59V;1V,1.7V;0V,–12V
4.25 If the diode in the circuit of Fig. 4.29(a) is reversed, find the transfer characteristic vO as a function of
vI.
Ans. vO =0forvI ≥0;vO =vI forvI ≤0
4.6 Limiting and Clamping Circuits
In this section, we shall present additional nonlinear circuit applications of diodes.
4.6.1 Limiter Circuits
Figure 4.30 shows the general transfer characteristic of a limiter circuit. As indicated, for inputs in a certain range, L−/K ≤ vI ≤ L+/K, the limiter acts as a linear circuit, providing an output proportional to the input, v O = K v I . Although in general K can be greater than 1, the
Figure 4.30 General transfer characteristic for a limiter circuit.
222 Chapter 4
Diodes
circuits discussed in this section have K ≤ 1 and are known as passive limiters. (Examples of
activelimiterswillbepresentedinChapter18.)IfvI exceedstheupperthreshold L+/K ,the outputvoltageislimitedorclampedtotheupperlimitinglevelL .Ontheotherhand,ifv is
+I reduced below the lower limiting threshold L−/K , the output voltage vO is limited to the
lower limiting level L−.
The general transfer characteristic of Fig. 4.30 describes a double limiter—that is, a
limiter that works on both the positive and negative peaks of an input waveform. Single limiters, of course, exist. Finally, note that if an input waveform such as that shown in Fig. 4.31 is fed to a double limiter, its two peaks will be clipped off. Limiters therefore are sometimes referred to as clippers.
The limiter whose characteristics are depicted in Fig. 4.30 is described as a hard limiter. Soft limiting is characterized by smoother transitions between the linear region and the saturation regions and a slope greater than zero in the saturation regions, as illustrated in Fig. 4.32. Depending on the application, either hard or soft limiting may be preferred.
Limiters find application in a variety of signal-processing systems. One of their simplest applications is in limiting the voltage between the two input terminals of an op amp to a value lower than the breakdown voltage of the transistors that make up the input stage of the op-amp circuit. We will have more to say on this and other limiter applications at later points in this book.
Diodes can be combined with resistors to provide simple realizations of the limiter function. A number of examples are depicted in Fig. 4.33. In each part of the figure both the circuit and its transfer characteristic are given. The transfer characteristics are obtained using the constant-voltage-drop (VD = 0.7 V) diode model but assuming a smooth transition between the linear and saturation regions of the transfer characteristic.
The circuit in Fig. 4.33(a) is that of the half-wave rectifier except that here the output is takenacrossthediode.ForvI <0.5V,thediodeiscutoff,nocurrentflows,andthevoltage drop across R is zero; thus vO = vI . As vI exceeds 0.5 V, the diode turns on, eventually limiting
Figure 4.31 Applying a sine wave to a limiter can result in clipping off its two peaks.
0
Figure 4.32 Soft limiting.
4.6 Limiting and Clamping Circuits 223
Figure 4.33 A variety of basic limiting circuits.
vO to one diode drop (0.7 V). The circuit of Fig. 4.33(b) is similar to that in Fig. 4.33(a) except that the diode is reversed.
Double limiting can be implemented by placing two diodes of opposite polarity in paral- lel, as shown in Fig. 4.33(c). Here the linear region of the characteristic is obtained for −0.5V≤vI ≤0.5V.ForthisrangeofvI,bothdiodesareoffandvO =vI.AsvI exceeds0.5V, D1 turnsonandeventuallylimitsvO to+0.7V.Similarly,asvI goesmorenegativethan–0.5V, D2 turns on and eventually limits vO to –0.7 V.
The thresholds and saturation levels of diode limiters can be controlled by using strings of diodes and/or by connecting a dc voltage in series with the diode(s). The latter idea is illustrated in Fig. 4.33(d). Finally, rather than strings of diodes, we may use two zener diodes in series, as shown in Fig. 4.33(e). In this circuit, limiting occurs in the positive direction at a voltage of VZ 2 + 0.7, where 0.7 V represents the voltage drop across zener diode Z1 when conducting in the forward direction. For negative inputs, Z1 acts as a zener, while Z2 conducts
224 Chapter 4
Diodes
in the forward direction. It should be mentioned that pairs of zener diodes connected in series are available commercially for applications of this type under the name double-anode zener.
More flexible limiter circuits are possible if op amps are combined with diodes and resistors. Examples of such circuits are discussed in Chapter 18.
EXERCISE
4.26 Assuming the diodes to be ideal, describe the transfer characteristic of the circuit shown in Fig. E4.26.
Ans. vO =vI
v =1v−2.5
for−5≤vI ≤+5 forv≤−5
O2II
v =1v+2.5 forv≥+5
Figure E4.26
O2II
4.6.2 The Clamped Capacitor or DC Restorer
If in the basic peak-rectifier circuit, the output is taken across the diode rather than across the capacitor, an interesting circuit with important applications results. The circuit, called a dc restorer, is shown in Fig. 4.34 fed with a square wave. Because of the polarity in which the diode is connected, the capacitor will charge to a voltage vC with the polarity indicated in Fig. 4.34 and equal to the magnitude of the most negative peak of the input signal. Subsequently, the diode turns off and the capacitor retains its voltage indefinitely. If,
vC
(a) (b) (c)
Figure 4.34 The clamped capacitor or dc restorer with a square-wave input and no load.
4.6 Limiting and Clamping Circuits 225 for instance, the input square wave has the arbitrary levels –6 V and +4 V, then vC will be
equal to 6 V. Now, since the output voltage vO is given by vO =vI +vC
it follows that the output waveform will be identical to that of the input, except that it is shifted upwardbyvC volts.Inourexampletheoutputwillthusbeasquarewavewithlevelsof0V and +10 V.
Another way of visualizing the operation of the circuit in Fig. 4.34 is to note that because the diode is connected across the output with the polarity shown, it prevents the output voltage from going below 0 V (by conducting and charging up the capacitor, thus causing the output to rise to 0 V), but this connection will not constrain the positive excursion of vO. The output waveform will therefore have its lowest peak clamped to 0 V, which is why the circuit is called a clamped capacitor. It should be obvious that reversing the diode polarity will provide an output waveform whose highest peak is clamped to 0 V. In either case, the output waveform will have a finite average value or dc component. This dc component is entirely unrelated to the average value of the input waveform. As an application, consider a pulse signal being transmitted through a capacitively coupled or ac-coupled system. The capacitive coupling will cause the pulse train to lose whatever dc component it originally had. Feeding the resulting pulse waveform to a clamping circuit provides it with a well-determined dc component, a process known as dc restoration. This is why the circuit is also called a dc restorer.
Restoring dc is useful because the dc component or average value of a pulse waveform is an effective measure of its duty cycle.5 The duty cycle of a pulse waveform can be modulated (in a process called pulsewidth modulation) and made to carry information. In such a system, detection or demodulation could be achieved simply by feeding the received pulse waveform to a dc restorer and then using a simple RC low-pass filter to separate the average of the output waveform from the superimposed pulses.
When a load resistance R is connected across the diode in a clamping circuit, as shown in Fig. 4.35, the situation changes significantly. While the output is above ground, a current must flow in R. Since at this time the diode is off, this current obviously comes from the capacitor,
(b)
(a)
Figure 4.35 The clamped capacitor with a load resistance R.
(c)
5The duty cycle of a pulse waveform is the proportion of each cycle occupied by the pulse. In other words, it is the pulse width expressed as a fraction of the pulse period.
226 Chapter 4
Diodes
thus causing the capacitor to discharge and the output voltage to fall. This is shown in Fig. 4.35 forasquare-waveinput.Duringtheintervalt0 tot1,theoutputvoltagefallsexponentiallywith time constant CR. At t1 the input decreases by Va volts, and the output attempts to follow. This causes the diode to conduct heavily and to quickly charge the capacitor. At the end of the interval t1 to t2, the output voltage would normally be a few tenths of a volt negative (e.g., –0.5 V). Then, as the input rises by Va volts (at t2 ), the output follows, and the cycle repeats itself. In the steady state the charge lost by the capacitor during the interval t0 to t1 is recovered during the interval t1 to t2. This charge equilibrium enables us to calculate the average diode current as well as the details of the output waveform.
4.6.3 The Voltage Doubler
Figure 4.36(a) shows a circuit composed of two sections in cascade: a clamped capacitor formed by C1 and D1, and a peak rectifier formed by D2 and C2. When excited by a sinusoid of amplitude Vp the clamping section provides the voltage waveform vD1 shown, assuming ideal diodes, in Fig. 4.36(b). Note that while the positive peaks are clamped to 0 V, the negative peak reaches –2Vp. In response to this waveform, the peak-detector section provides across capacitor C2 a dc voltage equal to the negative peak of vD1, that is, −2Vp. Because the output voltage is double the input peak, the circuit is known as a voltage doubler. The technique can be extended to provide output dc voltages that are higher multiples of Vp.
D
vI =Vp sinvt D
vO =2Vp
Vp
0
Vp
2Vp
vI
t
vD1
vO
(a)
(b)
Figure4.36 Voltagedoubler:(a)circuit;(b)waveformsoftheinputvoltage,thevoltageacrossD1,andthe output voltage vo = −2Vp .
4.7 Special Diode Types 227
EXERCISE
4.27 If the diode in the circuit of Fig. 4.34 is reversed, what will the dc component of vO become? Ans. –5 V
4.7 Special Diode Types
In this section, we discuss briefly some important special types of diodes.
4.7.1 The Schottky-Barrier Diode (SBD)
The Schottky-barrier diode (SBD) is formed by bringing metal into contact with a moderately doped n-type semiconductor material. The resulting metal–semiconductor junction behaves like a diode, conducting current in one direction (from the metal anode to the semiconductor cathode) and acting as an open circuit in the other, and is known as the Schottky-barrier diode or simply the Schottky diode. In fact, the current–voltage characteristic of the SBD is remarkably similar to that of a pn-junction diode, with two important exceptions:
1. In the SBD, current is conducted by majority carriers (electrons). Thus the SBD does not exhibit the minority-carrier charge-storage effects found in forward-biased pn junctions. As a result, Schottky diodes can be switched from on to off, and vice versa, much faster than is possible with pn-junction diodes.
2. The forward voltage drop of a conducting SBD is lower than that of a pn-junction diode. For example, an SBD made of silicon exhibits a forward voltage drop of 0.3 V to 0.5 V, compared to the 0.6 V to 0.8 V found in silicon pn-junction diodes. SBDs can also be made of gallium arsenide (GaAs) and, in fact, play an important role in the design of GaAs circuits.6 Gallium-arsenide SBDs exhibit forward voltage drops of about 0.7 V.
Apart from GaAs circuits, Schottky diodes find application in the design of a special form of bipolar-transistor logic circuits, known as Schottky-TTL, where TTL stands for transistor–transistor logic.
Before leaving the subject of Schottky-barrier diodes, it is important to note that not every metal–semiconductor contact is a diode. In fact, metal is commonly deposited on the semiconductor surface in order to make terminals for the semiconductor devices and to connect different devices in an integrated-circuit chip. Such metal–semiconductor contacts are known as ohmic contacts to distinguish them from the rectifying contacts that result in SBDs. Ohmic contacts are usually made by depositing metal on very heavily doped (and thus low-resistivity) semiconductor regions. (Recall that SBDs use moderately doped material.)
6The website accompanying this text contains material on GaAs circuits.
228 Chapter 4
Diodes
4.7.2 Varactors
In Chapter 3 we learned that reverse-biased pn junctions exhibit a charge-storage effect that ismodeledwiththedepletion-layerorjunctioncapacitanceCj.AsEq.(3.49)indicates,Cj is a function of the reverse-bias voltage VR. This dependence turns out to be useful in a number of applications, such as the automatic tuning of radio receivers. Special diodes are therefore fabricated to be used as voltage-variable capacitors known as varactors. These devices are optimized to make the capacitance a strong function of voltage by arranging that the grading coefficient m is 3 or 4.
4.7.3 Photodiodes
If a reverse-biased pn junction is illuminated—that is, exposed to incident light—the photons impacting the junction cause covalent bonds to break, and thus electron-hole pairs are generated in the depletion layer. The electric field in the depletion region then sweeps the liberated electrons to the n side and the holes to the p side, giving rise to a reverse current across the junction. This current, known as photocurrent, is proportional to the intensity of the incident light. Such a diode, called a photodiode, can be used to convert light signals into electrical signals.
Photodiodes are usually fabricated using a compound semiconductor7 such as gallium arsenide. The photodiode is an important component of a growing family of circuits known as optoelectronics or photonics. As the name implies, such circuits utilize an optimum combination of electronics and optics for signal processing, storage, and transmission. Usually, electronics is the preferred means for signal processing, whereas optics is most suited for transmission and storage. Examples include fiber-optic transmission of telephone and television signals and the use of optical storage in CD-ROM computer discs. Optical transmission provides very wide bandwidths and low signal attenuation. Optical storage allows vast amounts of data to be stored reliably in a small space.
Finally, we should note that without reverse bias, the illuminated photodiode functions as a solar cell. Usually fabricated from low-cost silicon, a solar cell converts light to electrical energy.
4.7.4 Light-Emitting Diodes (LEDs)
The light-emitting diode (LED) performs the inverse of the function of the photodiode; it con- verts a forward current into light. The reader will recall from Chapter 3 that in a forward-biased pn junction, minority carriers are injected across the junction and diffuse into thep and n regions. The diffusing minority carriers then recombine with the majority carriers. Such recombination can be made to give rise to light emission. This can be done by fabricating the pn junction using a semiconductor of the type known as direct-bandgap materials. Gallium arsenide belongs to this group and can thus be used to fabricate light-emitting diodes.
The light emitted by an LED is proportional to the number of recombinations that take place, which in turn is proportional to the forward current in the diode.
7 Whereas an elemental semiconductor, such as silicon, uses an element from column IV of the periodic table, a compound semiconductor uses a combination of elements from columns III and V or II and VI. For example, GaAs is formed of gallium (column III) and arsenic (column V) and is thus known as a III-V compound.
LEDs are very popular devices. They find application in the design of numerous types of displays, including the displays of laboratory instruments such as digital voltmeters. They can be made to produce light in a variety of colors. Furthermore, LEDs can be designed so as to produce coherent light with a very narrow bandwidth. The resulting device is a laser diode. Laser diodes find application in optical communication systems and in DVD players, among other things.
Combining an LED with a photodiode in the same package results in a device known as an optoisolator. The LED converts an electrical signal applied to the optoisolator into light, which the photodiode detects and converts back to an electrical signal at the output of the optoisolator. Use of the optoisolator provides complete electrical isolation between the electrical circuit that is connected to the isolator’s input and the circuit that is connected to its output. Such isolation can be useful in reducing the effect of electrical interference on signal transmission within a system, and thus optoisolators are frequently employed in the design of digital systems. They can also be used in the design of medical instruments to reduce the risk of electrical shock to patients.
Note that the optical coupling between an LED and a photodiode need not be accomplished inside a small package. Indeed, it can be implemented over a long distance using an optical fiber, as is done in fiber-optic communication links.
Summary 229
FROM INDICATION TO ILLUMINATION:
Light-emitting diodes (LEDs), which once served only as low-powered status indicators, are now lighting our way! Increasingly, automotive lighting uses LEDs; increasingly, too, LED bulbs of higher and higher power are replacing both incandescent and fluorescent lighting in homes and offices. Incandescent bulbs are only 5% efficient in the conversion of electricity into light—the other 95% is dissipated as heat. The light conversion efficiency of LEDs, however, is 60%. Moreover, LEDs last 25 times longer (25,000 hours) than incandescent bulbs and 3 times longer than fluorescents.
Summary
In the forward direction, the ideal diode conducts any current forced by the external circuit while displaying a zero voltage drop. The ideal diode does not conduct in the reverse direction; any applied voltage appears as reverse bias across the diode.
The unidirectional-current-flow property makes the diode useful in the design of rectifier circuits.
The forward conduction of practical silicon-junction
diodes is accurately characterized by the relationship
i=I ev/VT . S
A silicon diode conducts a negligible current until the forward voltage is at least 0.5V. Then the current increases rapidly, with the voltage drop increasing by 60 mV for every decade of current change.
In the reverse direction, a silicon diode conducts a current on the order of 10−9 A. This current is much greater than IS because of leakage effects and increases with the magnitude of reverse voltage.
Beyond a certain value of reverse voltage (that depends on the diode), breakdown occurs, and current increases rapidly with a small corresponding increase in voltage.
Diodes designed to operate in the breakdown region are called zener diodes. They are employed in the design of voltage regulators whose function is to provide a constant dc voltage that varies little with variations in power-supply voltage and/or load current.
230 Chapter 4 Diodes
In many applications, a conducting diode is modeled as having a constant voltage drop, usually approximately 0.7 V.
A diode biased to operate at a dc current ID has a small-signalresistancerd =VT/ID.
Rectifiers convert ac voltages into unipolar voltages. Half-wave rectifiers do this by passing the voltage in half of each cycle and blocking the opposite-polarity voltage in the other half of the cycle. Full-wave rectifiers accomplish the task by passing the voltage in half of each cycle and inverting the voltage in the other half-cycle.
The bridge-rectifier circuit is the preferred full-wave rectifier configuration.
The variation of the output waveform of the rectifier is reduced considerably by connecting a capacitor C across the output load resistance R. The resulting circuit is the peak rectifier. The output waveform then consists of a dc voltage almost equal to the peak of the input sine
PROBLEMS
Computer Simulation Problems
Problems identified by the Multisim/PSpice icon are intended to demonstrate the value of using SPICE simulation to verify hand analysis and design, and to investigate important issues such as allowable signal swing and amplifier nonlinear distortion. Instructions to assist in setting up PSPice and Multisim simulations for all the indicated problems can be found in the corresponding files on the website. Note that if a particular parameter value is not specified in the problem statement, you are to make a reasonable assumption.
Section 4.1: The Ideal Diode
4.1 An AA flashlight cell, whose The ́venin equivalent is a voltage source of 1.5 V and a resistance of 1 , is connected
wave, Vp , on which is superimposed a ripple component of frequency 2f (in the full-wave case) and of peak-to-peak amplitude Vr = Vp/2fCR. To reduce this ripple voltage further, a voltage regulator is employed.
Combination of diodes, resistors, and possibly reference voltages can be used to design voltage limiters that prevent one or both extremities of the output waveform from going beyond predetermined values, the limiting level(s).
Applying a time-varying waveform to a circuit consisting of a capacitor in series with a diode and taking the output across the diode provides a clamping function. Specifically, depending on the polarity of the diode, either the positive or negative peaks of the signal will be clamped to the voltage at the other terminal of the diode (usually ground). In this way the output waveform has a nonzero average or dc component, and the circuit is known as a dc restorer.
By cascading a clamping circuit with a peak-rectifier circuit, a voltage doubler is realized.
to the terminals of an ideal diode. Describe two possible situations that result. What are the diode current and terminal voltage when (a) the connection is between the diode cathode and the positive terminal of the battery and (b) the anode and the positive terminal are connected?
4.2 For the circuits shown in Fig. P4.2 using ideal diodes, find the values of the voltages and currents indicated.
4.3 For the circuits shown in Fig. P4.3 using ideal diodes, find the values of the labeled voltages and currents.
4.4 In each of the ideal-diode circuits shown in Fig. P4.4, vI is a 1-kHz, 5-V peak sine wave. Sketch the waveform resulting at v O . What are its positive and negative peak values?
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
Problems 231
CHAPTER 4 PROBLEMS
3333
3333
(b) (c)
(a)
Figure P4.2
(d)
Figure P4.3
D1 vI
(a)
vO vI
D1 D2
(b)
vO vI
D1 D2
(c)
vO
D
3
22
D
D
D
(a)
1 k
(b)
2
3
2
1 k
1 k
D3
D2
(f)
D1 D2 D1
vI vO vI 1 k
D2
(d)
Figure P4.4
vO vI
vO
1 k
1 k
D1
(e)
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
232 Chapter 4
Diodes
1 k D1 D1 D2 D1
vI
1 k
vO
1 k vI
1 k
vO vI vO
(g)
D1
1 k
(h) (i)
15 V
1 mA
vO
CHAPTER 4 PROBLEMS
vI
vO
1 k
D2
1 k
D1
vI
(j) (k)
FigureP4.4 continued
4.5 The circuit shown in Fig. P4.5 is a model for a battery
charger. Here vI is a 6-V peak sine wave, D1 and D2 are ideal diodes, I is a 60-mA current source, and B is a 3-V battery. Sketch and label the waveform of the battery current iB . What is its peak value? What is its average value? If the peak value of vI is reduced by 10%, what do the peak and average values of iB become?
I
iB I vI vO D1
D1D2 AX
4.6 The circuits shown in Fig. P4.6 can function as logic gates for input voltages that are either high or low. Using “1” to denote the high value and “0” to denote the low value, prepare a table with four columns including all possible input combinations and the resulting values of X and Y. What logic function is X of A and B? What logic function is Y of A and B? For what values of A and B do X and Y have the same value? For what values of A and B do X and Y have opposite values?
D3 A
BY D4
I
B
B
D2 Figure P4.6
(a)
(b)
Figure P4.5
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CHAPTER 4 PROBLEMS
D 4.7 For the logic gate of Fig. 4.5(a), assume ideal diodes and input voltage levels of 0 V and +5 V. Find a suitable value for R so that the current required from each of the input signal sources does not exceed 0.2 mA.
D 4.8 Repeat Problem 4.7 for the logic gate of Fig. 4.5(b). 4.9 Assuming that the diodes in the circuits of Fig. P4.9 are
ideal, find the values of the labeled voltages and currents.
3V 3V
be ideal. Select a suitable value for R so that the peak diode current does not exceed 40 mA. What is the greatest reverse voltage that will appear across the diode?
4.12 Consider the rectifier circuit of Fig. 4.3(a) in the event thattheinputsourcevI hasasourceresistanceRs.Forthecase Rs = R and assuming the diode to be ideal, sketch and clearly label the transfer characteristic v O versus v I .
4.13 A symmetrical square wave of 5-V peak-to-peak amplitude and zero average is applied to a circuit resembling that in Fig. 4.3(a) and employing a 100- resistor. What is the peak output voltage that results? What is the average output voltage that results? What is the peak diode current? What is the average diode current? What is the maximum reverse voltage across the diode?
4.14 Repeat Problem 4.13 for the situation in which the average voltage of the square wave is 1V, while its peak-to-peak value remains at 5 V.
D *4.15 Design a battery-charging circuit, resembling that in Fig. 4.4(a) and using an ideal diode, in which current flows to the 12-V battery 25% of the time with an average value of 100 mA. What peak-to-peak sine-wave voltage is required? What resistance is required? What peak diode current flows? What peak reverse voltage does the diode endure? If resistors can be specified to only one significant digit, and the peak-to-peak voltage only to the nearest volt, what design would you choose to guarantee the required charging current? What fraction of the cycle does diode current flow? What is the average diode current? What is the peak diode current? What peak reverse voltage does the diode endure?
4.16 The circuit of Fig. P4.16 can be used in a signaling system using one wire plus a common ground return. At any moment, the input has one of three values: +3 V, 0 V, –3 V.
DD
Figure P4.16
Problems 233
12 k
6 k
DD DD
Figure P4.9
6 k
12 k
3V 3V (a) (b)
4.10 Assuming that the diodes in the circuits of Fig. P4.10 are ideal, utilize The ́venin’s theorem to simplify the circuits and thus find the values of the labeled currents and voltages.
5 V
5 V
10 k
3 V
10 k
I
10
Figure P4.10
(a)
V
10 k 10 k
(b)
D 4.11 For the rectifier circuit of Fig. 4.3(a), let the input sine wave have 120-V rms value and assume the diode to
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234 Chapter 4 Diodes
What is the status of the lamps for each input value? (Note that the lamps can be located apart from each other and that there may be several of each type of connection, all on one wire!)
Section 4.2: Terminal Characteristics of Junction Diodes
4.17 Calculate the value of the thermal voltage, VT , at –55°C, 0°C, +40°C, and +125°C. At what temperature is VT exactly 25 mV?
4.18 Atwhatforwardvoltagedoesadiodeconductacurrent equal to 10,000IS? In terms of IS, what current flows in the same diode when its forward voltage is 0.7 V?
4.19 A diode for which the forward voltage drop is 0.7 V at 1.0 mA is operated at 0.5 V. What is the value of the current?
4.20 A particular diode is found to conduct 1 mA with a junction voltage of 0.7 V. What current will flow in this diode if the junction voltage is raised to 0.71 V? To 0.8 V? If the junction voltage is lowered to 0.69 V? To 0.6 V? What change in junction voltage will increase the diode current by a factor of 10?
4.21 The following measurements are taken on particular junction diodes for which V is the terminal voltage and I is the diode current. For each diode, estimate values of IS and the terminal voltage at 10% of the measured current.
(a) V=0.700VatI=1.00A (b) V=0.650VatI=1.00mA (c) V=0.650VatI=10μA (d) V=0.700VatI=100mA
4.22 Listed below are the results of measurements taken on several different junction diodes. For each diode, the data provided are the diode current I and the corresponding diode voltage V. In each case, estimate IS , and the diode voltage at 10I and I/10.
(a) 10.0 mA, 700 mV (b) 1.0 mA, 700 mV (c) 10 A, 800 mV
(d) 1mA,700mV (e) 10 μA, 600 mV
4.23 The circuit in Fig. P4.23 utilizes three identical diodes having IS = 10−14 A. Find the value of the current I required to obtain an output voltage VO = 2.0 V. If a current of 1 mA is drawn away from the output terminal by a load, what is the change in output voltage?
Figure P4.23
4.24 A junction diode is operated in a circuit in which it is supplied with a constant current I. What is the effect on the forward voltage of the diode if an identical diode is connected in parallel?
4.25 Two diodes with saturation currents IS1 and IS2 are connected in parallel with their cathodes joined together and connected to grounds. The two anodes are joined together and fed with a constant current I. Find the currents ID1 and ID2 that flow through the two diodes, and the voltage VD that appears across their parallel combination.
4.26 Four diodes are connected in parallel: anodes joined together and fed with a constant current I, and cathodes joined together and connected to ground. What relative junction areas should these diodes have if their currents must have binary-weighted ratios, with the smallest being 0.1 mA? What value of I is needed?
4.27 In the circuit shown in Fig. P4.27, D1 has 10 times the junction area of D2 . What value of V results? To obtain a value for V of 60 mV, what current I2 is needed?
CHAPTER 4 PROBLEMS
I1 10 mA
I2 V
D2
D1
3 mA
Figure P4.27
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CHAPTER 4 PROBLEMS
4.28 For the circuit shown in Fig. P4.28, both diodes are identical. Find the value of R for which V = 50 mV.
junction temperature? What is the power dissipated in the diode in its final state? What is the temperature rise per watt of power dissipation? (This is called the thermal resistance.)
*4.32 A designer of an instrument that must operate over a wide supply-voltage range, noting that a diode’s junction-voltage drop is relatively independent of junction current, considers the use of a large diode to establish a small relatively constant voltage. A power diode, for which the nominal current at 0.8 V is 10 A, is available. If the current source feeding the diode changes in the range 1 mA to 3 mA and if, in addition, the temperature changes by ±20°C, what is the expected range of diode voltage?
*4.33 As an alternative to the idea suggested in Prob- lem 4.32, the designer considers a second approach to produc- ing a relatively constant small voltage from a variable current supply: It relies on the ability to make quite accurate copies of any small current that is available (using a process called current mirroring). The designer proposes to use this idea to supply two diodes of different junction areas with equal cur- rents and to measure their junction-voltage difference. Two types of diodes are available: for a forward voltage of 700 mV, one conducts 0.1 mA, while the other conducts 1 A. Now, for identical currents in the range of 1 mA to 3 mA supplied to each, what range of difference voltages result? What is the effect of a temperature change of ±20°C on this arrangement?
Section 4.3: Modeling the Diode Forward Characteristic
*4.34 Consider the graphical analysis of the diode circuit of Fig. 4.10 with VDD =1 V, R=1 k, and a diode having IS = 10−15 A. Calculate a small number of points on the diode characteristic in the vicinity of where you expect the load line to intersect it, and use a graphical process to refine your estimate of diode current. What value of diode current and voltage do you find? Analytically, find the voltage corresponding to your estimate of current. By how much does it differ from the graphically estimated value?
4.35 Use the iterative-analysis procedure to determine the diode current and voltage in the circuit of Fig. 4.10 for VDD =1 V, R=1 k, and a diode having IS = 10−15 A.
4.36 A “1-mA diode” (i.e., one that has vD =0.7 V at iD = 1 mA) is connected in series with a 500- resistor to a 1.0 V supply.
Problems 235
D2
I
10 mA
V
D1
R
10 V
R1
Figure P4.28
4.29 A diode fed with a constant current I=1mA has a voltage V = 690 mV at 20°C. Find the diode voltage at −20°C and at +85°C.
4.30 In the circuit shown in Fig. P4.30, D1 is a large-area, high-current diode whose reverse leakage is high and independent of applied voltage, while D2 is a much smaller, low-current diode. At an ambient temperature of 20°C, resistor R1 is adjusted to make VR1 = V2 = 520 mV. Subsequent measurement indicates that R1 is 520 k. What do you expect the voltages VR1 and V2 to become at 0°C and at 40°C?
D1 V1
D2 V2
Figure P4.30
4.31 When a 10-A current is applied to a particular diode, it is found that the junction voltage immediately becomes 700 mV. However, as the power being dissipated in the diode raises its temperature, it is found that the voltage decreases and eventually reaches 600 mV. What is the apparent rise in
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236 Chapter 4 Diodes
(a) Provide a rough estimate of the diode current you would expect.
(b) Estimate the diode current more closely using iterative analysis.
D 4.37 Assuming the availability of diodes for which vD = 0.75 V at iD = 1 mA, design a circuit that utilizes four diodes connected in series, in series with a resistor R connected to a 15-V power supply. The voltage across the string of diodes is to be 3.3 V.
4.38 A diode operates in a series circuit with a resistance R and a dc source V. A designer, considering using a constant-voltage model, is uncertain whether to use 0.7 V or 0.6V for VD. For what value of V is the difference in the calculated values of current only 1%? For V = 3 V and R = 1 k, what two current estimates would result from the use of the two values of VD? What is their percentage difference?
4.39 A designer has a supply of diodes for which a current of 2 mA flows at 0.7 V. Using a 1-mA current source, the designer wishes to create a reference voltage of 1.3 V. Suggest a combination of series and parallel diodes that will do the job as well as possible. How many diodes are needed? What voltage is actually achieved?
4.46 The small-signal model is said to be valid for voltage variations of about 5 mV. To what percentage current change does this correspond? (Consider both positive and negative signals.) What is the maximum allowable voltage signal (positive or negative) if the current change is to be limited to 10%?
4.47 In a particular circuit application, ten “20-mA diodes” (a 20-mA diode is a diode that provides a 0.7-V drop when the current through it is 20 mA) connected in parallel operate at a total current of 0.1 A. For the diodes closely matched, what current flows in each? What is the corresponding small-signal resistance of each diode and of the combination? Compare this with the incremental resistance of a single diode conducting 0.1 A. If each of the 20-mA diodes has a series resistance of 0.2 associated with the wire bonds to the junction, what is the equivalent resistance of the 10 parallel-connected diodes? What connection resistance would a single diode need in order to be totally equivalent? (Note: This is why the parallel connection of real diodes can often be used to advantage.)
4.48 In the circuit shown in Fig. P4.48, I is a dc current and vs is a sinusoidal signal. Capacitors C1 and C2 are very large; their function is to couple the signal to and from the diode but block the dc current from flowing into the signal source or the load (not shown). Use the diode small-signal model to show that the signal component of the output voltage is
v=v VT
o s VT +IRs
Ifvs =10mV,findvo forI=1mA,0.1mA,and1μA.Let Rs = 1 k. At what value of I does vo become one-half of vs? Note that this circuit functions as a signal attenuator with the attenuation factor controlled by the value of the dc current I.
CHAPTER 4 PROBLEMS
4.40 Solve the problems in Example 4.2 constant-voltage-drop (VD = 0.7 V) diode model.
4.41 For the circuits shown in Fig. P4.2, constant-voltage-drop (VD = 0.7 V) diode model, find the voltages and currents indicated.
4.42 For the circuits shown in Fig. P4.3, using the constant-voltage-drop (VD = 0.7 V) diode model, find the voltages and currents indicated.
4.43 For the circuits in Fig. P4.9, using the constant-voltage-drop (VD = 0.7 V) diode model, find the values of the labeled currents and voltages.
4.44 For the circuits in Fig. P4.10, utilize The ́venin’s theo- rem to simplify the circuits and find the values of the labeled currents and voltages. Assume that conducting diodes can be represented by the constant-voltage-drop model (VD = 0.7 V).
D 4.45 Repeat Problem 4.11, representing the diode by the constant-voltage-drop (VD = 0.7 V) model. How different is the resulting design?
using the
using the
Figure P4.48
C1
C2
vo
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4.49 In the attenuator circuit of Fig. P4.48, let Rs = 10 k. The diode is a 1-mA device; that is, it exhibits a voltage drop of 0.7 V at a dc current of 1 mA. For small input signals, what value of current I is needed for v o /v s = 0.50? 0.10? 0.01? 0.001? In each case, what is the largest input signal that can be used while ensuring that the signal component of the diode current is limited to ±10% of its dc current? What output signals correspond?
4.50 In the capacitor-coupled attenuator circuit shown in
Fig. P4.50, I is a dc current that varies from 0 mA to 1 mA,
and C1 and C2 are large coupling capacitors. For very small
input signals, so that the diodes can be represented by their
small-signal resistances rd 1 and rd 2 , give the small-signal
(b)
(c)
For a forward-conducting diode, what is the largest signal-voltage magnitude that it can support while the corresponding signal current is limited to 10% of the dc bias current? Now, for the circuit in Fig. P4.51, for 10-mV peak input, what is the smallest value of I for which the diode currents remain within ±10% of their dc values? For I = 1 mA, what is the largest possible output signal for which the diode currents deviate by at most 10% of their dc values? What is the corresponding peak input? What is the total current in each diode?
equivalent circuit and thus show that v o = v vi
rd 2 rd1 +rd2
and hence
I
Problems 237
CHAPTER 4 PROBLEMS
that o =I,whereIisinmA.Findvo/vi forI=0μA,1μA, vi
10μA, 100μA, 500μA, 600μA, 900μA, 990μA, and 1 mA. Note that this is a signal attenuator whose transmission is linearly controlled by the dc current I.
D1
D3
1 mA
vo vi D2 D4 10 k
I
Figure P4.51
**4.52 In Problem 4.51 we investigated the operation of the circuit in Fig. P4.51 for small input signals. In this problem we wish to find the voltage-transfer characteristic (VTC) vO versus vI for −12V≤vI ≤12V for the case I =1mA and each of the diodes exhibits a voltage drop of 0.7 V at a current of 1 mA. Toward this end, use the diode exponential characteristic to construct a table that gives the values of: the currentiO inthe10-kresistor,thecurrentineachofthefour diodes, the voltage drop across each of the four diodes, and the input voltage vI, for vO =0, +1V, +2V, +5V, +9V, +9.9 V, +9.99 V, +10.5 V, +11 V, and +12 V. Use these data, with extrapolation to negative values of vI and vO, to sketch the required VTC. Also sketch the VTC that results if I is reduced to 0.5 mA. (Hint: From symmetry, observe that as vO increases and iO correspondingly increases, iD 3 and iD 2 increase by equal amounts and iD4 and iD1 decrease by (the same) equal amounts.)
C2
vo
vi
C1
D1
I
D2
Figure P4.50
*4.51 In the circuit shown in Fig. P4.51, diodes D1 through D4 are identical, and each exhibits a voltage drop of 0.7 V at a 1-mA current.
(a) For small input signals (e.g., 10-mV peak), find the small-signal equivalent circuit and use it to determine values of the small-signal transmission v o /v i for various values of I: 0μA, 1μA, 10μA, 100μA, 1mA, and 10 mA.
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238 Chapter 4 Diodes
*4.53 In the circuit shown in Fig. P4.53, I is a dc current and vi is a sinusoidal signal with small amplitude (less than 10 mV) and a frequency of 100 kHz. Representing the diode by its small-signal resistance rd , which is a function of I, sketch the small-signal equivalent circuit and use it to determine the sinusoidal output voltage Vo, and thus find the phase shift between Vi and Vo. Find the value of I that will provide a phase shift of –45°, and find the range of phase shift achieved as I is varied over the range of 0.1 times to 10 times this value.
(b) Generalize the expression above for the case of m diodes connected in series and the value of R adjusted so that the voltage across each diode is 0.7 V (and VO = 0.7m V).
(c) Calculate the value of line regulation for the case V+ = 15V(nominally)and(i)m=1and(ii)m=4.
*4.55 Consider the voltage-regulator circuit shown in FigP4.54undertheconditionthataloadcurrentIL isdrawn from the output terminal.
I
(a)
If the value of IL is sufficiently small that the corre- spondingchangeinregulatoroutputvoltageVO issmall enough to justify using the diode small-signal model, show that
VO =−rd∥R IL
This quantity is known as the load regulation and is usually expressed in mV/mA. IfthevalueofRisselectedsuchthatatnoloadthevoltage across the diode is 0.7 V and the diode current is ID , show that the expression derived in (a) becomes
VO =−VT V+−0.7
IL ID V+−0.7+VT
Select the lowest possible value for ID that results in a load regulation whose magnitude is ≤ 5 mV/mA. If V + is nominally 15 V, what value of R is required? Also, specify the diode required in terms of its IS .
Generalize the expression derived in (b) for the case of m diodes connected in series and R adjusted to obtain VO = 0.7m V at no load.
CHAPTER 4 PROBLEMS
vo 10 nF
*4.54 Consider the voltage-regulator circuit shown in Fig. P4.54. The value of R is selected to obtain an output voltage VO (across the diode) of 0.7 V.
V
C vi
(b)
Figure P4.53
R
(c)
VO
D *4.56 Design a diode voltage regulator to supply 1.5 V to a 1.5-k load. Use two diodes specified to have a 0.7-V drop at a current of 1 mA. The diodes are to be connected to a +5-V supply through a resistor R. Specify the value for R. What is the diode current with the load connected? What is the increase resulting in the output voltage when the load is disconnected? What change results if the load resistance is reduced to 1 k? To 750 ? To 500 ? (Hint: Use the small-signal diode model to calculate all changes in output voltage.)
D *4.57 A voltage regulator consisting of two diodes in series fed with a constant-current source is used as a replacement for a single carbon–zinc cell (battery) of nominal voltage 1.5 V. The regulator load current varies from 2 mA to
Figure P4.54
(a) Use the diode small-signal model to show that the change in output voltage corresponding to a change of 1 V in V+ is
VO= VT
V+ V+ +VT −0.7
This quantity is known as the line regulation and is usually expressed in mV/V.
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CHAPTER 4 PROBLEMS
7 mA. Constant-current supplies of 5 mA, 10 mA, and 15 mA are available. Which would you choose, and why? What change in output voltage would result when the load current varies over its full range?
**4.58 A particular design of a voltage regulator is shown in Fig. P4.58. Diodes D1 and D2 are 10-mA units; that is, each has a voltage drop of 0.7 V at a current of 10 mA. Use the diode exponential model and iterative analysis to answer the following questions:
(c) rz =2,VZ =6.8V,andVZK =6.6V
(d) VZ =18V,IZT =5mA,andVZK =17.6V (e) IZT =200mA,VZ =7.5V,andrz =1.5
Assuming that the power rating of a breakdown diode is established at about twice the specified zener current (IZT ), what is the power rating of each of the diodes described above?
D 4.60 A designer requires a shunt regulator of approxi- mately 20 V. Two kinds of zener diodes are available: 6.8-V deviceswithrz of10and5.1-Vdeviceswithrz of25.For the two major choices possible, find the load regulation. In this calculation neglect the effect of the regulator resistance R.
4.61 A shunt regulator utilizing a zener diode with an incremental resistance of 8 is fed through an 82- resistor. If the raw supply changes by 1.0 V, what is the corresponding change in the regulated output voltage?
4.62 A 9.1-V zener diode exhibits its nominal voltage at a test current of 20 mA. At this current the incremental resistance is specified as 10 . Find VZ0 of the zener model. Find the zener voltage at a current of 10 mA and at 50 mA.
D 4.63 Design a 7.5-V zener regulator circuit using a 7.5-V zener specified at 10 mA. The zener has an incremental resistance rz = 30 and a knee current of 0.5 mA. The regulator operates from a 10-V supply and has a 1.5-k load. What is the value of R you have chosen? What is the regulator output voltage when the supply is 10% high? Is 10% low? What is the output voltage when both the supply is 10% high and the load is removed? What is the smallest possible load resistor that can be used while the zener operates at a current no lower than the knee current while the supply is 10% low? What is the load voltage in this case?
D 4.64 Provide two designs of shunt regulators utilizing the 1N5235zenerdiode,whichisspecifiedasfollows:VZ =6.8V and rz =5 for IZ =20mA; at IZ =0.25mA (nearer the knee), rz = 750 . For both designs, the supply voltage is nominally 9 V and varies by ±1 V. For the first design, assume that the availability of supply current is not a problem, and thus operate the diode at 20 mA. For the second design, assume that the current from the raw supply is limited, and therefore you are forced to operate the diode at 0.25 mA. For the purpose of these initial designs, assume no load. For each design find the value of R and the line regulation.
D *4.65 A zener shunt regulator employs a 9.1-V zener diodeforwhichVZ =9.1VatIZ =9mA,withrz =40and
5 V
200
D1
VO
Problems 239
150
(a) What is the regulator output voltage V with the 150- O
load connected?
(b) Find VO with no load.
(c) Withtheloadconnected,towhatvaluecanthe5-Vsupply
be lowered while maintaining the loaded output voltage
within 0.1 V of its nominal value?
(d) What does the loaded output voltage become when the
5-V supply is raised by the same amount as the drop
found in (c)?
(e) For the range of changes explored in (c) and (d), by
what percentage does the output voltage change for each percentage change of supply voltage in the worst case?
Section 4.4: Operation in the Reverse Break- down Region—Zener Diodes
4.59 Partialspecificationsofacollectionofzenerdiodesare provided below. For each, identify the missing parameter and
D2
Figure P4.58
estimate its value. Note from Fig. 4.19 that VZK ≃ VZ 0 is very small.
(a) VZ =10.0V,VZK =9.6V,andIZT =50mA (b) IZT =10mA,VZ =9.1V,andrz =30
and IZK
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
240 Chapter 4 Diodes
IZK = 0.5 mA. The available supply voltage of 15 V can vary as much as ±10%. For this diode, what is the value of VZ0? For a nominal load resistance RL of 1 k and a nominal zener current of 10 mA, what current must flow in the supply resistor R? For the nominal value of supply voltage, select a value for resistor R, specified to one significant digit, to provide at least that current. What nominal output voltage results? For a ±10% change in the supply voltage, what variation in output voltage results? If the load current is reduced by 50%, what increase in VO results? What is the smallest value of load resistance that can be tolerated while maintaining regulation when the supply voltage is low? What is the lowest possible output voltage that results? Calculate values for the line regulation and for the load regulation for this circuit using the numerical results obtained in this problem.
D *4.66 It is required to design a zener shunt regulator to provide a regulated voltage of about 10 V. The available 10-V, 1-W zener of type 1N4740 is specified to have a 10-V drop at a test current of 25 mA. At this current, its rz is 7 . The raw supply, VS , available has a nominal value of 20 V but can vary by as much as ±25%. The regulator is required to supply a load current of 0 mA to 20 mA. Design for a minimum zener current of 5 mA.
(a) Find VZ 0 .
(b) Calculate the required value of R.
(c) Find the line regulation. What is the change in VO
expressed as a percentage, corresponding to the ±25%
change in VS ?
(d) Find the load regulation. By what percentage does VO
change from the no-load to the full-load condition?
(e) What is the maximum current that the zener in your design is required to conduct? What is the zener power
dissipation under this condition?
Section 4.5: Rectifier Circuits
4.67 Consider the half-wave rectifier circuit of Fig. 4.23(a) withthediodereversed.LetvS beasinusoidwith10-Vpeak amplitude, and let R = 1 k. Use the constant-voltage-drop diode model with VD = 0.7 V.
(a) Sketch the transfer characteristic. (b) Sketch the waveform of vO.
(c) Find the average value of vO.
(d) Find the peak current in the diode. (e) Find the PIV of the diode.
4.68 Using the exponential diode characteristic, show that for v S and v O both greater than zero, the circuit of Fig. 4.23(a) has the transfer characteristic
vO=vS−vD atiD=1mA−VTlnvO/R
where vS and vO are in volts and R is in kilohms. Note that this relationship can be used to obtain the voltage transfer characteristic vO vs. vS by finding vS corresponding to various values of vO.
4.69 Consider a half-wave rectifier circuit with a triangular-wave input of 5-V peak-to-peak amplitude and zero average, and with R = 1 k. Assume that the diode can be represented by the constant-voltage-drop model with VD = 0.7 V. Find the average value of vO.
4.70 A half-wave rectifier circuit with a 1-k load operates from a 120-V (rms) 60-Hz household supply through a 12-to-1 step-down transformer. It uses a silicon diode that can be modeled to have a 0.7-V drop for any current. What is the peak voltage of the rectified output? For what fraction of the cycle does the diode conduct? What is the average output voltage? What is the average current in the load?
4.71 A full-wave rectifier circuit with a 1-k load operates from a 120-V (rms) 60-Hz household supply through a 6-to-1 transformer having a center-tapped secondary winding. It uses two silicon diodes that can be modeled to have a 0.7-V drop for all currents. What is the peak voltage of the rectified output? For what fraction of a cycle does each diode conduct? What is the average output voltage? What is the average current in the load?
4.72 A full-wave bridge-rectifier circuit with a 1-k load operates from a 120-V (rms) 60-Hz household supply through a 12-to-1 step-down transformer having a single secondary winding. It uses four diodes, each of which can be modeled to have a 0.7-V drop for any current. What is the peak value of the rectified voltage across the load? For what fraction of a cycle does each diode conduct? What is the average voltage across the load? What is the average current through the load?
D 4.73 It is required to design a full-wave rectifier circuit using the circuit of Fig. 4.24 to provide an average output voltage of:
(a) 10V (b) 100 V
CHAPTER 4 PROBLEMS
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
In each case find the required turns ratio of the transformer. Assume that a conducting diode has a voltage drop of 0.7 V. The ac line voltage is 120 V rms.
D 4.74 Repeat Problem 4.73 for the bridge-rectifier circuit of Fig. 4.25.
D 4.75 Considerthefull-waverectifierinFig.4.24whenthe transformer turns ratio is such that the voltage across the entire secondary winding is 20 V rms. If the input ac line voltage (120 V rms) fluctuates by as much as ±10%, find the required PIV of the diodes. (Remember to use a factor of safety in your design.)
4.76 The
complementary-output rectifier. Sketch and clearly label the waveforms of v +O and v −O . Assume a 0.7-V drop across each conducting diode. If the magnitude of the average of each output is to be 12 V, find the required amplitude of the sine wave across the entire secondary winding. What is the PIV of each diode?
4.77 Augment the rectifier circuit of Problem 4.70 with a capacitor chosen to provide a peak-to-peak ripple voltage of (i) 10% of the peak output and (ii) 1% of the peak output. In each case:
(a) What average output voltage results?
(b) What fraction of the cycle does the diode conduct? (c) What is the average diode current?
(d) What is the peak diode current?
4.78 Repeat Problem 4.77 for the rectifier in Problem 4.71. 4.79 Repeat Problem 4.77 for the rectifier in Problem 4.72.
D *4.80 It is required to use a peak rectifier to design a dc power supply that provides an average dc output voltage of 12 V on which a maximum of ±1-V ripple is allowed. The rectifier feeds a load of 200 . The rectifier is fed from the line voltage (120 V rms, 60 Hz) through a transformer. The diodes available have 0.7-V drop when conducting. If the designer opts for the half-wave circuit:
(a) Specify the rms voltage that must appear across the transformer secondary.
(b) Find the required value of the filter capacitor.
(c) Findthemaximumreversevoltagethatwillappearacross
the diode, and specify the PIV rating of the diode.
(d) Calculate the average current through the diode during
conduction.
(e) Calculate the peak diode current.
D *4.81 Repeat Problem 4.80 for the case in which the designer opts for a full-wave circuit utilizing a center-tapped transformer.
D *4.82 Repeat Problem 4.80 for the case in which the designer opts for a full-wave bridge-rectifier circuit.
D *4.83 Consider a half-wave peak rectifier fed with a voltage vS having a triangular waveform with 24-V peak-to-peak amplitude, zero average, and 1-kHz frequency. Assume that the diode has a 0.7-V drop when conducting. Let the load resistance R = 100 and the filter capacitor C = 100 μF. Find the average dc output voltage, the time interval during which the diode conducts, the average diode current during conduction, and the maximum diode current.
circuit
in Fig. P4.76
implements a
Problems 241
CHAPTER 4 PROBLEMS
Figure P4.76
DD
DD
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
242 Chapter 4 Diodes
D *4.84 Consider the circuit in Fig. P4.76 with two equal filter capacitors placed across the load resistors R. Assume that the diodes available exhibit a 0.7-V drop when conducting. Design the circuit to provide ±12-V dc output voltages with a peak-to-peak ripple no greater than 1 V. Each supply should be capable of providing 100-mA dc current to its load resistor R. Completely specify the capacitors, diodes, and the transformer.
4.85 The op amp in the precision rectifier circuit of Fig. P4.85 is ideal with output saturation levels of ±13 V. Assume that when conducting the diode exhibits a constant voltage drop of 0.7 V. Find v−, vO, and vA for:
(a) vI =+1V
(b) vI=+3V
(c) vI =−1V
(d) vI =−3V
Also, find the average output voltage obtained when vI is a symmetrical square wave of 1-kHz frequency, 5-V amplitude, and zero average.
(c) vI =−1V (d)vI=−3V
D1
R
R
vI D2
vO
v Figure P4.86
vA
CHAPTER 4 PROBLEMS
vI D
vO
Section 4.6: Limiting and Clamping Circuits
4.87 Sketch the transfer characteristic v O versus v I for the limiter circuits shown in Fig. P4.87. All diodes begin conducting at a forward voltage drop of 0.5 V and have voltage drops of 0.7 V when conducting a current iD ≥ 1 mA.
vA
3 V
3 V
v
R
Figure P4.85
R RL
vI
vO
1 k (a)
4.86 The op amp in the circuit of Fig. P4.86 is ideal with output saturation levels of ±12 V. The diodes exhibit a constant 0.7-V drop when conducting. Find v − , v A , and v O for:
(a) vI =+1V (b) vI = +3 V
vI vO 1 k
(b)
Figure P4.87
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
CHAPTER 4 PROBLEMS
vI
1 k
Problems 243 the diodes can be represented by the constant-voltage-drop
model with VD = 0.7 V. Also assume that the zener voltage is 6.8Vandthatrz isnegligiblysmall.
*4.91 Plot the transfer characteristic of the circuit in Fig. P4.91 by evaluating v I corresponding to v O = 0.5 V, 0.6 V, 0.7 V, 0.8 V, 0 V, –0.5 V, –0.6 V, –0.7 V, and –0.8 V. Use the exponential model for the diodes, and assume that they have 0.7-V drops at 1-mA currents. Characterize the circuit as a hard or soft limiter. What is the value of K? Estimate L+ and L−.
Figure P4.91
4.92 Design limiter circuits using only diodes and 10-k resistors to provide an output signal limited to the range:
(a) –0.7 V and above (b) +2.1 V and below (c) ±1.4 V
Assume that each diode has a 0.7-V drop when conducting.
DD 4.93 Design a two-sided limiting circuit using a resistor, two diodes, and two power supplies to feed a 1-k load with nominal limiting levels of ±2.2 V. Use diodes modeled by a constant 0.7 V. In the nonlimiting region, the voltage gain
vO
3 V 1 k
(c)
vI vO
3 V (d)
FigureP4.87 continued
4.88 The circuits in Fig. P4.87(a) and (d) are connected as follows: The two input terminals are tied together, and the two output terminals are tied together. Sketch the transfer characteristic of the circuit resulting, assuming that the cut-in voltage of the diodes is 0.5 V and their voltage drop when conducting a current iD ≥ 1 mA is 0.7 V.
4.89 Repeat Problem 4.88 for the two circuits in Fig. P4.87(a) and (b) connected together as follows: The two input terminals are tied together, and the two output terminals are tied together.
4.90 Sketch and clearly label the transfer characteristic of thecircuitinFig. P4.90for−15V≤vI ≤ +15 V.Assumethat
Figure P4.90
DD
should be at least 0.94 V/V.
**4.94 In the circuit shown in Fig. P4.94, the diodes exhibit a 0.7-V drop at 0.1 mA. For inputs over the range of ±5 V, use the diode exponential model to provide a calibrated sketch of the voltages at outputs B and C versus vA. For a 5-V peak,
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
244 Chapter 4 Diodes
100-Hz sinusoid applied at A, sketch the signals at nodes B
and C.
5 k
A B 3 k
1 V
1 k D1
D2
1 k
vO
D2 D3 D1 D4
vI
C
1 k
D3
CHAPTER 4 PROBLEMS
Figure P4.94
2 V Figure P4.95
**4.95 Sketch and label the voltage-transfer characteristic vO versus vI of the circuit shown in Fig. P4.95 over a ±10-V range of input signals. Use the diode exponential model and assume that all diodes are 1-mA units (i.e., each exhibits a 0.7-V drop at a current of 1 mA). What are the slopes of the characteristics at the extreme ±10-V levels?
4.96 A clamped capacitor using an ideal diode with cathode grounded is supplied with a sine wave of 5-V rms. What is the average (dc) value of the resulting output?
*4.97 For the circuits in Fig. P4.97, each utilizing an ideal diode (or diodes), sketch the output for the input shown. Label the most positive and most negative output levels. Assume CR≫T.
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
Problems 245
CHAPTER 4 PROBLEMS
(a) (b) (c) (d)
Figure P4.97
(e) (f) (g) (h)
CHAPTER 5
MOS Field-Effect Transistors (MOSFETs)
Introduction 247
5.1 Device Structure and Physical Operation 248
5.2 Current–Voltage Characteristics 264
5.3 5.4
MOSFET Circuits at DC 276
The Body Effect and Other Topics 288 Summary 291
Problems 292
IN THIS CHAPTER YOU WILL LEARN
1. The physical structure of the MOS transistor and how it works.
2. How the voltage between two terminals of the transistor controls the current that flows through the third terminal, and the equations that describe these current–voltage characteristics.
3. How to analyze and design circuits that contain MOS transistors, resistors, and dc sources.
Introduction
Having studied the junction diode, which is the most basic two-terminal semiconductor device, we now turn our attention to three-terminal semiconductor devices. Three-terminal devices are far more useful than two-terminal ones because they can be used in a multitude of applications, ranging from signal amplification to digital logic and memory. The basic principle involved is the use of the voltage between two terminals to control the current flowing in the third terminal. In this way a three-terminal device can be used to realize a controlled source, which as we have learned in Chapter 1 is the basis for amplifier design. Also, in the extreme, the control signal can be used to cause the current in the third terminal to change from zero to a large value, thus allowing the device to act as a switch. As we shall see in Chapter 14, the switch is the basis for the realization of the logic inverter, the basic element of digital circuits.
There are two major types of three-terminal semiconductor devices: the metal-oxide- semiconductor field-effect transistor (MOSFET), which is studied in this chapter, and the bipolar junction transistor (BJT), which we shall study in Chapter 6. Although each of the two transistor types offers unique features and areas of application, the MOSFET has become by far the most widely used electronic device, especially in the design of integrated circuits (ICs), which are entire circuits fabricated on a single silicon chip.
Compared to BJTs, MOSFETs can be made quite small (i.e., requiring a small area on the silicon IC chip), and their manufacturing process is relatively simple (see Appendix A). Also, their operation requires comparatively little power. Furthermore, circuit designers have found ingenious ways to implement digital and analog functions utilizing MOSFETs almost exclusively (i.e., with very few or no resistors). All of these properties have made it possible to pack large numbers of MOSFETs (as many as 4 billion!) on a single IC chip to implement very sophisticated, very-large-scale-integrated (VLSI) digital circuits such as those for memory and microprocessors. Analog circuits such as amplifiers and filters can also be implemented in MOS technology, albeit in smaller, less-dense chips. Also, both analog and digital functions are increasingly being implemented on the same IC chip, in what is known as mixed-signal design.
247
248 Chapter 5
MOS Field-Effect Transistors (MOSFETs)
THE FIRST FIELD-EFFECT DEVICES:
The objective of this chapter is to develop in the reader a high degree of familiarity with the MOSFET: its physical structure and operation, terminal characteristics, and dc circuit applications. This will provide a solid foundation for the application of the MOSFET in amplifier design (Chapter 7) and in digital circuit design (Chapter 14). Although discrete MOS transistors exist, and the material studied in this chapter will enable the reader to design discrete MOS circuits, our study of the MOSFET is strongly influenced by the fact that most of its applications are in integrated-circuit design. The design of IC analog and digital MOS circuits occupies a large proportion of the remainder of this book.
In 1925 a patent for solid-state electric-field-controlled conductor was filed in Canada by Julius E. Lilienfeld, a physicist at the University of Leipzig, Germany. Other patent refinements followed in the United States in 1926 and 1928. Regrettably, no research papers were published. Consequently, in 1934 Oskar Heil, a German physicist working at the University of Cambridge, U.K., filed a patent on a similar idea. But all these early concepts of electric-field control of a semiconducting path languished because suitable technology was not available.
The invention of the bipolar transistor in 1947 at Bell Telephone Laboratories resulted in the speedy development of bipolar devices, a circumstance that further delayed the development of field-effect transistors. Although the field-effect device was described in a paper by William Shockley in 1952, it was not until 1960 that a patent on an insulated-gate field-effect device, the MOSFET, was filed by Dawon Kahng and Martin Atalla, also at Bell Labs. Clearly, the idea of field-effect control for amplification and switching has changed the world. With integrated-circuit chips today containing billions of MOS devices, MOS dominates the electronics world!
5.1 Device Structure and Physical Operation
The enhancement-type MOSFET is the most widely used field-effect transistor. Except for the last section, this chapter is devoted to the study of the enhancement-type MOSFET. We begin in this section by learning about its structure and physical operation. This will lead to the current–voltage characteristics of the device, studied in the next section.
5.1.1 Device Structure
Figure 5.1 shows the physical structure of the n-channel enhancement-type MOSFET. The meaning of the names “enhancement” and “n-channel” will become apparent shortly. The transistor is fabricated on a p-type substrate, which is a single-crystal silicon wafer that provides physical support for the device (and for the entire circuit in the case of an integrated circuit). Two heavily doped n-type regions, indicated in the figure as the n+ source1 and the n+ drain regions, are created in the substrate. A thin layer of silicon dioxide (SiO2) of thickness tox (typically 1 nm to 10 nm),2 which is an excellent electrical insulator, is grown on the surface of the substrate, covering the area between the source and drain regions. Metal is deposited on top of the oxide layer to form the gate electrode of the device. Metal contacts are
1The notation n+ indicates heavily doped n-type silicon. Conversely, n− is used to denote lightly doped n-type silicon. Similar notation applies for p-type silicon.
2 A nanometer (nm) is 10−9 m or 0.001 μm. A micrometer (μm), or micron, is 10−6 m. Sometimes the oxide thickness is expressed in angstroms. An angstrom (Å) is 10−1 nm, or 10−10 m.
S
Metal
5.1 Device Structure and Physical Operation 249
G
W
n
D
Oxide (SiO2)
Source region
p-type substrate (Body)
Channel region
Source (S)
L
B
n
Drain region (a)
Gate (G)
Drain (D)
Oxide (SiO2) (thickness = tox)
Metal
n Channel n region
L
p-type substrate (Body)
Body (B)
(b)
Figure 5.1 Physical structure of the enhancement-type NMOS transistor: (a) perspective view; (b) cross section. Typically L = 0.03 μm to 1 μm, W = 0.05 μm to 100 μm, and the thickness of the oxide layer (tox ) is in the range of 1 to 10 nm.
also made to the source region, the drain region, and the substrate, also known as the body.3 Thus four terminals are brought out: the gate terminal (G), the source terminal (S), the drain terminal (D), and the substrate or body terminal (B).
3 In Fig. 5.1, the contact to the body is shown on the bottom of the device. This will prove helpful in Section 5.4 in explaining a phenomenon known as the “body effect.” It is important to note, however, that in actual ICs, contact to the body is made at a location on the top of the device.
250 Chapter 5
MOS Field-Effect Transistors (MOSFETs)
At this point it should be clear that the name of the device (metal-oxide-semiconductor FET) is derived from its physical structure. The name, however, has become a general one and is used also for FETs that do not use metal for the gate electrode. In fact, most modern MOSFETs are fabricated using a process known as silicon-gate technology, in which a certain type of silicon, called polysilicon, is used to form the gate electrode (see Appendix A). Our description of MOSFET operation and characteristics applies irrespective of the type of gate electrode.
Another name for the MOSFET is the insulated-gate FET or IGFET. This name also arises from the physical structure of the device, emphasizing the fact that the gate electrode is electrically insulated from the device body (by the oxide layer). It is this insulation that causes the current in the gate terminal to be extremely small (of the order of 10−15 A).
Observe that the substrate forms pn junctions with the source and drain regions. In normal operation these pn junctions are kept reverse biased at all times. Since, as we shall see shortly, the drain will always be at a positive voltage relative to the source, the two pn junctions can be effectively cut off by simply connecting the substrate terminal to the source terminal. We shall assume this to be the case in the following description of MOSFET operation. Thus, here, the substrate will be considered as having no effect on device operation, and the MOSFET will be treated as a three-terminal device, with the terminals being the gate (G), the source (S), and the drain (D). It will be shown that a voltage applied to the gate controls current flow between source and drain. This current will flow in the longitudinal direction from drain to source in the region labeled “channel region.” Note that this region has a length L and a width W, two important parameters of the MOSFET. Typically, L is in the range of 0.03 μm to 1 μm, and W is in the range of 0.05 μm to 100 μm. Finally, note that the MOSFET is a symmetrical device; thus its source and drain can be interchanged with no change in device characteristics.
5.1.2 Operation with Zero Gate Voltage
With zero voltage applied to the gate, two back-to-back diodes exist in series between drain and source. One diode is formed by the pn junction between the n+ drain region and the p-type substrate, and the other diode is formed by the pn junction between the p-type substrate and the n+ source region. These back-to-back diodes prevent current conduction from drain to source when a voltage vDS is applied. In fact, the path between drain and source has a very high resistance (of the order of 1012 ).
5.1.3 Creating a Channel for Current Flow
Consider next the situation depicted in Fig. 5.2. Here we have grounded the source and the drain and applied a positive voltage to the gate. Since the source is grounded, the gate voltage appears in effect between gate and source and thus is denoted v GS . The positive voltage on the gate causes, in the first instance, the free holes (which are positively charged) to be repelled from the region of the substrate under the gate (the channel region). These holes are pushed downward into the substrate, leaving behind a carrier-depletion region. The depletion region is populated by the bound negative charge associated with the acceptor atoms. These charges are “uncovered” because the neutralizing holes have been pushed downward into the substrate.
As well, the positive gate voltage attracts electrons from the n+ source and drain regions (where they are in abundance) into the channel region. When a sufficient number of electrons accumulate near the surface of the substrate under the gate, an n region is in effect created, connecting the source and drain regions, as indicated in Fig. 5.2. Now if a voltage is applied between drain and source, current flows through this induced n region, carried by the mobile
Oxide (SiO2)
Depletion region
Gate electrode
Induced
S G n-type D
5.1 Device Structure and Physical Operation 251
vGS
channel
n L n
p-type substrate
B
Figure5.2 Theenhancement-typeNMOStransistorwithapositivevoltageappliedtothegate.Annchannel is induced at the top of the substrate beneath the gate.
electrons. The induced n region thus forms a channel for current flow from drain to source and is aptly called so. Correspondingly, the MOSFET of Fig. 5.2 is called an n-channel MOSFET or, alternatively, an NMOS transistor. Note that an n-channel MOSFET is formed in a p-type substrate: The channel is created by inverting the substrate surface from p type to n type. Hence the induced channel is also called an inversion layer.
The value of vGS at which a sufficient number of mobile electrons accumulate in the channel region to form a conducting channel is called the threshold voltage and is denoted Vt .4 Obviously, Vt for an n-channel FET is positive. The value of Vt is controlled during device fabrication and typically lies in the range of 0.3 V to 1.0 V.
The gate and the channel region of the MOSFET form a parallel-plate capacitor, with the oxide layer acting as the capacitor dielectric. The positive gate voltage causes positive charge to accumulate on the top plate of the capacitor (the gate electrode). The corresponding negative charge on the bottom plate is formed by the electrons in the induced channel. An electric field thus develops in the vertical direction. It is this field that controls the amount of charge in the channel, and thus it determines the channel conductivity and, in turn, the current thatwillflowthroughthechannelwhenavoltagevDS isapplied.Thisistheoriginofthename “field-effect transistor” (FET).
The voltage across this parallel-plate capacitor, that is, the voltage across the oxide, must exceed Vt for a channel to form. When vDS = 0, as in Fig. 5.2, the voltage at every point along the channel is zero, and the voltage across the oxide (i.e., between the gate and the points along the channel) is uniform and equal to vGS. The excess of vGS over Vt is termed the effective voltage or the overdrive voltage and is the quantity that determines the charge in the channel. In this book, we shall denote (vGS − Vt ) by vOV ,
vGS −Vt ≡vOV (5.1)
4Some texts use VT to denote the threshold voltage. We use Vt to avoid confusion with the thermal voltage VT .
252 Chapter 5
MOS Field-Effect Transistors (MOSFETs)
We can express the magnitude of the electron charge in the channel by
|Q| = Cox(WL)vOV (5.2)
where Cox , called the oxide capacitance, is the capacitance of the parallel-plate capacitor per unit gate area (in units of F/m2), W is the width of the channel, and L is the length of the channel. The oxide capacitance Cox is given by
Cox = eox (5.3) tox
where eox is the permittivity of the silicon dioxide,
eox =3.9e0 =3.9×8.854×10−12 =3.45×10−11 F/m
Theoxidethicknesstox isdeterminedbytheprocesstechnologyusedtofabricatetheMOSFET. As an example, for a process with tox = 4 nm,
3.45 × 10−11
Cox = 4×10−9 =8.6×10−3 F/m2
It is much more convenient to express Cox per micron squared. For our example, this yields 8.6 fF/μm2 , where fF denotes femtofarad (10−15 F). For a MOSFET fabricated in this technology with a channel length L = 0.18 μm and a channel width W = 0.72 μm, the total capacitance between gate and channel is
C = Cox WL = 8.6 × 0.18 × 0.72 = 1.1 fF
Finally, note from Eq. (5.2) that as vOV is increased, the magnitude of the channel charge increases proportionately. Sometimes this is depicted as an increase in the depth of the channel; that is, the larger the overdrive voltage, the deeper the channel.
5.1.4 Applying a Small vDS
Having induced a channel, we now apply a positive voltage vDS between drain and source, as shown in Fig. 5.3. We first consider the case where vDS is small (i.e., 50 mV or so). The voltagevDS causesacurrentiD toflowthroughtheinducednchannel.Currentiscarriedbyfree electrons traveling from source to drain (hence the names source and drain). By convention, the direction of current flow is opposite to that of the flow of negative charge. Thus the current in the channel, iD , will be from drain to source, as indicated in Fig. 5.3.
We now wish to calculate the value of iD. Toward that end, we first note that because vDS is small, we can continue to assume that the voltage between the gate and various points along the channel remains approximately constant and equal to the value at the source end, vGS. Thus, the effective voltage between the gate and the various points along the channel remains equal to vOV , and the channel charge Q is still given by Eq. (5.2). Of particular interest
5.1 Device Structure and Physical Operation 253
n+ iDn+
Figure 5.3 An NMOS transistor with vGS > Vt and with a small vDS applied. The device acts as a resistance whose value is determined by v GS . Specifically, the channel conductance is proportional to v GS – Vt , and thus iD is proportional to (v GS – Vt )v DS . Note that the depletion region is not shown (for simplicity).
in calculating the current iD is the charge per unit channel length, which can be found from Eq. (5.2) as
|Q| = CoxWvOV unit channel length
The voltage vDS establishes an electric field E across the length of the channel, |E| = vDS
L
(5.4)
(5.5)
This electric field in turn causes the channel electrons to drift toward the drain with a velocity given by
Electron drift velocity = μ |E| = μ vDS (5.6) nnL
where μn is the mobility of the electrons at the surface of the channel. It is a physical parameter whose value depends on the fabrication process technology. The value of iD can now be found by multiplying the charge per unit channel length (Eq. 5.4) by the electron drift velocity (Eq. 5.6),
W
iD = (μnCox) L vOV vDS (5.7)
254 Chapter 5
MOS Field-Effect Transistors (MOSFETs)
Thus, for small vDS, the channel behaves as a linear resistance whose value is controlled by the overdrive voltage vOV , which in turn is determined by vGS:
W
iD = (μnCox) L (vGS −Vt) vDS
The conductance gDS of the channel can be found from Eq. (5.7) or (5.8) as W
(5.8)
(5.9)
(5.10)
or
gDS =(μnCox) L vOV W
gDS =(μnCox) L (vGS −Vt)
Observe that the conductance is determined by the product of three factors: (μnCox), (W/L), and vOV (or equivalently, vGS −Vt). To gain insight into MOSFET operation, we consider each of the three factors in turn.
The first factor, (μnCox), is determined by the process technology used to fabricate the MOSFET. It is the product of the electron mobility, μn, and the oxide capacitance, Cox. It makes physical sense for the channel conductance to be proportional to each of μn and Cox (why?) and hence to their product, which is termed the process transconductance parameter5 and given the symbol kn′ , where the subscript n denotes n channel,
kn′ =μnCox (5.11)
It can be shown that with μn having the dimensions of meters squared per volt-second (m2/V·s) and Cox having the dimensions of farads per meter squared (F/m2), the dimensions ofkn′ areamperespervoltsquared(A/V2).
ThesecondfactorintheexpressionfortheconductancegDS inEqs.(5.9)and(5.10)isthe transistor aspect ratio (W/L). That the channel conductance is proportional to the channel width W and inversely proportional to the channel length L should make perfect physical sense. The (W/L) ratio is obviously a dimensionless quantity that is determined by the device designer. Indeed, the values of W and L can be selected by the device designer to give the device the i−v characteristics desired. For a given fabrication process, however, there is a minimum channel length, Lmin. In fact, the minimum channel length that is possible with a given fabrication process is used to characterize the process and is being continually reduced as technology advances. For instance, in 2014 the state-of-the-art in commercially available MOS technology was a 32-nm process, meaning that for this process the minimum channel length possible was 32 nm. Finally, we should note that the oxide thickness tox scales down withLmin.Thus,fora0.13-μmtechnology,tox is2.7nm,butforthecurrentlypopular65-nm technology,tox isabout2.2nm.
5ThisnamearisesfromthefactthatμC determinesthetransconductanceoftheMOSFET,aswill n ox
be seen shortly.
5.1 Device Structure and Physical Operation 255 The product of the process transconductance parameter kn′ and the transistor aspect ratio
(W/L) is the MOSFET transconductance parameter kn,
kn = kn′ (W/L) (5.12a)
or
kn =(μnCox)(W/L) (5.12b)
The MOSFET parameter kn has the dimensions of A/V2.
The third term in the expression of the channel conductance gDS is the overdrive voltage
vOV.Thisishardlysurprising,sincevOV directlydeterminesthemagnitudeofelectroncharge inthechannel.Aswillbeseen,vOV isaveryimportantcircuit-designparameter.Inthisbook, we will use vOV and vGS−Vt interchangeably.
WeconcludethissubsectionbynotingthatwithvDS keptsmall,theMOSFETbehavesas a linear resistance rDS whose value is controlled by the gate voltage vGS,
rDS = 1 gDS
rDS = 1 (μnCox)(W/L)vOV
rDS = 1 (μnCox)(W/L)(vGS −Vt)
(5.13a)
(5.13b)
The operation of the MOSFET as a voltage-controlled resistance is further illustrated in Fig.5.4,whichisasketchofiD versusvDS forvariousvaluesofvGS.Observethattheresistance is infinite for v GS ≤ Vt and decreases as v GS is increased above Vt . It is interesting to note that althoughvGS isusedastheparameterforthesetofgraphsinFig.5.4,thegraphsinfactdepend only on vOV (and, of course, kn).
The description above indicates that for the MOSFET to conduct, a channel has to be induced.Then,increasingvGS abovethethresholdvoltageVt enhancesthechannel,hencethe names enhancement-mode operation and enhancement-type MOSFET. Finally, we note that the current that leaves the source terminal (iS ) is equal to the current that enters the drain terminal (iD ), and the gate current iG = 0.
iD
Slope gDS = knVOV
vGS Vt + VOV3
vGS Vt + VOV2 vGS Vt + VOV1
vGS Vt vDS
0
vGS
Figure 5.4 The iD –v DS characteristics of the MOSFET in Fig. 5.3 when the voltage applied between drain and source, v DS , is kept small. The device operates as a linear resistance whose value is controlled by v GS .
256 Chapter 5 MOS Field-Effect Transistors (MOSFETs)
EXERCISE
5.1 A 0.18-μm fabrication process is specified to have tox = 4 nm, μn = 450 cm2 /V · s, and Vt = 0.5 V. Find the value of the process transconductance parameter kn′ . For a MOSFET with minimum length fabricated in this process, find the required value of W so that the device exhibits a channel resistance rDS of1katvGS =1V.
Ans. 388μA/V2;0.93μm
5.1.5 Operation as vDS Is Increased
WenextconsiderthesituationasvDS isincreased.Forthispurpose,letvGS beheldconstantata value greater than Vt ; that is, let the MOSFET be operated at a constant overdrive voltage VOV . RefertoFig.5.5,andnotethatvDS appearsasavoltagedropacrossthelengthofthechannel. That is, as we travel along the channel from source to drain, the voltage (measured relative to the source) increases from zero to v DS . Thus the voltage between the gate and points along the channeldecreasesfromvGS =Vt +VOV atthesourceendtovGD =vGS −vDS =Vt +VOV −vDS at the drain end. Since the channel depth depends on this voltage, and specifically on the amount by which this voltage exceeds Vt , we find that the channel is no longer of uniform depth; rather, the channel will take the tapered shape shown in Fig. 5.5, being deepest at the source end (where the depth is proportional to VOV ) and shallowest at the drain end6 (where thedepthisproportionaltoVOV −vDS).ThispointisfurtherillustratedinFig.5.6.
As vDS is increased, the channel becomes more tapered and its resistance increases correspondingly.Thus,theiD−vDS curvedoesnotcontinueasastraightlinebutbendsasshown inFig.5.7.TheequationdescribingthisportionoftheiD−vDS curvecanbeeasilyderivedby utilizing the information in Fig. 5.6. Specifically, note that the charge in the tapered channel is proportional to the channel cross-sectional area shown in Fig. 5.6(b). This area in turn can
be easily seen as proportional to 1 [V +(V −v )] or V − 1 v . Thus, the relationship 2OVOVDS OV2DS
betweeniD andvDS canbefoundbyreplacingVOV inEq.(5.7)by VOV−1vDS , 2
W 1 iD=kn′ VOV−vDS vDS
ThisrelationshipdescribesthesemiparabolicportionoftheiD−vDS curveinFig.5.7.Itapplies
to the entire segment down to vDS = 0. Specifically, note that as vDS is reduced, we can neglect
1vDS relativetoVOV inthefactorinparentheses,andtheexpressionreducestothatinEq.(5.7). 2
The latter of course is an approximation and applies only for small vDS (i.e., near the origin).
There is another useful interpretation of the expression in Eq. (5.14). From Fig. 5.6(a) we
L2
(5.14)
see that the average voltage along the channel is 1 v . Thus, the average voltage that gives
2 DS
rise to channel charge and hence to iD is no longer VOV but VOV − 1 v DS , which is indeed the
2
factor that appears in Eq. (5.14). Finally, we note that Eq. (5.14) is frequently written in the
6 For simplicity, we do not show in Fig. 5.5 the depletion region. Physically speaking, it is the widening ofthedepletionregionasaresultoftheincreasedvDS thatmakesthechannelshallowernearthedrain.
Figure 5.5 Operation of the enhancement NMOS transistor as vDS is increased. The induced channel acquires a tapered shape, and its resistance increases as vDS is increased. Here, vGS is kept constant at a value>Vt;vGS =Vt +VOV.
Voltage
VGS
Source
0
Voltage drop along the channel
v)
L Average = 1 v
2 2 DS
(a)
(b)
vGD
vDS
L Drain x
(VOVvDS) Drain
Vt
n n
5.1 Device Structure and Physical Operation 257
VOV
(VOV
1
2 DS
VOV Source
Channel
Figure 5.6 (a) For a MOSFET with vGS = Vt + VOV , application of vDS causes the voltage drop along the channel to vary linearly, with an average value of 1 v at the midpoint. Since v > V , the channel still exists
2DS GD t
at the drain end. (b) The channel shape corresponding to the situation in (a). While the depth of the channel
at the source end is still proportional to VOV , that at the drain end is proportional to (VOV −v DS ).
258 Chapter 5
MOS Field-Effect Transistors (MOSFETs)
iD
Triode Saturation
Curve bends because the channel resistance increases with vDS
Almost a straight line with slope proportional to VOV
(vDS ≤ VOV)
(vDS ≥ VOV)
Current saturates because the channel is pinched off at the drain end, and vDS no longer affects the channel.
vGS = Vt + VOV
VDSsat =VOV
Figure 5.7 The drain current iD versus the drain-to-source voltage vDS for an enhancement-type NMOS
0
transistor operated with vGS = Vt + VOV . alternate form
W 1 i =k′ V v − v2
Eq. (5.15) as
vDS
(5.15) by (v GS −Vt ) and rewrite
(5.16)
D n L OV DS 2 DS Furthermore, for an arbitrary value of VOV , we can replace VOV
W 1 i =k′ (v −V)v − v2
D n L GS t DS 2DS
5.1.6 Operation for vDS ≥ VOV: Channel Pinch-Off and Current Saturation
The above description of operation assumed that even though the channel became tapered, it still had a finite (nonzero) depth at the drain end. This in turn is achieved by keeping vDS sufficiently small that the voltage between the gate and the drain, vGD, exceeds Vt. This is indeed the situation shown in Fig. 5.6(a). Note that for this situation to obtain, vDS must not exceed VOV , for as vDS = VOV , vGD = Vt , and the channel depth at the drain end reduces to zero.
Figure5.8showsvDS reachingVOV andvGD correspondinglyreachingVt.Thezerodepthof the channel at the drain end gives rise to the term channel pinch-off. Increasing vDS beyond this value (i.e., v DS > VOV ) has no effect on the channel shape and charge, and the current through the channel remains constant at the value reached for v DS = VOV . The drain current thussaturatesatthevaluefoundbysubstitutingvDS=VOV inEq.(5.14),
1 W
i = k′ V2 (5.17) D 2n L OV
Voltage
VGS
Source 0
Source
1V
2 OV
L Average = 1 V
2 2 OV
(a)
(b)
L
vGD = Vt
vDS = VOV
Drain x
Drain
5.1
Device Structure and Physical Operation 259
Vt
VOV
Voltage drop along the channel
Channel
Figure 5.8 Operation of MOSFET with vGS = Vt + VOV , as vDS is increased to VOV . At the drain end, vGD decreasestoVt andthechanneldepthatthedrainendreducestozero(pinch-off).Atthispoint,theMOSFET enters the saturation mode of operation. Further increasing vDS (beyond VDSsat = VOV ) has no effect on the channel shape and iD remains constant.
The MOSFET is then said to have entered the saturation region (or, equivalently, the saturation mode of operation). The voltage vDS at which saturation occurs is denoted VDSsat,
VDSsat =VOV =VGS −Vt (5.18)
It should be noted that channel pinch-off does not mean channel blockage: Current continues to flow through the pinched-off channel, and the electrons that reach the drain end of the channel are accelerated through the depletion region that exists there (not shown in Fig. 5.5) and into the drain terminal. Any increase in vDS above VDSsat appears as a voltage drop across the depletion region. Thus, both the current through the channel and the voltage drop across it remain constant in saturation.
The saturation portion of the iD −vDS curve is, as expected, a horizontal straight line, as indicated in Fig. 5.7. Also indicated in Fig. 5.7 is the name of the region of operation obtained with a continuous (non-pinched-off) channel, the triode region. This name is a carryover from the days of vacuum-tube devices, whose operation a FET resembles.
Finally, we note that the expression for iD in saturation can be generalized by replacing theconstantoverdrivevoltageVOV byavariableone,vOV:
1 W
i = k′ v2 (5.19) D 2n L OV
260 Chapter 5
MOS Field-Effect Transistors (MOSFETs)
Also, v OV mode iD ,
can be replaced by (v GS −Vt ) to obtain the alternate expression for saturation-
1 W
iD = kn′ (vGS −Vt)2
2L
(5.20)
Example 5.1
Consider a process technology for which Lmin = 0.4 μm, tox = 8 nm, μn = 450 cm2 /V · s, and Vt = 0.7 V.
(a) Find Cox and kn′ .
(b) ForaMOSFETwithW/L=8μm/0.8μm,calculatethevaluesofVOV,VGS,andVDSmin neededtooperate
the transistor in the saturation region with a dc current ID = 100 μA.
(c) Forthedevicein(b),findthevaluesofVOV andVGS requiredtocausethedevicetooperateasa1000-
resistor for very small vDS. Solution
(a)
e 3.45 × 10−11
Cox = ox =
tox 8×10
−9 =4.32×10−3F/m2
= 4.32 fF/μm2
kn′ =μnCox =450(cm2/V·s)×4.32(fF/μm2)
=450×108 (μm2/V·s)×4.32×10−15 (F/μm2) =194×10−6 (F/V·s)
= 194 μA/V2
(b) For operation in the saturation region,
i =1k′WV2
Thus,
which results in
Thus,
and
D 2nLOV
100=1×194× 8 V2 2 0.8 OV
VOV =0.32V
VGS =Vt +VOV =1.02V VDSmin = VOV = 0.32 V
(c)FortheMOSFETinthetrioderegionwithvDS verysmall, rDS= 1
Thus
which yields
Thus,
EXERCISES
kn′ W VOV L
1000= 1 194×10−6 ×10×VOV
VOV =0.52V VGS =1.22V
5.1 Device Structure and Physical Operation 261
5.2 Fora0.18-μmprocesstechnologyforwhichtox=4nmandμn=450cm2/V·s,findCox,kn′,andthe overdrive voltage VOV required to operate a transistor having W/L = 20 in saturation with ID = 0.3 mA. WhatistheminimumvalueofVDS needed?
Ans. 8.6 fF/μm2 ; 387 μA/V2 ; 0.28 V; 0.28 V
D5.3
A circuit designer intending to operate a MOSFET in saturation is considering the effect of changing the device dimensions and operating voltages on the drain current ID. Specifically, by what factor does ID change in each of the following cases?
(a) The channel length is doubled.
(b) The channel width is doubled.
(c) The overdrive voltage is doubled.
(d) The drain-to-source voltage is doubled.
(e) Changes (a), (b), (c), and (d) are made simultaneously.
Which of these cases might cause the MOSFET to leave the saturation region? Ans. 0.5; 2; 4; no change; 4; case (c) if vDS is smaller than 2VOV
5.1.7 The p-Channel MOSFET
Figure 5.9(a) shows a cross-sectional view of a p-channel enhancement-type MOSFET. The structure is similar to that of the NMOS device except that here the substrate is n type and the source and the drain regions are p+ type; that is, all semiconductor regions are reversed in polarity relative to their counterparts in the NMOS case. The PMOS and NMOS transistors are said to be complementary devices.
262 Chapter 5
MOS Field-Effect Transistors (MOSFETs)
SGD
p+
p+
n-type substrate
B (a)
vGS
S G iD D
iG = 0
vDS
iD
p+
p+
induced p channel n-type substrate
iD
B (b)
Figure 5.9 (a) Physical structure of the PMOS transistor. Note that it is similar to the NMOS transistor shown in Fig. 5.1(b) except that all semiconductor regions are reversed in polarity. (b) A negative voltage v
GS of magnitude greater than Vtp induces a p channel, and a negative vDS causes a current iD to flow from source
to drain.
To induce a channel for current flow between source and drain, a negative voltage is applied to the gate, that is, between gate and source, as indicated in Fig. 5.9(b). By increasing the magnitude of the negative vGS beyond the magnitude of the threshold voltage Vtp, which by convention is negative, a p channel is established as shown in Fig. 5.9(b). This condition can be described as
vGS ≤Vtp or, to avoid dealing with negative signs,
|v |≥V GS tp
Now, to cause a current iD to flow in the p channel, a negative voltage vDS is applied to the drain.7 The current iD is carried by holes and flows through the channel from source to drain. As we have done for the NMOS transistor, we define the process transconductance parameter for the PMOS device as
kp′ =μpCox
where μp is the mobility of the holes in the induced p channel. Typically, μp = 0.25 μn to 0.5 μn and is process-technology dependent. The transistor transconductance parameter kp is obtainedbymultiplyingkp′ bytheaspectratioW/L,
k p = k p′ ( W / L )
The remainder of the description of the physical operation of the p-channel MOSFET follows that for the NMOS device, except of course for the sign reversals of all voltages. We will present the complete current–voltage characteristics of both NMOS and PMOS transistors in the next section.
PMOS technology originally dominated MOS integrated-circuit manufacturing, and the original microprocessors utilized PMOS transistors. As the technological difficulties of fabricating NMOS transistors were solved, NMOS completely supplanted PMOS. The main reason for this change is that electron mobility μn is higher by a factor of 2 to 4 than the hole mobility μp, resulting in NMOS transistors having greater gains and speeds of operation than PMOS devices. Subsequently, a technology was developed that permits the fabrication of both NMOS and PMOS transistors on the same chip. Appropriately called complementary MOS, or CMOS, this technology is currently the dominant electronics technology.
5.1.8 Complementary MOS or CMOS
As the name implies, complementary MOS technology employs MOS transistors of both polarities. Although CMOS circuits are somewhat more difficult to fabricate than NMOS, the availability of complementary devices makes possible many powerful circuit configurations. Indeed, at the present time CMOS is the most widely used of all the IC technologies. This statement applies to both analog and digital circuits. CMOS technology has virtually replaced designs based on NMOS transistors alone. Furthermore, by 2014 CMOS technology had taken over many applications that just a few years earlier were possible only with bipolar devices. Throughout this book, we will study many CMOS circuit techniques.
Figure 5.10 shows a cross section of a CMOS chip illustrating how the PMOS and NMOS transistors are fabricated. Observe that while the NMOS transistor is implemented directly in the p-type substrate, the PMOS transistor is fabricated in a specially created n region, known as an n well. The two devices are isolated from each other by a thick region of oxide that functions as an insulator. Not shown on the diagram are the connections made to the p-type body and to the n well. The latter connection serves as the body terminal for the PMOS transistor.
7If a positive voltage is applied to the drain, the pn junction between the drain region and the substrate will become forward biased, and the device will no longer operate as a MOSFET. Proper MOSFET operation is predicated on the pn junctions between the source and drain regions and the substrate being always reverse biased.
5.1 Device Structure and Physical Operation 263
264 Chapter 5
MOS Field-Effect Transistors (MOSFETs)
NMOS PMOS
SGD DGS
Gate oxide
Polysilicon
SiO2
Thick SiO2 (isolation) SiO2
n n
p-type body
n well
p p
Figure 5.10 Cross section of a CMOS integrated circuit. Note that the PMOS transistor is formed in a separate n-type region, known as an n well. Another arrangement is also possible in which an n-type substrate (body) is used and the n device is formed in a p well. Not shown are the connections made to the p-type body and to the n well; the latter functions as the body terminal for the p-channel device.
5.1.9 Operating the MOS Transistor in the Subthreshold Region
The above description of the n-channel MOSFET operation implies that for vGS < Vt, no current flows and the device is cut off. This is not entirely true, for it has been found that for values of vGS smaller than but close to Vt, a small drain current flows. In this subthreshold region of operation, the drain current is exponentially related to vGS, much like the iC–vBE relationship of a BJT, as will be shown in the next chapter.
Although in most applications the MOS transistor is operated with vGS >Vt, there are special, but a growing number of, applications that make use of subthreshold operation. In Chapter 14, we will briefly consider subthreshold operation.
5.2 Current–Voltage Characteristics
Building on the physical foundation established in the previous section for the operation of the enhancement MOS transistor, in this section we present its complete current–voltage characteristics. These characteristics can be measured at dc or at low frequencies and thus are called static characteristics. The dynamic effects that limit the operation of the MOSFET at high frequencies and high switching speeds will be discussed in Chapter 10.
5.2.1 Circuit Symbol
Figure 5.11(a) shows the circuit symbol for the n-channel enhancement-type MOSFET. Observe that the spacing between the two vertical lines that represent the gate and the channel indicates the fact that the gate electrode is insulated from the body of the device. The polarity of the p-type substrate (body) and the n channel is indicated by the arrowhead on the line representing the body (B). This arrowhead also indicates the polarity of the transistor, namely, that it is an n-channel device.
Although the MOSFET is a symmetrical device, it is often useful in circuit design to designate one terminal as the source and the other as the drain (without having to write S and
5.2 Current–Voltage Characteristics 265 DDD
GBGBG
SSS
(a) (b) (c)
Figure5.11 (a)Circuitsymbolforthen-channelenhancement-typeMOSFET.(b)Modifiedcircuitsymbol with an arrowhead on the source terminal to distinguish it from the drain and to indicate device polarity (i.e., n channel). (c) Simplified circuit symbol to be used when the source is connected to the body or when the effect of the body on device operation is unimportant.
D beside the terminals). This objective is achieved in the modified circuit symbol shown in Fig. 5.11(b). Here an arrowhead is placed on the source terminal, thus distinguishing it from the drain terminal. The arrowhead points in the normal direction of current flow and thus indicates the polarity of the device (i.e., n channel). Observe that in the modified symbol, there is no need to show the arrowhead on the body line. Although the circuit symbol of Fig. 5.11(b) clearly distinguishes the source from the drain, in practice it is the polarity of the voltage impressed across the device that determines source and drain; the drain is always positive relative to the source in an n-channel FET.
In applications where the source is connected to the body of the device, a further simplification of the circuit symbol is possible, as indicated in Fig. 5.11(c). This symbol is also used in applications when the effect of the body on circuit operation is not important, as will be seen later.
5.2.2 The iD–vDS Characteristics
Table 5.1 provides a compilation of the conditions and the formulas for the operation of the NMOS transistor in each of the three possible regions: the cutoff region, the triode region, and the saturation region. The first two are useful if the MOSFET is to be utilized as a switch. On the other hand, if the MOSFET is to be used to design an amplifier, it must be operated in the saturation region. The rationale for these choices will be addressed in Chapter 7.
At the top of Table 5.1 we show a circuit consisting of an NMOS transistor and two dc supplies providing v GS and v DS . This conceptual circuit can be used to measure the iD–vDS characteristic curves of the NMOS transistor. Each curve is measured by setting vGS to a desired constant value, varying vDS, and measuring the corresponding iD. Two of these characteristic curves are shown in the accompanying diagram: one for vGS
EXERCISES
5.12 For the circuit of Fig. 5.24, what is the largest value that RD can have while the transistor remains in the saturation mode?
Ans. 12 k
D5.13 Redesign the circuit of Fig. 5.24 for the following requirements: VDD = +5 V, ID = 0.32 mA,
VS = 1.6 V, VD = 3.4 V, with a 1-μA current through the voltage divider RG1 , RG2 . Assume the same MOSFET as in Example 5.6.
Ans. RG1 =1.6M;RG2 =3.4M,RS =RD =5k
Example 5.7
Design the circuit of Fig. 5.25 so that the transistor operates in saturation with ID = 0.5 mA and VD = +3 V. Let the PMOS transistor have Vtp = −1 V and kp′ (W/L) = 1 mA/V2 . Assume λ = 0. What is the largest value that RD can have while maintaining saturation-region operation?
284
Chapter 5 MOS Field-Effect Transistors (MOSFETs)
Example 5.7 continued VDD = 5 V
RG1
VD = 3 V RG2 RD
ID = 0.5 mA
Solution
Since the MOSFET is to be in saturation, we can write
I = 1 k ′ W V 2
D 2pLOV Substituting ID = 0.5 mA and kp′ W/L = 1 mA/V2, we obtain
Figure 5.25 Circuit for Example 5.7.
and
V =1V OV
V =V +V =1+1=2V SG tp OV
Since the source is at +5 V, the gate voltage must be set to +3 V. This can be achieved by the appropriate selection of the values of RG1 and RG2 . A possible selection is RG1 = 2 M and RG2 = 3 M.
The value of RD can be found from
RD=VD = 3 =6k ID 0.5
Saturation-mode operation will be maintained up to the point that V exceeds V by V ; that is, until D G tp
VDmax =3+1=4V This value of drain voltage is obtained with RD given by
RD= 4 =8k 0.5
5.3 MOSFET Circuits at DC 285
EXERCISE
D5.14 ForthecircuitinFig.E5.14,findthevalueofRthatresultsinthePMOStransistoroperatingwithan overdrive voltage V = 0.6 V. The threshold voltage is V = − 0.4 V, the process transconductance
OV
parameterkp′ =0.1mA/V2,andW/L=10μm/0.18μm.
tp
Ans. 800
1.8 V
R
Example 5.8
Figure E5.14
The NMOS and PMOS transistors in the circuit of Fig. 5.26(a) are matched, with k′ W /L =
nnn
kp′ Wp /Lp = 1 mA/V2 and Vtn = − Vtp = 1 V. Assuming λ = 0 for both devices, find the drain currents iDN
and iDP, as well as the voltage vO, for vI = 0 V, +2.5 V, and −2.5 V.
2.5 V
QP
2.5 V
QP
iDP
vI vO 0 V vO
iDN
QN
2.5 V (a)
IDP IDN
10 k
QN 10 k
2.5 V (b)
Figure 5.26 Circuits for Example 5.8.
286
Chapter 5 MOS Field-Effect Transistors (MOSFETs)
Example 5.8 continued
2.5 V
vO I
2.5 V
2.5 V
QP
IDP
vO 10 k
IDN
QN
2.5 V (c)
DN
IDP
10 k
Figure 5.26 continued
Solution
Figure 5.26(b) shows the circuit for the case v
I NP
= 0 V. We note that since Q and Q
and are operating at equal values of V = 2.5 V, the circuit is symmetrical, which dictates that v = 0 V.
GS O
Thus both QN and QP are operating with VDG = 0 and, hence, in saturation. The drain currents can now
be found from
I =I = 1 ×1×(2.5−1)2 =1.125mA DP DN 2
Next, we consider the circuit with vI = +2.5 V. Transistor QP will have a VSG of zero and thus will be cut off, reducing the circuit to that shown in Fig. 5.26(c). We note that vO will be negative, and thus vGD will be greater than Vtn, causing QN to operate in the triode region. For simplicity we shall assume that vDS is small and thus use
I ≃k′W/LV −VV DN n n n GS tn DS
=1[2.5−(−2.5)−1][vO −(−2.5)] From the circuit diagram shown in Fig. 5.26(c), we can also write
IDN(mA)= 0−vO 10(k)
(d)
are perfectly matched
These two equations can be solved simultaneously to yield
IDN = 0.244 mA vO = −2.44 V
Note that VDS = −2.44 − (−2.5) = 0.06 V, which is small as assumed.
Finally, the situation for the case vI = −2.5 V [Fig. 5.26(d)] will be the exact complement of the case
vI = +2.5 V: Transistor QN will be off. Thus IDN = 0, QP will be operating in the triode region with IDP =0.244mAandvO =+2.44V.
EXERCISE
5.3 MOSFET Circuits at DC 287
5.15 The NMOS and PMOS transistors in the circuit of Fig. E5.15 are matched with k′ W /L =
nnn
kp′ Wp /Lp = 1 mA/V2 and Vtn = − Vtp = 1 V. Assuming λ = 0 for both devices, find the drain currents
iDN andiDP andthevoltagevO forvI =0V,+2.5V,and–2.5V.
Ans. vI =0V: 0mA, 0mA, 0V; vI =+2.5V: 0.104mA, 0mA, 1.04V; vI = −2.5V: 0mA, 0.104 mA, –1.04 V
vI
2.5 V
QN
iDN iDP
QP
2.5 V
vO 10 k
Concluding Remark
If a MOSFET is conducting but its mode of operation (saturation or triode) is not known, we assume operation in the saturation region, solve the problem, and check whether the conditions for saturation-mode operation are satisfied. If not, then the
MOSFET is operating in the triode region and the analysis is done accordingly.
Figure E5.15
288 Chapter 5 MOS Field-Effect Transistors (MOSFETs)
GORDON MOORE— HIS LAW:
A half-century ago, Gordon Moore, who would go on to become a cofounder first of Fairchild Semiconductor and then of Intel, presented a startling idea in the issue of Electronics Magazine dated April 19, 1965. Moore, who had a doctorate in chemistry, had projected the potential growth of the integrated-circuit industry based on five points spanning a seven-year period from 1958 to 1965. The conclusion he reached—that the number of transistors per chip had been increasing and would continue to increase by a factor of 2 every two years or so—was destined to propel progress in integrated circuits over the succeeding decades into the twenty-first century. Doubling of the number of transistors was predicted on the basis of another prediction: the continuing shrinkage of transistor dimensions. In early recognition of the importance of this prediction, Carver Mead, a pioneer in very large scale integration (VLSI), soon began to refer to this prediction as “Moore’s law.” (See Chapter 15, Section 15.1, for the implications of Moore’s law).
5.4 The Body Effect and Other Topics
In this section we briefly consider a number of important though secondary issues.
5.4.1 The Role of the Substrate—The Body Effect
In many applications the source terminal is connected to the substrate (or body) terminal B, which results in the pn junction between the substrate and the induced channel (review Fig. 5.5) having a constant zero (cutoff) bias. In such a case the substrate does not play any role in circuit operation and its existence can be ignored altogether.
In integrated circuits, however, the substrate is usually common to many MOS transistors. In order to maintain the cutoff condition for all the substrate-to-channel junctions, the substrate is usually connected to the most negative power supply in an NMOS circuit (the most positive in a PMOS circuit). The resulting reverse-bias voltage between source and body (VSB in an n-channel device) will have an effect on device operation. To appreciate this fact, consider an NMOS transistor and let its substrate be made negative relative to the source. The reverse-bias voltage will widen the depletion region (refer to Fig. 5.2). This in turn reduces the channel depth. To return the channel to its former state, vGS has to be increased.
The effect of VSB on the channel can be most conveniently represented as a change in the threshold voltage Vt . Specifically, it has been shown that increasing the reverse substrate bias voltage VSB results in an increase in Vt according to the relationship
Vt=Vt0+γ 2φf+VSB− 2φf (5.30)
where Vt0 is the threshold voltage for VSB = 0; φf is a physical parameter with (2φf ) typically 0.6 V; γ is a fabrication-process parameter given by
γ = 2qNAes (5.31) Cox
where q is the magnitude of the electron charge (1.6 × 10−19 C), NA is the doping concentration
of the p-type substrate, and e is the permittivity of silicon (11.7e = 11.7 × 8.854 × 10−14 = −12 s √0 1/2
1.04 × 10 F/cm). The parameter γ has the dimension of V and is typically 0.4 V . Finally, note that Eq. (5.30) applies equally well for p-channel devices with VSB replaced by
the reverse bias of the substrate, VBS (or, alternatively, replace VSB by |VSB|) and note that γ is negative. Also, in evaluating γ , NA must be replaced with ND , the doping concentration of the n well in which the PMOS is formed. For p-channel devices, 2φf is typically 0.75 V, and γ is typically –0.5 V1/2.
EXERCISE
5.16 AnNMOStransistorhasVt0 =0.8V,2φf =0.7V,andγ =0.4V1/2.FindVt whenVSB =3V. Ans. 1.23 V
Equation (5.30) indicates that an incremental change in VSB gives rise to an incremental change in Vt, which in turn results in an incremental change in iD even though vGS might have been kept constant. It follows that the body voltage controls iD; thus the body acts as another gate for the MOSFET, a phenomenon known as the body effect. Here we note that the parameter γ is known as the body-effect parameter.
5.4.2 Temperature Effects
Both Vt and k′ are temperature sensitive. The magnitude of Vt decreases by about 2 mV for every 1°C rise in temperature. This decrease in |Vt | gives rise to a corresponding increase in drain current as temperature is increased. However, because k′ decreases with temperature and its effect is a dominant one, the overall observed effect of a temperature increase is a decrease in drain current. This very interesting result is put to use in applying the MOSFET in power circuits (Chapter 12).
5.4.3 Breakdown and Input Protection
As the voltage on the drain is increased, a value is reached at which the pn junction between the drain region and substrate suffers avalanche breakdown (see Section 3.5.3). This breakdown usually occurs at voltages of 20 V to 150 V and results in a somewhat rapid increase in current (known as a weak avalanche).
Another breakdown effect that occurs at lower voltages (about 20 V) in modern devices is called punch-through. It occurs in devices with relatively short channels when the drain voltage is increased to the point that the depletion region surrounding the drain region extends through the channel to the source. The drain current then increases rapidly. Normally, punch-through does not result in permanent damage to the device.
Yet another kind of breakdown occurs when the gate-to-source voltage exceeds about 30 V. This is the breakdown of the gate oxide and results in permanent damage to the device. Although 30 V may seem high, it must be remembered that the MOSFET has a very high input resistance and a very small input capacitance, and thus small amounts of static charge accumulating on the gate capacitor can cause its breakdown voltage to be exceeded.
To prevent the accumulation of static charge on the gate capacitor of a MOSFET, gate-protection devices are usually included at the input terminals of MOS integrated circuits. The protection mechanism invariably makes use of clamping diodes.
5.4 The Body Effect and Other Topics 289
290 Chapter 5
MOS Field-Effect Transistors (MOSFETs)
5.4.4 Velocity Saturation
At high longitudinal electric fields, the drift velocity of charge carriers in the channel reaches an upper limit (approximately 107 cm/s for electrons and holes in silicon). This effect, which in modern very-short-channel devices can occur for vDS lower than 1 V, is called velocity saturation. It can be shown that when velocity saturation occurs, the current iD will no longer be related to vGS by the square-law relationship. Rather, iD becomes linearly dependent on vGS and the transconductance gm becomes constant and independent of vGS. In Chapter 15, we shall consider velocity saturation in our study of deep-submicron (i.e., L < 0.25 μm) CMOS digital circuits.
5.4.5 The Depletion-Type MOSFET
We conclude this section with a brief discussion of another type of MOSFET, the depletion-type MOSFET. Its structure is similar to that of the enhancement-type MOSFET with one important difference: The depletion MOSFET has a physically implanted channel. Thus an n-channel depletion-type MOSFET has an n-type silicon region connecting the n+ source and the n+ drain regions at the top of the p-type substrate. Thus if a voltage vDS is applied between drain and source, a current iD flows for vGS = 0. In other words, there is no need to induce a channel, unlike the case of the enhancement MOSFET.
ThechanneldepthandhenceitsconductivitycanbecontrolledbyvGS inexactlythesame manner as in the enhancement-type device. Applying a positive vGS enhances the channel by attracting more electrons into it. Here, however, we also can apply a negative vGS, which causes electrons to be repelled from the channel, and thus the channel becomes shallower and itsconductivitydecreases.ThenegativevGS issaidtodepletethechannelofitschargecarriers,
Depletion mode
Enhancement mode
vDS ≥ vGS Vt
vGS
iD
D
iD
vDS
IDSS
(b)
iG = 0
G
vGS
S0 Vt
(a)
Figure 5.27 The circuit symbol (a) and the iD–vGS characteristic in saturation (b) for an n-channel depletion-type MOSFET.
and this mode of operation (negative vGS) is called depletion mode. As the magnitude of vGS is increased in the negative direction, a value is reached at which the channel is completely depleted of charge carriers and iD is reduced to zero even though vDS may be still applied. ThisnegativevalueofvGS isthethresholdvoltageofthen-channeldepletion-typeMOSFET.
The description above suggests (correctly) that a depletion-type MOSFET can be operated in the enhancement mode by applying a positive vGS and in the depletion mode by applying a negative v GS . This is illustrated in Fig. 5.27, which shows both the circuit symbol for the depletion NMOS transistor (Fig. 5.27a) and its iD–vGS characteristic. Observe that here the threshold voltage Vtn is negative. The iD–vDS characteristics (not shown) are similar to those for the enhancement-type MOSFET except for the negative Vtn. Finally, note that the device symbol denotes the existing channel via the shaded area next to the vertical line.
Depletion-type MOSFETs can be fabricated on the same IC chip as enhancement-type devices, resulting in circuits with improved characteristics, as will be shown in a later chapter. The depletion-type MOSFET, however, is a specialty device and is not commonly used.
EXERCISE
5.17 For a depletion-type NMOS transistor with Vt = −2 V and kn′ (W/L) = 2 mA/V2, find the minimum vDS required to operate in the saturation region when vGS = +1 V. What is the corresponding value of iD?
Ans. 3V;9mA
The overdrive voltage, v ≡ v − V , is the key OV GS t
voltage VA = VA L, where VA is a process-dependent parameter.
In the analysis of dc MOSFET circuits, if a MOSFET is conducting, but its region of operation (saturation or triode) is not known, one assumes saturation-mode operation. Then, one solves the problem and checks to determine whether the assumption was justified. If not, then the transistor is operating in the triode region, and the analysis is done accordingly.
The depletion-type MOSFET has an implanted channel and thus can be operated in either the depletion or enhancement mode. It is characterized by the same equations used for the enhancement device except for having a negative Vtn (positive Vtp for depletion PMOS transistors).
the MOSFET to operate in the saturation region, which
is the region for amplifier application, v ≥ v , and DS OV
the resulting i = 1 μ C (W/L)v2 (for NMOS; replace D 2noxOV
μn with μp for PMOS). If vDS < vOV , the MOSFET operates in the triode region, which together with cutoff is used for operating the MOSFET as a switch.
Tables 5.1 and 5.2 provide summaries of the conditions and relationships that describe the operation of NMOS and PMOS transistors, respectively.
decreases. It is modeled by ascribing an output resistance
r = V /I to the MOSFET model. Here, the Early o A D ′ ′
Summary 291
Summary
The enhancement-type MOSFET is currently the most widely used semiconductor device. It is the basis of CMOS technology, which is the most popular IC fab- rication technology at this time. CMOS provides both n-channel (NMOS) and p-channel (PMOS) transistors, which increases design flexibility. The minimum MOS- FET channel length achievable with a given CMOS process is used to characterize the process. This figure has been continually reduced and is currently 32 nm.
quantity that governs the operation of the MOSFET. For
In saturation, iD shows some linear dependence on vDS as a
result of the change in channel length. This channel-length
modulation phenomenon becomes more pronounced as L
PROBLEMS
Computer Simulations Problems
Problems identified by the Multisim/PSpice icon are intended to demonstrate the value of using SPICE simulation to verify hand analysis and design, and to investigate important issues such as allowable signal swing and amplifier nonlinear distortion. Instructions to assist in setting up PSPice and Multisim simulations for all the indicated problems can be found in the corresponding files on the website. Note that if a particular parameter value is not specified in the problem statement, you are to make a reasonable assumption.
Section 5.1: Device Structure and Physical Operation
5.1 MOStechnologyisusedtofabricateacapacitor,utilizing the gate metallization and the substrate as the capacitor electrodes. Find the area required per 1-pF capacitance for oxide thickness ranging from 2 nm to 10 nm. For a square plate capacitor of 10pF, what dimensions are needed?
5.2 Calculate the total charge stored in the channel of an NMOS transistor having Cox = 9 fF/μm2 , L = 0.36 μm, and W = 3.6μm, and operated at VOV = 0.2V and VDS =0V.
5.3 Use dimensional analysis to show that the units of the process transconductance parameter kn′ are A/V2. What are the dimensions of the MOSFET transconductance parameter kn?
5.4 An NMOS transistor that is operated with a small vDS is found to exhibit a resistance rDS. By what factor will rDS change in each of the following situations?
(a) VOV is doubled.
(b) The device is replaced with another fabricated in the same
technology but with double the width.
(c) The device is replaced with another fabricated in the same technology but with both the width and length doubled.
(d) The device is replaced with another fabricated in a more advanced technology for which the oxide thickness is halved and similarly for W and L (assume μn remains unchanged).
D 5.5 An NMOS transistor fabricated in a technology for which kn′ = 400 μA/V2 and Vt = 0.5 V is required to operate with a small vDS as a variable resistor ranging in value from 250 to 1 k. Specify the range required for the control voltageVGS andtherequiredtransistorwidthW.Itisrequired to use the smallest possible device, as limited by the minimum channel length of this technology (Lmin = 0.18 μm) and the maximum allowed voltage of 1.8 V.
5.6 SketchasetofiD−vDS characteristiccurvesforanNMOS transistoroperatingwithasmallvDS (inthemannershownin Fig. 5.4). Let the MOSFET have kn = 5 mA/V2 and Vtn = 0.5 V. Sketch and clearly label the graphs for VGS = 0.5, 1.0, 1.5, 2.0, and 2.5 V. Let VDS be in the range 0 to 50 mV. Give the value of rDS obtained for each of the five values of VGS . Although only a sketch, your diagram should be drawn to scale as much as possible.
D 5.7 An n-channel MOS device in a technology for which oxide thickness is 4 nm, minimum channel length is 0.18 μm, kn′ = 400 μA/V2 , and Vt = 0.5 V operates in the triode region, with small vDS and with the gate–source voltage in the range 0 V to +1.8 V. What device width is needed to ensure that the minimum available resistance is 1 k?
5.8 Consider an NMOS transistor operating in the triode region with an overdrive voltage VOV . Find an expression for the incremental resistance
rds≡1∂iD
∂vDS vDS =VDS
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
Give the values of rds in terms of kn and VOV for VDS = 0, 0.2VOV , 0.5VOV , 0.8VOV , and VOV .
5.9 An NMOS transistor with kn = 4 mA/V2 and Vt = 0.5 V is operated with VGS = 1.0 V. At what value of VDS does the transistor enter the saturation region? What value of ID is obtained in saturation?
5.10 Consider a CMOS process for which Lmin = 0.25 μm, tox =6nm,μn =460cm2/V·s,andVt =0.5V.
(a) Find Cox and kn′ .
(b) For an NMOS transistor with W/L = 20 μm/0.25 μm,
calculate the values of VOV , VGS , and VDS min needed to operate the transistor in the saturation region with a dc current ID = 0.5 mA.
(c) For the device in (b), find the values of VOV and VGS required to cause the device to operate as a 100- resistor
for very small v DS .
5.11 A p-channel MOSFET with a threshold voltage Vtp = −0.7 V has its source connected to ground.
(a) What should the gate voltage be for the device to operate with an overdrive voltage of V = 0.4 V?
OV
(b) With the gate voltage as in (a), what is the highest voltage allowed at the drain while the device operates in the saturation region?
(c) If the drain current obtained in (b) is 0.5 mA, what would thecurrentbeforVD=−20mVandforVD=−2V?
5.12 With the knowledge that μp = 0.4μn, what must be the relative width of n-channel and p-channel devices having equal channel lengths if they are to have equal drain currents when operated in the saturation mode with overdrive voltages of the same magnitude?
5.13 An n-channel device has kn′ = 100 μA/V2 , Vt = 0.7 V, and W/L = 20. The device is to operate as a switch for small v DS , utilizing a control voltage v GS in the range 0 V to 5 V. Find the switch closure resistance, rDS , and closure
voltage, VDS, obtained when vGS = 5 V and iD = 1 mA. If μp ≃ 0.4μn, what must W/L be for a p-channel device that provides the same performance as the n-channel device in this application?
5.14 Consider an n-channel MOSFET with tox = 6 nm, μn = 460 cm2/V·s, Vt = 0.5 V, and W/L = 10. Find the drain current in the following cases:
(a) vGS =2.5VandvDS =1V (b) vGS =2VandvDS =1.5V (c) vGS =2.5VandvDS =0.2V (d) vGS =vDS=2.5V
*5.15 This problem illustrates the central point in the electronics revolution that has been in effect for the past four decades: By continually reducing the MOSFET size, we are able to pack more devices on an IC chip. Gordon Moore, co-founder of Intel Corporation, predicted this exponential growth of chip-packing density very early in the history of the development of the integrated circuit in the formulation that has become known as Moore’s law.
The table on the next page shows four technology generations, each characterized by the minimum possible MOSFET channel length (row 1). In going from one generation to another, both L and tox are scaled by the same factor. The power supply utilized VDD is also scaled by the same factor, to keep the magnitudes of all electrical fields within the device unchanged. Unfortunately, but for good reasons,Vt cannotbescaledsimilarly.
Complete the table entries, noting that row 5 asks for the transconductance parameter of an NMOS transistor with W/L = 10; row 9 asks for the value of ID obtained with VGS = VDS = VDD; row 10 asks for the power P = VDDID dissipated in the circuit. An important quantity is the power density, P/A, asked for in row 11. Finally, you are asked to find the number of transistors that can be placed on an IC chip fabricated in each of the technologies in terms of the number obtained with the 0.5-μm technology (n).
Problems 293
CHAPTER 5 PROBLEMS
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
294 Chapter 5
MOS Field-Effect Transistors (MOSFETs)
1
2 3 4
5
6 7 8 9
10 11 12
L (μm) 0.5 tox (nm) 10 Cox (fF/μm2 )
kn′(μA/V2)
(μn =500cm2/V·s) kn (mA/V2 )
For W/L = 10 Device area, A (μm2 )
VDD (V) 5 Vt (V) 0.7
ID (mA)
ForVGS =VDS =VDD
P (mW)
P/A (mW/μm2)
Devices per chip n
0.25 0.18 0.13
CHAPTER 5 PROBLEMS
Section 5.2: Current–Voltage Characteristics
In the following problems, when λ is not specified, assume it is zero.
5.16 Showthatwhenchannel-lengthmodulationisneglected (i.e.,λ=0),plottingiD/kn versusvDS forvariousvaluesofvOV, andplottingiD/kn versusvOV forvDS ≥vOV,resultsinuniversal representation of the iD −v DS and iD −v GS characteristics of the NMOS transistor. That is, the resulting graphs are both technology and device independent. Furthermore, these graphs apply equally well to the PMOS transistor by a simple relabeling of variables. (How?) What is the slope at vDS = 0
of each of the iD /kn versus v DS
vOV graph, find the slope at a point vOV = VOV .
0.5 0.4 0.4
5.17 An NMOS transistor having Vt = 0.8 V is operated in the triode region with vDS small. With VGS = 1.2 V, it is found tohavearesistancerDS of1k.WhatvalueofVGS isrequired to obtain rDS = 200 ? Find the corresponding resistance values obtained with a device having twice the value of W.
5.18 A particular MOSFET for which Vtn = 0.5 V and kn′ (W/L) = 1.6 mA/V2 is to be operated in the saturation region. If iD is to be 50 μA, find the required vGS and the minimum required v DS . Repeat for iD = 200 μA.
graphs? For the iD /kn versus
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
Problems 295
CHAPTER 5 PROBLEMS
5.19 A particular n-channel MOSFET is measured to have a draincurrentof0.4mAatVGS =VDS =1Vandof0.1mAat VGS =VDS =0.8V.Whatarethevaluesofkn andVt forthis device?
D 5.20 ForaparticularIC-fabricationprocess,thetranscon- ductance parameter kn′ = 400 μA/V2 , and Vt = 0.5 V. In an application in which vGS = vDS = Vsupply = 1.8 V, a drain current of 2 mA is required of a device of minimum length of 0.18 μm. What value of channel width must the design use?
5.21 An NMOS transistor, operating in the linear-resistance
i
i
region with v
v =1V and 50μA for v =1.5V. What is the apparent
= 50 mV, is found to conduct 25 μA for GS GS
DS
valueofthresholdvoltageVt?Ifkn′ =50μA/V2,whatisthe device W/L ratio? What current would you expect to flow with vGS = 2 V and vDS = 0.1 V? If the device is operated at vGS = 2V, at what value of vDS will the drain end of the MOSFET channel just reach pinch-off, and what is the corresponding drain current?
5.22 For an NMOS transistor, for which Vt = 0.4 V, operatingwithvGS intherangeof1.0Vto1.8V,whatisthe largestvalueofvDS forwhichthechannelremainscontinuous?
5.23 An NMOS transistor, fabricated with W = 20 μm and L=1μminatechnologyforwhichkn′ =100μA/V2 andVt = 0.8V,istobeoperatedatverylowvaluesofvDS asalinear resistor.ForvGS varyingfrom1.0Vto4.8V,whatrangeof resistor values can be obtained? What is the available range if
(a) the device width is halved?
(b) the device length is halved?
(c) both the width and length are halved?
5.24 When the drain and gate of a MOSFET are connected together, a two-terminal device known as a “diode-connected transistor” results. Figure P5.24 shows such devices obtained from MOS transistors of both polarities. Show that
(a) the i–v relationship is given by
i = 1 k ′ W v − V 2
vS Figure P5.25
vv
5.25 For the circuit in Fig. P5.25, sketch iD versus vS for vS varying from 0 to VDD. Clearly label your sketch.
VDD
iD
5.26 For the circuit in Fig. P5.26, find an expression for v DS in terms of iD . Sketch and clearly label a graph for v DS versus iD .
iD
vDS
(a) (b)
Figure P5.24
2Lt
(b) theincrementalresistancerforadevicebiasedtooperate
atv=V+V isgivenby
t OV ∂i ′W
r≡1 ∂v=1 kLVOV
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
FigureP5.26
296 Chapter 5
MOS Field-Effect Transistors (MOSFETs)
Case
a b c d e f g h i j
VS
+1.0 +1.0 +1.0 +1.0 0 +1.0 −1.0 −1.5 −1.0 +0.5
Voltage (V)
VG VD VGS
+1.0 +2.0 +2.5 +2.0 +2.5 +1.5 +1.5 0 +2.5 +1.0 +1.0 +1.0 0 0
0 0
0 +1.0 +2.0 +0.5
VOV VDS
Region of operation
CHAPTER 5 PROBLEMS
*5.27 The table above lists 10 different cases labeled (a) to (j) for operating an NMOS transistor with Vt = 1 V. In each case the voltages at the source, gate, and drain (relative to the circuit ground) are specified. You are required to complete the table entries. Note that if you encounter a case for which vDS is negative, you should exchange the drain and source before solving the problem. You can do this because the MOSFET is a symmetric device.
5.28 The NMOS transistor in Fig. P5.28 has Vt = 0.4 V and kn′ (W/L) = 1 mA/V2. Sketch and clearly label iD versus vG with vG varying in the range 0 to +1.8 V. Give equations for the various portions of the resulting graph.
1V iD
5.29 FigureP5.29showstwoNMOStransistorsoperatingin saturationatequalVGS andVDS.
(a) If the two devices are matched except for a maxi- mum possible mismatch in their W/L ratios of 3%, what is the maximum resulting mismatch in the drain currents?
(b) If the two devices are matched except for a maximum possible mismatch in their Vt values of 10 mV, what is the maximum resulting mismatch in the drain currents? Assume that the nominal value of Vt is 0.6 V.
2.5 V
ID1 ID2
1.0 V Q1 Q2
Figure P5.29
vG
Figure P5.28
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
CHAPTER 5 PROBLEMS
5.30 For a particular MOSFET operating in the saturation regionataconstantvGS,iD isfoundtobe0.5mAforvDS =1V and 0.52mA for vDS = 2V. What values of ro, VA, and λ correspond?
5.31 A particular MOSFET has VA = 20 V. For operation at 0.1 mA and 1 mA, what are the expected output resistances?
In each case, for a change in v
change in drain current would you expect?
D 5.32 In a particular IC design in which the standard
channel length is 1 μm, an NMOS device with W/L of 10
operating at 200 μA is found to have an output resistance of
100 k, about 1 of that needed. What dimensional change 5
can be made to solve the problem? What is the new device length? The new device width? The new W/L ratio? What is VA for the standard device in this IC? The new device?
D 5.33 For a particular n-channel MOS technology, in which the minimum channel length is 0.5 μm, the associated value of λ is 0.03 V−1 . If a particular device for which L is 1.5 μm operates in saturation at vDS = 1 V with a drain current of 100 μA, what does the drain current become if v DS is raised to 5 V? What percentage change does this represent? What can be done to reduce the percentage by a factor of 2?
5.34 An NMOS transistor is fabricated in a 0.5-μm process
having kn′ = 200 μA/V2 and VA′ = 20 V/μm of channel length.
IfL=1.5μmandW =15μm,findV andλ.Findthevalue A
ofID thatresultswhenthedeviceisoperatedwithanoverdrive voltage of 0.5 V and VDS = 2 V. Also, find the value of ro at this operating point. If VDS is increased by 1 V, what is the corresponding change in ID?
Problems 297 5.35 If in an NMOS transistor, both W and L are quadrupled
and VOV is halved, by what factor does ro change?
D 5.36 Consider the circuit in Fig. P5.29 with both transis-
tors perfectly matched but with the dc voltage at the drain of Q1
lowered to +2 V. If the two drain currents are to be matched
within 1% (i.e., the maximum difference allowed between the
two currents is 1%), what is the minimum required value of
V ? If the technology is specified to have V ′ = 100 V/μm, AA
what is the minimum channel length the designer must use?
5.37 Complete the missing entries in the following table, which describes characteristics of suitably biased NMOS transistors:
MOS 1 2 3 4
DS
of 1 V, what percentage
λ (V−1) 0.02 VA (V) 20
ID (mA) 0.5
ro (k)
100 0.1
100 500
25
5.38 A PMOS transistor has kp′ (W/L) = 100 μA/V2 , Vt = −1.0 V, and λ = –0.02 V−1 . The gate is connected to ground and the source to +5 V. Find the drain current for vD = +4 V, +2 V, +1 V, 0 V, and –5 V.
5.39 A p-channel transistor for which V = 0.8 V and V = t A
40 V operates in saturation with vGS = 3 V, vDS = 4 V, and iD = 3 mA. Find corresponding signed values for v GS , v SG , vDS,vSD,Vt,VA,λ,andkp′(W/L).
VS VG VD VSG
a +2 +2 0
b +2 +1 0
c +2 0 0
d +2 0 +1
e +2 0 +1.5
f +2 0 +2
|VOV|
5.40 The table below lists the terminal voltages of a PMOS transistor in six cases, labeled a, b, c, d, e, and f. The transistor has Vtp = −1 V. Complete the table entries.
VSD Region of operation
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
298 Chapter 5 MOS Field-Effect Transistors (MOSFETs)
5.41 The PMOS transistor in Fig. P5.41 has Vtp = −0.5 V. As the gate voltage vG is varied from +3 V to 0 V, the transistor moves through all of its three possible modes of operation. Specify the values of vG at which the device changes modes of operation.
saturated-mode operation of each transistor at ID = I? In the latter limiting situation, what do V1, V2, V3, and V4 become?
2.5 V
1 V
1 V
Q2
V2
I
1.5 V (b)
1.25 V
3 V
1 V
I
v G Figure P5.41
V1 Q1
(a)
2.5 V
CHAPTER 5 PROBLEMS
*5.42 Various NMOS and PMOS transistors, numbered 1 to 4, are measured in operation, as shown in the table at the bottom of the page. For each transistor, find the values of μCoxW/LandVt thatapplyandcompletethetable,withVin volts, I in μA, and μCox W/L in μA/V2 . Assume λ = 0.
I
Q4
V4
*5.43 All the transistors in the circuits shown in Fig. P5.43 have the same values of V , k′, W/L, and λ. Moreover, λ is
V3
I
t negligibly small. All operate in saturation at I = I and V =
Q3
(c)
D GS VDS =1V. Find the voltages V1, V2, V3, and V4. If Vt =
0.5 V and I = 0.1 mA, how large a resistor can be inserted in series with each drain while maintaining saturation? If the current source I requires at least 0.5 V between its terminals to operate properly, what is the largest resistor that can be placed in series with each MOSFET source while ensuring
Case Transistor VS VG VD
Figure P5.43
ID Type 100
Mode
1.25 V (d)
μCox W/L
Vt
a 1
1 0
5
d 4
3 −4.5 2 −0.5 3 4 20
b 2
2 5
c 3
3 5
0 1 2.5 1.5 2.5
400 50 450 200 800 −2 0 0 72 4 −4 0 −3 270
5
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
Section 5.3: MOSFET Circuits at DC
Note: If λ is not specified, assume it is zero.
D 5.44 Design the circuit of Fig. P5.44 to establish a drain current of 0.1mA and a drain voltage of +0.3V. The MOSFET has Vt = 0.5 V, μnCox = 400 μA/V2, L = 0.4 μm, andW=5μm.SpecifytherequiredvaluesforRS andRD.
1 V
RD
RS
1 V Figure P5.44
5.45 The NMOS transistor in the circuit of Fig. P5.44 has Vt = 0.4 V and kn = 4 mA/V2. The voltages at the source and the drain are measured and found to be −0.6 V and +0.2 V, respectively. What current ID is flowing, and what must the values of RD and RS be? What is the largest value for RD for which ID remains unchanged from the value found?
D 5.46 For the circuit in Fig. E5.10, assume that Q1 and Q2 are matched except for having different widths, W1 and W2. Let Vt = 0.5V, kn′ = 0.4mA/V2, L1 = L2 = 0.36μm, W1 =1.44μm,andλ=0.
(a) FindthevalueofRrequiredtoestablishacurrentof50μA in Q1.
(b) FindW2 andR2 sothatQ2 operatesattheedgeofsaturation with a current of 0.5 mA.
5.47 The transistor in the circuit of Fig. P5.47 has kn′ = 0.4 mA/V2 , Vt = 0.4 V, and λ = 0. Show that operation at the
Problems 299 edge of saturation is obtained when the following condition
CHAPTER 5 PROBLEMS
is satisfied:
1.3 V
RD
Figure P5.47
W RD≃2.5k L
D 5.48 It is required to operate the transistor in the circuit of Fig. P5.47 at the edge of saturation with ID = 0.1 mA. If Vt = 0.4 V, find the required value of RD .
D 5.49 The PMOS transistor in the circuit of Fig. P5.49 hasVt =−0.5V,μpCox =100μA/V2,L=0.18μm,and λ = 0. Find the values required for W and R in order to establish a drain current of 180 μA and a voltage VD of 1 V.
1.8 V
Figure P5.49
D 5.50 The NMOS transistors in the circuit of Fig. P5.50 haveVt =0.5V,μnCox =250μA/V2,λ=0,andL1 =L2 = 0.25 μm. Find the required values of gate width for each of Q1
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
300 Chapter 5 MOS Field-Effect Transistors (MOSFETs) and Q2, and the value of R, to obtain the voltage and current
the drain current is 0.5 mA and the drain voltage is +7 V. If the transistor is replaced with another having Vt = 1.5 V with kn′ (W/L) = 1.5 mA/V2, find the new values of ID and VD. Comment on how tolerant (or intolerant) the circuit is to changes in device parameters.
D 5.53 Using a PMOS transistor with Vt = −1.5 V, kp′ (W/L) = 4 mA/V2 , and λ = 0, design a circuit that resembles that in Fig.5.24(a). Using a 10-V supply, design for a gate voltage of +6 V, a drain current of 0.5 mA, and a drain voltage of +5 V. Find the values of RS and RD . Also, find the values of the resistances in the voltage divider feeding the gate, assuming a 1-μA current in the divider.
5.54 The MOSFET in Fig. P5.54 has Vt = 0.4 V, kn′ = 500μA/V2, and λ = 0. Find the required values of W/L and of R so that when vI =VDD =+1.3V, rDS =50 and vO =50mV.
values indicated.
2.5 V
0.5 mA
Figure P5.50
1.8 V 1.0 V
CHAPTER 5 PROBLEMS
D 5.51 The NMOS transistors in the circuit of Fig. P5.51 haveVt =0.5V,μnCox =90μA/V2,λ=0,andL1 =L2 = L3 = 0.5 μm. Find the required values of gate width for each of Q1, Q2, and Q3 to obtain the voltage and current values indicated.
2.5 V
90 A
1.5 V 0.8 V
VDD
R
vO
Figure P5.51
t
(a) Find the labeled voltages V1 through V7.
(b) In each of the circuits, replace the current source with a resistor. Select the resistor value to yield a current as close to that of the current source as possible, while using resistors specified in the 1% table provided in Appendix J.
5.52 Consider the circuit of Fig. 5.24(a). In Example 5.5 it was found that when Vt =1V and kn′(W/L)=1mA/V2,
vI
Figure P5.54
5.55 In the circuits shown in Fig. P5.55, transistors are characterized by V = 1 V, k′W/L = 4 mA/V2, and λ = 0.
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
5 V
2 k V2
V1 2 mA
5 V
2 mA
V3
5 V
V1 10 A
(a)
5 V
5 V
V2 100 A
(b)
Problems 301
CHAPTER 5 PROBLEMS
5 V
(a) (b)
5 V
2 mA
5 V
V3 1 mA
10 A V4
V4 V6
V5 V7
(c)
1 mA
V5
(d)
1.5 k
5 V
400 k
2 mA
5.56 For each of the circuits in Fig. P5.56, find the labeled node voltages. For all transistors, kn′ (W/L) = 0.5 mA/V2 , Vt = 0.8 V, and λ = 0.
5 V
(c) (d)
Figure P5.55
V6
(e)
(f)
Figure P5.56 continued
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
302
Chapter 5
MOS Field-Effect Transistors (MOSFETs)
5 V
2.2 k
(g)
5 V
V8 400 k
5 V (h)
10 V
VSG
R
VSD
V7
Figure P5.56 continued
5.57 For each of the circuits shown in Fig. P5.57, find the
labeled node voltages. The NMOS transistors have Vt = 0.9 V ′2
Figure P5.58
I
CHAPTER 5 PROBLEMS
and kn (W/L) = 1.5 mA/V .
5.59 For the circuits in Fig. P5.59, μ C = 3μ C = n ox p ox
270μA/V2,Vt=0.5V,λ=0,L=1μm,andW=3μm, unless otherwise specified. Find the labeled currents and voltages.
3V 3 V
2.5 V
5 V
Q1
V1
Q2
V2
1k
2.5 V
(a)
5V
1 k
V3
Q1 I1 I3
V4 VV4
2
Q2
V5
1k (a) (b) 3V
Figure P5.57
W = 9 μm I6
V5
(b)
*5.58 For the circuit in Fig. P5.58:
(a) Show that for the PMOS transistor to operate in
saturation, the following condition must be satisfied:
IR≤|Vtp |
(b) If the transistor is specified to have |Vtp| = 1 V and
kp = 0.2 mA/V2 , and for I = 0.1 mA, find the voltages
VSD andVSG forR=0,10k,30k,and100k. (c)
FigureP5.59
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
*5.60 For the devices in the circuit of Fig. P5.60, Vt=1V,λ=0,μnCox =50μA/V2,L=1μm,and W = 10 μm. Find V2 and I2 . How do these values change ifQ3 andQ4 aremadetohaveW=100μm?
Problems 303 Section 5.4: The Body Effect and Other Topics
5.62 In a particular application, an n-channel MOSFET operates with VSB in the range 0 V to 4 V. If Vt0 is nominally 1.0 V, find the range of Vt that results if γ = 0.5 V1/2 and 2φf = 0.6 V. If the gate oxide thickness is increased by a factor of 4, what does the threshold voltage become?
5.63 A p-channel transistor operates in saturation with its source voltage 3 V lower than its substrate. For γ = 0.5 V1/2 , 2φf =0.75V,andVt0 =−0.7V,findVt.
*5.64 (a) Using the expression for iD in saturation and
neglecting the channel-length modulation effect (i.e., let
CHAPTER 5 PROBLEMS
Q4 V2
Q3
Figure P5.60
5 V
I2
Q2
Q1
λ = 0), derive an expression for the per unit change in i D
per °C ∂i /i /∂T in terms of the per unit change in k′ D D n
per °C ∂k′ /k′ /∂T , the temperature coefficient of V in nnt
5.61 In the circuit of Fig. P5.61, transistors Q1 and Q2 have Vt = 0.7 V, and the process transconductance parameter kn′ =
V/°C ∂Vt/∂T ,andVGS andVt.
(b)IfVt decreasesby2mVforevery°Criseintemperature, find the temperature coefficient of kn′ that results in iD decreasing by 0.2%/°C when the NMOS transistor with Vt = 1VisoperatedatVGS =5V.
5.65 A depletion-type n-channel MOSFET with kn′ W/L = 2 mA/V2 and Vt = −3 V has its source and gate grounded. Find the region of operation and the drain current for vD = 0.1V, 1V, 3V, and 5V. Neglect the channel-length-modulation effect.
5.66 For a particular depletion-mode NMOS device, Vt = −2 V, kn′ W/L = 200 μA/V2, and λ = 0.02 V−1. When oper- ated at vGS = 0, what is the drain current that flows for vDS = 1V, 2V, 3V, and 10V? What does each of these currents become if the device width is doubled with L the same? With L also doubled?
*5.67 Neglecting the channel-length-modulation effect, show that for the depletion-type NMOS transistor of Fig. P5.67, the i−v relationship is given by
125 μA/V2 . Find V1 , V2 , and cases:
(a) (W/L)1 =(W/L)2 =20 (b) (W/L)1 = 1.5(W/L)2 = 20
2.5 V
V3 for each of the
following
20 k VV21
20 k
i= 1kn′(W/L)v2 −2Vtv forv≥Vt i = − 2 kn′ (W/L)Vt2 for v ≤ Vt
(RecallthatVt isnegative.)Sketchthei−vrelationshipforthe case:Vt =−2Vandkn′(W/L)=2mA/V2.
i v
1
2
Q1 Q2
V3 200 A
Figure P5.67 = Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
Figure P5.61
CHAPTER 6
Bipolar Junction Transistors (BJTs)
Introduction 305
6.1 Device Structure and Physical Operation 306
6.2 Current–Voltage Characteristics 320
6.3 BJT Circuits at DC 333
6.4
Transistor Breakdown and Temperature Effects 351
Summary 354 Problems 355
IN THIS CHAPTER YOU WILL LEARN
1. The physical structure of the bipolar transistor and how it works.
2. How the voltage between two terminals of the transistor controls the current that flows through the third terminal, and the equations that describe these current–voltage characteristics.
3. Howtoanalyzeanddesigncircuitsthatcontainbipolartransistors,resistors,anddc sources.
Introduction
In this chapter, we study the other major three-terminal device: the bipolar junction transistor (BJT). The presentation of the material in this chapter parallels but does not rely on that for the MOSFET in Chapter 5; thus, if desired, the BJT can be studied before the MOSFET.
Three-terminal devices are far more useful than two-terminal ones, such as the diodes studied in Chapter 4, because they can be used in a multitude of applications, ranging from signal amplification to the design of digital logic and memory circuits. The basic principle involved is the use of the voltage between two terminals to control the current flowing in the third terminal. In this way, a three-terminal device can be used to realize a controlled source, which as we learned in Chapter 1 is the basis for amplifier design. Also, in the extreme, the control signal can be used to cause the current in the third terminal to change from zero to a large value, thus allowing the device to act as a switch. The switch is the basis for the realization of the logic inverter, the basic element of digital circuits.
The invention of the BJT in 1948 at the Bell Telephone Laboratories ushered in the era of solid-state circuits. The result was not just the replacement of vacuum tubes by transistors in radios and television sets but the eruption of an electronics revolution that led to major changes in the way we work, play, and indeed, live. The invention of the transistor also eventually led to the dominance of information technology and the emergence of the knowledge-based economy.
The bipolar transistor enjoyed nearly three decades as the device of choice in the design of both discrete and integrated circuits. Although the MOSFET had been known very early on, it was not until the 1970s and 1980s that it became a serious competitor to the BJT. By 2014, the MOSFET was undoubtedly the most widely used electronic device, and CMOS technology the technology of choice in the design of integrated circuits. Nevertheless, the BJT remains a significant device that excels in certain applications.
The BJT remains popular in discrete-circuit design, where it is used together with other discrete components such as resistors and capacitors to implement circuits that are assembled
305
306 Chapter 6
Bipolar Junction Transistors (BJTs)
on printed-circuit boards (PCBs). Here we note the availability of a very wide selection of BJT types that fit nearly every conceivable application. As well, the BJT is still the preferred device in some very demanding analog and digital integrated-circuit applications. This is especially true in very-high-frequency and high-speed circuits. In particular, a very-high-speed digital logic-circuit family based on bipolar transistors, namely, emitter-coupled logic, is still in use (Chapter 15). Finally, bipolar transistors can be combined with MOSFETs to create innovative circuits that take advantage of the high-input-impedance and low-power operation of MOSFETs and the very-high-frequency operation and high-current-driving capability of bipolar transistors. The resulting technology is known as BiCMOS, and it is finding increasingly larger areas of application (see Chapters 8, 9, 13, and 15).
In this chapter, we shall start with a description of the physical operation of the BJT. Though simple, this physical description provides considerable insight regarding the performance of the transistor as a circuit element. We then quickly move from describing current flow in terms of electrons and holes to a study of the transistor terminal characteristics. Circuit models for transistor operation in different modes will be developed and utilized in the analysis and design of transistor circuits. The main objective of this chapter is to develop in the reader a high degree of familiarity with the BJT. Thus, it lays the foundation for the use of the BJT in amplifier design (Chapter 7).
6.1 Device Structure and Physical Operation 6.1.1 Simplified Structure and Modes of Operation
Figure 6.1 shows a simplified structure for the BJT. A practical transistor structure will be shown later (see also Appendix A, which deals with fabrication technology).
As shown in Fig. 6.1, the BJT consists of three semiconductor regions: the emitter region (n type), the base region ( p type), and the collector region (n type). Such a transistor is called an npn transistor. Another transistor, a dual of the npn as shown in Fig. 6.2, has a p-type emitter, an n-type base, and a p-type collector, and is appropriately called a pnp transistor.
A terminal is connected to each of the three semiconductor regions of the transistor, with the terminals labeled emitter (E), base (B), and collector (C).
The transistor consists of two pn junctions, the emitter–base junction (EBJ) and the collector–base junction (CBJ). Depending on the bias condition (forward or reverse) of each of these junctions, different modes of operation of the BJT are obtained, as shown in Table 6.1. The active mode is the one used if the transistor is to operate as an amplifier. Switching applications (e.g., logic circuits) utilize both the cutoff mode and the saturation mode. As the name implies, in the cutoff mode no current flows because both junctions are reverse biased.
As we will see shortly, charge carriers of both polarities—that is, electrons and holes—participate in the current-conduction process in a bipolar transistor, which is the reason for the name bipolar.1
1This should be contrasted with the situation in the MOSFET, where current is conducted by charge carriers of one type only: electrons in n-channel devices or holes in p-channel devices. In earlier days, some referred to FETs as unipolar devices.
n-type
Emitter region
p-type
Base region
n-type
Collector region
Emitter (E)
6.1
Collector–base junction (CBJ)
Device Structure and Physical Operation 307 Metal
contact
Collector (C)
Emitter–base junction (EBJ)
Base (B)
Figure 6.1 A simplified structure of the npn transistor. Metal
p
Emitter region
n
Base region
p
Collector region
contact EC
B
Figure 6.2 A simplified structure of the pnp transistor.
Table 6.1
Mode
Cutoff Active Saturation
BJT Modes of Operation
EBJ
Reverse Forward Forward
CBJ
Reverse Reverse Forward
6.1.2 Operation of the npn Transistor in the Active Mode
Of the three modes of operation of the BJT, the active mode is the most important. Therefore, we begin our study of the BJT by considering its physical operation in the active mode.2 This situation is illustrated in Fig. 6.3 for the npn transistor. Two external voltage sources (shown as batteries) are used to establish the required bias conditions for active-mode operation. The voltage VBE causes the p-type base to be higher in potential than the n-type emitter, thus forward biasing the emitter–base junction. The collector–base voltage VCB causes the n-type collector to be at a higher potential than the p-type base, thus reverse biasing the collector–base junction.
2The material in this section assumes that the reader is familiar with the operation of the pn junction under forward-bias conditions (Section 3.5).
308 Chapter 6
Bipolar Junction Transistors (BJTs)
E
C
Forward-biased Reverse-biased
p
Diffusing electrons
iB2 (iB1)
iB
n
Collected electrons
iC
iE
n
Injected electrons
Injected holes
iE
Recombined electrons (iB2)
iC
iB
–+
vCB
–+
vBE
iE iEB
iC
iC
VBE VCB
Figure 6.3 Current flow in an npn transistor biased to operate in the active mode. (Reverse current
components due to drift of thermally generated minority carriers are not shown.)
Current Flow The forward bias on the emitter–base junction will cause current to flow across this junction. Current will consist of two components: electrons injected from the emitter into the base, and holes injected from the base into the emitter. As will become apparent shortly, it is highly desirable to have the first component (electrons from emitter to base) be much larger than the second component (holes from base to emitter). This can be accomplished by fabricating the device with a heavily doped emitter and a lightly doped base; that is, the device is designed to have a high density of electrons in the emitter and a low density of holes in the base.
The current that flows across the emitter–base junction will constitute the emitter current iE,asindicatedinFig.6.3.ThedirectionofiE is“outof”theemitterlead,which,followingthe usual conventions, is in the direction of the positive-charge flow (hole current) and opposite to the direction of the negative-charge flow (electron current), with the emitter current iE being equal to the sum of these two components. However, since the electron component is much larger than the hole component, the emitter current will be dominated by the electron component.
From our study in Section 3.5 of the current flow across a forward-biased pn junction, we know that the magnitude of both the electron component and the hole component of iE will be proportional to evBE /VT , where vBE is the forward voltage across the base–emitter junction andVT isthethermalvoltage(approximately25mVatroomtemperature).
Let’s now focus our attention on the first current component, namely, that carried by electrons injected from the emitter into the base. These electrons will be minority carriers in the p-type base region. Because their concentration will be highest at the emitter side of the base, the injected electrons will diffuse through the base region toward the collector. In their journey across the base, some of the electrons will combine with holes, which are majority carriers in the base. However, since the base is usually very thin and, as mentioned earlier, lightly doped, the proportion of electrons that are “lost” through this recombination process will be quite small. Thus, most of the diffusing electrons will reach the boundary of the collector–base depletion region. Because the collector is more positive than the base (by the
6.1 Device Structure and Physical Operation 309 reverse-bias voltage vCB), these successful electrons will be swept across the CBJ depletion
region into the collector. They will thus get collected and constitute the collector current iC .
The Collector Current From the foregoing statements, we see that the collector current is carried by the electrons that reach the collector region. Its direction will be opposite to that of the flow of electrons, and thus into the collector terminal. Its magnitude will be proportional to evBE /VT , thus
iC =ISevBE/VT (6.1)
where the constant of proportionality IS , as in the case of the diode, is called the saturation current and is a transistor parameter. We will have more to say about IS shortly.
AnimportantobservationtomakehereisthatiC isindependentofthevalueofvCB.That is, as long as the collector is positive with respect to the base, the electrons that reach the collector side of the base region will be swept into the collector and will register as collector current.
The Base Current Reference to Fig. 6.3 shows that the base current iB is composed of two components. The first component iB1 is due to the holes injected from the base region into the emitter region. This current component is proportional to evBE /VT . The second component of base current, iB2, is due to holes that have to be supplied by the external circuit in order to replace the holes lost from the base through the recombination process. Because iB2 is proportional to the number of electrons injected into the base, it also will be proportional to evBE /VT . Thus the total base current, iB = iB1 + iB2, will be proportional to evBE /VT , and can be expressedasafractionofthecollectorcurrentiC asfollows:
That is,
iB = iC β
I
S evBE /VT
β
(6.2)
(6.3)
iB =
where β is a transistor parameter.
For modern npn transistors, β is in the range 50 to 200, but it can be as high as 1000
for special devices. For reasons that will become clear later, the parameter β is called the common-emitter current gain.
The above description indicates that the value of β is highly influenced by two factors: the width of the base region, W, and the relative dopings of the base region and the emitter region, NA/ND. To obtain a high β (which is highly desirable since β represents a gain parameter) the base should be thin (W small) and lightly doped and the emitter heavily doped (making NA/ND small). For modern integrated circuit fabrication technologies, W is in the nanometer range.
The Emitter Current Since the current that enters a transistor must leave it, it can be seen fromFig.6.3thattheemittercurrentiE isequaltothesumofthecollectorcurrentiC andthe base current iB; that is,
iE =iC +iB (6.4)
310 Chapter 6
Bipolar Junction Transistors (BJTs)
Use of Eqs. (6.2) and (6.4) gives
That is,
iE =β+1iC β
iE =β+1ISevBE/VT β
(6.5)
(6.6)
(6.7)
(6.8)
(6.9)
(6.10)
Alternatively, we can express Eq. (6.5) in the form
where the constant α is related to β by
iC =αiE
α=β β+1
Thus the emitter current in Eq. (6.6) can be written
iE =(IS/α)evBE/VT
Finally, we can use Eq. (6.8) to express β in terms of α, that is, β= α
1−α
It can be seen from Eq. (6.8) that α is a constant (for a particular transistor) that is less than but very close to unity. For instance, if β = 100, then α ≃ 0.99. Equation (6.10) reveals an important fact: Small changes in α correspond to very large changes in β. This mathematical observation manifests itself physically, with the result that transistors of the same type may have widely different values of β. For reasons that will become apparent later, α is called the common-base current gain.
Minority-Carrier Distribution Our understanding of the physical operation of the BJT can be enhanced by considering the distribution of minority charge carriers in the base and the emitter. Figure 6.4 shows the profiles of the concentration of electrons in the base and holes in the emitter of an npn transistor operating in the active mode. Observe that since the doping concentration in the emitter, ND, is much higher than the doping concentration in the base, NA, the concentration of electrons injected from emitter to base, np(0), is much higher than the concentration of holes injected from the base to the emitter, pn(0). Both quantities are proportional to evBE /VT , thus
np(0) = np0 evBE /VT (6.11)
where np0 is the thermal-equilibrium value of the minority-carrier (electron) concentration in the base region.
Next, observe that because the base is very thin, the concentration of excess electrons decays almost linearly (as opposed to the usual exponential decay, as observed for the excess holes in the emitter region). Furthermore, the reverse bias on the collector–base junction causes the concentration of excess electrons at the collector side of the base to be zero. (Recall that electrons that reach that point are swept into the collector.)
The tapered minority-carrier concentration profile (Fig. 6.4) causes the electrons injected into the base to diffuse through the base region toward the collector. This electron diffusion
Emitter (n)
EBJ Base depletion ( p)
CBJ
depletion (n)
region
Distance (x)
Figure 6.4 Profiles of minority-carrier concentrations in the base and in the emitter of an npn transistor operating in the active mode: vBE > 0 and vCB ≥ 0.
current In is directly proportional to the slope of the straight-line concentration profile, I =A qD dnp(x)
region
np (0)
Electron concentration np (ideal)
6.1 Device Structure and Physical Operation 311
Collector
Hole concentration
pn0
pn (0) np (with recombination)
Effective base width W
n E n dx
np(0)
=AEqDn − W (6.12)
whereAE isthecross-sectionalareaofthebase–emitterjunction(inthedirectionperpendicular to the page), q is the magnitude of the electron charge, Dn is the electron diffusivity in the base, and W is the effective width of the base. Observe that the negative slope of the minority-carrier concentration results in a negative current In across the base; that is, In flows from right to left (in the negative direction of x), which corresponds to the usual convention, namely, opposite to the direction of electron flow.
The recombination in the base region, though slight, causes the excess minority-carrier concentration profile to deviate from a straight line and take the slightly concave shape indicated by the broken line in Fig. 6.4. The slope of the concentration profile at the EBJ is slightly higher than that at the CBJ, with the difference accounting for the small number of electrons lost in the base region through recombination.
Finally, we have the collector current iC = In , which will yield a negative value for iC , indicating that iC flows in the negative direction of the x axis (i.e., from right to left). Since we will take this to be the positive direction of iC , we can drop the negative sign in Eq. (6.12). Doing this and substituting for np (0) from Eq. (6.11), we can thus express the collector currentiC as
iC =ISevBE/VT
where the saturation current IS is given by
IS = AEqDnnp0/W
Carrier concentration
312 Chapter 6
Bipolar Junction Transistors (BJTs)
Substituting np0 = ni2 /NA , where ni is the intrinsic carrier concentration in the base, we can express IS as
AE qDn ni2 IS = NAW
density
and
NA
is
the
doping
(6.13)
The saturation current IS is inversely proportional to the base width W and is directly proportionaltotheareaoftheEBJ.TypicallyIS isintherangeof10−12 Ato10−18 A(depending onthesizeofthedevice).BecauseIS isproportionaltoni2,itisastrongfunctionoftemperature, approximately doubling for every 5°C rise in temperature. (For the dependence of ni2 on temperature, refer to Eq. 3.2.)
Since IS is directly proportional to the junction area (i.e., the device size), it will also be referred to as the scale current. Two transistors that are identical except that one has an EBJ area, say, twice that of the other will have saturation currents with that same ratio (i.e., 2). ThusforthesamevalueofvBE thelargerdevicewillhaveacollectorcurrenttwicethatinthe smaller device. This concept is frequently employed in integrated-circuit design.
Recapitulation and Equivalent-Circuit Models We have presented a first-order model for the operation of the npn transistor in the active mode. Basically, the forward-bias voltage vBE causesanexponentiallyrelatedcurrentiC toflowinthecollectorterminal.Thecollector current iC is independent of the value of the collector voltage as long as the collector–base junction remains reverse biased; that is, vCB ≥ 0. Thus in the active mode the collector terminal behaves as an ideal constant-current source where the value of the current is determined by v BE . The base current iB is a factor 1/β of the collector current, and the emitter current is equal to the sum of the collector and base currents. Since iB is much smaller than iC (i.e., β ≫ 1), iE ≃ iC . More precisely, the collector current is a fraction α of the emitter current, with α smaller than, but close to, unity.
This first-order model of transistor operation in the active mode can be represented by the equivalent circuit shown in Fig. 6.5(a). Here, diode DE has a scale current ISE equal to (IS/α)andthusprovidesacurrentiE relatedtovBE accordingtoEq.(6.9).Thecurrentofthe controlled source, which is equal to the collector current, is controlled by vBE according to the exponential relationship indicated, a restatement of Eq. (6.1). This model is in essence a nonlinear voltage-controlled current source. It can be converted to the current-controlled current-source model shown in Fig. 6.5(b) by expressing the current of the controlled source as αiE . Note that this model is also nonlinear because of the exponential relationship of the current iE through diode DE and the voltage vBE. From this model we observe that if the transistor is used as a two-port network with the input port between E and B and the output port between C and B (i.e., with B as a common terminal), then the current gain observed is equal to α. Thus α is called the common-base current gain.
Two other equivalent-circuit models, shown in Fig. 6.5(c) and (d), may be used to represent the operation of the BJT. The model of Fig. 6.5(c) is essentially a voltage-controlled current source. However, here diode DB conducts the base current and thus its current scale factor is IS/β, resulting in the iB–vBE relationship given in Eq. (6.3). By simply expressing the collector current as βiB we obtain the current-controlled current-source model shown in Fig. 6.5(d). From this latter model we observe that if the transistor is used as a two-port network with the input port between B and E and the output port between C and E (i.e., with E as the common terminal), then the current gain observed is equal to β. Thus β is called the common-emitter current gain.
6.1 Device Structure and Physical Operation 313
Figure 6.5 Large-signal equivalent-circuit models of the npn BJT operating in the forward active mode.
Finally, we note that the models in Fig. 6.5 apply for any positive value of v BE . That is, unlike the models we will be discussing in Chapter 7, here there is no limitation on the size of v BE , and thus these models are referred to as large-signal models.
Example 6.1
An npn transistor having IS = 10−15 A and β = 100 is connected as follows: The emitter is grounded, the base is fed with a constant-current source supplying a dc current of 10 μA, and the collector is connected to a 5-V dc supply via a resistance RC of 3 k. Assuming that the transistor is operating in the active mode,findVBE andVCE.Usethesevaluestoverifyactive-modeoperation.Replacethecurrentsourcewith a resistance connected from the base to the 5-V dc supply. What resistance value is needed to result in the same operating conditions?
314
Chapter 6 Bipolar Junction Transistors (BJTs)
Example 6.1 continued Solution
If the transistor is operating in the active mode, it can be represented by one of the four possible equivalent-circuit models shown in Fig. 6.5. Because the emitter is grounded, either the model in Fig. 6.5(c) or that in Fig. 6.5(d) would be suitable. Since we know the base current IB , the model of Fig. 6.5(d) is the most suitable.
10 A
VCC 5V VCC 5V
RC 3 k RB RC
IBB CICIBB CIC
VBE
DB bIB DB bIB VCE VBE
EE
VCE
(a) (b) Figure 6.6 Circuits for Example 6.1.
Figure 6.6(a) shows the circuit as described with the transistor represented by the model of Fig. 6.5(d). We can determine VBE from the exponential characteristic of DB as follows:
VBE =VT ln IB IS /β
=25ln 10×10−6 10−17
= 690 mV = 0.69 V
NextwedeterminethevalueofVCE from
where
VCE =VCC −RCIC
IC =βIB =100×10×10−6 =10−3 A=1mA
Thus,
VCE =5−3×1=+2V
Since VC at +2 V is higher than VB at 0.69 V, the transistor is indeed operating in the active mode.
Now, replacing the 10-μA current source with a resistance RB connected from the base to the 5-V dc
supplyVCC,asinFig.6.6(b),thevalueofRB mustbe RB = VCC −VBE
IB
= 5−0.69 =431k 10 μA
6.1 Device Structure and Physical Operation 315
EXERCISES
6.1 Consider an npn transistor with vBE =0.7 V at iC =1 mA. Find vBE at iC =0.1 mA and 10 mA. Ans. 0.64 V; 0.76 V
6.2 Transistors of a certain type are specified to have β values in the range of 50 to 150. Find the range of their α values.
Ans. 0.980 to 0.993
6.3 Measurement of an npn BJT in a particular circuit shows the base current to be 14.46 μA, the emitter
current to be 1.460 mA, and the base–emitter voltage to be 0.7 V. For these conditions, calculate α, β, and IS .
Ans. 0.99; 100; 10−15 A
6.4 Calculate β for two transistors for which α = 0.99 and 0.98. For collector currents of 10 mA, find the base current of each transistor.
Ans. 99; 49; 0.1 mA; 0.2 mA
6.5 A transistor for which IS = 10−16 A and β = 100 is conducting a collector current of 1 mA. Find vBE . Also, find ISE and ISB for this transistor.
Ans. 747.5mV;1.01×10−16 A;10−18A
6.6 ForthecircuitinFig.6.6(a)analyzedinExample6.1,findthemaximumvalueofRC thatwillstillresult in active-mode operation.
Ans. 4.31 k
6.1.3 Structure of Actual Transistors
Figure 6.7 shows a more realistic (but still simplified) cross section of an npn BJT. Note that the collector virtually surrounds the emitter region, thus making it difficult for the electrons injected into the thin base to escape being collected. In this way, the resulting α is close to
316 Chapter 6
Bipolar Junction Transistors (BJTs)
EBC
n n
Figure 6.7 Cross section of an npn BJT.
unity and β is large. Also, observe that the device is not symmetrical, and thus the emitter and collector cannot be interchanged.3 For more detail on the physical structure of actual devices, the reader is referred to Appendix A.
The structure in Fig. 6.7 indicates also that the CBJ has a much larger area than the EBJ. Thus the CB diode DC has a saturation current ISC that is much larger than the saturation current of the EB diode DE. Typically, ISC is 10 to 100 times larger than ISE (recall that ISE = IS/α ≃ IS).
p
EXERCISE
6.7 A particular transistor has IS = 10−15 A and α ≃ 1. If the CBJ area is 100 times the area of the EBJ, find the collector scale current ISC .
Ans. 10−13 A
6.1.4 Operation in the Saturation Mode4
As mentioned above, for the BJT to operate in the active mode, the CBJ must be reverse biased. Thus far, we have stated this condition for the npn transistor as vCB ≥ 0. However, we know that a pn junction does not effectively become forward biased until the forward voltage across it exceeds approximately 0.4 V. It follows that one can maintain active-mode operation of an npn transistor for negative vCB down to approximately −0.4 V. This is illustrated in Fig. 6.8, which is a sketch of iC versus vCB for an npn transistor operated with a constant emitter current IE. As expected, iC is independent of vCB in the active mode, a situation that extends
3If the emitter and collector are reversed—that is, the CBJ is forward biased and the EBJ is reverse biased—the device operates in a mode called the “reverse-active mode.” The resulting values of α and β, denoted αR and βR (with R denoting reverse), are much lower than the values of α and β, respectively, obtained in the “forward”-active mode discussed above. Hence, the reverse-active mode has no practical application. The MOSFET, on the other hand, being a perfectly symmetrical device, can operate equally well with its drain and source terminals interchanged.
4Saturation means something completely different in a BJT and in a MOSFET. The saturation mode of operation of the BJT is analogous to the triode region of operation of the MOSFET. On the other hand, the saturation region of operation of the MOSFET corresponds to the active mode of BJT operation.
Saturation mode
iC
aIE
Active mode
6.1 Device Structure and Physical Operation 317
iE IE
0.4 V
0
vCB
Expanded scale
Figure 6.8 The iC−vCB characteristic of an npn transistor fed with a constant emitter current IE . The transistor enters the saturation mode of operation for vCB < – 0.4 V, and the collector current diminishes.
iB ISC evBC /VT iC
BC
DC vBE DB
E
v /V ISeBE T
Figure 6.9 Modeling the operation of an npn transistor in saturation by augmenting the model of Fig. 6.5(c) with a forward-conducting diode DC . Note that the current through DC increases iB andreducesiC.
for vCB going negative to approximately −0.4 V. Below this value of vCB, the CBJ begins to conduct sufficiently that the transistor leaves the active mode and enters the saturation mode ofoperation,whereiC decreases.
To see why iC decreases in saturation, we can construct a model for the saturated npn transistor as follows. We augment the model of Fig. 6.5(c) with the forward-conducting CBJ diode DC, as shown in Fig.6.9. Observe that the current iBC will subtract from the controlled-sourcecurrent,resultinginthereducedcollectorcurrentiC givenby
iC =ISevBE/VT −ISCevBC/VT (6.14)
where ISC is the saturation current for DC and is related to IS by the ratio of the areas of the CBJandtheEBJ.ThesecondterminEq.(6.14)willplayanincreasingroleasvBC exceeds 0.4Vorso,causingiC todecreaseandeventuallyreachzero.
Figure 6.9 also indicates that in saturation the base current will increase to the value
iB = (IS /β)evBE /VT + ISC evBC /VT (6.15)
Equations (6.14) and (6.15) can be combined to obtain the ratio iC /iB for a saturated transistor. We observe that this ratio will be lower than the value of β. Furthermore, the ratio will decrease as vBC is increased and the transistor is driven deeper into saturation. Because iC/iB
318 Chapter 6
Bipolar Junction Transistors (BJTs)
of a saturated transistor can be set to any desired value lower than β by adjusting vBC, this ratio is known as forced β and denoted βforced ,
i
βforced= C ≤β (6.16)
iB saturation
As will be shown later, in analyzing a circuit we can determine whether the BJT is in the
saturation mode by either of the following two tests:
1. Is the CBJ forward biased by more than 0.4 V?
2. Is the ratio iC /iB lower than β ?
Thecollector-to-emittervoltagevCE ofasaturatedtransistorcanbefoundfromFig.6.9
as the difference between the forward-bias voltages of the EBJ and the CBJ,
VCEsat =VBE −VBC (6.17)
Recalling that the CBJ has a much larger area than the EBJ, VBC will be smaller than VBE by 0.1 to 0.3 V. Thus,
VCEsat ≃0.1to0.3V
Typically we will assume that a transistor at the edge of saturation has VCEsat = 0.3 V, while
a transistor deep in saturation has VCEsat = 0.2 V.
6.8 Use Eq. (6.14) to show that iC reaches zero at
VCE =VT ln ISC/IS
CalculateVCE foratransistorwhoseCBJhas100timestheareaoftheEBJ.
Ans. 115 mV
6.9 Use Eqs. (6.14), (6.15), and (6.16) to show that a BJT operating in saturation with VCE = VCEsat has a
forced β given by
Findβforced forβ=100,ISC/IS =100,andVCEsat =0.2V. Ans. 22.2
6.1.5 The pnp Transistor
The pnp transistor operates in a manner similar to that of the npn device described above. Figure 6.10 shows a pnp transistor biased to operate in the active mode. Here the voltage VEB causes the p-type emitter to be higher in potential than the n-type base, thus forward biasing the emitter–base junction. The collector–base junction is reverse biased by the voltage VBC , which keeps the p-type collector lower in potential than the n-type base.
EXERCISES
eVCEsat/VT −I /I SC S
β=β
forced eVCEsat /VT + βISC /IS
Forward biased
6.1 Device Structure and Physical Operation 319 Reverse biased
iE
iC
p
Injected holes
iE Injected electrons
n
Diffusing holes
iB2
iB1 iB
p
Collected holes iC
Recombined holes
E
iE
+– vEB
iB
B
+– vBC
iC
C
iC
iE
VEB
VBC
Figure 6.10 Current flow in a pnp transistor biased to operate in the active mode.
Unlike the npn transistor, current in the pnp device is mainly conducted by holes injected from the emitter into the base as a result of the forward-bias voltage VEB . Since the component of emitter current contributed by electrons injected from base to emitter is kept small by using a lightly doped base, most of the emitter current will be due to holes. The electrons injected from base to emitter give rise to the first component of base current, iB1. Also, a number of the holes injected into the base will recombine with the majority carriers in the base (electrons) and will thus be lost. The disappearing base electrons will have to be replaced from the external circuit, giving rise to the second component of base current, iB2. The holes that succeed in reaching the boundary of the depletion region of the collector–base junction will be attracted by the negative voltage on the collector. Thus these holes will be swept across the depletion region into the collector and appear as collector current.
It can easily be seen from the above description that the current–voltage relationship of the pnptransistorwillbeidenticaltothatofthenpntransistorexceptthatvBE hastobereplaced by vEB. Also, the large-signal, active-mode operation of the pnp transistor can be modeled by any of four equivalent circuits similar to those for the npn transistor in Fig. 6.5. Two of these four circuits are shown in Fig. 6.11. Finally, we note that the pnp transistor can operate in the saturation mode in a manner analogous to that described for the npn device.
EXERCISES
6.10 ConsiderthemodelinFig.6.11(a)appliedinthecaseofapnptransistorwhosebaseisgrounded,the emitter is fed by a constant-current source that supplies a 2-mA current into the emitter terminal, and the collector is connected to a –10-V dc supply. Find the emitter voltage, the base current, and the collector current if for this transistor β = 50 and IS = 10−14 A.
Ans. 0.650 V; 39.2 μA; 1.96 mA
6.11 For a pnp transistor having IS =10−11 A and β=100, calculate vEB for iC =1.5 A. Ans. 0.643 V
320 Chapter 6
Bipolar Junction Transistors (BJTs)
iE
iB
D (IS a)
IS evEB VT
iE
E
ISevEB VT
vEB
DB
(IS b)
(a)
iC B C iB iC
(b)
Figure 6.11 Two large-signal models for the pnp transistor operating in the active mode.
THE INVENTION OF THE BJT:
The first working transistor was demonstrated at the Bell Labs in late 1947 by John Bardeen and Walter Brattain, who were part of a team led by William Shockley. Made of germanium, the device became known as a point-contact transistor and operated on the field-effect principle. Within a few weeks, however, Shockley wrote a complete description of the bipolar junction transistor (BJT) and filed for a U.S. patent with the title “Circuit Element Utilizing Semiconductor Material.”
BJTs dominated the electronics world from the early 1950s to the mid-1970s, when MOSFETs took over the leading position. In 1956, Shockley, Bardeen, and Brattain shared the Nobel Prize in Physics for the discovery of the transistor effect.
6.2 Current–Voltage Characteristics 6.2.1 Circuit Symbols and Conventions
The physical structure used thus far to explain transistor operation is rather cumbersome to employ in drawing the schematic of a multitransistor circuit. Fortunately, a very descriptive and convenient circuit symbol exists for the BJT. Figure 6.12(a) shows the symbol for the npn transistor; the pnp symbol is given in Fig. 6.12(b). In both symbols the emitter is distinguished by an arrowhead. This distinction is important because, as we have seen in the last section, practical BJTs are not symmetric devices.
The polarity of the device—npn or pnp—is indicated by the direction of the arrowhead on the emitter. This arrowhead points in the direction of normal current flow in the emitter, which is also the forward direction of the base–emitter junction. Since we have adopted a drawing convention by which currents flow from top to bottom, we will always draw pnp transistors in the manner shown in Fig. 6.12(b) (i.e., with their emitters on top).
Figure 6.13 shows npn and pnp transistors connected to dc sources so as to operate in the active mode. Figure 6.13 also indicates the reference and actual directions of current flow throughout the transistor. Our convention will be to take the reference direction to coincide
6.2 Current–Voltage Characteristics 321
npn
(a)
pnp
(b)
Figure 6.12 Circuit symbols for BJTs.
(a)
(b)
Figure 6.13 Voltage polarities and current flow in transistors operating in the active mode.
with the normal direction of current flow. Hence, normally, we should not encounter a negative value for iE, iB, or iC.
The convenience of the circuit-drawing convention that we have adopted should be obvious from Fig. 6.13. Note that currents flow from top to bottom and that voltages are higher at the top and lower at the bottom. The arrowhead on the emitter also implies the polarity of the emitter–base voltage that should be applied in order to forward bias the emitter–base junction. Just a glance at the circuit symbol of the pnp transistor, for example, indicates that we should make the emitter higher in voltage than the base (by vEB) in order to cause current to flow into the emitter (downward). Note that the symbol vEB means the voltage by which the emitter (E) is higher than the base (B). Thus for a pnp transistor operating in the active mode vEB is positive,whileinannpntransistorvBE ispositive.
From the discussion of Section 6.1 it follows that an npn transistor whose EBJ is forward biased (usually, VBE ≃ 0.7 V) will operate in the active mode as long as the collector voltage does not fall below that of the base by more than approximately 0.4 V. Otherwise, the transistor leaves the active mode and enters the saturation region of operation.5
In a parallel manner, the pnp transistor will operate in the active mode if the EBJ is forward biased (usually, VEB ≃ 0.7 V) and the collector voltage is not allowed to rise above that of the base by more than 0.4 V or so. Otherwise, the CBJ becomes forward biased, and the pnp transistor enters the saturation region of operation.
5It is interesting to contrast the active-mode operation of the BJT with the corresponding mode of operation of the MOSFET: The BJT needs a minimum vCE of about 0.3 V, and the MOSFET needs a minimumvDS equaltoVOV,whichformoderntechnologiesisintherangeof0.2Vto0.3V.Thuswe see a great deal of similarity! Also note that reverse biasing the CBJ of the BJT corresponds to pinching off the channel of the MOSFET. This condition results in the collector current (drain current in the MOSFET) being independent of the collector voltage (the drain voltage in the MOSFET).
322 Chapter 6
Bipolar Junction Transistors (BJTs)
E
0.3 V
0.4 V
Saturation
0.7 V
B
(a) npn
Figure 6.14 Graphical representation of the conditions for operating the BJT in the active mode and in the
saturation mode.
Table 6.2 Summary of the BJT Current–Voltage Relationships in the Active Mode iC =ISevBE/VT
iB=iC=IS evBE/VT ββ
iE=iC=IS evBE/VT αα
B
Active
C
Saturation
C
0.7 V
0.4 V 0.3 V
Active
E
(b) pnp
Note: For the pnp transistor, replace vBE with vEB. iC =αiE iB =(1−α)iE = iE
β+1 iC =βiB iE =(β+1)iB
β=α α=β 1−α β+1
VT = thermal voltage = kT ≃ 25 mV at room temperature q
For greater emphasis, we show in Fig. 6.14 a graphical construction that illustrates the conditions for operating the BJT in the active mode and in the saturation mode. Also, for easy reference, we present in Table 6.2 a summary of the BJT current–voltage relationships in the active mode of operation.
The Collector–Base Reverse Current (ICBO) In our discussion of current flow in transistors we ignored the small reverse currents carried by thermally generated minority carriers. Although such currents can be safely neglected in modern transistors, the reverse current across the collector–base junction deserves some mention. This current, denoted ICBO , is the reverse current flowing from collector to base with the emitter open-circuited (hence the subscript O). This current is usually in the nanoampere range, a value that is many times higher than its theoretically predicted value. As with the diode reverse current, ICBO contains a substantial leakage component, and its value is dependent on vCB. ICBO depends strongly on temperature, approximately doubling for every 10°C rise.6
6ThetemperaturecoefficientofICBO isdifferentfromthatofIS becauseICBO containsasubstantialleakage component.
6.2 Current–VoltageCharacteristics 323
Example 6.2
The transistor in the circuit of Fig. 6.15(a) has β = 100 and exhibits a vBE of 0.7 V at iC = 1 mA. Design the circuit so that a current of 2 mA flows through the collector and a voltage of +5 V appears at the collector.
15 V 15 V
R IC 2 mA R CC
I 2 0.02 mA VC 5 V B
VBE
IE IC IB
2.02 mA
VE VBE
RE
15 V (a)
RE
15 V (b)
Figure 6.15 Circuit for Example 6.2.
Solution
Refer to Fig. 6.15(b). We note at the outset that since we are required to design for VC = +5 V, the CBJ willbereversebiasedandtheBJTwillbeoperatingintheactivemode.ToobtainavoltageVC =+5V,the voltage drop across RC must be 15 – 5 = 10 V. Now, since IC = 2 mA, the value of RC should be selected according to
RC = 10V =5k 2 mA
SincevBE =0.7VatiC =1mA,thevalueofvBE atiC =2mAis
VBE =0.7+VT ln 2 =0.717V 1
Since the base is at 0 V, the emitter voltage should be
VE =−0.717V
For β = 100, α = 100/101 = 0.99. Thus the emitter current should be
IE=IC= 2 =2.02mA α 0.99
324
Chapter 6 Bipolar Junction Transistors (BJTs)
Example 6.2 continued NowthevaluerequiredforRE canbedeterminedfrom
RE = VE−(−15)
IE
= −0.717 + 15 = 7.07 k 2.02
This completes the design. We should note, however, that the calculations above were made with a degree of precision that is usually neither necessary nor justified in practice in view, for instance, of the expected tolerances of component values. Nevertheless, we chose to do the design precisely in order to illustrate the various steps involved.
EXERCISES
D6.12 RepeatExample6.2foratransistorfabricatedinamodernintegrated-circuitprocess.Suchaprocess yieldsdevicesthatexhibitlargervBE atthesameiC becausetheyhavemuchsmallerjunctionareas. The dc power supplies utilized in modern IC technologies fall in the range of 1 V to 3 V. Design a circuit similar to that shown in Fig. 6.15 except that now the power supplies are ±1.5 V and the BJThasβ=100andexhibitsvBE of0.8VatiC =1mA.Designthecircuitsothatacurrentof2mA flows through the collector and a voltage of +0.5 V appears at the collector.
Ans. RC =500;RE =338
6.13 In the circuit shown in Fig. E6.13, the voltage at the emitter was measured and found to be –0.7 V.
If β = 50, find IE , IB , IC , and VC . 10 V
5k
IB
IE
10 V
IC
VC
VE
10 k
Figure E6.13
Ans. 0.93 mA; 18.2 μA; 0.91 mA; +5.45 V
6.2 Current–Voltage Characteristics 325
6.14 In the circuit shown in Fig. E6.14, measurement indicates VB to be +1.0 V and VE to be +1.7 V. Whatareαandβforthistransistor?WhatvoltageVC doyouexpectatthecollector?
VB
10 V
5k
VE
VC
100 k
5k
10 V
Figure E6.14
Ans. 0.994; 165; –1.75 V
6.2.2 Graphical Representation of Transistor Characteristics
It is sometimes useful to describe the transistor i–v characteristics graphically. Figure 6.16 shows the iC–vBE characteristic, which is the exponential relationship
iC =ISevBE/VT
which is identical to the diode i–v relationship. The iE –vBE and iB–vBE characteristics are also exponential but with different scale currents: IS /α for iE , and IS /β for iB . Since the constant of the exponential characteristic, 1/VT , is quite high (≃ 40), the curve rises very sharply. For vBE smaller than about 0.5 V, the current is negligibly small.7 Also, over most of the normal current rangevBE liesintherangeof0.6Vto0.8V.Inperformingrapidfirst-orderdccalculations,we normally will assume that VBE ≃ 0.7 V, which is similar to the approach used in the analysis of diode circuits (Chapter 4). For a pnp transistor, the iC –vEB characteristic will look identical to that of Fig. 6.16 with vBE replaced with vEB.
7The iC−vBE characteristic is the BJT’s counterpart of the iD–vGS characteristic of the MOSFET. They share an important attribute: In both cases the voltage has to exceed a “threshold” for the device to conduct appreciably. In the case of the MOSFET, there is a formal threshold voltage, Vt , which lies typically in the range of 0.4 V to 0.8 V. For the BJT, there is an “apparent threshold” of approximately 0.5 V. The iD –v GS characteristic of the MOSFET is parabolic, and thus is less steep than the iC –v BE characteristic of the BJT. As will be seen in Chapter 7, this difference has a direct and significant implication for the value of transconductance gm realized with each device.
326 Chapter 6
Bipolar Junction Transistors (BJTs)
Figure 6.16 The iC –vBE characteristic for an npn transistor.
Figure 6.17 Effect of temperature on the iC –vBE characteristic. At a constant emitter current (broken line), vBE changes by −2 mV/°C.
As in silicon diodes, the voltage across the emitter–base junction decreases by about 2 mV for each rise of 1°C in temperature, provided the junction is operating at a constant current. Figure 6.17 illustrates this temperature dependence by depicting iC–vBE curves for an npn transistor at three different temperatures.
EXERCISE
6.15 Consider a pnp transistor with vEB = 0.7 V at iE = 1 mA. Let the base be grounded, the emitter be fed by a 2-mA constant-current source, and the collector be connected to a –5-V supply through a 1-k resistance. If the temperature increases by 30°C, find the changes in emitter and collector voltages. Neglect the effect of ICBO.
Ans. –60 mV; 0 V
6.2.3 Dependence of iC on the Collector Voltage—The Early Effect
When operated in the active region, practical BJTs show some dependence of the collector current on the collector voltage, with the result that, unlike the graph shown in Fig. 6.8, their iC–vCB characteristicsarenotperfectlyhorizontalstraightlines.Toseethisdependencemore
Figure 6.18 (a) Conceptual circuit for measuring the iC –vCE characteristics of the BJT. (b) The iC –vCE characteristics of a practical BJT.
clearly, consider the conceptual circuit shown in Fig. 6.18(a). The transistor is connected in the common-emitter configuration; that is, here the emitter serves as a common terminal between the input and output ports. The voltage VBE can be set to any desired value by adjusting the dc source connected between base and emitter. At each value of VBE, the corresponding iC–vCE characteristic curve can be measured point by point by varying the dc source connected between collector and emitter and measuring the corresponding collector current. The result is the family of iC –v CE characteristic curves shown in Fig. 6.18(b) and known as common-emitter characteristics.
At low values of vCE (lower than about 0.3 V), as the collector voltage goes below that of the base by more than 0.4 V, the collector–base junction becomes forward biased and the transistor leaves the active mode and enters the saturation mode. Shortly, we shall look at the detailsoftheiC–vCE curvesinthesaturationregion.Atthistime,however,wewishtoexamine the characteristic curves in the active region in detail. We observe that the characteristic curves, though still straight lines, have finite slope. In fact, when extrapolated, the characteristic lines meet at a point on the negative v CE axis, at v CE = –VA . The voltage VA , a positive number, is a parameter for the particular BJT, with typical values in the range of 10 V to 100 V. As noted earlier, it is called the Early voltage, after J. M. Early, the engineering scientist who first studied this phenomenon.
At a given value of v BE , increasing v CE increases the reverse-bias voltage on the collector–base junction, and thus increases the width of the depletion region of this junction (refer to Fig. 6.4). This in turn results in a decrease in the effective base width W. Recalling that IS is inversely proportional to W (Eq. 6.13), we see that IS will increase and that iC increases proportionally. This is the Early effect. For obvious reasons, it is also known as the base-width modulation effect.8
8Recall that the MOSFET’s counterpart is the channel-length modulation effect. These two effects are remarkably similar and have been assigned the same name, Early effect.
6.2 Current–Voltage Characteristics 327
328 Chapter 6
Bipolar Junction Transistors (BJTs)
The linear dependence of iC on vCE can be explicitly accounted for by assuming that IS remainsconstantandincludingthefactor(1+vCE/VA)intheequationforiC asfollows:
v
iC =ISevBE/VT 1+ CE (6.18)
VA
The nonzero slope of the iC–vCE straight lines indicates that the output resistance looking into the collector is not infinite. Rather, it is finite and defined by
−1 ro≡ ∂iC
(6.19)
(6.20)
Using Eq. (6.18) we can show that
∂vCE vBE = constant
ro = VA + VCE IC
whereIC andVCE arethecoordinatesofthepointatwhichtheBJTisoperatingontheparticular iC–vCE curve(i.e.,thecurveobtainedforvBE equaltoconstantvalueVBE atwhichEq.(6.19) is evaluated). Alternatively, we can write
ro = VA (6.21) IC′
where IC′ is the value of the collector current with the Early effect neglected; that is,
IC′ =ISeVBE/VT (6.22)
ItisrarelynecessarytoincludethedependenceofiC onvCE indcbiasdesignandanalysis that is performed by hand. Such an effect, however, can be easily included in the SPICE simulation of circuit operation, which is frequently used to “fine-tune” pencil-and-paper analysis or design.
The finite output resistance ro can have a significant effect on the gain of transistor amplifiers. This is particularly the case in integrated-circuit amplifiers, as will be shown in Chapter 8. Fortunately, there are many situations in which ro can be included relatively easily in pencil-and-paper analysis.
The output resistance ro can be included in the circuit model of the transistor.9 This is illustrated in Fig. 6.19, where we show the two large-signal circuit models of a
Figure 6.19 Large-signal, equivalent-circuit models of an npn BJT operating in the active mode in the common-emitter configuration with the output resistance ro included.
9 In applying Eq. (6.21) to determine ro we will usually drop the prime and simply use ro = VA /IC where IC isthecollectorcurrentwithouttheEarlyeffect.
6.2 Current–Voltage Characteristics 329 common-emitter npn transistor operating in the active mode, those in Fig 6.5(c) and (d),
with the resistance ro connected between the collector and the emitter terminals. EXERCISES
6.16 Use the circuit model in Fig. 6.19(a) to express i in terms of evBE /VT and v and thus show that this C CE
circuit is a direct representation of Eq. (6.18).
6.17 Find the output resistance of a BJT for which VA = 100 V at IC = 0.1, 1, and 10 mA.
Ans. 1 M; 100 k; 10 k
6.18 Consider the circuit in Fig. 6.18(a). At VCE = 1 V, VBE is adjusted to yield a collector current of 1 mA.
Then,whileVBE iskeptconstant,VCE israisedto11V.FindthenewvalueofIC.Forthistransistor, VA =100V.
Ans. 1.1 mA
6.2.4 An Alternative Form of the Common-Emitter Characteristics
An alternative way of expressing the transistor common-emitter characteristics is illustrated in Fig. 6.20. Here the base current iB rather than the base–emitter voltage vBE is used as a parameter. That is, each iC–vCE curve is measured with the base fed with a constant current IB. The resulting characteristics, shown in Fig.6.20(b), look similar to those in Fig. 6.18. Figure 6.20(c) shows an expanded view of the characteristics in the saturation region.
The Common-Emitter Current Gain β In the active region of the characteristics shown in Fig. 6.20(b) we have identified a particular point Q. Note that this operating point for the transistor is characterized by a base current IB , a collector current IC , and a collector–emitter voltage VCE. The ratio IC/IB is the transistor β. However, there is another way to measure β: change the base current by an increment iB and measure the resulting increment iC , while keeping VCE constant. This is illustrated in Fig. 6.20(b). The ratio iC /iB should, according to our study thus far, yield an identical value for β. It turns out, however, that the latter value of β (called incremental, or ac, β) is a little different from the dc β (i.e., IC/IB). Such a distinction, however, is too subtle for our needs in this book. We shall use β to denote both dc and incremental values.10
The Saturation Voltage VCEsat and Saturation Resistance RCEsat Refer next to the expanded view of the common-emitter characteristics in the saturation region shown in Fig. 6.20(c). The “bunching together” of the curves in the saturation region implies that the incremental β is lower there than in the active region. A possible operating point in the saturation region is that labeled X. It is characterized by a base current IB, a collector current ICsat, and a collector–emitter voltage VCEsat. From our previous discussion of saturation, recall that ICsat = βforced IB, where βforced < β.
10ManufacturersofbipolartransistorsusehFE todenotethedcvalueofβandhfe todenotetheincremental β. These symbols come from the h-parameter description of two-port networks (see Appendix C), with the subscript F(f) denoting forward and E(e) denoting common emitter.
330 Chapter 6
Bipolar Junction Transistors (BJTs)
iC
IC
0
Saturation region
iB = . . .
iB = . . .
iB = IB + ΔiB
iB =IB
iB = . . .
iB = 0 vCE (b)
IB
1 RCEsat
(c)
iC
ΔiC
Active region
Q
VCE
IB
vCE iB
(a)
bIB
ICsat
iB
Slope
X
VCEsat
Figure 6.20 Common-emitter characteristics. (a) Basic CE circuit; note that in (b) the horizontal scale is expanded around the origin to show the saturation region in some detail. A much greater expansion of the saturation region is shown in (c) .
The iC–vCE curves in saturation are rather steep, indicating that the saturated transistor exhibits a low collector-to-emitter resistance RCEsat,
∂v
RCEsat ≡ CE (6.23) ∂iC iB =IB
iC =ICsat Typically, RCEsat ranges from a few ohms to a few tens of ohms.
IB
VBE
ICsat
VCEsat
6.2 Current–Voltage Characteristics 331
0.7 V
0.2 V
B
E
Figure 6.21 A simplified equivalent-circuit model of the saturated transistor.
That the collector-to-emitter resistance of a saturated BJT is small should have been anticipated from the fact that between C and E we now have two forward-conducting diodes in series11 (see also Fig. 6.9).
AsimplemodelforthesaturatedBJTisshowninFig.6.21.HereVBE isassumedconstant (approximately 0.7 V) and VCE also is assumed constant, VCEsat ≃ 0.2 V. That is, we have neglected the small saturation resistance RCEsat for the sake of making the model simple for hand calculations.
Example 6.3
For the circuit in Fig. 6.22, it is required to determine the value of the voltage VBB that results in the transistor operating
(a) in the active mode with VCE = 5 V (b) at the edge of saturation
(c) deep in saturation with βforced = 10
Forsimplicity,assumethatVBE remainsconstantat0.7V.Thetransistorβisspecifiedtobe50. VCC 10V
VBB RB
10 k
IC RC1k IB
VCE
VBE
11In the corresponding mode of operation for the MOSFET, the triode region, the resistance between drain and source is small because it is the resistance of the continuous (non-pinched-off) channel.
Figure 6.22 Circuit for Example 6.3.
332
Chapter 6 Bipolar Junction Transistors (BJTs)
Example 6.3 continued
Solution
(a) To operate in the active mode with VCE = 5 V,
IC = VCC −VCE RC
= 10−5 =5mA 1k
IB = IC = 5 = 0.1 mA β 50
Now the required value of VBB can be found as follows: VBB =IBRB +VBE
=0.1×10+0.7=1.7V
(b) Operation at the edge of saturation is obtained with VCE = 0.3 V. Thus
IC = 10−0.3 =9.7mA 1
Since, at the edge of saturation, IC and IB are still related by β, IB = 9.7 = 0.194 mA
50 The required value of VBB can be determined as
(c) To operate deep in saturation,
Thus,
VBB =0.194×10+0.7=2.64V VCE =VCEsat ≃0.2V
IC = 10−0.2 =9.8mA 1
We then use the value of forced β to determine the required value of IB as IB = IC = 9.8 = 0.98 mA
β forced 10 and the required VBB can now be found as
VBB =0.98×10+0.7=10.5V
Observe that once the transistor is in saturation, increasing VBB and thus IB results in negligible change in IC since VCEsat will change only slightly. Thus IC is said to saturate, which is the origin of the name “saturation mode of operation.”
6.3 BJT Circuits at DC 333
EXERCISES
6.19 Repeat Example 6.3 for RC = 10 k. Ans. 0.8 V; 0.894 V; 1.68 V
6.20 For the circuit in Fig. 6.22, find VCE for VBB = 0 V. Ans. + 10 V
6.21 For the circuit in Fig. 6.22, let VBB be set to the value obtained in Example 6.3, part (a), namely, VBB = 1.7 V. Verify that the transistor is indeed operating in the active mode. Now, while keeping VBB constant,findthevaluetowhichRC shouldbeincreasedinordertoobtain(a)operationattheedgeof saturation and (b) operation deep in saturation with βforced = 10.
Ans. (a) 1.94 k; (b) 9.8 k
6.3 BJT Circuits at DC
We are now ready to consider the analysis of BJT circuits to which only dc voltages are applied. In the following examples we will use the simple model in which |VBE| of a conducting transistor is 0.7 V and |VCE | of a saturated transistor is 0.2 V, and we will neglect the Early effect. These models are shown in Table 6.3. Better models can, of course, be used to obtain more accurate results. This, however, is usually achieved at the expense of speed of analysis; more importantly, the attendant complexity could impede the circuit designer’s ability to gain insight regarding circuit behavior. Accurate results using elaborate models can be obtained using circuit simulation with SPICE. This is almost always done in the final stages of a design and certainly before circuit fabrication. Computer simulation, however, is not a substitute for quick pencil-and-paper circuit analysis, an essential ability that aspiring circuit designers must master. The following series of examples is a step in that direction.
As will be seen, in analyzing a circuit the first question that one must answer is: In which mode is the transistor operating? In some cases, the answer will be obvious. For instance, a quick check of the terminal voltages will indicate whether the transistor is cut off or conducting. If it is conducting, we have to determine whether it is operating in the active mode or in saturation. In some cases, however, this may not be obvious. Needless to say, as the reader gains practice and experience in transistor circuit analysis and design, the answer will be apparent in a much larger proportion of problems. The answer, however, can always be determined by utilizing the following procedure.
Assume that the transistor is operating in the active mode and, using the active-mode model in Table 6.3, proceed to determine the various voltages and currents that correspond. Then check for consistency of the results with the assumption of active-mode operation; that is, is VCB of an npn transistor greater than −0.4 V (or VCB of a pnp transistor lower than 0.4 V)? If the answer is yes, then our task is complete. If the answer is no, assume saturation-mode operation and, using the saturation-mode model in Table 6.3, proceed to determine currents and voltages
334 Chapter 6 Bipolar Junction Transistors (BJTs)
Table 6.3
Active
EBJ: Forward Biased
CBJ: Reverse Biased
Saturation
EBJ: Forward Biased
CBJ: Forward Biased
Simplified Models for the Operation of the BJT in DC Circuits
IB
npn
pnp
E
BC
VBE
0.7 V
bIB
V > 0.3 V CE
VBE
IB
0.7 V
VCEsat
0.2 V
IC bforced IB BC
E
VEB
B
0.7 V
bIB
VEC > 0.3 V C
E IB
VEB
0.7 V
0.2 V
IB IC = bforcedIB
VECsat BC
E
and then check for consistency of the results with the assumption of saturation-mode operation. HerethetestisusuallytocomputetheratioIC/IB andtoverifythatitislowerthanthetransistor β (i.e., βforced < β). Since β for a given transistor type varies over a wide range,12 one must use the lowest specified β for this test. Finally, note that the order of these two assumptions can be reversed.
A Note on Units Except when otherwise specified, throughout this book we use a consistent set of units, namely, volts (V), milliamps (mA), and kilohms (k).
12That is, if one buys BJTs of a certain part number, the manufacturer guarantees only that their values of β fall within a certain range, say 50 to 150.
Example 6.4
Consider the circuit shown in Fig. 6.23(a), which is redrawn in Fig. 6.23(b) to remind the reader of the convention employed throughout this book for indicating connections to dc sources. We wish to analyze this circuit to determine all node voltages and branch currents. We will assume that β is specified to be 100.
4V
IB
VC VE
10 V
6.3 BJT Circuits at DC 335
IC
10 V
RC
IE
4.7 k
RC 4.7 k
RE
3.3 k
3 0.99
1.00 0.99
4V
10 V
4.7 k
3.3 3.3
(c)
RE
3.3 k
(a)
(b)
1
0.99 mA
4V
10 0.99
4.7 5.3 V 4
5
0.01 mA
3.3 k
4 0.7 3.3 V 1 1 mA 2
Figure 6.23 Analysis of the circuit for Example 6.4: (a) circuit; (b) circuit redrawn to remind the reader of the convention used in this book to show connections to the dc sources; (c) analysis with the steps numbered.
336
Chapter 6 Bipolar Junction Transistors (BJTs)
Example 6.4 continued Solution
Glancing at the circuit in Fig. 6.23(a), we note that the base is connected to +4 V and the emitter is connected to ground through a resistance RE . Therefore, it is reasonable to conclude that the base–emitter junction will be forward biased. Assuming that this is the case and assuming that VBE is approximately 0.7 V, it follows that the emitter voltage will be
VE =4−VBE ≃4−0.7=3.3V Wearenowinanopportuneposition;weknowthevoltagesatthetwoendsofRE andthuscandetermine
thecurrentIE throughit,
IE = VE − 0 = 3.3 = 1 mA RE 3.3
SincethecollectorisconnectedthroughRC tothe+10-Vpowersupply,itappearspossiblethatthecollector voltage will be higher than the base voltage, which implies active-mode operation. Assuming that this is the case, we can evaluate the collector current from
The value of α is obtained from
ThusIC willbegivenby
IC =αIE
α= β =100≃0.99 β+1 101
IC =0.99×1=0.99mA
We are now in a position to use Ohm’s law to determine the collector voltage VC ,
VC =10−ICRC =10−0.99×4.7≃+5.3 V
Since the base is at +4 V, the collector–base junction is reverse biased by 1.3 V, and the transistor is indeed in the active mode as assumed.
It remains only to determine the base current IB, as follows: IB= IE = 1 ≃0.01mA
Before leaving this example, we wish to emphasize strongly the value of carrying out the analysis directly on the circuit diagram. Only in this way will one be able to analyze complex circuits in a reasonable length of time. Figure 6.23(c) illustrates the above analysis on the circuit diagram, with the order of the analysis steps indicated by the circled numbers.
β+1 101
6.3 BJT Circuits at DC 337
Example 6.5
We wish to analyze the circuit of Fig. 6.24(a) to determine the voltages at all nodes and the currents through all branches. Note that this circuit is identical to that of Fig. 6.23 except that the voltage at the base is now +6 V. Assume that the transistor β is specified to be at least 50.
10 V
4.7 k
3.3 k
3 1.6 mA
6V
3.3 k
10 V
4.7 k
5.3
3.3
10
1.6 4.7 2.48 4 Impossible, not in
6 V
(a)
active mode
6 0.7 5.3 V 1
1.6 mA 2
(b)
(c)
Figure6.24 AnalysisofthecircuitforExample6.5.Notethatthecirclednumbersindicatetheorderoftheanalysis steps.
338
Chapter 6 Bipolar Junction Transistors (BJTs)
Example 6.5 continued Solution
With +6 V at the base, the base–emitter junction will be forward biased; thus, VE =+6−VBE ≃6−0.7=5.3V
and
IE = 5.3 =1.6mA 3.3
Now, assuming active-mode operation, IC = αIE ≃ IE ; thus,
VC =+10−4.7×IC ≃10−7.52=2.48V
The details of the analysis performed above are illustrated in Fig. 6.24(b).
Since the collector voltage calculated is less than the base voltage by 3.52 V, it follows that our original
assumption of active-mode operation is incorrect. In fact, the transistor has to be in the saturation mode. Assuming this to be the case, the values of VE and IE will remain unchanged. The collector voltage, however, becomes
VC =VE +VCEsat ≃5.3+0.2=+5.5V fromwhichwecandetermineIC as
IC = 10−5.5 =0.96mA 4.7
and IB can now be found as
IB =IE −IC =1.6−0.96=0.64mA Thus the transistor is operating at a forced β of
βforced = IC = 0.96 = 1.5 IB 0.64
Since βforced is less than the minimum specified value of β, the transistor is indeed saturated. We should emphasize here that in testing for saturation the minimum value of β should be used. By the same token, if we are designing a circuit in which a transistor is to be saturated, the design should be based on the minimum specified β. Obviously, if a transistor with this minimum β is saturated, then transistors with higher values of β will also be saturated. The details of the analysis are shown in Fig. 6.24(c), where the order of the steps used is indicated by the circled numbers.
Example 6.6
We wish to analyze the circuit in Fig. 6.25(a) to determine the voltages at all nodes and the currents through all branches. Note that this circuit is identical to that considered in Examples 6.4 and 6.5 except that now the base voltage is zero.
2 1
(a) (b)
Figure6.25 Example6.6:(a)circuit;(b)analysis,withtheorderoftheanalysisstepsindicatedbycirclednumbers. Solution
Since the base is at zero volts and the emitter is connected to ground through RE , the base–emitter junction cannot conduct and the emitter current is zero. Also, the collector–base junction cannot conduct, since the n-typecollectorisconnectedthroughRC tothepositivepowersupplywhilethep-typebaseisatground.It follows that the collector current will be zero. The base current will also have to be zero, and the transistor is in the cutoff mode of operation.
The emitter voltage will be zero, while the collector voltage will be equal to +10 V, since the voltage dropsacrossRE andRC arezero.Figure6.25(b)showstheanalysisdetails.
EXERCISES
D6.22 For the circuit in Fig. 6.23(a), find the highest voltage to which the base can be raised while the transistor remains in the active mode. Assume α ≃1.
Ans. +4.7 V
D6.23 RedesignthecircuitofFig.6.23(a)(i.e.,findnewvaluesforRE andRC)toestablishacollectorcurrent of 0.5 mA and a reverse-bias voltage on the collector–base junction of 2 V. Assume α ≃ 1.
Ans. RE =6.6 k; RC =8 k
6.3 BJTCircuitsatDC 339
340 Chapter 6 Bipolar Junction Transistors (BJTs)
D6.24 For the circuit in Fig. 6.24(a), find the value to which the base voltage should be changed so that the transistor operates in saturation with a forced β of 5.
Ans. +5.18 V
Example 6.7
We want to analyze the circuit of Fig. 6.26(a) to determine the voltages at all nodes and the currents through all branches.
V 10 V
RE 2 k
RC 1 k
V 10 V (a)
10 V
10
0.7
4.65 mA 2
5
0.99 4.65
2k
0.05 mA
4.6 mA
2
0.7 V 1
10 4.6 1 5.4 V 4
3
1k
10 V
(b)
Figure6.26 Example6.7:(a)circuit;(b)analysis,withthestepsindicatedbycirclednumbers. Solution
The base of this pnp transistor is grounded, while the emitter is connected to a positive supply (V + = +10 V) through RE . It follows that the emitter–base junction will be forward biased with
VE =VEB ≃0.7V
Thus the emitter current will be given by
IE = V+ −VE = 10−0.7 =4.65mA RE 2
Since the collector is connected to a negative supply (more negative than the base voltage) through RC , it is possible that this transistor is operating in the active mode. Assuming this to be the case, we obtain
IC =αIE
Since no value for β has been given, we shall assume β = 100, which results in α = 0.99. Since large variations in β result in small differences in α, this assumption will not be critical as far as determining thevalueofIC isconcerned.Thus,
The collector voltage will be
IC =0.99×4.65=4.6mA
VC =V−+ICRC =−10+4.6×1=−5.4V
Thus the collector–base junction is reverse biased by 5.4 V, and the transistor is indeed in the active mode, which supports our original assumption.
It remains only to calculate the base current,
IB = IE = 4.65 ≃ 0.05 mA β+1 101
Obviously, the value of β critically affects the base current. Note, however, that in this circuit the value of β will have no effect on the mode of operation of the transistor. Since β is generally an ill-specified parameter, this circuit represents a good design. As a rule, one should strive to design the circuit such that its performance is as insensitive to the value of β as possible. The analysis details are illustrated in Fig. 6.26(b).
EXERCISES
D6.25 For the circuit in Fig. 6.26(a), find the largest value to which RC can be raised while the transistor remains in the active mode.
Ans. 2.26 k
D6.26 Redesign the circuit of Fig. 6.26(a) (i.e., find new values for RE and RC ) to establish a collector
current of 1 mA and a reverse bias on the collector–base junction of 4 V. Assume α ≃ 1. Ans. RE =9.3 k; RC =6 k
6.3 BJTCircuitsatDC 341
342 Chapter 6 Bipolar Junction Transistors (BJTs)
Example 6.8
We want to analyze the circuit in Fig. 6.27(a) to determine the voltages at all nodes and the currents in all branches. Assume β = 100.
(a) (b)
Figure6.27 Example6.8:(a)circuit;(b)analysis,withthestepsindicatedbythecirclednumbers.
Solution
The base–emitter junction is clearly forward biased. Thus,
IB = +5−VBE ≃ 5−0.7 =0.043mA
RB 100
Assume that the transistor is operating in the active mode. We now can write
IC =βIB =100×0.043=4.3mA The collector voltage can now be determined as
VC =10−ICRC =10−4.3×2=+1.4V VB=VBE ≃+0.7V
Since the base voltage VB is
it follows that the collector–base junction is reverse biased by 0.7 V and the transistor is indeed in the
active mode. The emitter current will be given by
IE =(β+1)IB =101×0.043 ≃ 4.3mA
We note from this example that the collector and emitter currents depend critically on the value of β. In fact, if β were 10% higher, the transistor would leave the active mode and enter saturation. Therefore this clearly is a bad design. The analysis details are illustrated in Fig. 6.27(b).
6.3 BJT Circuits at DC 343
EXERCISE
D6.27 ThecircuitofFig.6.27(a)istobefabricatedusingatransistortypewhoseβisspecifiedtobeinthe range of 50 to 150. That is, individual units of this same transistor type can have β values anywhere in this range. Redesign the circuit by selecting a new value for RC so that all fabricated circuits are guaranteed to be in the active mode. What is the range of collector voltages that the fabricated circuits may exhibit?
Ans. RC =1.5k;VC =0.3Vto6.8V
Example 6.9
We want to analyze the circuit of Fig. 6.28(a) to determine the voltages at all nodes and the currents through all branches. The minimum value of β is specified to be 30.
5V
1k
10 k
5V
4 I 5 (VB 0.7)
E 1 1k
VE VEC sat
VB
0.7 3 5
2 IB
VB /10 10 k
10 k
0.2 V
VC VB 0.56
1
VB
I VB 0.5 ( 5) 10 k
7C 10
5 V (a)
5V
(b)
Figure6.28 Example6.9:(a)circuit;(b)analysiswithstepsnumbered. Solution
A quick glance at this circuit reveals that the transistor will be either active or saturated. Assuming active-mode operation and neglecting the base current, we see that the base voltage will be approximately zero volts, the emitter voltage will be approximately +0.7 V, and the emitter current will be approximately 4.3 mA. Since the maximum current that the collector can support while the transistor remains in the active mode is approximately 0.5 mA, it follows that the transistor is definitely saturated.
344
Chapter 6 Bipolar Junction Transistors (BJTs)
Example 6.9 continued AssumingthatthetransistorissaturatedanddenotingthevoltageatthebasebyVB (refertoFig.6.28b),
it follows that
VE =VB +VEB ≃VB +0.7
VC =VE −VECsat ≃VB +0.7−0.2=VB +0.5
IE = +5−VE = 5−VB −0.7 =4.3−VB mA 11
IB=VB =0.1VB mA 10
IC = VC −(−5) = VB +0.5+5 =0.1VB +0.55 mA 10 10
Using the relationship IE = IB + IC , we obtain
4.3−VB =0.1VB +0.1VB +0.55
which results in
VB = 3.75 ≃3.13V 1.2
Substituting in the equations above, we obtain
VE =3.83V VC =3.63V
IE =1.17mA IC =0.86mA IB =0.31mA
from which we see that the transistor is saturated, since the value of forced β is βforced = 0.86 ≃ 2.8
0.31 which is much smaller than the specified minimum β.
Example 6.10
We want to analyze the circuit of Fig. 6.29(a) to determine the voltages at all nodes and the currents through all branches. Assume β = 100.
15 V 15 V
RRC RC
6.3 BJT Circuits at DC 345
B1 100 k
RB2 50 k
5 k
VBB 5 V RBB
33.3 k
IB
5 k
IE
RE LRE
(a)
3k
15 V
5k
3k
3 k
15 V
0.013 mA 4.57 V
0.09 mA
1.28 mA
33.3 k
(b)
100 k
50 k
(d)
0.103 mA
5 V
0.013 mA
4.57 V
1.29 mA
(c)
Figure 6.29 Circuits for Example 6.10.
Solution
8.6 V
3.87 V
The first step in the analysis consists of simplifying the base circuit using The ́venin’s theorem. The result is shown in Fig. 6.29(b), where
VBB =+15 RB2 =15 50 =+5V RB1 +RB2 100+50
RBB = RB1 ∥RB2 =100∥50= 33.3 k
346
Chapter 6 Bipolar Junction Transistors (BJTs)
Example 6.10 continued
To evaluate the base or the emitter current, we have to write a loop equation around the loop labeled L in Fig. 6.29(b). Note, however, that the current through RBB is different from the current through RE . The loop equation will be
VBB =IBRBB +VBE +IERE Now, assuming active-mode operation, we replace IB with
and rearrange the equation to obtain
For the numerical values given we have
IE =
IB= IE β+1
VBB −VBE
RE +[RBB/(β+1)]
The base current will be
The base voltage is given by
IE =
IB = 1.29 = 0.0128 mA
101
VB =VBE +IERE =0.7+1.29×3=4.57V
5−0.7 =1.29mA 3 + (33.3/101)
We can evaluate the collector current as
IC =αIE =0.99×1.29=1.28mA
The collector voltage can now be evaluated as
VC =+15−ICRC =15−1.28×5=8.6V
It follows that the collector is higher in potential than the base by 4.03 V, which means that the transistor is in the active mode, as had been assumed. The results of the analysis are given in Fig. 6.29(c, d).
EXERCISE
6.28 If the transistor in the circuit of Fig. 6.29(a) is replaced with another having half the value of β (i.e., β=50),findthenewvalueofIC,andexpressthechangeinIC asapercentage.
Ans. IC = 1.15 mA; –10%
6.3 BJT Circuits at DC 347
Example 6.11
We wish to analyze the circuit in Fig. 6.30(a) to determine the voltages at all nodes and the currents through all branches.
RB1
RB2
100 k
15 V
RC1 5 k
Q2
RE2 2 k IE2
IC1 Q1
IB2
IC2
RC2 2.7 k
50 k
RE 3 k
(a) 15 V
1.252 mA
100 k
0.013 mA
50 k
0.09 mA
2.78 mA
0.103 mA
2k
2.7 k
2.75 mA
5k
Q2
8.74 V
9.44 V
7.43 V
4.57 V
Q1
0.0275 mA 1.28 mA
3.87 V
3k
1.29 mA
(b)
Figure 6.30 Circuits for Example 6.11.
348
Chapter 6 Bipolar Junction Transistors (BJTs)
Example 6.11 continued Solution
We first recognize that part of this circuit is identical to the circuit we analyzed in Example 6.10 —namely, the circuit of Fig. 6.29(a). The difference, of course, is that in the new circuit we have an additional transistor Q2 together with its associated resistors RE2 and RC2. Assume that Q1 is still in the active mode. The following values will be identical to those obtained in the previous example:
VB1 = +4.57 V IE1 = 1.29 mA IB1 = 0.0128 mA IC1 = 1.28 mA
However, the collector voltage will be different than previously calculated, since part of the collector current IC1 will flow in the base lead of Q2 (IB2). As a first approximation we may assume that IB2 is much smaller than IC1; that is, we may assume that the current through RC1 is almost equal to IC1. This will enable us to calculate VC1:
VC1 ≃ +15−IC1RC1 =15−1.28×5=+8.6V
Thus Q1 is in the active mode, as had been assumed.
As far as Q2 is concerned, we note that its emitter is connected to +15 V through RE2. It is therefore
safe to assume that the emitter–base junction of Q2 will be forward biased. Thus the emitter of Q2 will be at a voltage VE2 given by
V =V +V ≃8.6+0.7=+9.3V E2 C1 EB Q2
The emitter current of Q2 may now be calculated as
IE2 = +15−VE2 = 15−9.3 =2.85mA
RE2 2
SincethecollectorofQ2 isreturnedtogroundviaRC2,itispossiblethatQ2 isoperatingintheactivemode.
Assume this to be the case. We now find IC2 as IC2 =α2IE2
=0.99×2.85=2.82mA assumingβ2 =100 The collector voltage of Q2 will be
VC2 =IC2RC2 =2.82×2.7=7.62V
which is lower than VB2 by 0.98 V. Thus Q2 is in the active mode, as assumed.
It is important at this stage to find the magnitude of the error incurred in our calculations by the assumption that IB2 is negligible. The value of IB2 is given by
IB2 = IE2 = 2.85 = 0.028 mA β2 +1 101
which is indeed much smaller than IC1 (1.28 mA). If desired, we can obtain more accurate results by iterating one more time, assuming IB2 to be 0.028 mA. The new values will be
Current in RC1 = IC1 − IB2 = 1.28 − 0.028 = 1.252 mA VC1 =15−5×1.252=8.74V
VE2 =8.74+0.7=9.44V IE2 = 15−9.44 =2.78mA
2
IC2 =0.99×2.78=2.75mA
VC2 =2.75×2.7=7.43V IB2 = 2.78 = 0.0275 mA
101
Note that the new value of IB2 is very close to the value used in our iteration, and no further iterations are warranted. The final results are indicated in Fig. 6.30(b).
The reader justifiably might be wondering about the necessity for using an iterative scheme in solving a linear (or linearized) problem. Indeed, we can obtain the exact solution (if we can call anything we are doing with a first-order model exact!) by writing appropriate equations. The reader is encouraged to find this solution and then compare the results with those obtained above. It is important to emphasize, however, that in most such problems it is quite sufficient to obtain an approximate solution, provided we can obtain it quickly and, of course, correctly.
In the above examples, we frequently used a precise value of α to calculate the collector current. Since α ≃ 1, the error in such calculations will be very small if one assumes α = 1 and IC = IE . Therefore, except in calculations that depend critically on the value of α (e.g., the calculation of base current), one usually assumes α ≃ 1.
EXERCISES
6.29 ForthecircuitinFig.6.30,findthetotalcurrentdrawnfromthepowersupply.Hencefindthepower dissipated in the circuit.
Ans. 4.135 mA; 62 mW
6.30 ThecircuitinFig.E6.30istobeconnectedtothecircuitinFig.6.30(a)asindicated;specifically,the
base of Q3 is to be connected to the collector of Q2. If Q3 has β = 100, find the new value of VC2 and the values of VE3 and IC3.
6.3 BJT Circuits at DC 349
350 Chapter 6 Bipolar Junction Transistors (BJTs)
To collector of Q2 in Fig. 6.30 (a)
Ans. +7.06 V; +6.36 V; 13.4 mA
Example 6.12
Figure E6.30
We desire to evaluate the voltages at all nodes and the currents through all branches in the circuit of Fig. 6.31(a). Assume β = 100.
(a)
Figure6.31 Example6.12:(a)circuit;(b)analysiswiththestepsnumbered.
5 – 0.7 = 10 101 1 0.039 mA
On
0 3.9 mA
Off 0
–5V
(b)
Solution
By examining the circuit, we conclude that the two transistors Q1 and Q2 cannot be simultaneously conducting. Thus if Q1 is on, Q2 will be off, and vice versa. Assume that Q2 is on. It follows that current will flow from ground through the 1-k resistor into the emitter of Q2. Thus the base of Q2 will be at a negative voltage, and base current will be flowing out of the base through the 10-k resistor and into the +5-V supply. This is impossible, since if the base is negative, current in the 10-k resistor will have to flow into the base. Thus we conclude that our original assumption—that Q2 is on—is incorrect. It follows that Q2 will be off and Q1 will be on.
The question now is whether Q1 is active or saturated. The answer in this case is obvious: Since the base is fed with a +5-V supply and since base current flows into the base of Q1, it follows that the base of Q1 will be at a voltage lower than +5 V. Thus the collector–base junction of Q1 is reverse biased and Q1 is in the active mode. It remains only to determine the currents and voltages using techniques already described in detail. The results are given in Fig. 6.31(b).
EXERCISES
6.31 SolvetheprobleminExample6.12forthecaseofavoltageof–5Vfeedingthebases.Whatvoltage appears at the emitters?
Ans. –3.9 V
6.32 Solve the problem in Example 6.12 with the voltage feeding the bases changed to +10 V. Assume that
βmin =30, and find VE, VB, IC1, and IC2. Ans. +4.8 V; +5.5 V; 4.35 mA; 0
6.4 Transistor Breakdown and Temperature Effects
We conclude this chapter with a brief discussion of two important nonideal effects in the BJT: voltage breakdown, and the dependence of β on IC and temperature.
6.4.1 Transistor Breakdown
The maximum voltages that can be applied to a BJT are limited by the EBJ and CBJ breakdown effects that follow the avalanche multiplication mechanism described in Section3.5.3. Consider first the common-base configuration (Fig. 6.32(a)). The iC – v CB characteristics in Fig. 6.32(b) indicate that for iE = 0 (i.e., with the emitter open-circuited) the collector–base junctionbreaksdownatavoltagedenotedbyBVCBO.ForiE >0,breakdownoccursatvoltages smaller than BVCBO . Typically, for discrete BJTs, BVCBO is greater than 50 V.
6.4 TransistorBreakdownandTemperatureEffects 351
352 Chapter 6
Bipolar Junction Transistors (BJTs)
Saturation region
iC
E1
Active region
iE IE1 iE IE2
iE 0
aI aIE2
0
vCB
0.4 V
BVCBO
Expanded scale
(b)
vCB
iC
iE
(a)
Figure 6.32 The BJT common-base characteristics including the transistor breakdown region.
Figure 6.33 The BJT common-emitter characteristics including the breakdown region.
Next consider the common-emitter characteristics of Fig. 6.33, which show breakdown occurring at a voltage BVCEO. Here, although breakdown is still of the avalanche type, the effects on the characteristics are more complex than in the common-base configuration. We will not explain these in detail; it is sufficient to point out that typically BVCEO is about half BVCBO. On transistor data sheets, BVCEO is sometimes referred to as the sustaining voltage
LVCEO.
Breakdown of the CBJ in either the common-base or common-emitter configuration is not destructive as long as the power dissipation in the device is kept within safe limits. This, however, is not the case with the breakdown of the emitter–base junction. The EBJ breaks down in an avalanche manner at a voltage BVEBO much smaller than BVCBO. Typically, BVEBO is in the range of 6 V to 8 V, and the breakdown is destructive in the sense that the β of the transistor is permanently reduced. This does not prevent use of the EBJ as a zener diode to generate reference voltages in IC design. In such applications one is not concerned with the β-degradation effect. A circuit arrangement to prevent EBJ breakdown in IC amplifiers will be discussed in Chapter 13. Transistor breakdown and the maximum allowable power dissipation are important parameters in the design of power amplifiers (Chapter 12).
EXERCISE
6.33 What is the output voltage of the circuit in Fig. E6.33 if the transistor BVBCO = 70 V?
6.4 Transistor Breakdown and Temperature Effects 353
Ans. –60 V
μA
6.4.2 Dependence of β on IC and Temperature
Throughout this chapter we have assumed that the transistor common-emitter dc current gain, β or hFE , is constant for a given transistor. In fact, β depends on the dc current at which the transistor is operating, as shown in Fig. 6.34. The physical processes that give rise to this dependence are beyond the scope of this book. Note, however, that there is a current range over which β is highest. Normally, one arranges to operate the transistor at a current within this range.
Figure 6.34 also shows the dependence of β on temperature. The fact that β increases with temperature can lead to serious problems in transistors that operate at large power levels (see Chapter 12).
Figure E6.33
354 Chapter 6 Bipolar Junction Transistors (BJTs)
μ
Figure 6.34 Typical dependence of β on IC and on temperature in an integrated-circuit npn silicon transistor intended for operation around 1 mA.
Summary
Depending on the bias conditions on its two junctions, the BJT can operate in one of three possible modes: cutoff (both junctions reverse biased), active (the EBJ forward biased and the CBJ reverse biased), and saturation (both junctions forward biased). Refer to Table 6.1.
For amplifier applications, the BJT is operated in the active mode. Switching applications make use of the cutoff and saturation modes.
TheBJTwillbeattheedgeofsaturationwhenv is CE
reduced to about 0.3 V. In saturation, vCE ≃ 0.2 V, and the ratio of iC to iB is lower than β (i.e., βforced < β).
In the active mode, iC shows a slight dependence on vCE .
This phenomenon, known as the Early effect, is modeled
A BJT operating in the active mode provides a collector current i = I e|vBE |/VT . The base current i = i /β, and
is the dc collector current without the Early effect taken into account. In discrete circuits, ro plays a minor role and can usually be neglected. This is not the case, however, in integrated-circuit design (Chapter 8).
The dc analysis of transistor circuits is greatly simplified by assuming that V ≃ 0.7 V. Refer to Table 6.3.
BE
If the BJT is conducting, one assumes it is operating in the active mode and, using the active-mode model, proceeds to determine all currents and voltages. The validity of the initial assumption is then checked by determining whether the CBJ is reverse biased. If it is, the analysis is complete; otherwise, we assume the BJT is operating in saturation and redo the analysis, using the saturation-mode model and checking at the end that IC < β IB .
CS BC
the emitter current iE =iC +iB. Also, iC =αiE, and thus
β = α/(1 − α) and α = β/(β + 1). See Table 6.2.
To ensure operation in the active mode, the collector
voltage of an npn transistor must be kept higher than approximately 0.4 V below the base voltage. For a pnp transistor, the collector voltage must be lower than approximately 0.4 V above the base voltage. Otherwise, the CBJ becomes forward biased, and the transistor enters the saturation region.
At a constant collector current, the magnitude of the base–emitter voltage decreases by about 2 mV for every 1°C rise in temperature.
by ascribing a finite (i.e., noninfinite) output resistance to
the BJT: r = V /I′ , where V is the Early voltage and I′ oACAC
Computer Simulations Problems
Problems identified by the Multisim/PSpice icon are intended to demonstrate the value of using SPICE simulation to verify hand analysis and design, and to investigate important issues such as allowable signal swing and amplifier nonlinear distortion. Instructions to assist in setting up PSPice and Multisim simulations for all the indicated problems can be found in the corresponding files on the website. Note that if a particular parameter value is not specified in the problem statement, you are to make a reasonable assumption.
Section 6.1: Device Structure and Physical Operation
6.1 The terminal voltages of various npn transistors are measured during operation in their respective circuits with the following results:
Case E B C Mode
transistors are operated in the active mode and conduct equal collector currents, what do you expect the difference in their vBE values to be?
6.5 Find the collector currents that you would expect for operation at vBE = 700 mV for transistors for which IS = 10−13 A and IS = 10−18 A. For the transistor with the larger EBJ, what is the vBE required to provide a collector current equal to that provided by the smaller transistor at vBE = 700 mV? Assume active-mode operation in all cases.
6.6 In this problem, we contrast two BJT integrated-circuit fabrication technologies: For the “old” technology, a typical npn transistor has IS = 2 × 10−15 A, and for the “new” technology, a typical npn transistor has IS = 2 × 10−18 A. These typical devices have vastly different junction areas and base width. For our purpose here we wish to determine the vBE required to establish a collector current of 1 mA in each of the two typical devices. Assume active-mode operation.
6.7 Consider an npn transistor whose base–emitter drop is 0.76 V at a collector current of 5 mA. What current will it conduct at vBE = 0.70 V? What is its base–emitter voltage for iC =5μA?
6.8 In a particular BJT, the base current is 10 μA, and the collector current is 800 μA. Find β and α for this device.
6.9 Find the values of β that correspond to α values of 0.5, 0.8, 0.9, 0.95, 0.98, 0.99, 0.995, and 0.999.
6.10 Find the values of α that correspond to β values of 1, 2, 10, 20, 50, 100, 200, 500, and 1000.
*6.11 Show that for a transistor with α close to unity, if α changes by a small per-unit amount (α/α), the corresponding per-unit change in β is given approximately by
PROBLEMS
1 0
2 0
3 −0.7 4 −0.7 5 1.3 6 0
0.7 0.7 0.8 0.1 0 1.0 0 −0.6 2.0 5.0 0 5.0
In this table, where the entries are in volts, 0 indicates the reference terminal to which the black (negative) probe of the voltmeter is connected. For each case, identify the mode of operation of the transistor.
6.2 Two transistors, fabricated with the same technology but having different junction areas, when operated at a base-emitter voltage of 0.75 V, have collector currents of 0.5 mA and 2 mA. Find IS for each device. What are the relative junction areas?
6.3 In a particular technology, a small BJT operating at vBE = 30VT conducts a collector current of 200 μA. What is the corresponding saturation current? For a transistor in the same technology but with an emitter junction that is 32 times larger, what is the saturation current? What current will this transistor conduct at vBE = 30VT ? What is the base–emitter voltage of the latter transistor at iC = 1 mA? Assume active-mode operation in all cases.
6.4 Two transistors have EBJ areas as follows: AE1 = 200μm×200μmandAE2 =0.4μm×0.4μm.Ifthetwo
β α ≃β
βα
Now, for a transistor whose nominal β is 100, find the percentage change in its α value corresponding to a drop in its β of 10%.
6.12 Annpntransistorofatypewhoseβisspecifiedtorange from 50 to 300 is connected in a circuit with emitter grounded, collector at + 10 V, and a current of 10 μA injected into the base. Calculate the range of collector and emitter currents that can result. What is the maximum power dissipated in the transistor? (Note: Perhaps you can see why this is a bad way to establish the operating current in the collector of a BJT.)
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
356 Chapter 6 Bipolar Junction Transistors (BJTs)
6.13 ABJTisspecifiedtohaveIS =5×10−15 Aandβthat falls in the range of 50 to 200. If the transistor is operated in the active mode with vBE set to 0.700 V, find the expected range of iC, iB, and iE.
6.14 Measurements made on a number of transistors operat- ing in the active mode with iE = 1 mA indicate base currents of 10 μA, 20 μA, and 50 μA. For each device, find iC , β, and α.
6.15 Measurements of VBE and two terminal currents taken on a number of npn transistors operating in the active mode are tabulated below. For each, calculate the missing current valueaswellasα,β,andIS asindicatedbythetable.
Transistor a b c d e
and across CBJ when each is forward biased and conducting a current of 1 mA. Also find the forward current each junction would conduct when forward biased with 0.5 V.
*6.20 We wish to investigate the operation of the npn transistor in saturation using the model of Fig. 6.9. Let IS = 10−15 A,vBE =0.7V,β=100,andISC/IS =100.Foreachof three values of vCE (namely, 0.4 V, 0.3 V, and 0.2 V), find vBC, iBC, iBE, iB, iC, and iC/iB. Present your results in tabular form. Also find vCE that results in iC = 0.
*6.21 Use Eqs. (6.14), (6.15), and (6.16) to show that an npn transistor operated in saturation exhibits a collector-to-emitter voltage, VCEsat , given by
times that of the EBJ. Present your results in a table.
6.22 Consider the pnp large-signal model of Fig. 6.11(b) applied to a transistor having IS = 10−14 A and β = 50. If the emitter is connected to ground, the base is connected to a current source that pulls 10 μA out of the base terminal, and the collector is connected to a negative supply of −5 V via a 8.2-k resistor, find the collector voltage, the emitter current, and the base voltage.
6.23 A pnp transistor has vEB = 0.7 V at a collector current of1mA.WhatdoyouexpectvEB tobecomeatiC =10mA? AtiC=100mA?
6.24 A pnp transistor modeled with the circuit in Fig. 6.11 (b) is connected with its base at ground, collector at –2.0 V, and a 1-mA current is injected into its emitter. If the transistor is said to have β = 10, what are its base and collector currents? In which direction do they flow? If IS = 10−15 A, what voltage results at the emitter? What does the collector current become if a transistor with β = 1000 is substituted? (Note: The fact that the collector current changes by less than 10% for a large change in β illustrates that this is a good way to establish a specific collector current.)
6.25A pnp power transistor operates with an emitter-to-collector voltage of 5 V, an emitter current of 5 A, and VEB = 0.8 V. For β = 20, what base current is required? What is IS for this transistor? Compare the emitter–base junction area of this transistor with that of a small-signal
CHAPTER 6 PROBLEMS
I1+β SC forced
VCEsat = VT ln
Use this relationship to evaluate VCEsat for βforced = 50, 10, 5,
VBE (mV) IC (mA) IB (μA) IE (mA) α
β
IS
700 1.000 10
690 1.000
1.020
580
5 0.235
780 820 10.10
IS 1−βforced/β
and 1 for a transistor with β = 100 and with a CBJ area 100
6.16 When operated in the active mode, a particular npn BJT conducts a collector current of 1 mA and has vBE = 0.70 V and iB = 10 μA. Use these data to create specific transistor models of the form shown in Fig. 6.5(a) to (d).
6.17 Using the npn transistor model of Fig. 6.5(b), consider the case of a transistor for which the base is connected to ground, the collector is connected to a 5-V dc source through a 2-k resistor, and a 2-mA current source is connected to the emitter with the polarity so that current is drawn out of the emitter terminal. If β = 100 and IS = 5 × 10−15 A, find the voltages at the emitter and the collector and calculate the base current.
D 6.18 Consider an npn transistor operated in the active mode and represented by the model of Fig. 6.5(d). Let the transistor be connected as indicated by the equivalent circuit shown in Fig. 6.6(b). It is required to calculate the values of RB andRC thatwillestablishacollectorcurrentIC of0.5mAand acollector-to-emittervoltageVCE of1V.TheBJTisspecified tohaveβ=50andIS =5×10−15 A.
6.19 An npn transistor has a CBJ with an area 100 times that of the EBJ. If IS = 10−15 A, find the voltage drop across EBJ
120
1050 75.00
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
CHAPTER 6 PROBLEMS
transistor that conducts iC = 1 mA with vEB = 0.70 V. How much larger is it?
6.26 While Fig. 6.5 provides four possible large-signal equivalent circuits for the npn transistor, only two equivalent circuits for the pnp transistor are provided in Fig. 6.11. Supply the missing two.
6.27 By analogy to the npn case shown in Fig. 6.9, give the equivalent circuit of a pnp transistor in saturation.
Problems 357 Section 6.2: Current–Voltage Characteristics
6.28 ForthecircuitsinFig.P6.28,assumethatthetransistors have very large β. Some measurements have been made on these circuits, with the results indicated in the figure. Find the values of the other labeled voltages and currents.
6.29 Measurements on the circuits of Fig. P6.29 produce labeled voltages as indicated. Find the value of β for each transistor.
2
5 k
V2 5 k
(a)
Figure P6.28
5.6 k
2.4 k
V3
I5
20 k
9.1 k
3 k
(d)
V4 4V
0.7 V
15 k
V7
0 V
I6
(b)
(c)
7V
6.3 V
45 k
200 k
Figure P6.29
+ 3.0 V
2 k
27 k
(b)
750
1.5 k
(a)
(c)
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
358 Chapter 6 Bipolar Junction Transistors (BJTs)
6.30 A very simple circuit for measuring β of an npn transistor is shown in Fig. P6.30. In a particular design, VCC is provided by a 9-V battery; M is a current meter with a 50-μA full scale and relatively low resistance that you can neglect for our purposes here. Assuming that the transistor has VBE = 0.7 V at IE = 1 mA, what value of RC would establish a resistor current of 1 mA? Now, to what value of β does a meter reading of full scale correspond? What is β if the meter reading is 1/5 of full scale? 1/10 of full scale?
D 6.33 Examination of the table of standard values for resis- tors with 5% tolerance in Appendix J reveals that the closest values to those found in the design of Example 6.2 are 5.1 k and 6.8 k. For these values, use approximate calculations (e.g., VBE ≃ 0.7 V and α ≃ 1) to determine the values of collector current and collector voltage that are likely to result.
D 6.34 Design the circuit in Fig. P6.34 to establish IC = 0.2 mA and VC = 0.5 V. The transistor exhibits vBE of 0.8 V atiC =1mA,andβ=100.
VCC RC
M
1.5 V
RC
IC
VC
RE
1.5 V
CHAPTER 6 PROBLEMS
Figure P6.30
Figure P6.34
6.31 Repeat Exercise 6.13 for the situation in which the power supplies are reduced to ±2.5 V.
D 6.32 Design the circuit in Fig. P6.32 to establish a current of 0.5 mA in the emitter and a voltage of −0.5 V at the collector. The transistor vEB = 0.64 V at IE = 0.1 mA, and β=100.TowhatvaluecanRC beincreasedwhilethecollector current remains unchanged?
2.5 V
6.35 For each of the circuits shown in Fig. P6.35, find the
emitter, base, and collector voltages and currents. Use β = 50,
but assume V = 0.8 V independent of current level. BE
1.5 V
2.7 k
1.5 V
2 k
RE Q1Q2
RC
2.5 V
2.7 k
1.5 V (a)
Figure P6.35
2 k
1.5 V (b)
Figure P6.32
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
3V
10 k 1.0 V
Q3
5.6 k
(c)
Figure P6.35 continued
1.5 V
3 V
8.2 k
Q4
4.7 k
(d)
6.41 UseEq.(6.18)toplotiC versusvCE forannpntransistor having IS = 10−15 A and VA = 100 V. Provide curves for vBE = 0.65, 0.70, 0.72, 0.73, and 0.74 volts. Show the characteristics for vCE up to 15 V.
*6.42 In the circuit shown in Fig. P6.42, current source I is 1.1mA, and at 25°C vBE =680mV at iE =1mA. At 25°C with β = 100, what currents flow in R1 and R2 ? What voltage would you expect at node E? Noting that the temperature coefficient of vBE for IE constant is −2 mV/°C, what is the TC of vE ? For an ambient temperature of 75°C, what voltage would you expect at node E? Clearly state any simplifying assumptions you make.
Problems 359
CHAPTER 6 PROBLEMS
6.36 The current ICBO of a small transistor is measured to be 10 nA at 25°C. If the temperature of the device is raised to 125°C, what do you expect ICBO to become?
6.37 Augment the model of the npn BJT shown in Fig. 6.19(a) by a current source representing ICBO . Assume that ro is very large and thus can be neglected. In terms of this addition,whatdotheterminalcurrentsiB,iC,andiE become?If the base lead is open-circuited while the emitter is connected to ground, and the collector is connected to a positive supply, find the emitter and collector currents.
6.38 A BJT whose emitter current is fixed at 1 mA has a base–emitter voltage of 0.70 V at 25°C. What base–emitter voltage would you expect at 0°C? At 100°C?
6.39 A particular pnp transistor operating at an emitter current of 0.5 mA at 20°C has an emitter–base voltage of 692 mV.
(a) What does vEB become if the junction temperature rises to 50°C?
(b) Ifthetransistorisoperatedatafixedemitter–basevoltage of 700 mV, what emitter current flows at 20°C? At 50°C?
6.40 Consider a transistor for which the base–emitter voltage drop is 0.7 V at 10 mA. What current flows for vBE = 0.5 V? Evaluate the ratio of the slopes of the iC –v BE curve at v BE = 700 mV and at vBE = 500 mV. The large ratio confirms the point that the BJT has an “apparent threshold” at vBE ≃ 0.5 V.
R2 68 k
R1 6.8 k
Figure P6.42
E
I
6.43 For a particular npn transistor operating at a vBE of 680 mV and IC = 1 mA, the iC –v CE characteristic has a slope of 0.8 × 10−5 . To what value of output resistance does this correspond? What is the value of the Early voltage for this transistor? For operation at 10 mA, what would the output resistance become?
6.44 For a BJT having an Early voltage of 50 V, what is its output resistance at 1 mA? At 100 μA?
6.45 Measurements of the iC –v CE characteristic of a small-signal transistor operating at vBE = 710 mV show that iC =1.1mAatvCE =5VandthatiC =1.3mAatvCE =15V. What is the corresponding value of iC near saturation? At what value of vCE is iC = 1.2 mA? What is the value of the Early voltage for this transistor? What is the output resistance that corresponds to operation at vBE = 710 mV?
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
360 Chapter 6 Bipolar Junction Transistors (BJTs) 6.46 Give the pnp equivalent circuit models that correspond
to those shown in Fig. 6.19 for the npn case.
6.47 A BJT operating at iB = 10μA and iC = 1.0mA undergoes a reduction in base current of 1.0 μA. It is found that when vCE is held constant, the corresponding reduction in collector current is 0.08 mA. What are the values of β and the incrementalβorβac thatapply?Ifthebasecurrentisincreased from10μAto12μAandvCE isincreasedfrom8Vto10V, what collector current results? Assume VA = 100 V.
6.48 For the circuit in Fig. P6.48 let VCC = 10 V, RC = 1 k, and RB = 10 k. The BJT has β=50. Find the value of VBB that results in the transistor operating
5V
RB 10 k
VC
1k
CHAPTER 6 PROBLEMS
(a) in the active mode with VC = 2 V; (b) at the edge of saturation;
(c) deep in saturation with βforced = 10.
Figure P6.50
Assume VBE ≃ 0.7 V.
VBB
RB
Figure P6.48
IC
VCC RC
6.51 The transistor in the circuit of Fig. P6.51 has a very high β.FindVE andVC forVB (a)+2.0V,(b)+1.7V,and(c)0V.
3V
1k
VC
VE
Section 6.3: BJT Circuits at DC
VC
VB
1k
D *6.49 Consider the circuit of Fig. P6.48 for the case
VBB = VCC . If the BJT is saturated, use the equivalent circuit
Figure P6.51
of Fig. 6.21 to derive an expression for β in terms of V
forced CC and RB/RC . Also derive an expression for the total power
6.52 The transistor in the circuit of Fig. P6.51 has a very high β. Find the highest value of VB for which the transistor still operates in the active mode. Also, find the value of VB for which the transistor operates in saturation with a forced β of 2.
6.53 Consider the operation of the circuit shown in Fig.P6.53 for VB at –1V, 0V, and +1V. Assume that β is very high. What values of VE and VC result? At what value of VB does the emitter current reduce to one-tenth of
dissipated in the circuit. For VCC = 5 V, design the circuit to obtain operation at a forced β as close to 10 as possible while limiting the power dissipation to no larger than 20 mW. Use 1% resistors (see Appendix J).
6.50 The pnp transistor in the circuit in Fig. P6.50 has β = 50. Show that the BJT is operating in the saturation mode and find βforced and VC . To what value should RB be increased in order for the transistor to operate at the edge of saturation?
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
CHAPTER 6 PROBLEMS
its value for VB = 0 V? For what value of VB is the transistor just at the edge of conduction? (vBE = 0.5 V) What values of VE and VC correspond? For what value of VB does the transistor reach the edge of saturation? What values of VC and VE correspond? Find the value of VB for which the transistor operates in saturation with a forced β of 2.
D 6.55 Consider the circuit in Fig. P6.51 with the base voltage VB obtained using a voltage divider across the 3-V supply. Assuming the transistor β to be very large (i.e., ignoring the base current), design the voltage divider to obtain VB = 1.2 V. Design for a 0.1-mA current in the voltage divider. Now, if the BJT β = 100, analyze the circuit to determine the collector current and the collector voltage.
6.56 A single measurement indicates the emitter voltage of
3V
1k
VC
VE
the transistor in the circuit of Fig. P5.56 to be 1.0 V. Under
Problems 361
theassumptionthatV =0.7V,whatareV ,I ,I ,I ,V , BE BBECC
VB
β, and α ? (Note: Isn’t it surprising what a little measurement can lead to?)
1k
3V
3V
5k
VE
VC
Figure P6.53
VB
6.54 ForthetransistorshowninFig.P6.54,assumeα≃1and vBE = 0.5 V at the edge of conduction. What are the values of VE and VC for VB =0V? For what value of VB does the transistor cut off? Saturate? In each case, what values of VE andVC result?
50 k
+5 V
4 mA
2 mA
–5 V
5k
3V
Figure P6.56
VC
VE
1k
D 6.57 Design a circuit using a pnp transistor for which α ≃ 1 using two resistors connected appropriately to ±3 V sothatIE=0.5mAandVBC=1V.Whatexactvalues of RE and RC would be needed? Now, consult a table of standard 5% resistor values (e.g., that provided in Appendix J) to select suitable practical values. What values of resistors have you chosen? What are the values of IE and VBC that result?
6.58 In the circuit shown in Fig. P6.58, the transistor has β=40. Find the values of VB, VE, and VC. If RB is raised to 100 k, what voltages result? With RB = 100 k, what value of β would return the voltages to the values first calculated?
1k
VB
Figure P6.54
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
362
Chapter 6
Bipolar Junction Transistors (BJTs)
3V
RE
2.2 k
VE
VC
6.61 ForthecircuitsinFig.P6.61,findvaluesforthelabeled node voltages and branch currents. Assume β to be very high.
VB
RB
20 k
Figure P6.58
RC
2.2 k
3V
3V
3.6 k
V1 0.5 mA
3V
3.6 k
I4 4.7 k
3V
V3
V2
CHAPTER 6 PROBLEMS
43 k
6.59 In the circuit shown in Fig. P6.58, the transistor has β=50. Find the values of VB, VE, and VC, and verify that the transistor is operating in the active mode. What is the largest value that RC can have while the transistor remains in the active mode?
6.60 ForthecircuitinFig.P6.60,findVB,VE,andVC forRB =100k,10k,and1k.Letβ=100.
Figure P6.60
(a)
3V
3.6 k
V7
V5 4.7 k
(b)
3 V
43 k
V6
0.75 V
110 k
6.2 k
V8
V9 10 k
3 V
(d)
3V (c)
Figure P6.61
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
3V
180 k
V10
300 k
3V (e)
Figure P6.61 continued
*6.62 Repeat the analysis of the circuits in Problem 6.61
using β = 100. Find all the labeled node voltages and branch currents.
D **6.63 It is required to design the circuit in Fig. P6.63 so that a current of 1 mA is established in the emitter and a voltage of −1 V appears at the collector. The transistor type used has a nominal β of 100. However, the β value can be as low as 50 and as high as 150. Your design should ensure that the specified emitter current is obtained when β=100 and that at the extreme values of β the emitter current does not change by more than 10% of its nominal value. Also, design for as large a value for RB as possible. Give the values of RB, RE , and RC to the nearest kilohm. What is the expected range of collector current and collector voltage corresponding to the full range of β values?
D 6.64 The pnp transistor in the circuit of Fig. P6.64 has β =50. Find the value for RC to obtain VC = +2 V. What happens if the transistor is replaced with another
Problems 363
CHAPTER 6 PROBLEMS
6.2 k
V11
V12 10 k
having case.
β = 100?
Give the
3V
value of VC
in the
latter
Figure P6.64
***6.65 Consider
the circuit
shown in
Fig. P6.65. It
resembles that in Fig. 6.30 but includes other features. First,
note diodes D1 and D2 are included to make design (and
analysis) easier and to provide temperature compensation
for the emitter–base voltages of Q1 and Q2. Second, note
resistor R, whose purpose is to provide negative feedback
(more on this later in the book!). Using V and V = 0.7 V
BE D independent of current, and β =∞, find the voltages VB1, VE1,
VC1, VB2, VE2, and VC2, initially with R open-circuited and then with R connected. Repeat for β = 100, with R open-circuited initially, then connected.
+ 5V
C
– 5V
9V
2k
100
80 k
D2
E Q2
D1 40 k
Figure P6.65
Q1
R
2k
2 k 100
Figure P6.63
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
364 Chapter 6 Bipolar Junction Transistors (BJTs) *6.66 For the circuit shown in Fig. P6.66, find the labeled
are 0.5 mA, 0.5 mA, and 1 mA, respectively, and V3 = 0, V5 = −2 V, and V7 = 1 V. For each resistor, select the nearest standard value utilizing the table of standard values for 5% resistors in Appendix J. Now, for β = 100, find the values of V3, V4, V5, V6, and V7.
*6.68 For the circuit in Fig. P6.68, find VB and VE for vI = 0V, +2V, –2.5V, and –5V. The BJTs have β=50.
node voltages for: (a) β = ∞
(b) β = 100
V1 100 k
3V
9.1 k
V2
5.1 k
Q1
Q2
V5
2.5 V
CHAPTER 6 PROBLEMS
V3
9.1 k
3V
V4 4.3 k
Figure P6.66
β = ∞, design the 5V
R3 R2
Q2
D *6.67 Using
Fig.P6.67 so that the emitter currents of Q1, Q2, and Q3
circuit
shown in
2.5 V
Figure P6.68
R5 V4
**6.69 All the transistors in the circuits of Fig. P6.69 are specified to have a minimum β of 50. Find approximate values for the collector voltages and calculate forced β for each of the transistors. (Hint: Initially, assume all transistors are operating in saturation, and verify the assumption.)
Q V3
1 Q3
V7
V6
V2
V5 R4
5V
R1
R6
Figure P6.67
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
Problems 365
5V
CHAPTER 6 PROBLEMS
Figure P6.69
5V
5V
5V
20
CHAPTER 7
Transistor Amplifiers
Introduction 367
7.1 Basic Principles 368
7.2 Small-Signal Operation and Models
7.3 Basic Configurations 423
7.4 Biasing 454
383
7.5
Discrete-Circuit Amplifiers 467 Summary 479
Problems 480
IN THIS CHAPTER YOU WILL LEARN
1. How the transistor (a MOSFET or a BJT) can be used to make an amplifier.
2. How to obtain linear amplification from the fundamentally nonlinear MOS and bipolar
transistor.
3. How to model the linear operation of a transistor around a bias point by an equivalent circuit that can be used in the analysis and design of transistor amplifiers.
4. The three basic ways to connect a MOSFET or a BJT to construct amplifiers with different properties.
5. Practical circuits for MOS and bipolar transistor amplifiers that can be constructed using discrete components.
Introduction
Having studied the two major transistor types, the MOSFET (Chapter5) and the BJT (Chapter 6), we now begin the study of their application. There are two distinctly different kinds of transistor application: as a switch, in the design of digital circuits (Chapters 14–16) and as a controlled source, in the design of amplifiers for analog circuits. This chapter and the subsequent six focus on the latter application, namely, the use of the transistor in the design of a variety of amplifier types.
Since the basic principles that underlie the use of the MOSFET and the BJT in amplifier design are the same, the two devices are studied together in this chapter. Besides providing some economy in presentation, this unified study enables us to make important comparisons between MOS and bipolar amplifiers.
The bulk of this chapter is concerned with the fundamental principles and concepts that are the basis for the application of transistors in amplifier design: We study in detail the models that are used to represent both transistor types in the analysis and design of small-signal linear amplifiers. We also study the three basic configurations in which each of the two transistor types can be connected to realize an amplifier.
The chapter concludes with examples of discrete-circuit amplifiers. These are circuits that can be assembled using discrete transistors, resistors, and capacitors on printed-circuit boards (PCBs). They predominantly use BJTs, and their design differs in significant ways from the design of integrated-circuit (IC) amplifiers. The latter predominantly use MOSFETs, and their study begins in Chapter 8. However, the fundamental principles and concepts introduced in this chapter apply equally well to both discrete and integrated amplifiers.
367
368 Chapter 7
Transistor Amplifiers
7.1 Basic Principles
7.1.1 The Basis for Amplifier Operation
The basis for the application of the transistor (a MOSFET or a BJT) in amplifier design is that when the device is operated in the active region, a voltage-controlled current source is realized. Specifically, when a MOSFET is operated in the saturation or pinch-off region, also referred to in this chapter as the active region, the voltage between gate and source, vGS, controls the drain current iD according to the square-law relationship which, for an NMOS transistor, is expressed as
iD = 1kn(vGS −Vtn)2 (7.1) 2
We note that in this first-order model of MOSFET operation, the drain current iD does not depend on the drain voltage vDS because the channel is pinched off at the drain end,1 thus “isolating” the drain.
Similarly,whenaBJTisoperatedintheactiveregion,thebase-emittervoltagevBE controls thecollectorcurrentiC accordingtotheexponentialrelationshipwhich,forannpntransistor, is expressed as
iC =ISevBE/VT (7.2)
Here, this first-order model of BJT operation indicates that the collector current iC does not dependonthecollectorvoltagevCE becausethecollector–basejunctionisreversebiased,thus “isolating” the collector.
Figure 7.1 shows an NMOS transistor and an npn transistor operating in the active mode. ObservethatfortheNMOStransistor,thepinch-offconditionisensuredbykeepingvDS ≥vOV. Since the overdrive voltage vOV = vGS − Vtn , this condition implies that vGD ≤ Vtn , which indeed ensures channel pinch-off at the drain end.
Similarly, for the npn transistor in Fig. 7.1(b), the CBJ reverse-bias condition is ensured by keeping vCE ≥ 0.3 V. Since vBE is usually in the vicinity of 0.7 V, vBC is thus kept
vGD≤Vtn Channel pinched off
at drain
i vBC ≤0.4V i DC
CBJ reverse biased
vDS ≥vOV
vCE ≥0.3V
vGS =Vtn vOV
iD = 12 kn (vGS –Vtn)2
(a)
vBE
iC =IS evBE/VT
(b)
Figure 7.1 Operating (a) an NMOS transistor and (b) an npn transistor in the active mode. Note that vGS = Vtn + vOV and vDS ≥ vOV ; thus vGD ≤ Vtn , which ensures channel pinch-off at the drain end. Similarly, vBE ≃ 0.7 V, and vCE ≥ 0.3 V results in vBC ≤ 0.4 V, which is sufficient to keep the CBJ from conducting.
1To focus on essentials, we shall neglect the Early effect until a later point.
smaller than 0.4 V, which is sufficient to prevent this relatively large-area junction from conducting.
Although we used NMOS and npn transistors to illustrate the conditions for active-mode operation, similar conditions apply for PMOS and pnp transistors, as studied in Chapters 5 and 6, respectively.
Finally, we note that the control relationships in Eqs. (7.1) and (7.2) are nonlinear. Nevertheless, we shall shortly devise a technique for obtaining almost-linear amplification from these fundamentally nonlinear devices.
7.1.2 Obtaining a Voltage Amplifier
From the above we see that the transistor is basically a transconductance amplifier: that is, an amplifier whose input signal is a voltage and whose output signal is a current. More commonly, however, one is interested in voltage amplifiers. A simple way to convert a transconductance amplifier to a voltage amplifier is to pass the output current through a resistor and take the voltage across the resistor as the output. Doing this for a MOSFET results in the simple amplifier circuit shown in Fig. 7.2(a). Here vGS is the input voltage, RD (known as a load resistance) converts the drain current iD to a voltage (iDRD), and VDD is the supply voltage that powers up the amplifier and, together with RD, establishes operation in the active region, as will be shown shortly.
In the amplifier circuit of Fig. 7.2(a) the output voltage is taken between the drain and ground, rather than simply across RD . This is done because of the need to maintain a common ground reference between the input and the output. The output voltage vDS is given by
vDS =VDD −iDRD (7.3)
Thusitisaninvertedversion(notetheminussign)ofiDRD thatisshiftedbytheconstantvalue of the supply voltage VDD.
An exactly similar arrangement applies for the BJT amplifier, as illustrated in Fig. 7.2(c). HeretheoutputvoltagevCE isgivenby
vCE =VCC −iCRC
Cut- Saturation
(7.4)
7.1 Basic Principles 369
off A
or Active region
Triode
B
iD
+
vO=vDS –
VDSB
C
0 Vt
(a)
(b)
Figure 7.2 (a) An NMOS amplifier and (b) its VTC; and (c) an npn amplifier and (d) its VTC.
370 Chapter 7
Transistor Amplifiers
VCC
vCE VCC
0.3 V 0
Active mode
Cutoff
Saturation
Edge
of saturation
B
A
iC
RC
vBE
0.5 V
vBE
Figure 7.2 continued
(c)
(d)
7.1.3 The Voltage-Transfer Characteristic (VTC)
A useful tool that provides insight into the operation of an amplifier circuit is its voltage-transfer characteristic (VTC). This is simply a plot (or a clearly labeled sketch) of the output voltage versus the input voltage. For the MOS amplifier in Fig. 7.2(a), this is the plot ofvDS versusvGS showninFig.7.2(b).
Observe that for vGS < Vt , the transistor is cut off, iD = 0 and, from Eq. (7.3), vDS = VDD . AsvGS exceedsVt,thetransistorturnsonandvDS decreases.However,sinceinitiallyvDS is still high, the MOSFET will be operating in saturation or the active region. This continues as vGS is increased until the value of vGS is reached that results in vDS becoming lower than vGS by Vt volts [point B on the VTC in Fig. 7.2(b)]. For vGS greater than that at point B, the transistor operates in the triode region and vDS decreases more slowly.
The VTC in Fig. 7.2(b) indicates that the segment of greatest slope (hence potentially the largest amplifier gain) is that labeled AB, which corresponds to operation in the active region. When a MOSFET is operated as an amplifier, its operating point is confined to the segment AB at all times. An expression for the segment AB can be obtained by substituting for iD in Eq. (7.3) by its active-region value from Eq. (7.1), thus
vDS = VDD − 1 kn RD (vGS − Vt )2 (7.5) 2
This is obviously a nonlinear relationship. Nevertheless, linear (or almost-linear) amplification can be obtained by using the technique of biasing the MOSFET. Before considering biasing, however, it is useful to determine the coordinates of point B, which is at the boundary between the saturation and the triode regions of operation. These can be obtained by substituting in Eq.(7.5),v =V andv =V =V −V.Theresultis
2kRV +1−1
VGS=Vt+ n D DD (7.6)
GS GSB DS DSB GSB t
BkR nD
Point B can be alternatively characterized by the overdrive voltage
and
EXERCISE
2kRV +1−1 VOV ≡VGS −Vt = n D DD
(7.7)
(7.8)
7.1 Basic Principles 371
BBkR nD
V =V DS B OV B
7.1 Consider the amplifier of Fig. 7.2(a) with VDD = 1.8 V, RD = 17.5 k, and with a MOSFET specified to have V = 0.4 V, k = 4 mA/V2, and λ = 0. Determine the coordinates of the end points of the
tn active-region segment of the VTC. Also, determine V assuming V = V .
DSC Ans. A:0.4V,1.8V;B:0.613V,0.213V;VDS C =18mV
GSC DD
An exactly similar development applies to the BJT case. This is illustrated in Fig. 7.2(c) and (d). In this case, over the active-region or amplifier segment AB, the output voltage vCE isrelatedtotheinputvoltagevBE by
vCE = VCC − RC IS evBE /VT (7.9) Here also, the input–output relationship is nonlinear. Nevertheless, linear (or almost-linear)
amplification can be obtained by using the biasing technique discussed next.
7.1.4 Obtaining Linear Amplification by Biasing the Transistor
Biasing enables us to obtain almost-linear amplification from the MOSFET and the BJT. The technique is illustrated for the MOSFET case in Fig. 7.3(a). A dc voltage VGS is selected to obtain operation at a point Q on the segment AB of the VTC. How to select an appropriate location for the bias point Q will be discussed shortly. For the time being, observe that the coordinatesofQarethedcvoltagesVGS andVDS,whicharerelatedby
VDS = VDD − 1 kn RD (VGS − Vt )2 (7.10) 2
Point Q is known as the bias point or the dc operating point. Also, since at Q no signal component is present, it is also known as the quiescent point (which is the origin of the symbol Q).
Next, the signal to be amplified, vgs, a function of time t, is superimposed on the bias voltageVGS,asshowninFig.7.4(a).ThusthetotalinstantaneousvalueofvGS becomes
vGS(t)=VGS +vgs(t)
The resulting vDS (t) can be obtained by substituting for vGS (t) into Eq. (7.5). Graphically, we can use the VTC to obtain vDS (t) point by point, as illustrated in Fig. 7.4(b). Here we show
372 Chapter 7
Transistor Amplifiers
+
VGS
VDD
ID RD
+
VDS
–
vDS
A
VDD
VDS Q B
–
(a)
the case of vgs being a triangular wave of “small” amplitude. Specifically, the amplitude of vgs is small enough to restrict the excursion of the instantaneous operating point to a short, almost-linear segment of the VTC around the bias point Q. The shorter the segment, the greater the linearity achieved, and the closer to an ideal triangular wave the signal component at the output, vds, will be. This is the essence of obtaining linear amplification from the nonlinear MOSFET.
Before leaving Fig. 7.4(b) we wish to draw the reader’s attention to the consequence of increasing the amplitude of the signal vgs . As the instantaneous operating point will no longer be confined to the almost-linear segment of the VTC, the output signal vds will deviate from its ideal triangular shape; that is, it will exhibit nonlinear distortion. Worse yet, if the input signal amplitude becomes sufficiently large, the instantaneous operating point may leave the segment AB altogether. If this happens at the negative peaks of vgs, the transistor will cut off for a portion of the cycle and the positive peaks of vds will be “clipped off.” If it occurs at the positive peaks of vgs, the transistor will enter the triode region for a portion of the cycle, and the negative peaks of vds will become flattened. It follows that the selection of the location of the bias point Q can have a profound effect on the maximum allowable amplitude of vds, referred to as the allowable signal swing at the output. We will have more to say later on this important point.
An exactly parallel development can be applied to the BJT amplifier. In fact, all we need to do is replace the NMOS transistor in Figs. 7.3 and 7.4 with an npn transistor and change the voltage and current symbols to their BJT counterparts. The resulting bias point Q will be characterizedbydcvoltagesVBE andVCE,whicharerelatedby
C
VDD vGS Figure 7.3 Biasing the MOSFET amplifier at a point Q located on the segment AB of the VTC.
and a dc current IC ,
VCE = VCC − RC IS eVBE /VT
(7.11)
(7.12)
IC =ISeVBE/VT
Also, superimposing a small-signal vbe on the dc bias voltage VBE results in
vBE(t)=VBE +vbe(t)
0 Vt VGS
(b)
iD
VDD
RD
7.1 Basic Principles 373
vD S
vgs vGS
VGS
vDS VDD
A
(a)
Slope at Q = voltage gain vds
VDS
Q
Time
C
VDD vGS
Vt
B
vgs
Time
VGS
(b)
Figure 7.4 The MOSFET amplifier with a small time-varying signal vgs(t) superimposed on the dc bias voltage VGS . The MOSFET operates on a short almost-linear segment of the VTC around the bias point Q and providesanoutputvoltagevds =Avvgs.
374 Chapter 7
Transistor Amplifiers
which can be substituted into Eq. (7.9) to obtain the total instantaneous value of the output voltage vCE(t). Here again, almost-linear operation is obtained by keeping vbe small enough to restrict the excursion of the instantaneous operating point to a short, almost-linear segment of the VTC around the bias point Q. Similar comments also apply to the maximum allowable signal swing at the output.
7.1.5 The Small-Signal Voltage Gain
The MOSFET Case Consider the MOSFET amplifier in Fig. 7.4(a). If the input signal vgs is kept small, the corresponding signal at the output vds will be nearly proportional to vgs with the constant of proportionality being the slope of the almost-linear segment of the VTC around Q. This is the voltage gain of the amplifier, and its value can be determined by evaluating the slope of the tangent to the VTC at the bias point Q,
dv Av = DS
(7.13)
(7.14)
(7.15)
Utilizing Eq. (7.5) we obtain
Av =−kn(VGS −Vt)RD
which can be expressed in terms of the overdrive voltage at the bias point, VOV , as
Av =−knVOVRD
We make the following observations on this expression for the voltage gain.
dvGS vGS=VGS
1. The gain is negative, which signifies that the amplifier is inverting; that is, there is a 180° phase shift between the input and the output. This inversion is obvious in Fig. 7.4(b) and should have been anticipated from Eq. (7.5).
2. The gain is proportional to the load resistance RD, to the transistor transconductance parameter kn , and to the overdrive voltage VOV . This all makes intuitive sense.
AnothersimpleandinsightfulexpressionforthevoltagegainAv canbederivedbyrecalling thatthedccurrentinthedrainatthebiaspointisrelatedtoVOV by
I =1kV2 D 2nOV
This equation can be combined with Eq. (7.15) to obtain
VOV /2. It can be expressed in the alternative form
Av =−VDD −VDS (7.17)
VOV/2
Since the maximum slope of the VTC in Fig. 7.4(b) occurs at point B, the maximum gain
magnitude |Av max | is obtained by biasing the transistor at point B, V −V
Av =−IDRD VOV/2
(7.16) That is, the gain is simply the ratio of the dc voltage drop across the load resistance RD to
|A |=DD DSB
v max
VOVB/2
and since V = V , DS B OV B
V −V |A |=DD OVB
biasing at B would leave no room for negative signal swing at the output. Nevertheless, the
result in Eq. (7.18) is valuable as it provides an upper bound on the magnitude of voltage gain
achievable from this basic amplifier circuit. As an example, for a discrete-circuit amplifier
operated with V = 5 V and V = 0.5 V, the maximum achievable gain is 18 V/V. An DD OV B
integrated-circuit amplifier utilizing a modern submicron MOSFET operated with V = 1.3 V
and with V OV B
DD
= 0.2 V realizes a maximum gain of 11 V/V.
Finally, note that to maximize the gain, the bias point Q should be as close to point B as
possible, consistent with the required signal swing at the output. This point will be explored further in the end-of-chapter problems.
Example 7.1
Consider the amplifier circuit shown in Fig. 7.4(a). The transistor is specified to have Vt = 0.4 V, kn′ = 0.4mA/V2,W/L=10,andλ=0.Also,letVDD =1.8V,RD =17.5k,andVGS =0.6V.
(a) Forvgs =0(andhencevds =0),findVOV,ID,VDS,andAv.
(b) What is the maximum symmetrical signal swing allowed at the drain? Hence, find the maximum
allowable amplitude of a sinusoidal vgs.
Solution
(a) WithVGS =0.6V,VOV =0.6−0.4=0.2V.Thus,
I=1k′ WV2 D 2n L OV
= 1 ×0.4×10×0.22 =0.08mA 2
VDS =VDD −RDID
= 1.8 − 17.5 × 0.08 = 0.4 V
SinceVDS isgreaterthanVOV,thetransistorisindeedoperatinginsaturation.Thevoltagegaincanbe found from Eq. (7.15),
Av =−knVOVRD =−0.4×10×0.2×17.5 = −14 V/V
An identical result can be found using Eq. (7.17).
(b) Since VOV = 0.2 V and VDS = 0.4 V, we see that the maximum allowable negative signal swing at
the drain is 0.2 V. In the positive direction, a swing of +0.2 V would not cause the transistor to
7.1 BasicPrinciples 375
where V
OV B
is given by Eq. (7.7). Of course, this result is only of theoretical importance since
v max
VOVB/2
(7.18)
376 Chapter 7 Transistor Amplifiers
Example 7.1 continued
cutoff(sincetheresultingvDS wouldbestilllowerthanVDD)andthusisallowed.Thusthemaximum symmetrical signal swing allowable at the drain is ±0.2 V. The corresponding amplitude of vgs can be found from
vˆgs = vˆds = 0.2V =14.2mV |Av | 14
Since vˆgs ≪ VOV , the operation will be reasonably linear (more on this in later sections).
Greater insight into the issue of allowable signal swing can be obtained by examining the signal waveforms shown in Fig. 7.5. Note that for the MOSFET to remain in saturation at the negative peak
of vds, we must ensure that that is,
which results in
vDSmin ≥ vGSmax − Vt 0.4−|Av|vˆgs ≥0.6+vˆgs −0.4
vˆgs ≤ 0.2 =13.3mV |Av | + 1
This result differs slightly from the one obtained earlier.
vGS
vgs
VGS Vt
vGSmax = VGS vˆgs
0t vDS vds
VDS
Figure7.5 SignalwaveformsatgateanddrainfortheamplifierinExample7.1.Notethattoensureoperation inthesaturationregionatalltimes,vDSmin ≥vGSmax−Vt.
vDSmin = VDS vˆds 0t
dvBE vBE =VBE Utilizing Eq. (7.9) together with Eq. (7.12), we obtain
dv Av = CE
7.1 Basic Principles 377
EXERCISE
D7.2 FortheamplifiercircuitstudiedinExample7.1,createtwoalternativedesigns,eachprovidingavoltage gain of −10 by (a) changing RD while keeping VOV constant and (b) changing VOV while keeping RD constant. For each design, specify VGS , ID , RD , and VDS .
Ans. (a) 0.6 V, 0.08 mA, 12.5 k, 0.8 V; (b) 0.54 V, 0.04 mA, 17.5 k, 1.1 V
The BJT Case A similar development can be used to obtain the small-signal voltage gain of the BJT amplifier shown in Fig. 7.6,
(7.19)
(7.20)
I Av=− C RC
VT
We make the following observations on this expression for the voltage gain:
1. The gain is negative, which signifies that the amplifier is inverting; that is, there is a 180° phase shift between the input and the output. This inversion should have been anticipated from Eq. (7.9).
2. The gain is proportional to the collector bias current IC and to the load resistance RC .
AdditionalinsightintothevoltagegainAv canbeobtainedbyexpressingEq.(7.20)as
Av =−ICRC VT
(7.21)
VCC
iC
RC
vCE
Figure 7.6 BJT amplifier biased at a point Q, with a small voltage signal v be superimposed on the dc bias voltage VBE . The resulting output signal vce appears superimposed on the dc collector voltage VCE. The amplitude of vce is larger than that of vbe by the voltage gain Av .
vbe
V vBE BE
378 Chapter 7
Transistor Amplifiers
Thatis,thegainistheratioofthedcvoltagedropacrosstheloadresistanceRC tothephysical constantVT (recallthatthethermalvoltageVT ≃25mVatroomtemperature).Thisrelationship is similar in form to that for the MOSFET (Eq. 7.16) except that here the denominator is a physical constant (VT ) rather than a design parameter (VOV /2). Usually, VOV /2 is larger than (VT ), thus we can obtain higher voltage gain from the BJT amplifier than from the MOSFET amplifier.Thisshouldnotbesurprising,astheexponentialiC–vBE relationshipismuchsteeper than the square-law relationship iD–vGS.
ThegainAv inEq.(7.21)canbeexpressedalternatelyas
Av =−VCC −VCE (7.22)
VT
from which we see that maximum gain is achieved when VCE is at its minimum value of
about 0.3 V,
|Av max | = VCC − 0.3 (7.23) VT
Here again, this is only a theoretical maximum, since biasing the BJT at the edge of saturation leaves no room for negative signal swing at the output. Equation (7.23) nevertheless provides an upper bound on the voltage gain achievable from the basic BJT amplifier. As an example, for VCC = 5 V, the maximum gain is 188 V/V, considerably larger than in the MOSFET case. For modern low-voltage technologies, a VCC of 1.3 V provides a gain of 40 V/V, again much larger than the MOSFET case. The reader should not, however, jump to the conclusion that the BJT is preferred to the MOSFET in the design of modern integrated-circuit amplifiers; in fact, the opposite is true, as we shall see in Chapter 8 and beyond.
Finally, we conclude from Eq. (7.22) that to maximize |Av | the transistor should be biased at the lowest possible VCE consistent with the desired value of negative signal swing at the output.
Example 7.2
Consider an amplifier circuit using a BJT having IS = 10−15 A, a collector resistance RC = 6.8 k, and a power supply VCC = 10 V.
(a) Determine the value of the bias voltage VBE required to operate the transistor at VCE = 3.2 V. What is the corresponding value of IC ?
(b) Find the voltage gain Av at this bias point. If an input sine-wave signal of 5-mV peak amplitude is superimposed on VBE , find the amplitude of the output sine-wave signal (assume linear operation).
(c) Find the positive increment in vBE (above VBE ) that drives the transistor to the edge of saturation, where vCE = 0.3 V.
(d) Find the negative increment in vBE that drives the transistor to within 1% of cutoff (i.e.,tovCE =0.99VCC).
Solution
(a)
(b)
(c) ForvCE =0.3V,
VBE =690.8mV
Av =−VCC −VCE VT
= 10−3.2 =−272V/V 0.025
vˆce =272×0.005=1.36V
iC = 10−0.3 =1.617mA 6.8
IC = VCC −VCE RC
= 10−3.2 =1mA 6.8
7.1 Basic Principles 379
ThevalueofVBE canbedeterminedfrom
1 × 10−3 = 10−15 eVBE /VT
which results in
ToincreaseiC from1mAto1.617mA,vBE mustbeincreasedby
(d) For vCE = 0.99VCC = 9.9 V,
△vBE = VT ln 1.617 1
= 12 mV
iC = 10−9.9 =0.0147mA 6.8
TodecreaseiC from1mAto0.0147mA,vBE mustchangeby
△vBE = VT ln 0.0147 1
= −105.5 mV
380 Chapter 7 Transistor Amplifiers
EXERCISE
7.3 For the situation described in Example 7.2, while keeping IC unchanged at 1 mA, find the value of RC that will result in a voltage gain of −320 V/V. What is the largest negative signal swing allowed at the output (assume that vCE is not to decrease below 0.3 V)? What (approximately) is the corresponding input signal amplitude? (Assume linear operation.)
Ans. 8 k; 1.7 V; 5.3 mV
7.1.6 Determining the VTC by Graphical Analysis
Figure 7.7 shows a graphical method for determining the VTC of the amplifier of Fig. 7.4(a). Although graphical analysis of transistor circuits is rarely employed in practice, it is useful to us at this stage for gaining greater insight into circuit operation, especially in answering the question of where to locate the bias point Q.
The graphical analysis is based on the observation that for each value of vGS , the circuit will be operating at the point of intersection of the iD−vDS graph corresponding to the particular
Figure 7.7 Graphical construction to determine the voltage-transfer characteristic of the amplifier in Fig. 7.4(a).
0
VDD RD
vGS ≤Vt (a)
VDD RD
vDS = VDSC rDS
vGS =VDD (b)
vDS = VDD
7.1 Basic Principles 381
Figure 7.8 Operation of the MOSFET in Fig. 7.4(a) as a switch: (a) open, corre- sponding to point A in Fig. 7.7; (b) closed, corresponding to point C in Fig. 7.7. The closure resistance is approximately equal to rDS because VDS is usually very small.
value of vGS and the straight line representing Eq. (7.3), which can be rewritten in the form iD = VDD − 1 vDS (7.24)
RD RD
The straight line representing this relationship is superimposed on the iD−vDS characteristics in Fig. 7.7. It intersects the horizontal axis at vDS = VDD and has a slope of −1/RD . Since this straight line represents in effect the load resistance RD, it is called the load line. The VTC is then determined point by point. Note that we have labeled four important points: point A at which vGS = Vt , point Q at which the MOSFET can be biased for amplifier operation (vGS = VGS and vDS = VDS ), point B at which the MOSFET leaves saturation and enters the triode region, and point C, which is deep into the triode region and for which vGS = VDD . If the MOSFET is to be used as a switch, then operating points A and C are applicable: At A the transistor is off (open switch), and at C the transistor operates as a low-valued resistance rDS andhasasmallvoltagedrop(closedswitch).TheincrementalresistanceatpointCisalso known as the closure resistance. The operation of the MOSFET as a switch is illustrated in Fig. 7.8. A detailed study of the application of the MOSFET as a switch is undertaken in Chapter 14, dealing with CMOS digital logic circuits.
The graphical analysis method above can be applied to determine the VTC of the BJT amplifier in Fig. 7.2(c). Here point A, Fig. 7.2(d), corresponds to the BJT just turning on (vBE ≃ 0.5 V) and point B corresponds to the BJT leaving the active region and entering the saturation region. If the BJT is to be operated as a switch, the two modes of operation are cutoff (open switch) and saturation (closed switch). As discussed in Section 6.2, in saturation, the BJT has a small closure resistance RCEsat as well as an offset voltage. More seriously, switching the BJT out of its saturation region can require a relatively long delay time to ensure the removal of the charge stored in the BJT base region. This phenomenon has made the BJT much less attractive in digital logic applications relative to the MOSFET.2
7.1.7 Deciding on a Location for the Bias Point Q
For the MOSFET amplifier, the bias point Q is determined by the value of VGS and that of the load resistance RD. Two important considerations in deciding on the location of Q
2 The only exception is a nonsaturating form of BJT logic circuits known as emitter-coupled logic (ECL).
382 Chapter 7
Transistor Amplifiers
iD
0
Q2
Figure 7.9 Two load lines and corresponding bias points. Bias point Q1 does not leave sufficient room for positive signal swing at the drain (too close to VDD). Bias point Q2 is too close to the boundary of the triode region and might not allow for sufficient negative signal swing.
are the required gain and the desired signal swing at the output. To illustrate, consider the VTC shown in Fig. 7.4(b). Here the value of RD is fixed and the only variable remaining is the value of VGS. Since the slope increases as we move closer to point B, we obtain higher gain by locating Q as close to B as possible. However, the closer Q is to the boundary point B, the smaller the allowable magnitude of negative signal swing. Thus, as often happens in engineering design, we encounter a situation requiring a trade-off. The answer here is relatively simple: For a given RD, locate Q as close to the triode region (point B) as possible to obtain high gain but sufficiently distant to allow for the required negative signal swing.
IndecidingonavalueforRD,itisusefultorefertotheiD−vDS plane.Figure7.9shows two load lines resulting in two extreme bias points: Point Q1 is too close to VDD, resulting in a severe constraint on the positive signal swing of vds. Exceeding the allowable positive maximum results in the positive peaks of the signal being clipped off, since the MOSFET will turn off for the part of each cycle near the positive peak. We speak of this situation by saying that the circuit does not have sufficient “headroom.” Similarly, point Q2 is too close to the boundary of the triode region, thus severely limiting the allowable negative signal swing of vds. Exceeding this limit would result in the transistor entering the triode region for part of each cycle near the negative peaks, resulting in a distorted output signal. In this situation we say that the circuit does not have sufficient “legroom.” We will have more to say on bias design in Section 7.4.
Finally, we note that exactly similar considerations apply to the case of the BJT amplifier.
Q1
vGS
VDD
VGS
vDS
7.2 Small-Signal Operation and Models 383 7.2 Small-Signal Operation and Models
In our study of the operation of the MOSFET and BJT amplifiers in Section 7.1 we learned that linear amplification can be obtained by biasing the transistor to operate in the active region and by keeping the input signal small. In this section, we explore the small-signal operation in greater detail.
7.2.1 The MOSFET Case
Consider the conceptual amplifier circuit shown in Fig. 7.10. Here the MOS transistor is biased by applying a dc voltage3 VGS, and the input signal to be amplified, vgs, is superimposed on the dc bias voltage VGS . The output voltage is taken at the drain.
The DC Bias Point The dc bias current ID can be found by setting the signal vgs to zero; thus,
I =1k(V −V)2=1kV2 (7.25) D2nGS t 2nOV
where we have neglected channel-length modulation (i.e., we have assumed λ = 0). Here VOV = VGS − Vt is the overdrive voltage at which the MOSFET is biased to operate. The dc voltage at the drain, VDS , will be
VDS =VDD −RDID (7.26) To ensure saturation-region operation, we must have
VDS >VOV
Furthermore, since the total voltage at the drain will have a signal component superimposed on VDS, VDS has to be sufficiently greater than VOV to allow for the required negative signal swing.
VDD
iD RD
vDS
vgs vGS VGS
Figure 7.10
Conceptual circuit utilized to study the operation of the MOSFET as a small-signal amplifier.
3 Practical biasing arrangements will be studied in Section 7.4.
384 Chapter 7
Transistor Amplifiers
The Signal Current in the Drain Terminal Next, consider the situation with the input signal vgs applied. The total instantaneous gate-to-source voltage will be
vGS =VGS +vgs resulting in a total instantaneous drain current iD,
i =1kV +v −V2 D 2n GS gs t
= 1kn(VGS −Vt)2 +kn(VGS −Vt)vgs + 1knv2gs 22
(7.27)
(7.28)
The first term on the right-hand side of Eq. (7.28) can be recognized as the dc bias current ID (Eq. 7.25). The second term represents a current component that is directly proportional to the input signal vgs. The third term is a current component that is proportional to the square of the input signal. This last component is undesirable because it represents nonlinear distortion. To reduce the nonlinear distortion introduced by the MOSFET, the input signal should be kept small so that
resulting in
or, equivalently,
1knv2gs ≪kn(VGS −Vt)vgs 2
vgs ≪2(VGS −Vt) vgs ≪ 2VOV
(7.29)
(7.30) If this small-signal condition is satisfied, we may neglect the last term in Eq. (7.28) and
express iD as
where
iD ≃ ID + id
id =kn(VGS −Vt)vgs
(7.31)
(7.32)
The parameter that relates id and vgs is the MOSFET transconductance gm,
g ≡ id =k(V −V) m vgs n GS t
or in terms of the overdrive voltage VOV ,
gm =knVOV
amplifier. Note that gm is equal to the slope of the iD–vGS characteristic at the bias point,
∂i
gm≡ D (7.34)
This is the formal definition of gm, which can be shown to yield the expressions given in Eqs. (7.32) and (7.33).
(7.33) Figure 7.11 presents a graphical interpretation of the small-signal operation of the MOSFET
∂vGS vGS=VGS
7.2 Small-Signal Operation and Models 385
An almost-line-ar segment
Q
VOV
VGS
0
The Voltage Gain Returning to the circuit of Fig.7.10, we can express the total instantaneous drain voltage vDS as follows:
vDS =VDD −RDiD Under the small-signal condition, we have
vDS =VDD −RD(ID +id)
which can be rewritten as
vDS =VDS −RDid Thus the signal component of the drain voltage is
vds =−idRD =−gmvgsRD which indicates that the voltage gain is given by
A ≡vds =−g R vvgs mD
(7.35)
(7.36)
Figure 7.11 Small-signal operation of the MOSFET amplifier.
The minus sign in Eq. (7.36) indicates that the output signal vds is 180° out of phase with respect to the input signal vgs. This is illustrated in Fig. 7.12, which shows vGS and vDS. The input signal is assumed to have a triangular waveform with an amplitude much smaller than 2(VGS –Vt),thesmall-signalconditioninEq.(7.29),toensurelinearoperation.Foroperation in the saturation (active) region at all times, the minimum value of vDS should not fall below the corresponding value of vGS by more than Vt. Also, the maximum value of vDS should be
386 Chapter 7
Transistor Amplifiers
vGS
V
V
2
2(VGS Vt)
VGS
vGS
0t
vDS
vDSmax ≤VDD
(gmRD)V
VDS
vDSmin ≥vGSmaxVt
0t Figure 7.12 Total instantaneous voltages vGS and vDS for the circuit in Fig. 7.10.
smaller than VDD; otherwise the FET will enter the cutoff region and the peaks of the output signal waveform will be clipped off.
Finally, we note that by substituting for gm from Eq. (7.33) the voltage-gain expression in Eq. (7.36) becomes identical to that derived in Section 7.1—namely, Eq. (7.15).
Separating the DC Analysis and the Signal Analysis From the preceding analysis, we see that under the small-signal approximation, signal quantities are superimposed on dc quantities.Forinstance,thetotaldraincurrentiD equalsthedccurrentID plusthesignalcurrent id , the total drain voltage v DS = VDS + v ds , and so on. It follows that the analysis and design can be greatly simplified by separating dc or bias calculations from small-signal calculations. That is, once a stable dc operating point has been established and all dc quantities calculated, we may then perform signal analysis ignoring dc quantities.
Small-Signal Equivalent-Circuit Models From a signal point of view, the FET behaves as a voltage-controlled current source. It accepts a signal vgs between gate and source and provides a current gmvgs at the drain terminal. The input resistance of this controlled source is very high—ideally, infinite. The output resistance—that is, the resistance looking into the
7.2 Small-Signal Operation and Models 387 GDGD
SS
(a) (b)
Figure 7.13 Small-signal models for the MOSFET: (a) neglecting the dependence of iD on vDS in the active
vgs gmvgs
vgs gmvgs ro
region (the channel-length modulation effect) and (b) including the effect of channel-length modulation,
modeled by output resistance r = V /I . These models apply equally well for both NMOS and PMOS oAD
transistors.
drain—also is high, and we have assumed it to be infinite thus far. Putting all of this together, we arrive at the circuit in Fig. 7.13(a), which represents the small-signal operation of the MOSFET and is thus a small-signal model or a small-signal equivalent circuit.
In the analysis of a MOSFET amplifier circuit, the transistor can be replaced by the equivalent-circuit model shown in Fig. 7.13(a). The rest of the circuit remains unchanged except that ideal constant dc voltage sources are replaced by short circuits. This is a result of the fact that the voltage across an ideal constant dc voltage source does not change, and thus there will always be a zero voltage signal across a constant dc voltage source. A dual statement applies for constant dc current sources; namely, the signal current of an ideal constant dc current source will always be zero, and thus an ideal constant dc current source can be replaced by an open circuit in the small-signal equivalent circuit of the amplifier. The circuit resulting can then be used to perform any required signal analysis, such as calculating voltage gain.
The most serious shortcoming of the small-signal model of Fig. 7.13(a) is that it assumes the drain current in saturation to be independent of the drain voltage. From our study of the MOSFET characteristics in saturation, we know that the drain current does in fact depend on vDS in a linear manner. Such dependence was modeled by a finite resistance ro between drain and source, whose value was given by Eq. (5.27) in Section 5.2.4, which we repeat here (with the prime on ID dropped) as
ro = |VA| (7.37) ID
where VA = 1/λ is a MOSFET parameter that either is specified or can be measured. It should be recalled that for a given process technology, VA is proportional to the MOSFET channel length.ThecurrentID isthevalueofthedcdraincurrentwithoutthechannel-lengthmodulation taken into account; that is,
I = 1k V2 (7.38) D 2nOV
Typically, ro is in the range of 10 k to 1000 k. It follows that the accuracy of the small-signal model can be improved by including ro in parallel with the controlled source, as shown in Fig. 7.13(b).
388 Chapter 7
Transistor Amplifiers
It is important to note that the small-signal model parameters gm and ro depend on the dc bias point of the MOSFET.
Returning to the amplifier of Fig. 7.10, we find that replacing the MOSFET with the small-signal model of Fig. 7.13(b) results in the voltage-gain expression
A =vds =−g (R ∥r) (7.39) v vgs m D o
Thus, the finite output resistance ro results in a reduction in the magnitude of the voltage gain. Although the analysis above is performed on an NMOS transistor, the results, and the equivalent-circuit models of Fig. 7.13, apply equally well to PMOS devices, except for using
|VGS|,|Vt|,|VOV|,and|VA|andreplacingkn withkp.
The Transconductance gm We shall now take a closer look at the MOSFET
transconductance given by Eq. (7.32), which we rewrite with kn = kn′ (W/L) as follows:
gm = kn′ (W/L)(VGS − Vt ) = kn′ (W/L)VOV (7.40)
This relationship indicates that gm is proportional to the process transconductance parameter kn′ = μnCox and to the W/L ratio of the MOS transistor; hence to obtain relatively large transconductance the device must be short and wide. We also observe that for a given device the transconductance is proportional to the overdrive voltage, VOV = VGS − Vt , the amount by which the bias voltage VGS exceeds the threshold voltage Vt . Note, however, that increasing gm by biasing the device at a larger VGS has the disadvantage of reducing the allowable voltage signal swing at the drain.
Another useful expression for gm can be obtained by substituting for VOV in Eq. (7.40) by 2ID/(kn′ (W/L)) [from Eq. (7.25)]:
√
gm=2kn′ W/LID (7.41)
This expression shows two things:
In contrast, as we shall see shortly, the transconductance of the bipolar junction transistor (BJT) is proportional to the bias current and is independent of the physical size and geometry of the device.
To gain some insight into the values of gm obtained in MOSFETs consider an integrated-circuit device operating at ID = 0.5 mA and having kn′ = 120 μA/V2 . Equation (7.41) shows that for W/L = 1, gm = 0.35 mA/V, whereas a device for which W/L = 100 has gm = 3.5 mA/V. In contrast, a BJT operating at a collector current of 0.5 mA has gm = 20 mA/V.
Yet another useful expression for gm of the MOSFET can be obtained by substituting for kn′ (W/L) in Eq. (7.40) by 2ID /(VGS – Vt )2 :
gm = 2ID = 2ID (7.42) VGS −Vt VOV
1. For a given MOSFET, g
2. At a given bias current, gm is proportional to
m
√
is proportional to the square root of the dc bias current.
W/L.
iD
ID
Q
Slope ID
g m = 12 V O V
7.2 Small-SignalOperationandModels 389
0 1 V 2 VOV
OV
v
OV
Figure 7.14 The slope of the tangent at the bias point Q intersects the vOV axis at
1V .Thus,g =I /(1V ). 2OV mD2OV
A convenient graphical construction that clearly illustrates this relationship is shown in Fig. 7.14.
In summary, there are three different relationships for determining gm —Eqs. (7.40), (7.41), and (7.42)—and there are three design parameters—(W/L), VOV , and ID, any two of which can be chosen independently. That is, the designer may choose to operate the MOSFET with a certain overdrive voltage VOV and at a particular current ID; the required W/L ratio can then be found and the resulting gm determined.4
Example 7.3
Figure 7.15(a) shows a discrete MOSFET amplifier utilizing a drain-to-gate resistance RG for biasing purposes. Such a biasing arrangement will be studied in Section 7.4. The input signal vi is coupled to the gate via a large capacitor, and the output signal at the drain is coupled to the load resistance RL via another large capacitor. We wish to analyze this amplifier circuit to determine its small-signal voltage gain, its input resistance, and the largest allowable input signal. The transistor has Vt = 1.5 V, kn′ (W/L) = 0.25 mA/V2 , and VA = 50 V. Assume the coupling capacitors to be sufficiently large so as to act as short circuits at the signal frequencies of interest.
4 This assumes that the circuit designer is also designing the device, as is typically the case in IC design. On the other hand, a circuit designer working with a discrete-circuit MOSFET obviously does not have the freedom to change its W/L ratio. Thus, in this case there are only two design parameters—VOV and ID, and only one can be specified by the designer.
390
Chapter 7 Transistor Amplifiers
Example 7.3 continued
VDD =
(a)
VDD
ID
RD
VDS
(b)
IG = 0
RG
ID
VGS
(c)
Figure 7.15 Example 7.3: (a) amplifier circuit; (b) circuit for determining the dc operating point; (c) the amplifier small-signal equivalent circuit; (d) a simplified version of the circuit in (c).
ii
Rin= vi ii
RG
(ii−gmvgs)
7.2 Small-SignalOperationandModels 391
vgs =vi
vi
gmvgs
(d)
RL vo
RL = RL RD ro
Figure 7.15 continued
Solution
We first determine the dc operating point. For this purpose, we eliminate the input signal v i , and open-circuit the two coupling capacitors (since they block dc currents). The result is the circuit shown in Fig. 7.14(b). We note that since IG = 0, the dc voltage drop across RG will be zero, and
VGS =VDS =VDD −RDID (7.43) With VDS = VGS , the NMOS transistor will be operating in saturation. Thus,
I =1kV −V2 (7.44) D 2n GS t
where, for simplicity, we have neglected the effect of channel-length modulation on the dc operating point. Substituting VDD = 15 V, RD = 10 k, kn = 0.25 mA/V2 , and Vt = 1.5 V in Eqs. (7.43) and (7.44), and substitutingforVGS fromEq.(7.43)intoEq.(7.44)resultsinaquadraticequationinID.Solvingthelatter and discarding the root that is not physically meaningful yields the solution
which corresponds to
and
ID =1.06mA
VGS =VDS =4.4V
VOV =4.4−1.5=2.9V
Next we proceed with the small-signal analysis of the amplifier. Toward that end we replace the MOSFET with its small-signal model to obtain the small-signal equivalent circuit of the amplifier, shown in Fig. 7.15(c). Observe that we have replaced the coupling capacitors with short circuits. The dc voltage supply VDD has also been replaced with a short circuit to ground.
392
Chapter 7 Transistor Amplifiers
Example 7.3 continued
The values of the transistor small-signal parameters gm and ro can be determined by using the dc bias
quantities found above, as follows:
gm =knVOV
= 0.25 × 2.9 = 0.725 mA/V
ro=VA = 50 =47k ID 1.06
NextweusetheequivalentcircuitofFig.7.15(c)todeterminetheinputresistanceRin ≡vi/ii andthevoltage gainAv =vo/vi.Towardthatendwesimplifythecircuitbycombiningthethreeparallelresistancesro,RD, and RL in a single resistance RL′ ,
RL′ = RL ||RD ||ro
= 10||10||47 = 4.52 k
as shown in Fig. 7.15(d). For the latter circuit we can write the two equations
and
v =i −g v R′ o i m gs L
′ 1− 1/gmRG Av =−gmRL 1+R′ /R
LG
(7.45)
ii = vgs −vo RG
(7.46) Substituting for ii from Eq. (7.46) into Eq. (7.45) results in the following expression for the voltage gain
Av ≡vo/vi =vo/vgs:
Since RG is very large, gm RG ≫ 1 and RL′ /RG ≪ 1 (the reader can easily verify this), and the gain expression can be approximated as
Av ≃−gmRL′ (7.47) Substituting gm = 0.725 mA/V and RL′ = 4.52 k yields
Av =−3.3V/V
Toobtaintheinputresistance,wesubstituteinEq.(7.46)forvo =Avvgs =−gmRL′ vgs,thenuseRin ≡vi/ii = vgs/ii to obtain
R= RG (7.48) in 1 + gm RL′
This is an interesting relationship: The input resistance decreases as the gain gmRL′ is increased. The value of Rin can now be determined; it is
Rin = 10M =2.33M 1+3.3
which is still very large.
The largest allowable input signal vˆi is constrained by the need to keep the transistor in saturation at
all times; that is,
vDS ≥vGS −Vt EnforcingthisconditionwithequalityatthepointvGS ismaximumandvDS isminimum,wewrite
Since VDS = VGS , we obtain
vDSmin =vGSmax −Vt
V −A vˆ =V +vˆ −V
DS v i GS i t
Vt
vˆ i = A + 1
v
This is a general relationship that applies to this circuit irrespective of the component values. Observe that it simply states that the maximum signal swing is determined by the fact that the bias arrangement makes VD = VG and thus, to keep the MOSFET out of the triode region, the signal between D and G is constrained to be equal to Vt . For our particular design,
vˆi = 1.5 =0.35V 3.3+1
Since VOV = 2.9 V, a vi of 0.35 is indeed much smaller than 2VOV = 5.8 V; thus the assumption of linear operation is justified.
A modification of this circuit that increases the allowable signal swing is investigated in Problem 7.103.
EXERCISE
D7.4 Consider the amplifier circuit of Fig. 7.15(a) without the load resistance RL and with channel-length modulation neglected. Let VDD = 5 V, Vt = 0.7 V, and kn = 1 mA/V2. Find VOV , ID, RD, and RG to obtain a voltage gain of −25 V/V and an input resistance of 0.5 M . What is the maximum allowable input signal, vˆi?
Ans. 0.319 V; 50.9 μA; 78.5 k; 13 M; 27 mV
7.2 Small-SignalOperationandModels 393
394 Chapter 7
Transistor Amplifiers
The T Equivalent-Circuit Model Through a simple circuit transformation it is possible to develop an alternative equivalent-circuit model for the MOSFET. The development of such a model, known as the T model, is illustrated in Fig. 7.16. Figure 7.16(a) shows the equivalent circuitstudiedabovewithoutro.InFig.7.16(b)wehaveaddedasecondgmvgs currentsourcein series with the original controlled source. This addition obviously does not change the terminal currents and is thus allowed. The newly created circuit node, labeled X, is joined to the gate terminal G in Fig. 7.16(c). Observe that the gate current does not change—that is, it remains equal to zero—and thus this connection does not alter the terminal characteristics. We now note that we have a controlled current source gmvgs connected across its control voltage vgs. We can replace this controlled source by a resistance as long as this resistance draws an equal current as the source. (See the source-absorption theorem in Appendix D.) Thus the value of the resistance is vgs/gmvgs = 1/gm. This replacement is shown in Fig. 7.16(d), which depicts
ig = 0 id ig = 0
GDGD
vgs
gmvgs X
gm vgs
vgs gmvgs
id
is is
SS
(a)
(b)
D
vgs
gmvgs X
gm vgs
id
ig = 0
ig = 0
G
GD
id
vgs
gmvgs
1/gm
is
(d)
is
S
S (c)
Figure 7.16 Development of the T equivalent-circuit model for the MOSFET. For simplicity, ro has been omitted; however, it may be added between D and S in the T model of (d).
DD
GG
SS
(a) (b)
Figure 7.17 (a) The T model of the MOSFET augmented with the drain-to-source resistance ro. (b) An alternative representation of the T model.
the alternative model. Observe that ig is still zero, id = gmvgs, and is = vgs/(1/gm) = gmvgs, all the same as in the original model in Fig. 7.16(a).
The model of Fig. 7.16(d) shows that the resistance between gate and source looking into the source is 1/gm . This observation and the T model prove useful in many applications. Note that the resistance between gate and source, looking into the gate, is infinite.
In developing the T model we did not include ro. If desired, this can be done by incorporating in the circuit of Fig.7.16(d) a resistance ro between drain and source, as shown in Fig.7.17(a). An alternative representation of the T model, in which the voltage-controlled current source is replaced with a current-controlled current source, is shown in Fig. 7.17(b).
Finally, we should note that in order to distinguish the model of Fig. 7.13(b) from the equivalent T model, the former is sometimes referred to as the hybrid-π model, a carryover from the bipolar transistor literature. The origin of this name will be explained shortly.
Example 7.4
Figure 7.18(a) shows a MOSFET amplifier biased by a constant-current source I. Assume that the values of I and RD are such that the MOSFET operates in the saturation region. The input signal vi is coupled to the source terminal by utilizing a large capacitor CC1. Similarly, the output signal at the drain is taken through a large coupling capacitor CC2. Find the input resistance Rin and the voltage gain vo/vi. Neglect channel-length modulation.
7.2 Small-SignalOperationandModels 395
gmvgs
1i
vgs 1/g m
ro
i
1/g m
ro
396
Chapter 7 Transistor Amplifiers
Example 7.4 continued
VDD
RD
I
D
1i
v RDvo
o
CC2
G
i
Rin
CC1 vi
Rin
(a)
S
1
gm
−VSS
vi (b)
Figure 7.18 (a) Amplifier circuit for Example 7.4. (b) Small-signal equivalent circuit of the amplifier in (a).
Solution
Replacing the MOSFET with its T equivalent-circuit model results in the amplifier equivalent circuit shown in Fig. 7.18(b). Observe that the dc current source I is replaced with an open circuit and the dc voltagesourceVDD isreplacedbyashortcircuit.Thelargecouplingcapacitorshavebeenreplacedbyshort circuits. From the equivalent-circuit model we determine
and
Thus,
Rin = vi =1/gm −i
v
vo =−iRD = i RD =gmRDvi
1/gm
A ≡vo =g R v vi mD
We note that this amplifier, known as the common-gate amplifier because the gate at ground potential is
common to both the input and output ports, has a low input resistance 1/gm and a noninverting gain. We shall study this amplifier type in Section 7.3.5.
7.2 Small-Signal Operation and Models 397
EXERCISE
7.5 Use the T model of Fig. 7.17(b) to show that a MOSFET whose drain is connected to its gate exhibits
an incremental resistance equal to [ 1/gm Ans. See Fig. E7.5.
∥ro].
ro
1
gm
Q
(a)
0i
i
Modeling the Body Effect
As mentioned earlier (see Section 5.4), the body effect occurs in a MOSFET when the source is not tied to the substrate (which is always connected to the most negative power supply in the integrated circuit for n-channel devices and to the most positive for p-channel devices). Thus the substrate (body) will be at signal ground, but since the source is not, a signal voltage vbs develops between the body (B) and the source (S). The substrate then acts as a “second gate” or a backgate for the MOSFET. Thus the signal vbs gives rise to a drain-current component, which we shall write as gmbvbs, where gmb is the body
transconductance, defined as
∂i
gmb ≡ D (7.49) ∂vBS vGS =constant
vDS =constant
Recalling that iD depends on vBS through the dependence of Vt on VBS, we can show that
r=(1 )ro gm
(b)
FigureE7.5CircuitsforExercise7.5.Notethat the bias arrangement of Q is not shown.
where
gmb =χgm (7.50)
χ≡∂Vt = γ (7.51) ∂VSB 2 2φf +VSB
Typically the value of χ lies in the range 0.1 to 0.3.
Figure 7.19 shows the MOSFET model augmented to include the controlled source gmbvbs
that models the body effect. Ideally, this is the model to be used whenever the source is not connected to the substrate. It has been found, however, that except in some very particular
398 Chapter 7 Transistor Amplifiers
D
D
GB
(a)
(b)
S
Figure 7.19 Small-signal, equivalent-circuit model of a MOSFET in which the source is not connected to the body.
situations, the body effect can generally be ignored in the initial, pencil-and-paper design of MOSFET amplifiers.
Finally, although the analysis above was performed on an NMOS transistor, the results and the equivalent circuit of Fig. 7.19 apply equally well to PMOS transistors, except for using |VGS|, |Vt|, |VOV|, |VA|, |VSB|, |γ|, and |λ| and replacing kn′ with kp′ in the appropriate formula.
EXERCISES
7.6 FortheamplifierinFig.7.4,letVDD =5V,RD =10k,Vt =1V,kn′ =20μA/V2,W/L=20,VGS =2V, and λ = 0.
(a)FindthedccurrentID andthedcvoltageVDS.
(b) Find gm.
(c) Find the voltage gain.
(d) If vgs = 0.2 sin ωt volts, find vds assuming that the small-signal approximation holds. What are the minimum and maximum values of vDS?
(e)UseEq.(7.28)todeterminethevariouscomponentsofi .Usingtheidentity(sin2ωt= 1 −1 cos2ωt), D22
show that there is a slight shift in ID (by how much?) and that there is a second-harmonic component (i.e., a component with frequency 2 ω). Express the amplitude of the second-harmonic component as a percentage of the amplitude of the fundamental. (This value is known as the second-harmonic distortion.)
Ans. (a) 200μA, 3V; (b) 0.4mA/V; (c) –4V/V; (d) vds =−0.8 sinωt volts, 2.2V, 3.8V; (e)iD =
(204+80 sinωt–4cos2ωt)μA,5%
7.7 AnNMOStransistorhasμnCox =60μA/V2,W/L=40,Vt =1V,andVA =15V.Findgm andro when
(a) the bias voltage VGS = 1.5 V, (b) the bias current ID = 0.5 mA. Ans. (a) 1.2 mA/V, 50 k; (b) 1.55 mA/V, 30 k
7.2 Small-Signal Operation and Models 399
7.8 A MOSFET is to operate at ID =0.1mA and is to have gm =1mA/V. If kn′ = 50μA/V2, find the required W/L ratio and the overdrive voltage.
Ans. 100; 0.2 V
7.9 For a fabrication process for which μp ≃ 0.4 μn , find the ratio of the width of a PMOS transistor to the width of an NMOS transistor so that the two devices have equal gm for the same bias conditions. The two devices have equal channel lengths.
Ans. 2.5
7.10 A PMOS transistor has Vt = −1 V, kp′ = 60 μA/V2, and W/L = 16 μm/0.8 μm. Find ID and gm when thedeviceisbiasedatVGS =−1.6V.Also,findthevalueofro ifλ(atL=1μm)=–0.04V−1.
Ans. 216 μA; 0.72 mA/V; 92.6 k
7.11 Deriveanexpressionfor(gmro)intermsofVA andVOV.AsweshallseeinChapter8,thisisanimportant transistorparameterandisknownastheintrinsicgain.Evaluatethevalueofgmro foranNMOStransistor fabricated in a 0.8-μm CMOS process for which VA′ = 12.5 V/μm of channel length. Let the device have minimum channel length and be operated at an overdrive voltage of 0.2 V.
Ans. gmro = 2VA/VOV ; 100 V/V
7.2.2 The BJT Case
We next consider the small-signal operation of the BJT and develop small-signal equivalent-circuit models that represent its operation at a given bias point. The following development parallels what we used for the MOSFET except that here we have an added complication: The BJT draws a finite base current. As will be seen shortly, this phenomenon (finite β) manifests itself as a finite input resistance looking into the base of the BJT (as compared to the infinite input resistance looking into the gate of the MOSFET).
Consider the conceptual amplifier circuit shown in Fig. 7.20(a). Here the base–emitter junction is forward biased by a dc voltage VBE . The reverse bias of the collector–base junction is established by connecting the collector to another power supply of voltage VCC through a resistor RC. The input signal to be amplified is represented by the voltage source vbe that is superimposed on VBE .
The DC Bias Point We consider first the dc bias conditions by setting the signal vbe to zero. The circuit reduces to that in Fig. 7.20(b), and we can write the following relationships for the dc currents and voltages:
IC =ISeVBE/VT IE =IC/α
IB =IC/β
VCE =VCC −ICRC
(7.52) (7.53) (7.54) (7.55)
Foractive-modeoperation,VCE shouldbegreaterthan(VBE −0.4)byanamountthatallows for the required negative signal swing at the collector.
400 Chapter 7
Transistor Amplifiers
VCC RC
vCE iE
VCC RC
VCE IE
vbe VBE
iC
iB
vBE
(a)
IC
IB
VBE
vBE =VBE +vbe Correspondingly, the collector current becomes
Use of Eq. (7.52) yields
iC = IS evBE /VT = IS e(VBE +vbe )/VT =ISeVBE/VT evbe/VT
iC =ICevbe/VT
Now, if vbe ≪ VT , we may approximate Eq. (7.56) as v
iC≃IC 1+be VT
(7.56)
(7.57)
(b)
Figure7.20 (a)Conceptualcircuittoillustratetheoperationofthetransistorasanamplifier.(b)Thecircuit of (a) with the signal source vbe eliminated for dc (bias) analysis.
The Collector Current and the Transconductance If a signal vbe is applied as shown inFig.7.20(a),thetotalinstantaneousbase–emittervoltagevBE becomes
Here we have expanded the exponential in Eq. (7.56) in a series and retained only the first two terms. That is, we have assumed that
vbe ≪ VT (7.58)
so that we can neglect the higher-order terms in the exponential series expansion. The condition in Eq. (7.58) is the small-signal approximation for the BJT and corresponds to that in Eq. (7.29) for the MOSFET case. The small-signal approximation for the BJT is valid only for vbe less than 5 mV or 10 mV, at most. Under this approximation, the total collector current is given by Eq. (7.57) and can be rewritten
iC = IC + IC vbe (7.59) VT
7.2 Small-Signal Operation and Models 401 ThusthecollectorcurrentiscomposedofthedcbiasvalueIC andasignalcomponentic,
ic = IC vbe (7.60) VT
This equation relates the signal current in the collector to the corresponding base–emitter signal voltage. It can be rewritten as
ic = gmvbe (7.61) where gm is the transconductance, and from Eq. (7.60), it is given by
gm = IC (7.62) VT
We observe that the transconductance of the BJT is directly proportional to the collector bias current IC . Thus to obtain a constant predictable value for gm , we need a constant predictable IC . Also, we note that BJTs have relatively high transconductance in comparison to MOSFETs: for instance, at IC = 1 mA, gm ≃ 40 mA/V. Finally, unlike the MOSFET, whose gm depends on the device dimensions (W and L), gm of a BJT depends only on the dc collector current at which it is biased to operate.
A graphical interpretation for gm is given in Fig. 7.21, where it is shown that gm is equal to the slope of the tangent to the iC –v BE characteristic curve at iC = IC (i.e., at the bias point Q). Thus,
∂i
gm= C (7.63)
The small-signal approximation implies keeping the signal amplitude sufficiently small that operationisrestrictedtoanalmost-linearsegmentoftheiC–vBE exponentialcurve.Increasing the signal amplitude will result in the collector current having components nonlinearly related to vbe.
EXERCISES
7.12 UseEq.(7.63)toderivetheexpressionforgm inEq.(7.62).
7.13 Calculate the value of gm for a BJT biased at IC = 0.5 mA. Ans. 20 mA/V
∂vBE iC=IC
402 Chapter 7
Transistor Amplifiers
Q
Figure 7.21 Linear operation of the transistor under the small-signal condition: A small-signal vbe with a triangular waveform is superimposed on the dc voltage VBE . It gives rise to a collector-signal current ic , also of triangular waveform, superimposed on the dc current IC . Here, ic = gm v be , where gm is the slope of the iC –v BE curve at the bias point Q.
The Base Current and the Input Resistance at the Base To determine the resistance seen by vbe, we first evaluate the total base current iB using Eq. (7.59), as follows:
iB = iC = IC + 1 IC vbe β β βVT
Thus,
iB = IB + ib
where IB is equal to IC /β and the signal component ib is given by
(7.64)
(7.65)
(7.66)
SubstitutingforIC/VT bygm gives
ib = 1 IC vbe β VT
ib = gm vbe β
7.2 Small-Signal Operation and Models 403 The small-signal input resistance between base and emitter, looking into the base, is denoted
byrπ andisdefinedas
Using Eq. (7.66) gives
rπ ≡ vbe ib
rπ = β gm
(7.67)
(7.68)
Thus rπ is directly dependent on β and is inversely proportional to the bias current IC. Substituting for gm in Eq. (7.68) from Eq. (7.62) and replacing IC /β by IB gives an alternative expression for rπ ,
rπ = VT (7.69) IB
Here, we recall that because the gate current of the MOSFET is zero (at dc and low frequencies) the input resistance at the gate is infinite; that is, in the MOSFET there is no counterpart to rπ .5
EXERCISE
7.14 A BJT amplifier is biased to operate at a constant collector current IC = 0.5 mA irrespective of the value β. If the transistor manufacturer specifies β to range from 50 to 200, give the expected range of gm, IB, and rπ .
Ans. gm isconstantat20mA/V;IB =10μAto2.5μA;rπ =2.5kto10k
The Emitter Current and the Input Resistance at the Emitter
currentiE canbedeterminedusingEq.(7.59)as
iE = iC = IC + ic
ααα
Thus,
iE = IE + ie
where IE is equal to IC /α and the signal current ie is given by
ie=ic = IC vbe=IEvbe ααVT VT
The total emitter
(7.70)
(7.71)
5At high frequencies, the input capacitance at the MOSFET gate makes the input current finite (see Chapter 10).
404 Chapter 7
Transistor Amplifiers
If we denote the small-signal resistance between base and emitter looking into the emitter by re, it can be defined as
re ≡ vbe ie
Using Eq. (7.71) we find that re , called the emitter resistance, is given by re = VT
IE
Comparison with Eq. (7.62) reveals that
re = α ≃ 1
(7.72)
(7.73)
(7.74)
gm gm
The relationship between rπ and re can be found by combining their respective definitions in
Eqs. (7.67) and (7.72) as
Thus,
which yields
vbe =ibrπ =iere
rπ = (ie/ib)re
rπ =(β+1)re Figure7.22illustratesthedefinitionofrπ andre.
ib
v vbeie be
(7.75)
r vbe ib
re vbe ie
r = (b1)re
Figure 7.22 Illustrating the definition of rπ and re.
Finally, a comparison with the MOSFET would be useful: For the MOSFET, α = 1 and the resistance looking into the source is simply 1/gm.
SHOCKLEY AND SILICON VALLEY:
In 1956 William Bradford Shockley started a new company, Shockley Semiconductor Laboratory in Mountain View, California (near Stanford, his birthplace). While at Bell Labs, together with John Bardeen and Walter Brattain, he had invented the BJT. At Shockley, the initial concentration was on developing semiconductor devices, particularly a new four-layer diode. But Shockley’s scientific genius and ability to select and attract good team members, first demonstrated at Bell Labs, was not accompanied by comparable talent for management. Consequently, in 1957, eight of his team members (the so-called Traitorous Eight, including Gordon Moore and Robert Noyce) left Shockley to create Fairchild Semiconductor. It was a propitious time: The first Sputnik was launched a month later, and the ensuing space race accelerated demand for solid-state circuits. Decades passed, and in 2002 a group of some 30 individuals who had been associated with Silicon Valley since 1956 met at Stanford University to reminisce about Shockley’s contributions to the information technology age. They unanimously concluded that Shockley was the man who brought silicon to Silicon Valley!
7.2 Small-Signal Operation and Models 405
EXERCISE
7.15 A BJT having β = 100 is biased at a dc collector current of 1 mA. Find the value of gm, re, and rπ at the bias point.
Ans. 40 mA/V; 25 ; 2.5 k
The Voltage Gain The total collector voltage vCE is vCE =VCC −iCRC
=VCC −(IC +ic)RC =(VCC −ICRC)−icRC =VCE −icRC
(7.76)
Thus, superimposed on the collector bias voltage VCE we have signal voltage vce given by vce = −icRC = −gmvbeRC (7.77)
=(−gmRC)vbe fromwhichwefindthevoltagegainAv ofthisamplifieras
A ≡vce =−g R (7.78) vvbe mC
Here again we note that because gm is directly proportional to the collector bias current, the gain will be as stable as the collector bias current is made. Substituting for gm from Eq. (7.62)
406 Chapter 7
Transistor Amplifiers
enables us to express the gain in the form
Av =−ICRC (7.79) VT
which is identical to the expression we derived in Section 7.1 (Eq. 7.21). Finally, we note that the gain expression in Eq. (7.78) is identical in form to that for the MOSFET amplifier (namely, −gmRD).
EXERCISE
7.16 In the circuit of Fig. 7.20(a), VBE is adjusted to yield a dc collector current of 1 mA. Let VCC = 15 V, RC =10k,andβ=100.Findthevoltagegainvce/vbe.Ifvbe =0.005sinωtvolt,findvC(t)andiB(t). Ans. −400 V/V; 5 – 2 sinωt volts; 10+2 sinωt μA
Separating the Signal and the DC Quantities The analysis above indicates that every current and voltage in the amplifier circuit of Fig. 7.20(a) is composed of two components: a dc component and a signal component. For instance, vBE = VBE + vbe, IC = IC + ic, and so on. The dc components are determined from the dc circuit given in Fig. 7.20(b) and from the relationships imposed by the transistor (Eqs. 7.52 through 7.54). On the other hand, a representation of the signal operation of the BJT can be obtained by eliminating the dc sources, as shown in Fig. 7.23. Observe that since the voltage of an ideal dc supply does not change, the signalvoltageacrossitwillbezero.ForthisreasonwehavereplacedVCC andVBE withshort circuits. Had the circuit contained ideal dc current sources, these would have been replaced by open circuits. Note, however, that the circuit of Fig. 7.23 is useful only insofar as it shows the various signal currents and voltages; it is not an actual amplifier circuit, since the dc bias circuit is not shown.
Figure 7.23 also shows the expressions for the current increments (ic, ib, and ie) obtained when a small signal vbe is applied. These relationships can be represented by a circuit. Such
RC
ic
vce E ie
gm vbe
C
ib
vbe /r
vbe
vbe
vbe
re dc sources (VBE and VCC) eliminated (short-circuited). Thus
B
Figure 7.23 The amplifier circuit of Fig. 7.20(a) with the
only the signal components are present. Note that this is a representation of the signal operation of the BJT and not an actual amplifier circuit.
a circuit should have three terminals—C, B, and E—and should yield the same terminal currents indicated in Fig. 7.23. The resulting circuit is then equivalent to the transistor as far as small-signal operation is concerned, and thus it can be considered an equivalent small-signal circuit model.
The Hybrid-π Model An equivalent-circuit model for the BJT is shown in Fig. 7.24(a). This model represents the BJT as a voltage-controlled current source and explicitly includes the inputresistancelookingintothebase,rπ.Themodelobviouslyyieldsic =gmvbe andib =vbe/rπ. Not so obvious, however, is the fact that the model also yields the correct expression for ie. This can be shown as follows: At the emitter node we have
i=vbe+gv =vbe1+gr e r mbe r mπ
ππ vbe rπ
= r (1+β)=vbe 1+β π
7.2 Small-Signal Operation and Models 407
=vbe/re
A slightly different equivalent-circuit model can be obtained by expressing the current of the controlled source (gmvbe) in terms of the base current ib as follows:
gmvbe = gm ibrπ
=gmrπ ib=βib
This results in the alternative equivalent-circuit model shown in Fig. 7.24(b). Here the transistor is represented as a current-controlled current source, with the control current being ib . As we have done in the case of the MOSFET’s small-signal models, we can account for theEarlyeffect(theslightdependenceofiC onvCE duetobasewidthmodulation)byadding the resistance ro = VA/IC between collector and emitter, as shown in Fig. 7.25. Note that to
conform with the literature, we have renamed vbe as vπ . The two models of Fig. 7.25 are versions of the hybrid-π model, the most widely used model for the BJT. The equivalent circuit of Fig. 7.25(a) corresponds to that of the MOSFET [Fig. 7.13(b)] except for rπ , which accounts for the finite base current (or finite β) of the BJT. However, the equivalent circuit of Fig. 7.25(b) has no MOS counterpart.
ib ic
BC
i ic
BC
+
vbe rp –
+
vbe –
E
ie
(a)
gm = IC/VT
rp =VT/IB =b/gm
ie
E
gmvbe
Figure7.24 Twoslightlydifferentversionsofthehybrid-πmodelforthesmall-signaloperationoftheBJT. The equivalent circuit in (a) represents the BJT as a voltage-controlled current source (a transconductance amplifier), and that in (b) represents the BJT as a current-controlled current source (a current amplifier).
b
rp
bib
(b)
408 Chapter 7 Transistor Amplifiers
Figure 7.25 The hybrid-π small-signal model, in its two versions, with the resistance ro included.
It is important to note that the small-signal equivalent circuits of Fig. 7.25 model the operation of the BJT at a given bias point. This should be obvious from the fact that the model parameters gm , rπ , and ro depend on the value of the dc bias current IC , as indicated in Fig. 7.25. That is, these equivalent circuits model the incremental operation of the BJT around the bias point.
As in the case of the MOSFET amplifier, including ro in the BJT model causes the voltage gain of the conceptual amplifier of Fig. 7.20(a) to become
vo =−g(R∥r) vbe mCo
Thus, the magnitude of the gain is reduced somewhat.
(7.80)
EXERCISE
7.17 For the model in Fig. 7.24(b) show that ic = gmvbe and ie = vbe/re.
The T Model Although the hybrid-π model (in one of its two variants shown in Fig. 7.24) can be used to carry out small-signal analysis of any transistor circuit, there are situations in which an alternative model, shown in Fig. 7.26, is much more convenient. This model, called, as in the case of the MOSFET, the T model, is shown in two versions in Fig. 7.26. The model of Fig. 7.26(a) represents the BJT as a voltage-controlled current source with the control voltage being vbe. Here, however, the resistance between base and emitter, looking into the emitter, is explicitly shown. From Fig. 7.26(a) we see clearly that the model yields the correct expressions for ic and ie. It can also be shown to yield the correct expression for ib (see Exercise 7.18 on the next page).
7.2 Small-Signal Operation and Models 409
C
ic
(a)
(b)
ib
B
vbe
Figure 7.26 Two slightly different versions of what is known as the T model of the BJT. The circuit in (a) is a voltage-controlled current source representation and that in (b) is a current-controlled current source representation.Thesemodelsexplicitlyshowtheemitterresistancere ratherthanthebaseresistancerπ featured in the hybrid-π model.
If in the model of Fig. 7.26(a) the current of the controlled source is expressed in terms of the emitter current as
gmvbe = gm(iere)
= (gmre)ie = αie
we obtain the alternative T model shown in Fig. 7.26(b). Here the BJT is represented as a current-controlled current source but with the control signal being ie.
Finally, the T models can be augmented by ro to account for the dependence of ic to vce (the Early effect) to obtain the equivalent circuits shown in Fig. 7.27.
EXERCISE
7.18 Show that for the T model in Fig. 7.24(a), ib = vbe /rπ .
Small-Signal Models of the pnp Transistor Although the small-signal models in Figs. 7.25 and 7.27 were developed for the case of the npn transistor, they apply equally well to the pnp transistor with no change in polarities.
ie
E
e
re
410 Chapter 7
Transistor Amplifiers
CC
B
gm = IC/VT
r = VT = a
gmvp
ro
vp re
e IE gm B ro = VA/IC
ai
ro
re
i
Figure 7.27 The T models of the BJT.
EE (a) (b)
Example 7.5
We wish to analyze the transistor amplifier shown in Fig. 7.28(a) to determine its voltage gain vo/vi. Assume β = 100 and neglect the Early effect.
VCC 10 V
10 V 2.3 mA
RC 3 k VC
vo
3 V
100 k
0.023 mA
0.7 V
(b)
3 k
3.1 V
2.323 mA
RBB
100 k
vi
VBB 3 V
(a)
Figure 7.28 Example 7.5: (a) amplifier circuit; (b) circuit for dc analysis; (c) amplifier circuit with dc sources replaced by short circuits; (d) amplifier circuit with transistor replaced by its hybrid-π, small-signal model.
RBB
RBB 100 k
RC
7.2 Small-Signal Operation and Models 411
vo
i m be RC 3 k
BC
vi
Figure 7.28 continued
Solution
vov rvbe gv
E
(c)
(d)
We shall follow a five-step process:
1. The first step in the analysis consists of determining the quiescent operating point. For this purpose
we assume that vi = 0 and thus obtain the dc circuit shown in Fig. 7.28(b). The dc base current will be IB = VBB −VBE
RBB
≃ 3−0.7 =0.023mA 100
The dc collector current will be
IC =βIB =100×0.023=2.3mA The dc voltage at the collector will be
VC =VCC −ICRC =+10−2.3×3=+3.1V
Since VB at +0.7 V is less than VC , it follows that in the quiescent condition the transistor will be operating in the active mode. The dc analysis is illustrated in Fig. 7.28(b).
412 Chapter 7 Transistor Amplifiers
Example 7.5 continued
2. Having determined the operating point, we can now proceed to determine the small-signal model
parameters:
re=VT = 25mV =10.8 IE (2.3/0.99) mA
gm = IC = 2.3mA =92mA/V VT 25mV
rπ = β = 100 = 1.09 k gm 92
3. Replacing VBB and VCC with short circuits results in the circuit in Fig. 7.28(c).
4. To carry out the small-signal analysis it is equally convenient to employ either of the two hybrid-π, equivalent-circuit models of Fig. 7.24 to replace the transistor in the circuit of Fig. 7.28(c). Using the first results in the amplifier equivalent circuit given in Fig. 7.28(d).
5. Analysis of the equivalent circuit in Fig. 7.28(d) proceeds as follows: v=v rπ
The output voltage vo is given by
Thus the voltage gain will be
Example 7.6
i
= −92 × 0.011vi × 3 = −3.04vi
Av = vo = −3.04 V/V vi
be i rπ +RBB
= v 1.09 = 0.011v
(7.81)
(7.82)
i 101.09 vo =−gmvbeRC
To gain more insight into the operation of transistor amplifiers, we wish to consider the waveforms at various points in the circuit analyzed in the previous example. For this purpose assume that vi has a triangular waveform. First determine the maximum amplitude that vi is allowed to have. Then, with the amplitude of v i set to this value, give the waveforms of the total quantities iB (t), v BE (t), iC (t), and vC(t).
Solution
One constraint on signal amplitude is the small-signal approximation, which stipulates that vbe should not exceed about 10 mV. If we take the triangular waveform vbe to be 20 mV peak-to-peak and work backward, Eq. (7.81) can be used to determine the maximum possible peak of vi,
vˆi=vˆbe =10=0.91V 0.011 0.011
To check whether the transistor remains in the active mode with vi having a peak value vˆi = 0.91V, we have to evaluate the collector voltage. The voltage at the collector will consist of a triangular wave vo superimposed on the dc value VC = 3.1 V. The peak voltage of the triangular waveform will be
vˆo =vˆi ×gain=0.91×3.04=2.77V
It follows that when the output swings negative, the collector voltage reaches a minimum of 3.1 − 2.77 = 0.33 V, which is lower than the base voltage by less than 0.4 V. Thus the transistor will remain in the active mode with vi having a peak value of 0.91 V. Nevertheless, to be on the safe side, we will use a somewhat lower value for vˆi of approximately 0.8 V, as shown in Fig. 7.29(a), and complete the analysis of this problem utilizing the equivalent circuit in Fig. 7.28(d). The signal current in the base will be triangular, with a peak value iˆb of
iˆb = vˆi = 0.8 =0.008mA RBB +rπ 100+1.09
This triangular-wave current will be superimposed on the quiescent base current IB , as shown in Fig. 7.29(b). Thebase–emittervoltagewillconsistofatriangular-wavecomponentsuperimposedonthedcVBE thatis approximately 0.7 V. The peak value of the triangular waveform will be
vˆ = vˆ rπ = 0.8 1.09 = 8.6 mV be i rπ +RBB 100+1.09
ThetotalvBE issketchedinFig.7.29(c).
The signal current in the collector will be triangular in waveform, with a peak value iˆc given by
iˆc =βiˆb =100×0.008=0.8mA
This current will be superimposed on the quiescent collector current IC (=2.3mA), as shown in Fig. 7.29(d).
The signal voltage at the collector can be obtained by multiplying vi by the voltage gain; that is,
vˆo =3.04×0.8=2.43V
Figure7.29(e)showsasketchofthetotalcollectorvoltagevC versustime.Notethephasereversalbetween the input signal vi and the output signal vo.
Finally, we observe that each of the total quantities is the sum of a dc quantity (found from the dc circuit in Fig. 7.28b), and a signal quantity (found from the circuit in Fig. 7.28d).
7.2 Small-SignalOperationandModels 413
414
Chapter 7 Transistor Amplifiers
Example 7.6 continued
vi 0.8 V 0 0.8 V
iB (mA)
0.03 0.02 0.01
0
vBE 0.7 V
0
iC (mA)
3
2
1ˆ
0
vˆi
(a) ib 0.008 mA
t
ˆ
ib
iB
IB 0.023 mA
(b)
t
vˆbe
IC 2.3 mA
8.6 mV
vBE
vbe
ic
VBE
(c)
t
ic
0.8 mA
iC
IC
Figure 7.29 Signal waveforms in the circuit of Fig. 7.28.
(d)
t
vC (V) 6
4 2 0
Figure 7.29 continued
Example 7.7
vˆo 2.43 V
0.67 V
vo
7.2
Small-Signal Operation and Models 415
vo
VC 3.1 V
vC (e)
t
We need to analyze the circuit of Fig. 7.30(a) to determine the voltage gain and the signal waveforms at various points. The capacitor CC1 is a coupling capacitor whose purpose is to couple the signal vi to the emitter while blocking dc. In this way the dc bias established by V + and V − together with RE and RC will
V 10 V
10 V
10 k
5 k
10 V
(b)
RE
10 k
0.93 mA
0.7 V
0.92 mA
CC1 vi
V
(a)
CC2 RC 5 k
10 V
vo
5.4 V
Figure 7.30 Example 7.7: (a) circuit; (b) dc analysis; (c) circuit with the dc sources eliminated; (d) small-signal analysis using the T model for the BJT.
416
Chapter 7 Transistor Amplifiers
Example 7.7 continued
RE
vi E ie re
vi RE ie re vo ieRC B RCvi
re
vi
ie
vC
o vo
RC
RC
(d)
Figure 7.30 continued
(c)
not be disturbed when the signal vi is connected. For the purpose of this example, CC1 will be assumed to be very large so as to act as a perfect short circuit at signal frequencies of interest. Similarly, another very large capacitor CC2 is used to couple the output signal vo to other parts of the system. You may neglect the Early effect.
Solution
Here again we shall follow a five-step process:
1. Figure 7.30(b) shows the circuit with the signal source and the coupling capacitors eliminated. The dc operating point can be determined as follows:
IE = +10−VE ≃ +10−0.7 =0.93mA RE 10
Assuming β = 100, then α = 0.99, and
IC =0.99IE =0.92mA VC =−10+ICRC
= −10 + 0.92 × 5 = −5.4 V Thus the transistor is in the active mode.
2. We now determine the small-signal parameters as follows:
gm = IC = 0.92 =36.8mA/V VT 0.025
re=VT =0.025=27.2 IE 0.92
7.2 Small-SignalOperationandModels 417
β = 100
rπ = β = 100 =2.72k
gm 36.8
3. To prepare the circuit for small-signal analysis, we replace the dc sources with short circuits. The resulting circuit is shown in Fig. 7.30(c). Observe that we have also eliminated the two coupling capacitors, since they are assumed to be acting as perfect short circuits.
4. We are now ready to replace the BJT with one of the four equivalent-circuit models of Figs. 7.24 and 7.26. Although any of the four will work, the T models of Fig. 7.26 will be more convenient because the base is grounded. Selecting the version in Fig. 7.26(b) results in the amplifier equivalent circuit shown in Fig. 7.30(d).
5. Analysis of the circuit in Fig. 7.30(d) to determine the output voltage vo and hence the voltage gain vo/vi is straightforward and is given in the figure. The result is
A =vo =αRC =0.99×5=182V/V
v vi re 0.0272
Note that the voltage gain is positive, indicating that the output is in phase with the input signal. This property is due to the fact that the input signal is applied to the emitter rather than to the base, as was done in Example 7.5. We should emphasize that the positive gain has nothing to do with the fact that the transistor used in this example is of the pnp type.
Returningtothequestionofallowablesignalmagnitude,weobservefromFig.7.30(d)thatveb =vi. Thus, if small-signal operation is desired (for linearity), then the peak of vi should be limited to approximately 10 mV. With Vˆi set to this value, as shown for a sine-wave input in Fig. 7.31, the peak amplitude at the collector, Vˆo, will be
Vˆo =182×0.01=1.82V
α = 0.99
418 Chapter 7 Transistor Amplifiers
Example 7.7 continued
1.82
Figure 7.31 Input and output waveforms for the circuit of Fig. 7.30. Observe that this amplifier is noninverting, a property of the grounded-base configuration.
EXERCISE
7.19 To increase the voltage gain of the amplifier analyzed in Example 7.7, the collector resistance RC is increased to 7.5 k. Find the new values of VC , Av , and the peak amplitude of the output sine wave corresponding to an input sine wave vi of 10-mV peak.
Ans. –3.1 V; 276 V/V; 2.76 V
Performing Small-Signal Analysis Directly on the Circuit Diagram In most cases one should explicitly replace each BJT with its small-signal model and analyze the resulting circuit, as we have done in the examples above. This systematic procedure is particularly recommended for beginning students. Experienced circuit designers, however, often perform a first-order analysis directly on the circuit. Figure 7.32 illustrates this process for the two
circuits we analyzed in Examples 7.5 and 7.7. The reader is urged to follow this direct analysis procedure (the steps are numbered). Observe that the equivalent-circuit model is implicitly utilized; we are only saving the step of drawing the circuit with the BJT replaced by its model. Direct analysis, however, has an additional very important benefit: It provides insight regarding the signal transmission through the circuit. Such insight can prove invaluable in design, particularly at the stage of selecting a circuit configuration appropriate for a given application. Direct analysis can be utilized also for MOS amplifier circuits.
7.2 Small-Signal Operation and Models 419
ic RC3
ib RBB
vi 2
v
1r
(a)
RE
4
5 Avo v vi
1
bRC vi bRC
i
re
vi
ie
v 2re
i
4
vi
re
3
r vi RC
e vo
5 Avvi (b)
re
Figure 7.32 Performing signal analysis directly on the circuit diagram with the BJT small-signal model implicitly employed: (a) circuit for Example 7.5; (b) circuit for Example 7.7.
420 Chapter 7 Transistor Amplifiers
EXERCISE
7.20 The transistor in Fig. E7.20 is biased with a constant current source I = 1 mA and has β = 100 and VA =100V.
(a) Neglecting the Early effect, find the dc voltages at the base, emitter, and collector.
(b) Find gm, rπ , and ro.
(c) If terminal Z is connected to ground, X to a signal source vsig with a source resistance Rsig =
2 k, and Y to an 8-k load resistance, use the hybrid-π model shown earlier (Fig. 7.25) to draw the small-signal equivalent circuit of the amplifier. (Note that the current source I should be replaced with an open circuit.) Calculate the overall voltage gain vy/vsig. If ro is neglected, what is the error in estimating the gain magnitude? (Note: An infinite capacitance is used to indicate that the capacitance is sufficiently large that it acts as a short circuit at all signal frequencies of interest. However, the capacitor still blocks dc.)
Ans. (a) –0.1 V, –0.8 V, +2.1 V; (b) 40 mA/V, 2.5 k, 100 k; (c) –77 V/V, +3.9%
7.2.3 Summary Tables
We conclude this section by presenting three useful summary tables: Table 7.1 lists the five steps to be followed in the analysis of a MOSFET or a BJT amplifier circuit. Table 7.2 presents the MOSFET small-signal, equivalent-circuit models, together with the formulas for calculating the parameter values of the models. Finally, Table 7.3 supplies the corresponding data for the BJT.
Figure E7.20
7.2 Small-Signal Operation and Models 421
Table 7.1 Systematic Procedure for the Analysis of Transistor Amplifier Circuits
1. Eliminate the signal source and determine the dc operating point of the transistor.
2. Calculate the values of the parameters of the small-signal model.
3. Eliminate the dc sources by replacing each dc voltage source by a short circuit and each dc current source by an open circuit.
4. Replace the transistor with one of its small-signal, equivalent-circuit models. Although any of the models can be used, one might be more convenient than the others for the particular circuit being analyzed. This point will be made clearer in the next section.
5. Analyze the resulting circuit to determine the required quantities (e.g., voltage gain, input resistance).
Table 7.2 Small-Signal Models of the MOSFET
Small-Signal Parameters
NMOS transistors Transconductance:
g=μCWV = 2μCWI=2I LLV
Output resistance: r = V /I = 1/λI
PMOS transistors
Same formulas as for NMOS except using |V |, V , |λ| and replacing μ with μ . Small-Signal, Equivalent-Circuit Models
DD
i
gv GDGrGr
gv vrv
1i1 gg
SSS Hybrid-π model T models
422 Chapter 7
Transistor Amplifiers
Table 7.3 Small-Signal Models of the BJT Hybrid-π Model
(gmvπ ) Version (βib) Version i
BCBC
vrrrr
gv
EE
(αi) Version CC
i
i
T Model
(gmvπ ) Version
gmv
B ro B ro
v re
re
EE
i
Model Parameters in Terms of DC Bias Currents
re=VT =αVT IE IC
rπ = β gm
ro=|VA| IB IC IC
gm=IC VT
In Terms of gm re = α
gm
In Terms of re gm = α
re
β=α α=β β+1=1 1−α β+1 1−α
rπ=VT =βVT
rπ = (β + 1)re Relationships between α and β
gm + 1 = 1 rπ re
7.3 Basic Configurations
It is useful at this point to take stock of where we are and where we are going in our study of transistor amplifiers. In Section 7.1 we examined the underlying principle for the application of the MOSFET, and of the BJT, as an amplifier. There we found that almost-linear amplification can be obtained by dc biasing the transistor at an appropriate point in its active region of operation,andbykeepingtheinputsignal(vgs orvbe)small.Wethendeveloped,inSection7.2, circuit models that represent the small-signal operation of each of the two transistor types (Tables 7.2 and 7.3), thus providing a systematic procedure (Table 7.1) for the analysis of transistor amplifiers.
We are now ready to consider the various possible configurations of MOSFET and BJT amplifiers, and we will do that in the present section. To focus our attention on the salient features of the various configurations, we shall present them in their most simple, or “stripped-down,” version. Thus, we will not show the dc biasing arrangements, leaving the study of bias design to the next section. Finally, in Section 7.5 we will bring everything together and present practical discrete-circuit amplifiers, namely, amplifier circuits that can be constructed using discrete components. The study of integrated-circuit amplifiers begins in Chapter 8.
7.3.1 The Three Basic Configurations
There are three basic configurations for connecting a MOSFET or a BJT as an amplifier. Each of these configurations is obtained by connecting one of the device terminals to ground, thus creating a two-port network with the grounded terminal being common to the input and output ports. The resulting configurations are shown in Fig. 7.33(a–c) for the MOSFET and in Fig. 7.33(d–f) for the BJT.
In the circuit of Fig. 7.33(a) the source terminal is connected to ground, the input voltage signal vi is applied between the gate and ground, and the output voltage signal vo is taken between the drain and ground, across the resistance RD . This configuration, therefore, is called the grounded-source or common-source (CS) amplifier. It is by far the most popular MOS amplifier configuration, and we utilized it in Sections 7.1 and 7.2 to study MOS amplifier operation. A parallel set of remarks apply to the BJT counterpart, the grounded-emitter or common-emitter (CE) amplifier in Fig. 7.33(d).
The common-gate (CG) or grounded-gate amplifier is shown in Fig. 7.33(b), and its BJT counterpart, the common-base (CB) or grounded-base amplifier in Fig. 7.33(e). Here the gate (base) is grounded, the input signal vi is applied to the source (emitter), and the output signal vo is taken at the drain (collector) across the resistance RD (RC ). We encountered a CG amplifier in Example 7.4 and a CB amplifier in Example 7.7.
Finally, Fig. 7.33(c) shows the common drain (CD) or grounded-drain amplifier, and Fig. 7.31(f) shows its BJT counterpart, the common-collector (CC) or grounded collector amplifier.Herethedrain(collector)terminalisgrounded,theinputsignalvi isappliedbetween gate (base) and ground, and the output voltage vo is taken between the source (emitter) and ground, across a resistance RL. For reasons that will become apparent shortly, this pair of configurations is more commonly called the source follower and the emitter follower.
Our study of the three basic amplifier configurations of the MOSFET and of the BJT will reveal that each has distinctly different attributes, hence areas of application. As well, it will be shown that although each pair of configurations, (e.g., CS and CE), has many common attributes, important differences remain.
7.3 Basic Configurations 423
424 Chapter 7
Transistor Amplifiers
vo
Rvo vi
RD
viDvi Rv Lo
(a) Common Source (CS) (b) Common Gate (CG) (c) Common Drain (CD) or Source Follower
RC vo Rv vi
Co
v v RLvo
i i
(d) Common-Emitter (CE) (e) Common-Base (CB) (f) Common-Collector (CC) or Emitter Follower
Figure 7.33 The basic configurations of transistor amplifiers. (a)–(c) For the MOSFET; (d)–(f) for the BJT.
Our next step is to replace the transistor in each of the six circuits in Fig.7.33 by an appropriate equivalent-circuit model (from Tables 7.2 and 7.3) and analyze the resulting circuits to determine important characteristic parameters of the particular amplifier configuration. To simplify matters, we shall not include ro in the initial analysis. At the end of the section we will offer a number of comments about when to include ro in the analysis, and on the expected magnitude of its effect.
7.3.2 Characterizing Amplifiers
Before we begin our study of the different transistor amplifier configurations, we consider how to characterize the performance of an amplifier as a circuit building block. An introduction to this topic was presented in Section 1.5.
Figure 7.34(a) shows an amplifier fed with a signal source having an open-circuit voltage vsig and an internal resistance Rsig. These can be the parameters of an actual signal source or, in a cascade amplifier, the The ́venin equivalent of the output circuit of another amplifier stage preceding the one under study. The amplifier is shown with a load resistance RL connected to the output terminal. Here, RL can be an actual load resistance or the input resistance of a succeeding amplifier stage in a cascade amplifier.
Figure7.34(b) shows the amplifier circuit with the amplifier block replaced by its equivalent-circuitmodel.TheinputresistanceRin representstheloadingeffectoftheamplifier
Rsig
Rsig
ii io
7.3 Basic Configurations 425
vsig
vsig
vi
ii
RL vo
(a)
(b)
io
Ro
vi Rin
Av ovi
RL vo
vi=0
Ro
vx
RL ix
(c)
Figure7.34 Characterizationoftheamplifierasafunctionalblock:(a)Anamplifierfedwithavoltagesignal vsig having a source resistance Rsig, and feeding a load resistance RL; (b) equivalent-circuit representation of the circuit in (a); (c) determining the amplifier output resistance Ro.
input on the signal source. It is found from
Rin ≡ vi
ii
and together with the resistance Rsig forms a voltage divider that reduces vsig to the value vi
that appears at the amplifier input,
vi = Rin vsig (7.83) Rin +Rsig
Most of the amplifier circuits studied in this section are unilateral. That is, they do not contain internal feedback, and thus Rin will be independent of RL. However, in general Rin may depend on the load resistance RL. Indeed one of the six configurations studied in this section, the emitter follower, exhibits such dependence.
The second parameter in characterizing amplifier performance is the open-circuit voltage gain Av o , defined as
v
A ≡ o
vo vi RL=∞
426 Chapter 7
Transistor Amplifiers
The third and final parameter is the output resistance Ro . Observe from Fig. 7.34(b) that Ro is the resistance seen looking back into the amplifier output terminal with vi set to zero. Thus Ro can be determined, at least conceptually, as indicated in Fig. 7.34(c) with
Ro = vx ix
Because Ro is determined with vi = 0, the value of Ro does not depend on Rsig.
The controlled source Av ovi and the output resistance Ro represent the The ́venin equivalent
(7.84)
(7.85)
(7.86)
of the amplifier output circuit, and the output voltage vo can be found from vo = RL Avovi
RL +Ro
Thus the voltage gain of the amplifier proper, Av , can be found as
A ≡vo =A RL
v v voR+R
and the overall voltage gain, Gv ,
Gv ≡ vo
iLo
v sig
can be determined by combining Eqs. (7.83) and (7.85):
G= Rin A RL vR+RvoR+R
7.3.3 The Common-Source (CS) and Common-Emitter (CE) Amplifiers
in sig L o
Of the three basic transistor amplifier configurations, the common-source (common-emitter, for BJT), is the most widely used. Typically, in an amplifier formed by cascading a number of gain stages, the bulk of the voltage gain is obtained by using one or more common-source (or common-emitter, for BJT) stages in cascade.
Characteristic Parameters of the CS Amplifier Figure 7.35(a) shows a common-source amplifier (with the biasing arrangement omitted) fed with a signal source vsig having a source resistance Rsig . We wish to analyze this circuit to determine Rin , Av o , and Ro . For this purpose, we assume that RD is part of the amplifier; thus if a load resistance RL is connected to the amplifier output, RL appears in parallel with RD. In such a case, we wish to determine Av and Gv aswell.
Replacing the MOSFET with its hybrid-π model (without ro), we obtain the CS amplifier equivalent circuit in Fig. 7.35(b) for which, tracing the signal from input to output, we can write by inspection
Rin =∞ (7.87) vi =vsig
vgs =vi
vo =−gmvgsRD
Rsig
7.3 Basic Configurations 427
Rsig
v RD
vo
sig
vi
Rin
Ro
(a)
vgs vi gmvgs
vsig
RD vo
Ro = RD
Rin=
(b)
Figure 7.35 (a) Common-source amplifier fed with a signal vsig from a generator with a resistance Rsig. The bias circuit is omitted. (b) The common-source amplifier with the MOSFET replaced with its hybrid-π model.
Thus,
Avo ≡vo =−gmRD (7.88) vi
Ro =RD (7.89) If a load resistance RL is connected across RD, the voltage gain Av can be obtained from
A =A RL (7.90) v vo RL +Ro
where Av o is given by Eq. (7.88) and Ro by Eq. (7.89), or alternatively by simply adding RL in parallel with RD in Eq. (7.88), thus
Av =−gm(RD∥RL) (7.91)
The reader can easily show that the expression obtained from Eq. (7.90) is identical to that in Eq. (7.91). Finally, since Rin = ∞ and thus vi = vsig , the overall voltage gain Gv is equal to Av ,
G≡vo =−g(R∥R) (7.92) v vsig m D L
428 Chapter 7 Transistor Amplifiers
EXERCISE
7.21 A CS amplifier utilizes a MOSFET biased at ID = 0.25 mA with VOV = 0.25 V and RD = 20 k. The amplifier is fed with a signal source having Rsig = 100 k, and a 20-k load is connected to the output. Find Rin , Av o , Ro , Av , and Gv . If, to maintain reasonable linearity, the peak of the input sine-wave signal is limited to 10% of 2VOV , what is the peak of the sine-wave voltage at the output?
Ans. ∞; −40 V/V; 20 k; −20 V/V; −20 V/V; 1 V
Characteristic Parameters of the CE Amplifier Figure 7.36(a) shows a common-emitter amplifier. Its equivalent circuit, obtained by replacing the BJT with its hybrid-π model (without ro), is shown in Fig.7.36(b). The latter circuit can be analyzed to obtain the characteristic parameters of the CE amplifier. The analysis parallels that for the MOSFET above except that here we have the added complexity of a finite input resistance rπ . Tracing the signal through the amplifier from input to output, we can write by inspection
Rsig
vsig
vi
Rin
Rin =rπ
RC
(a)
vo
Ro
Rsig
vsig
RC
r
vo
(b)
Figure 7.36 (a) Common-emitter amplifier fed with a signal vsig from a generator with a resistance Rsig. The bias circuit is omitted. (b) The common-emitter amplifier circuit with the BJT replaced by its hybrid-π model.
Then we write
Thus,
vi= rπ vsig rπ +Rsig
vπ =vi
vo =−gmvπRC
A ≡vo=−gR vovi mC
(7.93)
(7.94) (7.95)
(7.96)
(7.97)
7.3 Basic Configurations 429
Ro =RC WithaloadresistanceRL connectedacrossRC,
Av =−gm(RC∥RL) andtheoverallvoltagegainGv canbefoundfrom
Thus,
G ≡ vo = vi vo v vsig vsig vi
Gv =− rπ gm(RC∥RL) rπ +Rsig
It is important to note here the effect of the finite input resistance (rπ ) in reducing the magnitude of the voltage gain by the voltage-divider ratio rπ /(rπ + Rsig ). The extent of the gain reduction depends on the relative values of rπ and Rsig. However, there is a compensating effect in the CE amplifier: gm of the BJT is usually much higher than the corresponding value of the MOSFET.
Example 7.8
ACEamplifierutilizesaBJTwithβ=100isbiasedatIC =1mAandhasacollectorresistanceRC =5k. Find Rin , Ro , and Av o . If the amplifier is fed with a signal source having a resistance of 5 k, and a load resistance RL = 5 k is connected to the output terminal, find the resulting Av and Gv . If vˆπ is to be limited to 5 mV, what are the corresponding vˆsig and vˆo with the load connected?
Solution
AtIC =1mA,
gm = IC = 1mA =40mA/V VT 0.025 V
rπ = β = 100 =2.5k gm 40 mA/V
430
Chapter 7 Transistor Amplifiers
Example 7.8 continued
The amplifier characteristic parameters can now be found as
Rin =rπ =2.5k
Avo =−gmRC
= −40 mA/V × 5 k = −200 V/V
Ro =RC =5k
With a load resistance RL = 5 k connected at the output, we can find Av by either of the following two
approaches:
or
A=A RL
v v o RL + Ro
=−200× 5 =−100V/V 5+5
Av =−gm(RC∥RL) =−40(5∥5)=−100V/V
TheoverallvoltagegainGv cannowbedeterminedas Gv = Rin Av
Rin
and the amplitude of the signal at the output will be
vˆsig = in
sig vˆπ =
×5=15mV
Rin +Rsig
= 2.5 × −100 = −33.3 V/V
2.5+5
If the maximum amplitude of vπ is to be 5 mV, the corresponding value of vˆsig will be
R +R
2.5+5 2.5
vˆo =Gvvˆsig =33.3×0.015=0.5V
7.3 Basic Configurations 431
EXERCISE
7.22 ThedesigneroftheamplifierinExample7.8decidestolowerthebiascurrenttohalfitsoriginalvalue in order to raise the input resistance and hence increase the fraction of vsig that appears at the input of the amplifier proper. In an attempt to maintain the voltage gain, the designer decides to double the value of RC. For the new design, determine Rin, Avo, Ro, Av, and Gv. If the peak amplitude of vπ is to be limited to 5 mV, what are the corresponding values of vˆsig and vˆo (with the load connected)? Ans. 5 k; −200 V/V; 10 k; −66.7 V/V; −33.3 V/V; 10 mV; 0.33 V
Comment: Although a larger fraction of the input signal reaches the amplifier input, linearity considerations cause the output signal to be in fact smaller than in the original design!
Final Remarks
1. The CS and CE amplifiers are the most useful of all transistor amplifier configurations. They exhibit a moderate to high input resistance (infinite for the CS), a moderate to high output resistance, and reasonably high voltage gain.
2. The input resistance of the CE amplifier, Rin = rπ = β/gm, is inversely proportional to the dc bias current IC. To increase Rin one is tempted to lower the bias current IC; however, this also lowers gm and hence the voltage gain. This is a significant design trade-off. If a much higher input resistance is desired, then a modification of the CE configuration (to be discussed in Section 7.3.4) can be applied, or an emitter-follower stage can be inserted between the signal source and the CE amplifier (see Section 7.3.6).
3. Reducing RD or RC to lower the output resistance of the CS or CE amplifier, respectively, is usually not a viable proposition because the voltage gain is also reduced. Alternatively, if a very low output resistance (in the ohms or tens-of-ohms range) is needed, a source-follower or an emitter-follower stage can be utilized between the output of the CS or CE amplifier and the load resistance (see Section 7.3.6).
4. Although the CS and the CE configurations are the workhorses of transistor amplifiers, both suffer from a limitation on their high-frequency response. As will be shown in Chapter 10, combining the CS (CE) amplifier with a CG (CB) amplifier can extend the bandwidth considerably. The CG and CB amplifiers are studied in Section 7.3.5.
7.3.4 The Common-Source (Common-Emitter) Amplifier with a Source (Emitter) Resistance
ItisoftenbeneficialtoinsertaresistanceRs (aresistanceRe)inthesourcelead(theemitterlead) of a common-source (common-emitter) amplifier. Figure 7.37(a) shows a CS amplifier with a resistance Rs in its source lead. The corresponding small-signal equivalent circuit is shown
432 Chapter 7
Transistor Amplifiers
Figure 7.37 The CS amplifier with a source resistance Rs : (a) circuit without bias details; (b) equivalent circuit with the MOSFET represented by its T model.
in Fig. 7.37(b), where we have utilized the T model for the MOSFET. The T model is used in preference to the hybrid-π model because it makes the analysis in this case considerably simpler. In general, whenever a resistance is connected in the source lead, the T model is preferred. The source resistance then simply appears in series with the model resistance 1/gm and can be added to it.
From Fig. 7.37(b) we see that as expected, the input resistance Rin is infinite and thus vi = vsig. Unlike the CS amplifier, however, here only a fraction of vi appears between gate and source as v gs . The voltage divider composed of 1/gm and Rs , which appears across the amplifier input, can be used to determine vgs, as follows:
v =v 1/gm = vi (7.98) gs i 1/gm +Rs 1+gmRs
Thus we can use the value of Rs to control the magnitude of the signal vgs and thereby ensure that vgs does not become too large and cause unacceptably high nonlinear distortion. This is the first benefit of including resistor Rs. Other benefits will be encountered in later sections and chapters. For instance, it will be shown in Chapter 10 that Rs causes the useful bandwidth of the amplifier to be extended. The mechanism by which Rs causes such improvements in amplifierperformanceisnegativefeedback.ToseehowRs introducesnegativefeedback,refer to Fig. 7.37(a): If with vsig and hence vi kept constant, the drain current increases for some
reason, the source current also will increase, resulting in an increased voltage drop across Rs. Thus the source voltage rises, and the gate-to-source voltage decreases. The latter effect causes the drain current to decrease, counteracting the initially assumed change, an indication of the presence of negative feedback. In Chapter 11 we shall study negative feedback formally. There we will learn that the improvements that negative feedback provides are obtained at the expense of a reduction in gain. We will now show this to be the case in the circuit of Fig. 7.37.
The output voltage vo is obtained by multiplying the controlled-source current i by RD, vo =−iRD
The current i in the source lead can be found by dividing vi by the total resistance in the source,
vg i= i = m vi
(7.99)
(7.100)
(7.101)
7.3 Basic Configurations 433
1/gm +Rs 1+gmRs Thus, the voltage gain Av o can be found as
which can also be expressed as
Avo≡vo =− gmRD vi 1+gmRs
Avo =− RD 1/gm +Rs
Equation (7.100) indicates that including the resistance Rs reduces the voltage gain by the factor (1 + gm Rs ). This is the price paid for the improvements that accrue as a result of Rs . It is interesting to note that in Chapter 11, we will find that the factor (1 + gm Rs ) is the “amount of negative feedback” introduced by Rs . It is also the same factor by which linearity, bandwidth, and other performance parameters improve. Because of the negative-feedback action of Rs it is known as a source-degeneration resistance.
There is another useful interpretation of the expression for the drain current in Eq. (7.99): The quantity between brackets on the right-hand side can be thought of as the “effective transconductance with Rs included.” Thus, including Rs reduces the transconductance by the factor (1+gmRs). This, of course, is simply the result of the fact that only a fraction 1/(1+gmRs)ofvi appearsasvgs (seeEq.7.98).
The alternative gain expression in Eq. (7.101) has a powerful and insightful interpretation: The voltage gain between gate and drain is equal to the ratio of the total resistance in the drain (RD) to the total resistance in the source (1/gm +Rs),
Voltage gain from gate to drain = − Total resistance in drain (7.102) Total resistance in source
This is a general expression. For instance, setting Rs = 0 in Eq. (7.101) yields Av o of the CS amplifier.
434 Chapter 7
Transistor Amplifiers
Finally, we consider the situation of a load resistance RL connected at the output. We can obtain the gain Av using the open-circuit voltage gain Av o together with the output resistance Ro, which can be found by inspection to be
Ro =RD
Alternatively,Av canbeobtainedbysimplyreplacingRD inEq.(7.101)or(7.100)by(RD∥RL);
thus,
or
Av =−gm(RD∥RL) 1+gmRs
Av =− RD∥RL 1/gm +Rs
(7.103)
(7.104)
Observe that Eq.(7.104) is a direct application of the ratio of total resistance rule of Eq. (7.102). Finally, note that because Rin is infinite, vi = vsig and the overall voltage gain Gv is equal to Av .
EXERCISE
7.23 In Exercise 7.21 we applied an input signal vsig of 50 mV peak and obtained an output signal of approximately 1 V peak. Assume that for some reason we now have an input signal vsig that is 0.2 V peak and that we wish to modify the circuit to keep vgs unchanged, and thus keep the nonlinear distortionfromincreasing.WhatvalueshouldweuseforRs?WhatvalueofGv willresult?Whatwill the peak signal at the output become? Assume ro = ∞.
Ans. 1.5 k; −5 V/V; 1 V
We next turn our attention to the BJT case. Figure 7.38(a) shows a CE amplifier with a resistance Re in its emitter. The corresponding equivalent circuit, utilizing the T model, is shown in Fig. 7.38(b). Note that in the BJT case also, as a general rule, the T model results in a simpler analysis and should be employed whenever there is a resistance in series with the emitter.
To determine the amplifier input resistance Rin , we note from Fig. 7.38(b) that Rin ≡ vi
where
and
ib ib =(1−α)ie =
ie
β+1
(7.105)
(7.106)
ie = vi
re +Re
7.3 Basic Configurations 435
Rsig
vsig vi Re Rin
RC
vo
Ro
ie
ie re
Rsig
B ib
C ic
RC
vo
Ro
vsig
vi E Re
(b)
Rin
Figure 7.38 The CE amplifier with an emitter resistance Re; (a) circuit without bias details; (b) equivalent circuit with the BJT replaced with its T model.
Thus,
Rin = (β + 1)(re + Re) (7.107)
This is a very important result. It states that the input resistance looking into the base is (β + 1) times the total resistance in the emitter, and is known as the resistance-reflection rule. The factor (β + 1) arises because the base current is 1/(β + 1) times the emitter current. The expres- sion for Rin in Eq. (7.107) shows clearly that including a resistance Re in the emitter can sub- stantially increase Rin , a very desirable result. Indeed, the value of Rin is increased by the ratio
Rin(withRe included)=(β+1)(re+Re) Rin (without Re ) (β + 1)re
=1+ Re ≃1+gmRe (7.108) re
Thus the circuit designer can use the value of Re to control the value of Rin.
436 Chapter 7
Transistor Amplifiers
To determine the voltage gain Av o , we see from Fig. 7.38(b) that vo =−icRC
=−αieRC Substituting for ie from Eq. (7.106) gives
Avo =−α RC (7.109) re +Re
This is a very useful result: It states that the gain from base to collector is α times the ratio of the total resistance in the collector to the total resistance in the emitter (in this case, re + Re ),
Voltage gain from base to collector = −α Total resistance in collector (7.110) Total resistance in emitter
This is the BJT version of the MOSFET expression in Eq. (7.102) except that here we have the additional factor α. This factor arises because ic = αie, unlike the MOSFET case where id = is . Usually, α ≃ 1 and can be dropped from Eq. (7.110).
The open-circuit voltage gain in Eq. (7.109) can be expressed alternatively as
Thus,
Avo =−α RC
re 1+Re/re
Avo=− gmRC ≃− gmRC 1+Re/re 1+gmRe
(7.111)
Thus,includingRe reducesthevoltagegainbythefactor(1+gmRe),whichisthesamefactor by which Rin is increased. This points out an interesting trade-off between gain and input resistance, a trade-off that the designer can exercise through the choice of an appropriate value for Re.
The output resistance Ro can be found from the circuit in Fig. 7.38(b) by inspection: Ro =RC
If a load resistance RL is connected at the amplifier output, Av can be found as
A=A RL
v v o RL + Ro
=−α RC RL re+Re RL+RC
= −α RC ∥ RL re +Re
(7.112)
which could have been written directly using Eq. (7.110). The overall voltage gain Gv can now be found:
Gv = Rin ×−αRC∥RL Rin +Rsig re +Re
SubstitutingforRin fromEq.(7.107)andreplacingαwithβ/(β+1)resultsin
Gv =−β RC∥RL (7.113)
Careful examination of this expression reveals that the denominator comprises the total resistance in the base circuit [recall that (β + 1)(re + Re ) is the reflection of (re + Re ) from the emitter side to the base side]. Thus the expression in Eq. (7.113) states that the voltage gain from base to collector is equal to β times the ratio of the total resistance in the collector to the total resistance in the base. The factor β appears because it is the ratio of the collector current to the base current. This general and useful expression has no counterpart in the MOS case. We observe that the overall voltage gain Gv is lower than the value without Re, namely,
Gv =−β RC∥RL (7.114) Rsig + (β + 1)re
because of the additional term (β + 1)Re in the denominator. The gain, however, is now less sensitive to the value of β, a desirable result because of the typical wide variability in the value of β.
Another important consequence of including the resistance Re in the emitter is that it enables the amplifier to handle larger input signals without incurring nonlinear distortion. This is because only a fraction of the input signal at the base, vi, appears between the base and the emitter. Specifically, from the circuit in Fig. 7.38(b), we see that
vπ= re ≃ 1 (7.115) vi re +Re 1+gmRe
Thus, for the same v π , the signal at the input terminal of the amplifier, v i , can be greater than for the CE amplifier by the factor (1 + gm Re ).
To summarize, including a resistance Re in the emitter of the CE amplifier results in the following characteristics:
1. The input resistance Rin is increased by the factor (1 + gm Re ).
2. The voltage gain from base to collector, Av , is reduced by the factor (1 + gm Re ).
3. For the same nonlinear distortion, the input signal vi can be increased by the factor
(1 + gmRe).
4. The overall voltage gain is less dependent on the value of β.
5. The high-frequency response is significantly improved (as we shall see in Chapter 10).
With the exception of gain reduction, these characteristics represent performance improve- ments. Indeed, the reduction in gain is the price paid for obtaining the other performance improvements. In many cases this is a good bargain; it is the underlying philosophy for the use of negative feedback. That the resistance Re introduces negative feedback in the amplifier circuit can be verified by utilizing a procedure similar to that we used above for the MOSFET case. In Chapter 11, where we shall study negative feedback formally, we will find that the factor (1 + gm Re ), which appears repeatedly, is the “amount of negative feedback” introduced by Re . Finally, we note that the negative-feedback action of Re gives it the name emitter degeneration resistance.
7.3 Basic Configurations 437
Rsig +(β+1)(re +Re)
438 Chapter 7 Transistor Amplifiers
Example 7.9
For the CE amplifier specified in Example 7.8, what value of Re is needed to raise Rin to a value four timesthatofRsig?WithRe included,findAvo,Ro,Av,andGv.Also,ifvˆπ islimitedto5mV,whatarethe corresponding values of vˆsig and vˆo?
Solution
ToobtainRin =4Rsig =4×5=20k,therequiredRe isfoundfrom
With β = 100,
Thus,
20=(β+1) re +Re re + Re ≃ 200
Re =200−25=175 Avo=−α RC
re +Re
≃− 5000 =−25V/V
25+175
Ro = RC = 5 k (unchanged)
A =A RL =−25× 5 =−12.5V/V v v o RL + Ro 5 + 5
Gv = Rin Av =− 20 ×12.5=−10V/V Rin +Rsig 20+5
Forvˆπ =5mV,
r +R vˆ=vˆe e
i π re
=5 1+175 =40mV 25
vˆ =vˆRin+Rsig sig i Rin
v
=401+5 =50mV 20
vˆ=vˆ ×G o sig v
= 50 × 10 = 500 mV = 0.5 V
Thus, while G has decreased to about a third of its original value, the amplifier is able to produce as
large an output signal as before for the same nonlinear distortion.
7.3 Basic Configurations 439
EXERCISE
7.24 Show that with Re included, and vπ limited to a maximum value vˆπ , the maximum allowable input signal, vˆsig, is given by
RR vˆsig=vˆπ 1+e+sig
re rπ
If the transistor is biased at IC = 0.5 mA and has a β of 100, what value of Re is needed to permit an input signal vˆsig of 100 mV from a source with a resistance Rsig = 10 k while limiting vˆπ to 10 mV? What is Rin for this amplifier? If the total resistance in the collector is 10 k, what Gv value results? Ans. 350 ; 40.4 k; −19.8 V/V
7.3.5 The Common-Gate (CG) and the Common-Base (CB) Amplifiers
Figure 7.39(a) shows a common-gate amplifier with the biasing circuit omitted. The amplifier is fed with a signal source characterized by vsig and Rsig. Since Rsig appears in series with the source, it is more convenient to represent the transistor with the T model than with the π model. Doing this, we obtain the amplifier equivalent circuit shown in Fig. 7.39(b).
From inspection of the equivalent circuit of Fig. 7.39(b), we see that the input resistance Rin = 1 (7.116)
gm
Figure 7.39 (a) Common-gate (CG) amplifier with bias arrangement omitted. (b) Equivalent circuit of the CG amplifier with the MOSFET replaced with its T model.
440 Chapter 7
Transistor Amplifiers
This should have been expected, since we are looking into the source and the gate is grounded. Typically 1/gm is a few hundred ohms; thus the CG amplifier has a low input resistance.
To determine the voltage gain Av o , we write at the drain node vo =−iRD
and substitute for the source current i from
i=− vi
to obtain
1/gm
A ≡vo=gR
vo vi mD
(7.117)
which except for the positive sign is identical to the expression for Av o of the CS amplifier. The output resistance of the CG circuit can be found by inspection of the circuit in
Fig. 7.39(b) as
Ro = RD (7.118)
which is the same as in the case of the CS amplifier.
Although the gain of the CG amplifier proper has the same magnitude as that of the CS
amplifier, this is usually not the case as far as the overall voltage gain is concerned. The low input resistance of the CG amplifier can cause the input signal to be severely attenuated. Specifically,
vi = vsig
Rin = 1/gm (7.119) Rin + Rsig 1/gm + Rsig
from which we see that except for situations in which Rsig is on the order of 1/gm, the signal transmission factor v i /v sig can be very small and the overall voltage gain Gv can be correspondingly small. Specifically, with a resistance RL connected at the output
Thus,
Gv = 1/gm [gm(RD∥RL)] Rsig +1/gm
Gv = (RD∥RL) (7.120) Rsig +1/gm
Observe that the overall voltage gain is simply the ratio of the total resistance in the drain circuit to the total resistance in the source circuit. If Rsig is of the same order as RD and RL , Gv will be very small.
Because of its low input resistance, the CG amplifier alone has very limited application. One such application is to amplify high-frequency signals that come from sources with relatively low resistances. These include cables, where it is usually necessary for the input resistance of the amplifier to match the characteristic resistance of the cable. As will be shown in Chapter 10, the CG amplifier has excellent high-frequency response. Thus it can be combined with the CS amplifier in a very beneficial way that takes advantage of the best features of each of the two configurations. A very significant circuit of this kind will be studied in Chapter 8.
Rin = re = α ≃ 1/gm gm
Avo = αRC =gmRC re
(7.121)
(7.122)
7.3 Basic Configurations 441
EXERCISE
7.25 A CG amplifier is required to match a signal source with Rsig = 100 . At what current ID should the MOSFET be biased if it is operated at an overdrive voltage of 0.20 V? If the total resistance in the drain circuit is 2 k, what overall voltage gain is realized?
Ans. 1 mA; 10 V/V
Very similar results can be obtained for the CB amplifier shown in Fig.7.40(a). Specifically, from the equivalent circuit in Fig. 7.40(b) we can find
Ro = RC
and with a load resistance RL connected to the output, the overall voltage gain is given by
Gv≡vo =αRC∥RL
(7.123)
(7.124)
vsig
Rsig +re
RC vo
RC
vo Ro
Rsig
re ie
Rsig
vsig
vi
Rin
vsig
vi
(a)
(b)
Figure 7.40 (a) CB amplifier with bias details omitted; (b) amplifier equivalent circuit with the BJT represented by its T model.
442 Chapter 7
Transistor Amplifiers
Since α ≃ 1, we see that as in the case of the CG amplifier, the overall voltage gain is simply the ratio of the total resistance in the collector to the total resistance in the emitter. We also note that the overall voltage gain is almost independent of the value of β (except through the small dependence of α on β), a desirable property. Observe that for Rsig of the same order as RC andRL,thegainwillbeverysmall.
In summary, the CB and CG amplifiers exhibit a very low input resistance (1/gm), an open-circuit voltage gain that is positive and equal in magnitude to that of the CE (CG) amplifier (gmRC or gmRD), and, like the CE (CS) amplifier, a relatively high output resistance (RC or RD). Because of its very low input resistance, the CB (CG) circuit alone is not attractive as a voltage amplifier except in specialized applications, such as the cable amplifier mentioned above. The CB (CG) amplifier has excellent high-frequency performance, which as we shall see in Chapters 8 and 10, makes it useful in combination with other circuits in the implementation of high-frequency amplifiers.
EXERCISES
7.26 Consider a CB amplifier utilizing a BJT biased at IC = 1 mA and with RC = 5 k. Determine Rin , Av o , and Ro . If the amplifier is loaded in RL = 5 k, what value of Av results? What Gv is obtained if Rsig = 5 k?
Ans. 25 ; 200 V/V; 5 k; 100 V/V; 0.5 V/V
7.27 A CB amplifier is required to amplify a signal delivered by a coaxial cable having a characteristic resistance of 50 . What bias current IC should be utilized to obtain Rin that is matched to the cable resistance?ToobtainanoverallvoltagegainofGv of40V/V,whatshouldthetotalresistanceinthe collector (i.e., RC ∥RL) be?
Ans. 0.5 mA; 4 k
7.3.6 The Source and Emitter Followers
The last of the basic transistor amplifier configurations is the common-drain (common-collector) amplifier, an important circuit that finds application in the design of both small-signal amplifiers and amplifiers that are required to handle large signals and deliver substantial amounts of signal power to a load. This latter variety will be studied in Chapter 12. The common-drain amplifier is more commonly known as the source follower, and the common-collector amplifier is more commonly known as the emitter follower. The reason behind these names will become apparent shortly.
The Need for Voltage Buffers Before embarking on the analysis of the source and the emitter followers, it is useful to look at one of their more common applications. Consider the situation depicted in Fig. 7.41(a). A signal source delivering a signal of reasonable strength (1 V) with an internal resistance of 1 M is to be connected to a 1-k load resistance. Connecting the source to the load directly as in Fig. 7.41(b) would result in severe attenuation
vsig=1V
Rsig =1 M
(a)
RL
1 k
v = sig
1V
Rsig 1 M
RL v 1 k
o 1 mV
7.3 Basic Configurations 443
Rsig = 1 M
1V
Ro =100 Avo1
(b)
v = 1 V sig
RL
1 k
vo 0.9 V
Figure 7.41 Illustrating the need for a unity-gain voltage buffer amplifier.
Rin very large (c)
of the signal; the signal appearing across the load will be only 1/(1000 + 1) of the input signal, or about 1 mV. An alternative course of action is suggested in Fig. 7.41(c). Here we have interposed an amplifier between the source and the load. Our amplifier, however, is unlike the amplifiers we have been studying in this chapter thus far; it has a voltage gain of only unity. This is because our signal is already of sufficient strength and we do not need to increase its amplitude. Note, however, that our amplifier has a very high input resistance, thus almost all of vsig (i.e., 1 V) will appear at the input of the amplifier proper. Since the amplifier has a low output resistance (100 ), 90% of this signal (0.9 V) will appear at the output, obviously a very significant improvement over the situation without the amplifier. As will be seen next, the source follower can easily implement the unity-gain buffer amplifier shown in Fig. 7.41(c).
Characteristic Parameters of the Source Follower Figure 7.42(a) shows a source follower with the bias circuit omitted. The source follower is fed with a signal generator (v sig , Rsig ) and has a load resistance RL connected between the source terminal and ground. We shall assume that RL includes both the actual load and any other resistance that may be present between the source terminal and ground (e.g., for biasing purposes). Normally, the actual load resistance would be much lower in value than such other resistances and thus would dominate.
Since the MOSFET has a resistance RL connected in its source terminal, it is most convenient to use the T model, as shown in Fig. 7.40(b). From the latter circuit we can write by inspection
Rin =∞
444 Chapter 7
Transistor Amplifiers
vsig
Rsig
vi
(a)
0
RL vo
Rin
Rsig
Ro
i
i
1
gm
v R=1 sigv ogm
i
Rin =
(b)
RL vo
Figure 7.42 (a) Common-drain amplifier or source follower with the bias circuit omitted. (b) Equivalent circuit of the source follower obtained by replacing the MOSFET with its T model.
and obtain Av from the voltage divider formed by 1/gm and RL as A ≡vo = RL
(7.125)
Setting RL = ∞ we obtain
v vi RL +1/gm Avo =1
(7.126) The output resistance Ro is found by setting vi = 0 (i.e., by grounding the gate). Now looking
back into the output terminal, excluding RL , we simply see 1/gm , thus
Ro = 1/gm (7.127)
The unity open-circuit voltage gain together with Ro in Eq. (7.127) can be used to find Av when a load resistance RL is connected. The result is simply the expression in Eq. (7.125).
Finally, because of the infinite Rin, vi = vsig, and the overall voltage gain is
Gv =Av = RL (7.128)
RL +1/gm
Thus Gv will be lower than unity. However, because 1/gm is usually low, the voltage gain can be close to unity. The unity open-circuit voltage gain in Eq. (7.126) indicates that the voltage at the source terminal will follow that at the input, hence the name source follower.
In conclusion, the source follower features a very high input resistance (ideally, infinite), a relatively low output resistance (1/gm), and an open-circuit voltage gain that is near unity (ideally, unity). Thus the source follower is ideally suited for implementing the unity-gain voltage buffer of Fig. 7.41(c). The source follower is also used as the output (i.e., last) stage in a multistage amplifier, where its function is to equip the overall amplifier with a low output resistance, thus enabling it to supply relatively large load currents without loss of gain (i.e., with little reduction of output signal level). The design of output stages is studied in Chapter 12.
EXERCISES
D7.28 ItisrequiredtodesignasourcefollowerthatimplementsthebufferamplifiershowninFig.7.41(c). IftheMOSFETisoperatedwithanoverdrivevoltageVOV =0.25V,atwhatdraincurrentshouldit be biased? Find the output signal amplitude and the signal amplitude between gate and source. Ans. 1.25 mA; 0.91 V; 91 mV
D7.29 A MOSFET is connected in the source-follower configuration and employed as the output stage of a cascade amplifier. It is required to provide an output resistance of 200 . If the MOSFET has kn′ = 0.4 mA/V2 and is operated at VOV = 0.25 V, find the required W/L ratio. Also specify the dc bias current ID . If the amplifier load resistance varies over the range 1 k to 10 k, what is the rangeofGv ofthesourcefollower?
Ans. 50; 0.625 mA; 0.83 V/V to 0.98 V/V
Characteristic Parameters of the Emitter Follower Although the emitter follower does not have an infinite input resistance (as in the case of the source follower), it is still widely used as a voltage buffer. In fact, it is a very versatile and popular circuit. We will therefore study it in some detail.
Figure 7.43(a) shows an emitter follower with the equivalent circuit shown in Fig. 7.43(b). The input resistance Rin is found from
Rin = vi ib
Substituting for ib = ie /(β + 1) where ie is given by
ie= vi
re +RL
7.3 Basic Configurations 445
446 Chapter 7
Transistor Amplifiers
Rsig
vsig
Rin
vi
RL
vo
Ro
(a)
Figure7.43 (a)Common-collectoramplifieroremitterfollowerwiththebiascircuitomitted.(b)Equivalent circuit obtained by replacing the BJT with its T model.
we obtain
Rin =(β+1)(re +RL) (7.129)
a result that we could have written directly, utilizing the resistance-reflection rule. Note that as expected the emitter follower takes the low load resistance and reflects it to the base side, where the signal source is, after increasing its value by a factor (β+1). It is this impedance transformation property of the emitter follower that makes it useful in
vsig
vi
Rsig
ie
re
(b)
RL
vo
connecting a low-resistance load to a high-resistance source, that is, to implement a buffer amplifier.
The voltage gain Av is given by
SettingRL =∞yieldsAvo,
Av≡vo= RL
vi RL +re
Avo =1
(7.130)
(7.131)
7.3 Basic Configurations 447
Thus, as expected, the open-circuit voltage gain of the emitter follower proper is unity, which means that the signal voltage at the emitter follows that at the base, which is the origin of the name “emitter follower.”
To determine Ro, refer to Fig.7.43(b) and look back into the emitter (i.e., behind or excluding RL ) while setting v i = 0 (i.e., grounding the base). You will see re of the BJT, thus
Ro = re (7.132) This result together with Av o = 1 yields Av in Eq. (7.130), thus confirming our earlier analysis.
We next determine the overall voltage gain Gv , as follows:
vi = Rin vsig Rin +Rsig
= (β+1)(re +RL) (β +1)(re +RL)+Rsig
G≡vo =vi ×A v vsig vsig v
SubstitutingforAv fromEq.(7.130)resultsin
Gv = (β+1)RL (7.133)
This equation indicates that the overall gain, though lower than one, can be close to one if (β+1)RL islargerorcomparableinvaluetoRsig.Thisagainconfirmstheactionoftheemitter follower in delivering a large proportion of vsig to a low-valued load resistance RL even though Rsig can be much larger than RL . The key point is that RL is multiplied by (β + 1) before it is “presented to the source.” Figure 7.44(a) shows an equivalent circuit of the emitter follower obtained by simply reflecting re and RL to the base side. The overall voltage gain Gv ≡ vo/vsig can be determined directly and very simply from this circuit by using the voltage divider rule. The result is the expression for Gv already given in Eq. (7.133).
Dividing all resistances in the circuit of Fig. 7.44(a) by β + 1 does not change the voltage ratio vo/vsig. Thus we obtain another equivalent circuit, shown in Fig. 7.44(b), that can be used to determine Gv ≡ vo/vsig of the emitter follower. A glance at this circuit reveals that it is simply the equivalent circuit obtained by reflecting vsig and Rsig from the base side to the emitter side. In this reflection, vsig does not change, but Rsig is divided by β + 1. Thus, we
(β +1)RL +(β +1)re +Rsig
448 Chapter 7
Transistor Amplifiers
Rsig
vsig
re
vsig
v RLv
oo
(a)
(b)
Figure 7.44 Simple equivalent circuits for the emitter follower obtained by (a) reflecting re and RL to the base side, and (b) reflecting vsig and Rsig to the emitter side. Note that the circuit in (b) can be obtained from that in (a) by simply dividing all resistances by (β + 1).
either reflect to the base side and obtain the circuit in Fig. 7.44(a) or reflect to the emitter side and obtain the circuit in Fig. 7.44(b). From the latter, Gv can be found as
Gv≡vo = RL (7.134) vsig RL +re +Rsig/(β+1)
Observe that this expression is the same as that in Eq. (7.133) except for dividing both the numerator and denominator by β + 1.
TheexpressionforGv inEq.(7.134)hasaninterestinginterpretation:Theemitterfollower reducesRsig bythefactor(β+1)before“presentingittotheloadresistanceRL”:animpedance transformation that has the same buffering effect.
At this point it is important to note that although the emitter follower does not provide voltage gain it has a current gain of β + 1.
Thévenin Representation of the Emitter-Follower Output A more general representation of the emitter-follower output is shown in Fig. 7.45(a). Here Gv o is the overall open-circuit voltage gain that can be obtained by setting RL = ∞ in the circuit of Fig. 7.44(b), as illustrated in Fig. 7.45(b). The result is Gv o = 1. The output resistance Rout is different from Ro. To determine Rout we set vsig to zero (rather than setting vi to zero). Again we can use the equivalent circuit in Fig. 7.44(b) to do this, as illustrated in Fig. 7.45(c). We see that
Rout = re + Rsig (7.135) β+1
Finally, we show in Fig. 7.45(d) the emitter-follower circuit together with its Rin and Rout . Observe that Rin is determined by reflecting re and RL to the base side (by multiplying their values by β + 1). To determine Rout , grab hold of the emitter and walk (or just look!) backward while v sig = 0. You will see re in series with Rsig , which because it is in the base must be divided by (β + 1).
We note that unlike the amplifier circuits we studied earlier, the emitter follower is not unilateral. This is manifested by the fact that Rin depends on RL and Rout depends on Rsig.
7.3 Basic Configurations 449
vsig
Rsig
re
re
(b)
re
(d)
Rsig
E vsig
RL
(c)
Figure 7.45 (a) The ́venin representation of the output of the emitter follower. (b) Obtaining Gvo from the equivalent circuit in Fig. 7.44(b). (c) Obtaining Rout from the equivalent circuit in Fig. 7.44(b) with vsig set to zero. (d) The emitter follower with Rin and Rout determined simply by looking into the input and output terminals, respectively.
Example 7.10
It is required to design an emitter follower to implement the buffer amplifier of Fig. 7.46(a). Specify the required bias current IE and the minimum value the transistor β must have. Determine the maximum allowed value of vsig if vπ is to be limited to 5 mV in order to obtain reasonably linear operation. With vsig = 200 mV, determine the signal voltage at the output if RL is changed to 2 k, and to 0.5 k.
Ro
10
Rsig vsig
200 mV
100 k
Rin
Avo 1
(a)
RL
1 k
vo
Figure 7.46 Circuit for Example 7.10.
100 k
450
Chapter 7 Transistor Amplifiers
Example 7.10 continued
vsig 200 mV
Rsig
Rin
100 k
100 k
Ro 10 vo
RL 1 k
Figure 7.46 continued Solution
The emitter-follower circuit is shown in Fig. 7.46(b). To obtain Ro = 10 , we bias the transistor to obtain re = 10 . Thus,
(b)
The input resistance Rin will be
10 = VT IE
IE =2.5mA
Rin =(β+1) re +RL 100=(β+1)(0.01+1)
Thus, the BJT should have a β with a minimum value of 98. A higher β would obviously be beneficial. The overall voltage gain can be determined from
G ≡ vo = RL
v vsig Assumingβ=100,thevalueofGv obtainedis
Gv =0.5
RL +re + Rsig (β+1)
Thus when vsig = 200 mV, the signal at the output will be 100 mV. Since the 100 mV appears across the 1-k load, the signal across the base–emitter junction can be found from
vπ = vo ×re RL
= 100 ×10=1mV 1000
If vˆπ = 5 mV then vsig can be increased by a factor of 5, resulting in vˆsig = 1 V.
To obtain vo as the load is varied, we use the The ́venin equivalent of the emitter follower, shown in
Fig. 7.45(a) with Gv o = 1 and
to obtain
ForRL =2k,
andforRL =0.5k,
Rout = Rsig +re =100+0.01=1k β+1 101
v=v RL
o sig RL +Rout
vo =200mV× 2 =133.3mV 2+1
vo =200mV× 0.5 0.5+1
=66.7mV
7.3 Basic Configurations 451
EXERCISE
7.30 An emitter follower utilizes a transistor with β = 100 and is biased at IC = 5 mA. It operates between a source having a resistance of 10k and a load of 1k. Find Rin, Gvo, Rout, and Gv. What is the peak amplitude of vsig that results in vπ having a peak amplitude of 5 mV? Find the resulting peak amplitude at the output.
Ans. 101.5 k; 1 V/V; 104 ; 0.91 V/V; 1.1 V; 1 V
452 Chapter 7
Transistor Amplifiers
7.3.7 Summary Tables and Comparisons
For easy reference and to enable comparisons, we present in Tables 7.4 and 7.5 the formulas for determining the characteristic parameters for the various configurations of MOSFET and BJT amplifiers, respectively. In addition to the remarks made throughout this section about the characteristics and areas of applicability of the various configurations, we make the following concluding points:
1. MOS amplifiers provide much higher, ideally infinite input resistances (except, of course, for the CG configuration). This is a definite advantage over BJT amplifiers.
2. BJTs exhibit higher gm values than MOSFETs, resulting in higher gains.
3. For discrete-circuit amplifiers—that is, those that are assembled from discrete components on a printed-circuit board (PCB)—the BJT remains the device of choice. This is because discrete BJTs are much easier to handle physically than discrete MOSFETs and, more important, a very wide variety of discrete BJTs is available commercially. The remainder of this chapter is concerned with discrete-circuit
amplifiers.
4. Integrated-circuit (IC) amplifiers predominantly use MOSFETs, although BJTs are
utilized in certain niche areas. Chapters 8 to 13 are mainly concerned with IC
amplifiers.
5. The CS and CE configurations are the best suited for realizing the bulk of the gain
required in an amplifier. Depending on the magnitude of the gain required, either a
single stage or a cascade of two or three stages can be used.
6. Including a resistance Rs in the source of the CS amplifier (a resistance Re in the
emitter of the CE amplifier) provides a number of performance improvements at the expense of gain reduction.
Table 7.4 Characteristics of MOSFET Amplifiers
Amplifier type
Common source (Fig. 7.35)
Rin Av o ∞ −gm RD
Characteristicsa
Ro Av Gv
RD −gm RD ∥ RL −gm RD ∥ RL
R −gm RD ∥RL −gm RD ∥RL
Common source with R
s
(Fig. 7.37)
∞ −
1RL RL
gm RL +1/gm RL +1/gm
Commongate(Fig.7.39)
Source follower (Fig. 7.42)
a For the interpretation of Rin, Avo, and Ro, refer to Fig. 7.34(b).
gmRD
1+gR D 1+gR 1+gR msmsms
1 g R R g R ∥R
m sig m
RD∥RL gmD DmDLR+1/g
∞ 1
− RD∥RL 1/gm +Rs
− RD∥RL 1/gm +Rs
gmRC
(β+1)re+Re
−1+g R m e
RC
1+g R me
−αRC∥RL re +Re
Commonbase r gR R e mC C
αRC∥RL mCL Rsig+re
(Fig. 7.40)
Emitter follower (Fig. 7.43)
α
RC ∥RL re
(β+1)r +R eL
1
r
RL
e RL+re
RL
RL +re +Rsig/(β +1)
Gvo =1 Rout=re+ Rsig
β+1
b Setting β = ∞ (α = 1) and replacing re with 1/gm , RC with RD , and Re with Rs results in the corresponding formulas for MOSFET amplifiers
a For the interpretation of Rm , Av o , and Ro refer to Fig. 7.34. (Table 7.4).
7. The low input resistance of the CG and CB amplifiers makes them useful only in specific applications. As we shall see in Chapter 10, these two configurations exhibit a much better high-frequency response than that available from the CS and CE amplifiers. This makes them useful as high-frequency amplifiers, especially when combined with the CS or CE circuit. We shall study one such combination in Chapter 8.
8. The source follower (emitter follower) finds application as a voltage buffer for connecting a high-resistance source to a low-resistance load, and as the output stage in a multistage amplifier, where its purpose is to equip the amplifier with a low output resistance.
7.3.8 When and How to Include the Output Resistance ro
So far we have been neglecting the output resistance ro of the MOSFET and the BJT. We
have done this for two reasons:
1. To keep things simple and focus attention on the significant features of each of the basic configurations, and
2. Because our main interest in this chapter is discrete-circuit design, where the circuit resistances (e.g., RC, RD, and RL) are usually much smaller than ro.
gR∥R
7.3 Basic Configurations 453
Table 7.5
Common emitter (Fig. 7.36)
Common emitter with Re (Fig. 7.38)
Characteristics of BJT Amplifiersa,b
Rin Avo Ro
(β+1)r −g R R e mC C
Av Gv −gR∥R −β RC∥RL
RC ∥RL
−βR +(β+1)r+R
mCL Rsig+(β+1)re
RC ∥RL re
−α
−gm RC∥RL
sig ee
454 Chapter 7 Transistor Amplifiers
LEE DE FOREST—A FATHER OF THE ELECTRONICS AGE:
In 1906 self-employed inventor Lee de Forest (1873–1961) created a three-terminal vacuum tube; it was the first electronic amplifier of weak signals. The device was known initially as the de Forest valve. The patent filed in 1907, however, used the name Audion, with the “-ion” indicating that the device was not completely evacuated. By 1919, engineers had realized that complete evacuation of internal gases produced a more reliable device.
De Forest’s first amplifier became known as the vacuum tube triode. Through its impact on radio, telephony, motion picture sound, and television, this invention, one of de Forest’s 180 patents, is credited with introducing the electronics age. The vacuum tube, in a variety of types, remained the device for implementing amplifiers until the appearance of transistors in the early 1950s.
Nevertheless, in some instances it is relatively easy to include ro in the analysis. Specifically:
1. In the CS and CE amplifiers, it can be seen that ro of the transistor appears in parallelwithRD andRC,respectively,andcanbesimplyincludedinthecorresponding formulas in Tables 7.4 and 7.5 by replacing RD with (RD ∥ro) and RC with (RC ∥ro). The effect will be a reduction in the magnitude of gain, of perhaps 5% to 10%.
2. In the source and emitter followers, it can be seen that the transistor ro appears in parallel with RL and can be taken into account by replacing RL in the corresponding formulas with (RL ∥ro). Thus, here too, the effect of taking ro into account is a small reduction in gain. More significant, however, taking ro into account reduces the open-circuitvoltagegainAvo fromunityto
Avo = ro (7.136) ro +(1/gm)
There are configurations in which taking ro into account complicates the analysis considerably. These are the CS (CE) amplifiers with a source (emitter) resistance, and the CG (CB) amplifier. Fortunately, for discrete implementation of these configurations, the effect of neglecting ro is usually small (which can be verified by computer simulation).
Finally, a very important point: In the analysis and design of IC amplifiers, ro must always be taken into account. This is because, as will be seen in the next chapter, all the circuit resistances are of the same order of magnitude as ro; thus, neglecting ro can result in completely erroneous results.
7.4 Biasing
As discussed in Section 7.1, an essential step in the design of a transistor amplifier is the establishment of an appropriate dc operating point for the transistor. This is the step known as biasing or bias design. In this section, we study the biasing methods commonly employed in discrete-circuit amplifiers. Biasing of integrated-circuit amplifiers will be studied in Chapter 8.
Bias design aims to establish in the drain (collector) a dc current that is predictable and insensitive to variations in temperature and to the large variations in parameter values between devices of the same type. For instance, discrete BJTs belonging to the same manufacturer’s part number can exhibit β values that range, say, from 50 to 150. Nevertheless, the bias design
for an amplifier utilizing this particular transistor type may specify that the dc collector current shall always be within, say, ±10% of the nominal value of, say, 1 mA. A similar statement can be made about the desired insensitivity of the dc drain current to the wide variations encountered in Vt of discrete MOSFETs.
A second consideration in bias design is locating the dc operating point in the active region of operation of the transistor so as to obtain high voltage gain while allowing for the required output signal swing without the transistor leaving the active region at any time (in order to avoid nonlinear distortion). We discussed this point in Section 7.1.7.
Although we shall consider the biasing of MOSFET and BJT amplifiers separately, the resulting circuits are very similar. Also, it will be seen that good bias designs incorporate a feedback mechanism that works to keep the dc bias point as constant as possible.
In order to keep matters simple and thus focus our attention on significant issues, we will neglect the Early effect; that is assume λ = 0 or VA = ∞. This is certainly allowed in initial designs of discrete circuits. Of course, the design can be fine-tuned at a later point with the assistance of a circuit-simulation program such as SPICE.
7.4.1 The MOSFET Case
Biasing by Fixing VGS The most straightforward approach to biasing a MOSFET is to fix its gate-to-source voltage VGS to the value required6 to provide the desired ID . This voltage value can be derived from the power-supply voltage VDD through the use of an appropriate voltage divider, as shown in Fig. 7.47(a). Alternatively, it can be derived from another suitable reference voltage that might be available in the system. Independent of how the voltage VGS may be generated, this is not a good approach to biasing a MOSFET. To understand the reason for this statement, recall that
I =1μC W(V −V)2 D 2noxLGS t
and note that the values of the threshold voltage Vt , the oxide-capacitance Co x , and (to a lesser extent) the transistor aspect ratio W/L vary widely among devices of supposedly the same size and type. This is certainly the case for discrete devices, in which large spreads in the values of these parameters occur among devices of the same manufacturer’s part number. The spread can also be large in integrated circuits, especially among devices fabricated on different wafers and certainly between different batches of wafers. Furthermore, both Vt and μn depend on temperature, with the result that if we fix the value of VGS , the drain current ID becomes very much temperature dependent.
To emphasize the point that biasing by fixing VGS is not a good technique, we show in Fig.7.47twoiD–vGS characteristiccurvesrepresentingextremevaluesinabatchofMOSFETs of the same type. Observe that for the fixed value of VGS , the resultant spread in the values of the drain current can be substantial.
Biasing by Fixing VG and Connecting a Resistance in the Source An excellent biasingtechniquefordiscreteMOSFETcircuitsconsistsoffixingthedcvoltageatthegate,VG, and connecting a resistance in the source lead, as shown in Fig. 7.48(a). For this circuit
6 That is indeed what we were doing in Section 7.1. However, the amplifier circuits studied there were conceptual ones, not actual practical circuits. Our purpose in this section is to study the latter.
7.4 Biasing 455
456 Chapter 7
Transistor Amplifiers
iD
ID2
ID
ID1
Device 2
VDD
VGS
Device 1
RG1
RG2
RD
0 VGS vGS (a) (b)
Figure 7.47 (a) Biasing the MOSFET with a constant VGS generated from VDD using a voltage divider (RG1,RG2); (b) the use of fixed bias (constant VGS) can result in a large variability in the value of ID. Devices 1 and 2 represent extremes among units of the same type.
we can write
VG =VGS +RSID (7.137)
Now, if VG is much greater than VGS , ID will be mostly determined by the values of VG and RS . However, even if VG is not much larger than VGS , resistor RS provides negative feedback, which acts to stabilize the value of the bias current ID. To see how this comes about, consider what happens when ID increases for whatever reason. Equation (7.137) indicates that since VG is con- stant,VGS willhavetodecrease.ThisinturnresultsinadecreaseinID,achangethatisopposite to that initially assumed. Thus the action of RS works to keep ID as constant as possible.7
Figure 7.48(b) provides a graphical illustration of the effectiveness of this biasing scheme. Here too we show the iD–vGS characteristics for two devices that represent the extremes of a batch of MOSFETs. Superimposed on the device characteristics is a straight line that represents the constraint imposed by the bias circuit—namely, Eq. (7.137). The intersection of this straight line with the iD–vGS characteristic curve provides the coordinates (ID and VGS) of the bias point. Observe that compared to the case of fixed VGS , here the variability obtained in ID is much smaller. Also, note that the variability decreases as VG and RS are made larger (thus providing a bias line that is less steep).
Two possible practical discrete implementations of this bias scheme are shown in Fig. 7.48(c) and (e). The circuit in Fig. 7.48(c) utilizes one power-supply VDD and derives VG
7The action of RS in stabilizing the value of the bias current ID is not unlike that of the resistance Rs, which we included in the source lead of a CS amplifier in Section 7.3.4. In the latter case also, Rs works to reduce the change in iD with the result that the amplifier gain is reduced.
iD
ID
ID
ID2 RS I
Device 2
Device 1
7.4 Biasing 457
VG
VDD
VGS (a)
D1
Slope = 1RS
VG vGS
0
VGS2 VGS1
(b)
VDD
VDD
RD
RG1 RD
0ID D
I RG1 RD 0RCC1 I
VG RG2
sig
RG
VGS D
ID VGS
RS vsig
RS
RG2
RS
VSS
(c)
(d)
(e)
Figure 7.48 Biasing using a fixed voltage at the gate, VG , and a resistance in the source lead, RS : (a) basic arrangement; (b) reduced variability in ID ; (c) practical implementation using a single supply; (d) coupling of a signal source to the gate using a capacitor CC1; (e) practical implementation using two supplies.
through a voltage divider (RG1 , RG2 ). Since IG = 0, RG1 and RG2 can be selected to be very large (in the megohm range), allowing the MOSFET to present a large input resistance to a signal source that may be connected to the gate through a coupling capacitor, as shown in Fig. 7.48(d). Here capacitor CC1 blocks dc and thus allows us to couple the signal vsig to the amplifier input without disturbing the MOSFET dc bias point. The value of CC1 should be selected large enough to approximate a short circuit at all signal frequencies of interest. We shall study capacitively coupled MOSFET amplifiers, which are suitable only in discrete-circuit design, in Section 7.5. Finally, note that in the circuit of Fig. 7.48(c), resistor RD is selected to be as large as possible to obtain high gain but small enough to allow for the desired signal swing at the drain while keeping the MOSFET in saturation at all times.
When two power supplies are available, as is often the case, the somewhat simpler bias arrangement of Fig. 7.48(e) can be utilized. This circuit is an implementation of Eq. (7.137), withVG replacedbyVSS.ResistorRG establishesadcgroundatthegateandpresentsahighinput resistance to a signal source that may be connected to the gate through a coupling capacitor.
458 Chapter 7 Transistor Amplifiers
Example 7.11
It is required to design the circuit of Fig. 7.48(c) to establish a dc drain current ID = 0.5 mA. The MOSFET is specified to have Vt = 1 V and kn′ W/L = 1 mA/V2 . For simplicity, neglect the channel-length modulation effect (i.e., assume λ = 0). Use a power-supply VDD = 15 V. Calculate the percentage change in the value of ID obtained when the MOSFET is replaced with another unit having the same kn′ W/L butVt =1.5V.
Solution
As a rule of thumb for designing this classical biasing circuit, we choose RD and RS to provide one-third of thepower-supplyvoltageVDD asadropacrosseachofRD,thetransistor(i.e.,VDS),andRS.ForVDD=15V, this choice makes VD = +10 V and VS = +5 V. Now, since ID is required to be 0.5 mA, we can find the values of RD and RS as follows:
RD=VDD−VD =15−10=10k ID 0.5
RS=VS = 5 =10k RS 0.5
The required value of VGS can be determined by first calculating the overdrive voltage VOV from I =1k′(W/L)V2
whichyieldsVOV =1V,andthus,
Now,sinceVS =+5V,VG mustbe
D2n OV 0.5 = 1 × 1 × V 2
2 OV
VGS =Vt +VOV =1+1=2V
VG =VS +VGS =5+2=7V
To establish this voltage at the gate we may select RG1 = 8 M and RG2 = 7 M. The final circuit is shown in Fig. 7.49. Observe that the dc voltage at the drain (+10 V) allows for a positive signal swing of +5 V (i.e.,uptoVDD)andanegativesignalswingof4V[i.e.,downto(VG –Vt)].
If the NMOS transistor is replaced with another having Vt = 1.5 V, the new value of ID can be found as follows:
ID = 1 ×1×VGS −1.52 (7.138) 2
VG =VGS +IDRS
7 = VGS + 10ID (7.139)
8 M
VG = 7 V
7 M
VDD = 15 V ID =
0.5 mA
ID = 0.5 mA
RD = 10 k
VD = 10 V
VS = 5 V
RS = 10 k
7.4 Biasing 459
Solving Eqs. (7.138) and (7.139) together yields
ID = 0.455 mA
Thus the change in ID is
ID =0.455−0.5=−0.045mA which is −0.045 × 100 = −9% change.
0.5
EXERCISES
7.31 ConsidertheMOSFETinExample7.11whenfixed-VGS biasisused.FindtherequiredvalueofVGS to establish a dc bias current ID = 0.5 mA. Recall that the device parameters are Vt = 1 V, kn′ W/L = 1mA/V2,andλ=0.WhatisthepercentagechangeinID obtainedwhenthetransistorisreplaced with another having Vt = 1.5 V?
Ans. VGS = 2 V; –75%
D7.32 Design the circuit of Fig. 7.48(e) to operate at a dc drain current of 0.5 mA and VD = +2 V. Let Vt =
1 V, kn′ W/L = 1 mA/V2, λ = 0, VDD = VSS = 5 V. Use standard 5% resistor values (see Appendix J), and give the resulting values of ID, VD, and VS.
Ans. RD =RS =6.2k;ID =0.49mA,VS =−1.96V,andVD =+1.96V.RG canbeselectedinthe range of 1 M to 10 M.
Figure 7.49 Circuit for Example 7.11.
460 Chapter 7
Transistor Amplifiers
0
VGS
VDD
RD
ID
ID VDS
RG
Figure 7.50 Biasing the MOSFET using a large drain-to-gate feedback resistance, RG.
Biasing Using a Drain-to-Gate Feedback Resistor A simple and effective discrete- circuit biasing arrangement utilizing a feedback resistor connected between the drain and the gate is shown in Fig. 7.50. Here the large feedback resistance RG (usually in the megohm range) forces the dc voltage at the gate to be equal to that at the drain (because IG = 0). Thus we can write
VGS =VDS =VDD −RDID which can be rewritten in the form
VDD =VGS +RDID (7.140)
which is identical in form to Eq. (7.137), which describes the operation of the bias scheme discussed above [that in Fig. 7.48(a)]. Thus, here too, if ID for some reason changes, say increases, then Eq. (7.140) indicates that VGS must decrease. The decrease in VGS in turn causes a decrease in ID, a change that is opposite in direction to the one originally assumed. Thus the negative feedback or degeneration provided by RG works to keep the value of ID as constant as possible.
The circuit of Fig. 7.50 can be utilized as an amplifier by applying the input voltage signal to the gate via a coupling capacitor so as not to disturb the dc bias conditions already established. The amplified output signal at the drain can be coupled to another part of the circuit, again via a capacitor. We considered such an amplifier circuit in Section 7.2 (Example 7.3).
EXERCISE
D7.33 Design the circuit in Fig. 7.50 to operate at a dc drain current of 0.5 mA. Assume VDD = +5 V, kn′ W/L = 1 mA/V2, Vt = 1 V, and λ = 0. Use a standard 5% resistance value for RD, and give the actual values obtained for ID and VD.
Ans. RD =6.2k;ID ≃0.49mA;VD ≃1.96V
Figure7.51 TwoobviousschemesforbiasingtheBJT:(a)byfixingVBE;(b)byfixingIB.Bothresultinwide variationsinIC andhenceinVCE andthereforeareconsideredtobe“bad.”Neitherschemeisrecommended.
7.4.2 The BJT Case
Before presenting the “good” biasing schemes, we should point out why two obvious arrangements are not good. First, attempting to bias the BJT by fixing the voltage VBE by, for instance, using a voltage divider across the power supply VCC , as shown in Fig. 7.51(a), is not a viable approach: The very sharp exponential relationship iC−vBE means that any small and inevitable differences in VBE from the desired value will result in large differences in IC and in VCE . Second, biasing the BJT by establishing a constant current in the base, as shown in Fig. 7.51(b), where IB ≃ (VCC − 0.7)/RB , is also not a recommended approach. Here the typically large variations in the value of β among units of the same device type will result in correspondinglylargevariationsinIC andhenceinVCE.
The Classical Discrete-Circuit Bias Arrangement Figure 7.52(a) shows the arrange- ment most commonly used for biasing a discrete-circuit transistor amplifier if only a single power supply is available. The technique consists of supplying the base of the transistor with afractionofthesupplyvoltageVCC throughthevoltagedividerR1,R2.Inaddition,aresistor RE is connected to the emitter. This circuit is very similar to one we used for the MOSFET [Fig. 7.48(c)]. Here, however, the design must take into account the finite base current.
Figure 7.52(b) shows the same circuit with the voltage-divider network replaced by its The ́venin equivalent,
VBB = R2 VCC (7.141) R1 +R2
RB = R1R2 (7.142) R1 +R2
ThecurrentIE canbedeterminedbywritingaKirchhoffloopequationforthebase–emitter– ground loop, labeled L, and substituting IB = IE /(β + 1):
IE = VBB −VBE (7.143) RE +RB/(β+1)
7.4 Biasing 461
RB1
RB2
VCC
IC
IB
VBE
(a)
RC
VCE
RB
VCC
IC
VBE
(b)
RC
VCE
IB
462 Chapter 7
Transistor Amplifiers
VCC
R2
RC
VCC
VBB VCC
R1
R2 IB
R1
R2
RC
RE
RB R1R2 L
(b)
IC
IE
RE
(a)
Figure 7.52 Classical biasing for BJTs using a single power supply: (a) circuit; (b) circuit with the voltage divider supplying the base replaced with its The ́venin equivalent.
To make IE insensitive to temperature and β variation,8 we design the circuit to satisfy the following two constraints:
VBB ≫ VBE (7.144) RE ≫ RB (7.145)
β+1
Condition(7.144)ensuresthatsmallvariationsinVBE (≃0.7V)willbeswampedbythemuch
larger VBB . There is a limit, however, on how large VBB can be: For a given value of the supply
voltage VCC , the higher the value we use for VBB , the lower will be the sum of voltages across RC
andthecollector–basejunction(VCB).Ontheotherhand,wewantthevoltageacrossRC tobe
large in order to obtain high voltage gain and large signal swing (before transistor cutoff). We
also want VCB (or VCE ) to be large, to provide a large signal swing (before transistor saturation).
Thus, as is the case in any design, we have a set of conflicting requirements, and the solution
must be a trade-off. As a rule of thumb, one designs for VBB about 1 VCC , VCB (or VCE ) about
1 VCC, and IC RC about 1 VCC. 33
3
Condition(7.145)makesIE insensitivetovariationsinβandcouldbesatisfiedbyselecting RB small. This in turn is achieved by using low values for R1 and R2. Lower values for R1 and R2, however, will mean a higher current drain from the power supply, and will result in a lowering of the input resistance of the amplifier (if the input signal is coupled to the base),9 which is the trade-off involved in this part of the design. It should be noted that condition (7.145) means that we want to make the base voltage independent of the value of β and determined solely by the voltage divider. This will obviously be satisfied if the current in the divider is made much larger than the base current. Typically one selects R1 and R2 such that theircurrentisintherangeofIE to0.1IE.
Further insight regarding the mechanism by which the bias arrangement of Fig. 7.52(a) stabilizes the dc emitter (and hence collector) current is obtained by considering the feedback
8Bias design seeks to stabilize either IE or IC since IC =αIE and α varies very little. That is, a stable IE will result in an equally stable IC , and vice versa. 9Iftheinputsignaliscoupledtothetransistorbase,thetwobiasresistancesR1 andR2 effectivelyappear in parallel between the base and ground. Thus, low values for R1 and R2 will result in lowering Rin .
action provided by RE. Consider that for some reason the emitter current increases. The voltage drop across RE , and hence VE , will increase correspondingly. Now, if the base voltage is determined primarily by the voltage divider R1, R2, which is the case if RB is small, it will remainconstant,andtheincreaseinVE willresultinacorrespondingdecreaseinVBE.Thisin turn reduces the collector (and emitter) current, a change opposite to that originally assumed. Thus RE provides a negative feedback action that stabilizes the bias current. This should remind the reader of the resistance Re that we included in the emitter lead of the CE amplifier inSection7.3.4.Also,thefeedbackactionofRE inthecircuitofFig.7.52(a)issimilartothe feedbackactionofRS inthecircuitofFig.7.48(c).Weshallstudynegativefeedbackformally in Chapter 11.
Example 7.12
We wish to design the bias network of the amplifier in Fig. 7.52 to establish a current IE = 1 mA using a power supply VCC = +12 V. The transistor is specified to have a nominal β value of 100.
Solution
We shall follow the rule of thumb mentioned above and allocate one-third of the supply voltage to the voltage drop across R2 and another one-third to the voltage drop across RC , leaving one-third for possible negative signal swing at the collector. Thus,
7.4 Biasing 463
andRE isdeterminedfrom
VB =+4V
VE =4−VBE ≃3.3V
RE=VE =3.3=3.3k IE 1
From the discussion above we select a voltage-divider current of 0.1IE = 0.1 × 1 = 0.1 mA. Neglecting the base current, we find
and
R1 +R2 = 12 =120k 0.1
R2 VCC =4V R1 +R2
Thus R2 =40 k and R1 =80 k.
At this point, it is desirable to find a more accurate estimate for IE , taking into account the nonzero
base current. Using Eq. (7.143),
I = 4−0.7
=0.93mA
E (80∥40)(k)
3.3(k)+
101
464
Chapter 7 Transistor Amplifiers
Example 7.12 continued
This is quite a bit lower than 1 mA, the value we are aiming for. It is easy to see from the above equation that a simple way to restore IE to its nominal value would be to reduce RE from 3.3 k by the magnitude of the second term in the denominator (0.267 k). Thus a more suitable value for RE in this case would be RE =3 k, which results in IE =1.01 mA ≃ 1 mA.10
It should be noted that if we are willing to draw a higher current from the power supply and to accept alowerinputresistancefortheamplifier,thenwemayuseavoltage-dividercurrentequal,say,toIE (i.e., 1 mA), resulting in R1 = 8 k and R2 = 4 k. We shall refer to the circuit using these latter values as design2,forwhichtheactualvalueofIE usingtheinitialvalueofRE of3.3kwillbe
IE = 4−0.7 =0.99≃1mA 3.3 + 0.027
In this case, design 2, we need not change the value of RE . Finally,thevalueofRC canbedeterminedfrom
RC = 12−VC IC
SubstitutingIC =αIE =0.99×1=0.99mA≃1mAresults,forbothdesigns,in RC =12−8=4k
1
EXERCISE
7.34 For design 1 in Example 7.12, calculate the expected range of IE if the transistor used has β in the rangeof50to150.ExpresstherangeofIE asapercentageofthenominalvalue(IE ≃1mA)obtained for β = 100. Repeat for design 2.
Ans. For design 1: 0.94 mA to 1.04 mA, a 10% range; for design 2: 0.984 mA to 0.995 mA, a 1.1% range.
A Two-Power-Supply Version of the Classical Bias Arrangement A somewhat simpler bias arrangement is possible if two power supplies are available, as shown in Fig. 7.53.
10Although reducing RE restores IE to the design value of 1 mA, it does not solve the problem of the dependenceofthevalueofIE onβ.SeeExercise7.34.
Figure 7.53 Biasing the BJT using two power supplies. Resistor RB is needed only if the signal is to be capacitively coupled to the base. Otherwise, the base can be connected directly to ground, or to a grounded signal source, resulting in almost total β-independence of the bias current.
Writing a loop equation for the loop labeled L gives
IE = VEE −VBE (7.146) RE +RB/(β+1)
ThisequationisidenticaltoEq.(7.143)exceptforVEE replacingVBB.Thusthetwoconstraints of Eqs. (7.144) and (7.145) apply here as well. Note that if the transistor is to be used with the base grounded (i.e., in the common-base configuration), then RB can be eliminated altogether. On the other hand, if the input signal is to be coupled to the base, then RB is needed. We shall study complete circuits of the various BJT amplifier configurations in Section 7.5. Finally, observe that the circuit in Fig. 7.53 is the counterpart of the MOS circuit in Fig. 7.48(e).
EXERCISE
D7.35 The bias arrangement of Fig. 7.53 is to be used for a common-base amplifier. Design the circuit to establish a dc emitter current of 1 mA and provide the highest possible voltage gain while allowing for a signal swing at the collector of ±2 V. Use +10-V and –5-V power supplies.
Ans. RB =0; RE =4.3 k; RC =8.4 k
Biasing Using a Collector-to-Base Feedback Resistor In the BJT case, there is a counterpart to the MOSFET circuit of Fig. 7.50. Figure 7.54(a) shows such a simple but effective biasing arrangement that is suitable for common-emitter amplifiers. The circuit employs a resistor RB connected between the collector and the base. Resistor RB provides negative feedback, which helps to stabilize the bias point of the BJT.
7.4 Biasing 465
466 Chapter 7
Transistor Amplifiers
+ VBE
(a)
(b)
Figure7.54 (a)Acommon-emittertransistoramplifierbiasedbyafeedbackresistorRB.(b)Analysisofthe circuit in (a).
Analysis of the circuit is shown in Fig. 7.54(b), from which we can write
VCC =IERC +IBRB +VBE =IERC+ IE RB+VBE
Thus the emitter bias current is given by
IE = VCC −VBE (7.147)
RC +RB/(β+1)
It is interesting to note that this equation is identical to Eq. (7.143), which governs the operation of the traditional bias circuit, except that VCC replaces VBB and RC replaces RE . It follows that toobtainavalueofIE thatisinsensitivetovariationofβ,weselectRB/(β+1)≪RC.Note, however, that the value of RB determines the allowable negative signal swing at the collector since
V =IR=I RB (7.148) CB B B Eβ+1
β+1
EXERCISE
D7.36 Design the circuit of Fig. 7.54 to obtain a dc emitter current of 1 mA, maximum gain, and a ±2-V signal swing at the collector; that is, design for VCE = +2.3 V. Let VCC = 10 V and β = 100.
Ans. RB = 162 k; RC = 7.7 k. Note that if standard 5% resistor values are used (Appendix J), we select RB =160 k and RC =7.5 k. This results in IE =1.02 mA and VC =+2.3 V.
7.5 Discrete-Circuit Amplifiers
With our study of transistor amplifier basics complete, we now put everything together by presenting practical circuits for discrete-circuit amplifiers. These circuits, which utilize the amplifier configurations studied in Section 7.3 and the biasing methods of Section 7.4, can be assembled using off-the-shelf discrete transistors, resistors, and capacitors. Though practical and carefully selected to illustrate some important points, the circuits presented in this section should be regarded as examples of discrete-circuit transistor amplifiers. Indeed, there is a great variety of such circuits, a number of which are explored in the end-of-chapter problems.
As mentioned earlier, the vast majority of discrete-circuit amplifiers utilize BJTs. This is reflected in this section where all the circuits presented except for one utilize BJTs. Of course, if desired, one can utilize MOSFETs in the same amplifier configurations presented here. Also, the MOSFET is the device of choice in the design of integrated-circuit (IC) amplifiers. We begin our study of IC amplifiers in Chapter 8.
As will be seen shortly, the circuits presented in this section utilize large capacitors (in the μF range) to couple the signal source to the input of the amplifier, and to couple the amplifier output signal to a load resistance or to the input of another amplifier stage. As well, a large capacitor is employed to establish a signal ground at the desired terminal of the transistor (e.g., at the emitter of a CE amplifier). The use of capacitors for these purposes simplifies the design considerably: Since capacitors block dc, one is able to first carry out the dc bias design and then connect the signal source and load to the amplifier without disturbing the dc design. There amplifiers are therefore known as capacitively coupled amplifiers.
7.5.1 A Common-Source (CS) Amplifier
As mentioned in Section 7.3, the common-source (CS) configuration is the most widely used of all MOSFET amplifier circuits. A common-source amplifier realized using the bias circuit of Fig. 7.48(c) is shown in Fig. 7.55(a). Observe that to establish a signal ground, or an ac ground as it is sometimes called, at the source, we have connected a large capacitor, CS, between the source and ground. This capacitor, usually in the microfarad range, is required to provide a very small impedance (ideally, zero impedance—i.e., in effect, a short circuit) at all signal frequencies of interest. In this way, the signal current passes through CS to ground and thus bypasses the resistance RS; hence, CS is called a bypass capacitor. Obviously, the lower the signal frequency, the less effective the bypass capacitor becomes. This issue will be studied in Section 10.1. For our purposes here we shall assume that CS is acting as a perfect short circuit and thus is establishing a zero signal voltage at the MOSFET source.
To prevent disturbances to the dc bias current and voltages, the signal to be amplified, shown as voltage source vsig with an internal resistance Rsig, is connected to the gate through a large capacitor CC1. Capacitor CC1, known as a coupling capacitor, is required to act as a perfect short circuit at all signal frequencies of interest while blocking dc. Here again, we note that as the signal frequency is lowered, the impedance of CC1 (i.e., 1/jωCC1) will increase and its effectiveness as a coupling capacitor will be correspondingly reduced. This problem, too, will be considered in Section 10.1 in connection with the dependence of the amplifier
7.5 Discrete-Circuit Amplifiers 467
468
Chapter 7
Transistor Amplifiers
VDD
VDD
RG1
(0 V)
ID
RD
RD CC2
RG1
VG
VD
V S
R
CC1
0 vd
sig
v = v 0 V RL
gs i vo
vsig vi RG2 RS CS RG2 ID RS
Rin Ro (a)
(b)
Figure 7.55 (a) A common-source amplifier using the classical biasing arrangement of Fig. 7.48(c). (b) Circuit for determining the bias point. (c) Equivalent circuit and analysis.
operation on frequency. For our purposes here we shall assume that CC1 is acting as a perfect short circuit as far as the signal is concerned.
The voltage signal resulting at the drain is coupled to the load resistance RL via another coupling capacitor CC2. We shall assume that CC2 acts as a perfect short circuit at all signal frequencies of interest and thus that the output voltage vo = vd . Note that RL can be either an actual load resistor, to which the amplifier is required to provide its output voltage signal, or it can be the input resistance of another amplifier stage in cases where more than one stage of amplification is needed. (We will study multistage amplifiers in Chapter 9).
Since a capacitor behaves as an open circuit at dc, the circuit for performing the dc bias design and analysis is obtained by open-circuiting all capacitors. The resulting circuit is shown in Fig. 7.55(b) and can be designed as discussed in Section 7.4.1.
To determine the terminal characteristics of the CS amplifier of Fig. 7.55(a)—that is, its input resistance, voltage gain, and output resistance—we replace the MOSFET with its hybrid-π small-signal model, replace VDD with a signal ground, and replace all coupling and bypass capacitors with short circuits. The result is the circuit in Fig. 7.55(c). Analysis is straightforward and is shown on the figure, thus
Rin =RG1∥RG2 (7.149) which shows that to keep Rin high, large values should be used for RG1 and RG2, usually in the
megohmrange.TheoverallvoltagegainGv is
Gv =− Rin gm(RD∥RL∥ro) (7.150)
Rin +Rsig
Observe that we have taken ro into account, simply because it is easy to do so. Its effect, however, is usually small (this is not the case for IC amplifiers, as will be explained in Chapter 8). Finally, to encourage the reader to do the small-signal analysis directly on the original circuit diagram, with the MOSFET model used implicitly, we show some of the analysis on the circuit of Fig. 7.55(a).
EXERCISES
D7.37 Design the bias circuit in Fig.7.55(b) for the CS amplifier of Fig. 7.55(a). Assume the MOSFET is specified to have Vt = 1 V, kn = 4 mA/V2 , and VA = 100 V. Neglecting the Early effect, design for ID =0.5mA,VS =3.5V,andVD =6Vusingapower-supplyVDD =15V.SpecifythevaluesofRS and RD. If a current of 2 μA is used in the voltage divider, specify the values of RG1 and RG2. Give the values of the MOSFET parameters gm and ro at the bias point.
Ans. RS =7k;RD =18k;RG1 =5M;RG2 =2.5M;gm =2mA/V;ro =200k
7.38 FortheCSamplifierofFig.7.55(a)usethedesignobtainedinExercise7.37todetermineRin,Ro,
and the overall voltage gain Gv when Rsig = 100 k and RL = 20 k.
Ans. 1.67 M; 16.5 k; −17.1 V/V
D7.39 As discussed in Section 7.3, beneficial effects can be realized by having an unbypassed resistance
Rs in the source lead of the CS amplifier. This can be implemented in the circuit of Fig. 7.55(a) by splitting the resistance RS into two resistances: Rs, which is left unbypassed, and (RS −Rs), across which the bypass capacitor CS is connected. Now, if in order to improve linearity of the amplifier in Exercises 7.37 and 7.38, vgs is to be reduced to half its value, what value should Rs have? What wouldtheamplifiergainGv become?RecallthatwhenRs isincludeditbecomesdifficulttoinclude ro in the analysis, so neglect it.
Ans. Rs =500;Gv =−8.9V/V
7.5 Discrete-Circuit Amplifiers 469
470
Chapter 7
Transistor Amplifiers
7.5.2 A Common-Emitter Amplifier
The common-emitter (CE) amplifier is the most widely used of all BJT amplifier configurations. Figure 7.56(a) shows a CE amplifier utilizing the classical biasing arrangement of Fig.7.48(c), the design of which was considered in Section7.4. The CE circuit in Fig. 7.54(a) is the BJT counterpart of the CS amplifier of Fig. 7.55(a). It utilizes coupling capacitors CC1 and CC2 and bypass capacitor CE . Here we assume that these capacitors, while blocking dc, behave as perfect short circuits at all signal frequencies of interest.
To determine the characteristic parameters of the CE amplifier, we replace the BJT with its hybrid-π model, replace VCC with a short circuit to ground, and replace the coupling and bypass capacitor with short circuits. The resulting small-signal equivalent circuit of the CE amplifier is shown in Fig. 7.56(b). The analysis is straightforward and is given in the
VCC
(0 V)
RB1
RC
CC2 vc
Rsig
CC1
0 V RL
vsig
vp = vi vo –
vi RB2 RE CE
Ro
(a)
Rin
Figure 7.56 (a) A common-emitter amplifier using the classical biasing arrangement of Fig. 7.52(a). (b) Equivalent circuit and analysis.
figure, thus
Rin =RB1∥RB2∥rπ
(7.151)
which indicates that to keep Rin relatively high, RB1 and RB2 should be selected large (typically in the range of tens or hundreds of kilohms). This requirement conflicts with the need to keep RB1 and RB2 low so as to minimize the dependence of the dc current IC on the transistor β. We discussed this design trade-off in Section 7.4.
ThevoltagegainGv isgivenby
Gv =− Rin gm(RC∥RL∥ro) (7.152)
Rin +Rsig
Note that we have taken ro into account because it is easy to do so. However, as already mentioned, the effect of this parameter on discrete-circuit amplifier performance is usually small.
EXERCISES
D7.40 Design the bias circuit of the CE amplifier of Fig. 7.56(a) to obtain IE = 0.5 mA and VC = +6 V. Design for a dc voltage at the base of 5 V and a current through RB2 of 50 μA. Let VCC =+15V,β=100,andVBE ≃0.7V.SpecifythevaluesofRB1,RB2,RE,andRC.Alsogivethe valuesoftheBJTsmall-signalparametersgm,rπ,andro atthebiaspoint.(Forthecalculationofro, let VA = 100 V.)
Ans. RB1 =182k;RB2 =100k;RE =8.6k;RC =18k;gm =20mA/V,rπ =5k,ro =200k 7.41 For the amplifier designed in Exercise 7.40, find Rin , Ro , and Gv when Rsig = 10 k and RL = 20 k.
Ans. Rin = 4.64 k; Ro = 16.51 k; Gv = −57.3 V/V
7.5.3 A Common-Emitter Amplifier with an Emitter Resistance Re
As discussed in Section 7.3.4, it is beneficial to include a small resistance in the transistor emitter lead. This can be implemented in the circuit of Fig. 7.56(a) by splitting the emitter bias resistance RE into two components: an unbypassed resistance Re, and a resistance (RE−Re)acrosswhichthebypasscapacitorCE isconnected.Theresultingcircuitisshown in Fig. 7.57(a) and its small-signal model is shown in Fig. 7.57(b). In the latter we utilize the T model of the BJT because it results in much simpler analysis (recall that this is always the case when a resistance is connected in series with the emitter). Also note that we have not included ro, for doing so would complicate the analysis significantly. This burden would not be justified given that ro has little effect on the performance of discrete-circuit amplifiers.
7.5 Discrete-Circuit Amplifiers 471
472 Chapter 7
Transistor Amplifiers
VCC
RB1 RC
CC2
Rsig
CC1
RL vo vsig R
Re
B2
(RE – Re)
(a)
CE
Figure 7.57 (a) A common-emitter amplifier with an unbiased emitter resistance Re. (b) The amplifier small-signal model and analysis.
Analysis of the circuit in Fig. 7.57(b) is straightforward and is shown in the figure. Thus,
Rin =RB1∥RB2∥(β+1)(re +Re)
=RB1∥RB2∥[rπ +(β+1)Re] (7.153)
from which we note that including Re increases Rin because it increases the input resistance looking into the base by adding a component (β + 1)Re to rπ . The overall voltage gainGv is
Gv =− Rin Rin + Rsig
= − α Rin Rin +Rsig
×αTotalresistanceincollector Total resistance in emitter
7.5 Discrete-Circuit Amplifiers 473
RC ∥ RL re +Re
(7.154)
EXERCISE
7.42 For the amplifier designed in Exercise 7.40 and analyzed in Exercise 7.41, let it be required to raise Rin to 10 k. What is the required value of Re , and what does the overall voltage gain Gv become? Ans. Re = 67.7 ; Gv = −39.8 V/V
7.5.4 A Common-Base (CB) Amplifier
Figure 7.58(a) shows a CB amplifier designed using the biasing arrangement of Fig. 7.53. Notethattheavailabilityoftwopowersupplies,VCC and−VEE,enablesustoconnectthebase directly to ground, obviating the need for a large bypass capacitor to establish a signal ground at the base.
The small-signal equivalent circuit of the CB amplifier is shown in Fig 7.58(b). As expected, we have utilized the T model of the BJT and have not included ro. Including ro would complicate the analysis significantly without making much difference to the results in the case of discrete-circuit amplifiers. From the circuit in Fig. 7.58(b) we find
Rin =re∥RE ≃re ≃1/gm
which as expected can be very small, causing vi to be a small fraction of vsig,
Now,
and
v =v Rin
i sig Rin +Rsig
ie =−vi re
vo =−αie(RC∥RL)
474 Chapter 7
Transistor Amplifiers
VCC (0 V)
RC
CC2
aie
vo
vo
RL
re
Ro
Rsig
Rin
ii
vi
CC1 ie
vsig
RE
VEE
(a)
B
E
vi
C
vo=– ie(RCRL)
aie ie = –
re
RC
RL
vi /re
Ro = RC
Rsig
ii
vsig
RE
Rin = re RE
(b)
Figure 7.58 (a) A common-base amplifier using the structure of Fig. 7.53 with RB omitted (since the base is grounded). (b) Equivalent circuit obtained by replacing the transistor with its T model.
Thus, the overall voltage gain is given by
Gv =α Rin RC∥RL = Rin gm(RC∥RL) (7.155) Rin +Rsig re Rin +Rsig
to load,
and
Thus,
v =v Rin
i sig Rin +Rsig
v =v RE∥ro∥RL
o i re+(RE∥ro∥RL)
Gv ≡ vo = Rin (RE∥ro∥RL) vsig Rin +Rsig re +(RE∥ro∥RL)
(7.158)
(7.159)
(7.160)
7.5 Discrete-Circuit Amplifiers 475
EXERCISE
D7.43 Design the CB amplifier of Fig. 7.58(a) to provide an input resistance Rin that matches the source resistance of a cable with a characteristic resistance of 50 . Assume that RE ≫ re. The available power supplies are ±5 V and RL = 8 k. Design for a dc collector voltage VC = +1 V. Specify the values of RC and RE . What overall voltage gain is obtained? If vsig is a sine wave with a peak amplitude of 10 mV, what is the peak amplitude of the output voltage? Let α ≃ 1.
Ans. RC =8k;RE =8.6k;40V/V;0.4V
7.5.5 An Emitter Follower
Figure 7.59(a) shows an emitter follower designed using the bias arrangement of Fig. 7.53 and two power supplies, VCC and −VEE . The bias resistance RB affects the input resistance of the follower and should be chosen as large as possible while limiting the dc voltage drop acrossittoasmallfractionofVEE;otherwisethedependenceofthebiascurrentIC onβcan become unacceptably large.
Figure 7.59(b) shows the small-signal equivalent circuit of the emitter follower. Here, as expected, we have replaced the BJT with its T model and included ro (since this can be done very simply). The input resistance of the emitter follower can be seen to be
Rin =RB∥Rib (7.156)
where Rib, the input resistance looking into the base, can be obtained by using the resistance-reflection rule. Toward that end, note that ro appears in parallel with RE and RL (which is why it can be easily taken into account). Thus,
Rib =(β+1)[re +(RE∥ro∥RL)] (7.157) The overall voltage gain can be determined by tracking the signal transmission from source
476 Chapter 7
Transistor Amplifiers
Rsig
CC1
VCC
CC2
RE RLvo
vsig
RB
Rin
VEE
Ro, Rout
(a)
ai
ro
i
re
Rsig
i
ib (1 a)i b 1
C
E
Ro, Rout
B
vsig
RB
vi
ib
(b)
RE
RL vo
Rin
R
Figure7.59 (a)Anemitter-followercircuit.(b)Small-signalequivalentcircuitoftheemitterfollowerwith the transistor replaced by its T model. Note that ro is included because it is easy to do so. Normally, its effect on performance is small.
Finally, the output resistance Rout can be obtained by short-circuiting vsig and looking back into the output terminal, excluding RL , as
R∥R
Rout=ro∥RE∥ re+ B sig (7.161)
β+1
Note that we have used the inverse resistance-reflection rule, namely, dividing the total resistance in the base, (RB ∥ Rsig ), by (β + 1).
7.5 Discrete-Circuit Amplifiers 477
EXERCISE
D7.44 Design the emitter follower of Fig. 7.59(a) to operate at a dc emitter current IE = 1 mA. Allow a dc voltage drop across RB of 1 V. The available power supplies are ±5 V, β = 100, VBE = 0.7 V, and VA = 100 V. Specify the values required for RB and RE . Now if Rsig = 50 k and RL =1k,findRin,vi/vsig,vo/vi,Gv,andRout.(Note:Inperformingthebiasdesign,neglecttheEarly effect.)
Ans. RB = 100 k; RE = 3.3 k; 44.3 k; 0.469 V/V; 0.968 V/V; 0.454 V/V; 320
7.5.6 The Amplifier Frequency Response
Thus far, we have assumed that the gain of transistor amplifiers is constant independent of the frequency of the input signal. This would imply that transistor amplifiers have infinite bandwidth, which of course is not true. To illustrate, we show in Fig. 7.60 a sketch of the magnitude of the gain of a common-emitter or a CS amplifier such as those shown in Figs. 7.56 and 7.55, respectively, versus frequency. Observe that there is indeed a wide frequency range over which the gain remains almost constant. This obviously is the useful frequency range of
Vo
V (dB)
sig
Low-frequency band
• Gain falls off due to the effects of CC1, CC2,
and CE
fL
Midband
• All capacitances can be neglected
3 dB
High-frequency band
• Gain falls off
due to the internal capacitive effects in
the BJT and the MOSFET
f (Hz) (log scale)
20 log A
M (dB)
Figure 7.60 Sketch of the magnitude of the gain of a CE (Fig. 7.56) or CS (Fig. 7.55) amplifier versus frequency. The graph delineates the three frequency bands relevant to frequency-response determination.
fH
478 Chapter 7
Transistor Amplifiers
operation for the particular amplifier. Thus far, we have been assuming that our amplifiers are operating in this frequency band, called the midband.
Figure 7.60 indicates that at lower frequencies, the magnitude of amplifier gain falls off. This is because the coupling and bypass capacitors no longer have low impedances. Recall that we assumed that their impedances were small enough to act as short circuits. Although this can be true at midband frequencies, as the frequency of the input signal is lowered, the reactance 1/jωC of each of these capacitors becomes significant, and it can be shown that this results in the overall voltage gain of the amplifier decreasing.
Figure 7.60 indicates also that the gain of the amplifier falls off at the high-frequency end. This is due to the internal capacitive effects in the BJT and the MOSFET. In Chapter 10 we shall study the internal capacitive effects of both transistor types and will augment their hybrid-π models with capacitances that model these effects.
We will undertake a detailed study of the frequency response of transistor amplifiers in Chapter10. For the time being, however, it is important for the reader to realize that for every transistor amplifier, there is a finite band over which the gain is almost constant. The boundaries of this useful frequency band, or midband, are the two frequencies fL and fH at which the gain drops by a certain number of decibels (usually 3 dB) below its value at midband. As indicated in Fig. 7.60, the amplifier bandwidth, or 3-dB bandwidth, is defined as the difference between the lower (fL ) and upper or higher (fH ) 3-dB frequencies:
BW = fH − fL
and since usually fL ≪ fH ,
BW ≃ fH
A figure of merit for the amplifier is its gain–bandwidth product, defined as
GB = |AM|BW
where |AM | is the magnitude of the amplifier gain in the midband. It will be seen in Chapter 10 that in amplifier design it is usually possible to trade off gain for bandwidth. One way to accomplish this, for instance, is by including resistance Re in the emitter of the CE amplifier.
Summary
The essence of the use of the MOSFET (the BJT) as an amplifier is that when the transistor is operated in the active region, vGS controls iD (vBE controls iC) in the manner of a voltage-controlled current source. When the device is dc biased in the active region, and the signal vgs (vbe) is kept small, the operation becomes almost linear, with id = gm vgs (ic = gm vbe ).
The most fundamental parameter in characterizing the
small-signal linear operation of a transistor is the transcon-
ductance g . For a MOSFET, g =μC (W/L)V = m m nox OV
2μnCox(W/L)ID =2ID/VOV;andfortheBJT,gm =IC/VT.
A systematic procedure for the analysis of a transistor amplifier circuit is presented in Table 7.1. Tables 7.2 and 7.3 present the small-signal models for the MOSFET and the BJT, respectively.
When a resistance is connected in series with the source (or emitter), the T model is the most convenient to use.
The three basic configurations of MOS and BJT amplifiers are presented in Fig. 7.33. Their characteristic parameter values are provided in Table 7.4 (for the MOS case) and in Table 7.5 (for the BJT case).
The CS amplifier, which has (ideally) infinite input resistance and a reasonably high gain but a rather high output resistance and a limited high-frequency response (more on the latter point in Chapter 10), is used to obtain most of the gain in a cascade amplifier. Similar remarks apply to the CE amplifier, except that it has a relatively low input resistance (rπ = β /gm ) arising from the finite base current of the BJT (finite β). Its voltage gain, however, can be larger than that of the CS amplifier because of the higher values of gm obtained with BJTs.
Adding a resistance Rs in the source of a CS amplifier (a resistance Re in the emitter of a CE amplifier) can lead to beneficial effects including the following: raising the input resistance of the CE amplifier, increasing linearity, and extending the useful amplifier bandwidth, at the expense of reducing the gain, all by a factor equal to (1+gmRs) [(1+gmRe) for the BJT case].
The CG (CB) amplifier has a low input resistance and thus, used alone, it has limited and specialized applications. However, its excellent high-frequency response makes it attractive in combination with the CS (CE) amplifier (Chapters 8 and 10).
The source follower has (ideally) infinite input resistance, a voltage gain lower than but close to unity, and a low output resistance. It is employed as a voltage buffer and as the output stage of a multistage amplifier. Similar remarks apply to the emitter follower except that its input resistance, though large, is finite. Specifically, the emitter follower multiplies the total resistance in the emitter by (β + 1) before presenting it to the signal source.
The resistance-reflection rule is a powerful tool in the analysis of BJT amplifier circuits: All resistances in the emitter circuit including the emitter resistance re can be reflected to the base side by multiplying them by (β + 1). Conversely, we can reflect all resistances in the base circuit to the emitter side by dividing them by (β + 1).
In the analysis and design of discrete-circuit amplifiers, it is rarely necessary to take the transistor output resistance ro into account. In some situations, however, ro can be easily taken into account; specifically in the CS (CE) amplifier and in the source (emitter) follower. In IC amplifiers, ro must always be taken into account.
A key step in the design of transistor amplifiers is to bias the transistor to operate at an appropriate point in the active region. A good bias design ensures that the parameters of the operating point (ID , VOV , and VDS for the MOSFET; IC and VCE for the BJT) are predictable and stable and do not vary by large amounts when the transistor is replaced by another of the same type. The bias methods studied in this chapter are suited for discrete-circuit amplifiers only because they utilize large coupling and bypass capacitors.
Discrete-circuit amplifiers predominantly employ BJTs. The opposite is true for IC amplifiers, where the device of choice is the MOSFET.
Summary 479
PROBLEMS
Computer Simulation Problems
Problems identified by the Multisim/PSpice icon are intended to demonstrate the value of using SPICE simulation to verify hand analysis and design, and to investigate important issues such as allowable signal swing and amplifier nonlinear distortion. Instructions to assist in setting up PSpice and Multisim simulations for all the indicated problems can be found in the corresponding files on the website. Note that if a particular parameter value is not specified in the problem statement, you are to make a reasonable assumption.
Section 7.1: Basic Principles
7.1 For the MOS amplifier of Fig. 7.2(a) with VDD = 5 V, Vt =0.5V,kn =10mA/V2,andRD =20k,determinethe coordinates of the active-region segment (AB) of the VTC [Fig. 7.2(b)].
D 7.2 For the MOS amplifier of Fig. 7.2(a) with VDD = 5 V and kn = 5 mA/V2 , it is required to have the end point of the VTC, point B, at VDS = 0.5 V. What value of RD is required? If the transistor is replaced with another having twice the value of the transconductance parameter kn, what new value of RD is needed?
D 7.3 It is required to bias the MOS amplifier of Fig. 7.3
at point Q for which VOV =0.2V and VDS =1 V. Find the
required value of RD when VDD = 5 V, Vt = 0.5 V, and
k = 10 mA/V2. Also specify the coordinates of the VTC n
end point B. What is the small-signal voltage gain of this amplifier? Assuming linear operation, what is the maximum allowable negative signal swing at the output? What is the corresponding peak input signal?
7.4 The MOS amplifier of Fig. 7.4(a), when operated with VDD = 2 V, is found to have a maximum small-signal voltage gain magnitude of 14 V/V. Find VOV and VDS for bias point Q at which a voltage gain of −12 V/V is obtained.
7.5 Consider the amplifier of Fig. 7.4(a) for the case VDD = 5V,RD =24k,kn′(W/L)=1mA/V2,andVt =1V.
(a) Find the coordinates of the two end points of the saturation-region segment of the amplifier transfer char- acteristic, that is, points A and B on the sketch of Fig. 7.4(b).
(b) If the amplifier is biased to operate with an overdrive voltage VOV of 0.5 V, find the coordinates of the bias point
Q on the transfer characteristic. Also, find the value of ID
and of the incremental gain Av at the bias point.
(c) For the situation in (b), and disregarding the distortion caused by the MOSFET’s square-law characteristic, what is the largest amplitude of a sine-wave voltage signal that can be applied at the input while the transistor remains in saturation? What is the amplitude of the output voltage signal that results? What gain value does the combination of these amplitudes imply? By what percentage is this gain value different from the incremental gain value
calculated above? Why is there a difference?
7.6 Various measurements are made on an NMOS amplifier for which the drain resistor RD is 20 k. First, dc measure- ments show the voltage across the drain resistor, VRD, to be 1.5 V and the gate-to-source bias voltage to be 0.7 V. Then, ac measurements with small signals show the voltage gain to be–10V/V.WhatisthevalueofVt forthistransistor?Ifthe processtransconductanceparameterkn′ is200μA/V2,whatis the MOSFET’s W/L?
*7.7 The expression for the incremental voltage gain Av given in Eq. (7.16) can be written in as
2V −V DD DS
VOV
indicates that for given values of V and V , the gain DD OV
magnitude can be increased by biasing the transistor at a lower VDS . This, however, reduces the allowable output signal swing in the negative direction. Assuming linear operation around the bias point, show that the largest possible negative output signal peak vˆo that is achievable while the transistor remains saturated is
Av =−
where VDS is the bias voltage at the drain. This expression
vˆ=V−V 1+1
o DS OV Av
ForVDD =5VandVOV =0.5V,provideatableofvaluesfor Av,vˆo,andthecorrespondingvˆi forVDS =1V,1.5V,2V,and 2.5 V. If kn′ (W/L) = 1 mA/V2 , find ID and RD for the design forwhichVDS=1V.
D *7.8 Design the MOS amplifier of Fig. 7.4(a) to obtain maximum gain while allowing for an output voltage swing of at least ±0.5 V. Let VDD = 5 V, and utilize an overdrive
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
CHAPTER 7 PROBLEMS
voltage of approximately 0.2 V.
(a) Specify VDS at the bias point.
(b) What is the gain achieved? What is the signal amplitude
vˆgs thatresultsinthe0.5-Vsignalamplitudeattheoutput?
(c) If the dc bias current in the drain is to be 100 μA, what
value of RD is needed?
(d) If kn′ = 200 μA/V2, what W/L ratio is required for the
MOSFET?
*7.9 Figure P7.9 shows an amplifier in which the load resistor RD has been replaced with another NMOS transistor Q2 connected as a two-terminal device. Note that because vDG of Q2 is zero, it will be operating in saturation at all times, even when vI =0 and iD2 =iD1 =0. Note also that the two transistors conduct equal drain currents. Using iD1 = iD2 , show that for the range of v I over which Q1 is operating in saturation, that is, for
Vt1 ≤vI ≤vO +Vt1 the output voltage will be given by
vO=VDD−Vt+ (W/L)1Vt− (W/L)1vI
(W/L)2 (W/L)2
where we have assumed Vt1 = Vt2 = Vt. Thus the circuit functions as a linear amplifier, even for large input signals. For (W/L)1 = (50 μm/0.5 μm) and (W/L)2 = (5 μm/0.5 μm), find the voltage gain.
VDD
iD2 Q2
iD1 vI Q1
Figure P7.9
7.10 A BJT amplifier circuit such as that in Fig. 7.6 is operated with VCC = +5V and is biased at VCE = +1V. Find the voltage gain, the maximum allowed output negative swing without the transistor entering saturation, and the corresponding maximum input signal permitted.
7.11 For the amplifier circuit in Fig. 7.6 with VCC = + 5 V and RC = 1 k, find VCE and the voltage gain at the following dc collector bias currents: 0.5 mA, 1 mA, 2.5 mA, 4 mA, and 4.5 mA. For each, give the maximum possible positive- and negative-output signal swing as determined by the need to keep the transistor in the active region. Present your results in a table.
D 7.12 Consider the CE amplifier circuit of Fig. 7.6 when operated with a dc supply VCC = +5 V. It is required to find the point at which the transistor should be biased; that is, find the value of VCE so that the output sine-wave signal vce resulting from an input sine-wave signal vbe of 5-mV peak amplitude has the maximum possible magnitude. What is the peak amplitude of the output sine wave and the value of the gain obtained? Assume linear operation around the bias point. (Hint: To obtain the maximum possible output amplitude for a given input, you need to bias the transistor as close to the edge of saturation as possible without entering saturation at anytime,thatis,withoutvCE decreasingbelow0.3V.)
7.13 A designer considers a number of low-voltage BJT amplifier designs utilizing power supplies with voltage VCC of 1.0, 1.5, 2.0, or 3.0 V. For transistors that saturate at VCE = 0.3 V, what is the largest possible voltage gain achievable with each of these supply voltages? If in each case biasing is adjusted so that VCE = VCC /2, what gains are achieved? If a negative-going output signal swing of 0.4 V is required, at whatVCE shouldthetransistorbebiasedtoobtainmaximum gain? What is the gain achieved with each of the supply voltages? (Notice that all of these gains are independent of thevalueofIC chosen!)
D *7.14 A BJT amplifier such as that in Fig. 7.6 is to be designed to support relatively undistorted sine-wave output signals of peak amplitudes P volt without the BJT entering saturation or cutoff and to have the largest possible voltage gain,denotedAv V/V.Showthattheminimumsupplyvoltage VCC neededisgivenby
V =V +P+AV CCCEsat vT
Problems 481
vO
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
482 Chapter 7 Transistor Amplifiers
Also, find VCC , following situations:
specified to the
nearest
0.5 V,
for the
*7.17 In deriving the expression for small-signal voltage gain Av in Eq. (7.21) we neglected the Early effect. Derive this expression including the Early effect by substituting
(a)Av =−20V/V,P=0.2V (b)Av =−50V/V,P=0.5V (c)Av =−100V/V,P=0.5V (d)Av =−100V/V,P=1.0V (e)Av =−200V/V,P=1.0V (f)Av =−500V/V,P=1.0V (g)Av =−500V/V,P=2.0V
i =IevBE/VT 1+vCE CS VA
7.15 The transistor in the circuit of Fig. P7.15 is biased at a dc collector current of 0.3 mA. What is the voltage gain? (Hint: Use The ́venin’s theorem to convert the circuit to the form in Fig. 7.6.)
−ICRC/VT VCC −VCE VT Av= IR=−V−V
1+CC 1+CC CE VA +VCE VA +VCE
ForthecaseVCC =5VandVCE =3V,whatisthegain without and with the Early effect taken into account? Let VA = 100 V.
7.18 When the amplifier circuit of Fig. 7.6 is biased with a certain VBE , the dc voltage at the collector is found to be +2 V. For VCC = +5 V and RC = 1 k, find IC and the small-signal voltage gain. For a change vBE = +5 mV, calculate the resulting v O . Calculate it two ways: by using the transistor exponential characteristic iC, and approximately, using the small-signal voltage gain. Repeat for vBE = −5 mV. Summarize your results in a table.
*7.19 Consider the amplifier circuit of Fig. 7.6 when oper- ated with a supply voltage VCC = +3V.
(a) What is the theoretical maximum voltage gain that this amplifier can provide?
(b) What value of VCE must this amplifier be biased at to provide a voltage gain of –60 V/V?
(c) If the dc collector current IC at the bias point in (b) is to be0.5mA,whatvalueofRC shouldbeused?
(d) What is the value of VBE required to provide the bias point mentioned above? Assume that the BJT has IS = 10−15 A.
(e) If a sine-wave signal vbe having a 5-mV peak ampli- tude is superimposed on VBE, find the corresponding output voltage signal vce that will be superimposed on VCE assuming linear operation around the bias point.
(f) Characterize the signal current ic that will be superim- posed on the dc bias current IC .
in
Eq. (7.11). Show that the gain expression changes to
Eq. (7.4)
and including the factor
1 + VCE /VA in
CHAPTER 7 PROBLEMS
5V
10 k
vO
vI
10 k
Figure P7.15
7.16 Sketch and label the voltage-transfer characteristics of the pnp amplifiers shown in Fig. P7.16.
vI
VCC 5V
vI
O vO
R
v
RC
VCC = 5 V (a)
C
Figure P7.16
(b)
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CHAPTER 7 PROBLEMS
(g) What is the value of the dc base current IB at the bias point? Assume β = 100. Characterize the signal current ib that will be superimposed on the base current IB.
(h) Dividing the amplitude of v be by the amplitude of ib , evaluate the incremental (or small-signal) input resistance of the amplifier.
(i) Sketch and clearly label correlated graphs for vBE , vCE , iC , and iB versus time. Note that each graph consists of a dc or average value and a superimposed sine wave. Be careful of the phase relationships of the sine waves.
7.20 The essence of transistor operation is that a change in vBE, vBE, produces a change in iC, iC. By keep- ing vBE small, iC is approximately linearly related to vBE, iC = gmvBE, where gm is known as the transistor transconductance. By passing iC through RC, an output voltage signal vO is obtained. Use the expression for the small-signal voltage gain in Eq. (7.20) to derive an expression for gm. Find the value of gm for a transistor biased at IC =0.5mA.
7.21 The purpose of this problem is to illustrate the applica-
tion of graphical analysis to the circuit shown in Fig. P7.21.
Sketch i −v characteristic curves for the BJT for i = C CE B
10 μA, 20 μA, 30 μA, and 40 μA. Assume the lines to be horizontal (i.e., neglect the Early effect), and let β=100. For VCC =5V and RC =1 k, sketch the load line. What peak-to-peakcollectorvoltageswingwillresultforiB varying
Problems 483 over the range 10 μA to 40 μA? If the BJT is biased
at V = 1 V , find the value of I and I . If at this CE 2CC C B
current VBE = 0.7 V and if RB = 100 k, find the required value of VBB .
*7.22 Sketch the iC−vCE characteristics of an npn transistor
having β = 100 and VA = 100 V. Sketch characteristic curves
for iB = 20 μA, 50 μA, 80 μA, and 100 μA. For the purpose
of this sketch, assume that i = β i at v = 0. Also, sketch C B CE
theloadlineobtainedforV =10VandR =1k.Ifthedc CC C
bias current into the base is 50 μA, write the equation for the correspondingiC−vCE curve.Also,writetheequationforthe load line, and solve the two equations to obtain VCE and IC . If the input signal causes a sinusoidal signal of 30-μA peak amplitude to be superimposed on IB, find the corresponding signal components of iC and vCE .
Section 7.2: Small-Signal Operation and Models
*7.23 This problem investigates the nonlinear distortion
introduced by a MOSFET amplifier. Let the signal vgs
be a sine wave with amplitude Vgs , and substitute v gs =
Vgs sin ωt in Eq. (7.28). Using the trigonometric identity
sin2θ = 1 − 1 cos2θ, show that the ratio of the signal at 22
frequency 2ω to that at frequency ω, expressed as a percentage (known as the second-harmonic distortion) is
Second-harmonic distortion = 1 Vgs × 100 4 VOV
If in a particular application Vgs is 10 mV, find the minimum overdrive voltage at which the transistor should be operated so that the second-harmonic distortion is kept to less than 1%.
7.24 Consider an NMOS transistor having kn = 10 mA/V2 . Let the transistor be biased at VOV = 0.2 V. For operation in saturation, what dc bias current ID results? If a 0.02-V signal is superimposed on VGS , find the corresponding increment in collector current by evaluating the total collector current iD and subtracting the dc bias current ID. Repeat for a –0.02-V signal. Use these results to estimate gm of the FET at this bias point. Compare with the value of gm obtained using Eq. (7.33).
VCC
VBB iC RC
RB
iB
Figure P7.21
vCE
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484 Chapter 7 Transistor Amplifiers
7.25 Consider the FET amplifier of Fig. 7.10 for the case
Vt =0.4V,kn =5mA/V2,VGS =0.6V,VDD =1.8V,and
R =10k. D
(a) Find the dc quantities ID and VDS .
(b) Calculate the value of gm at the bias point.
(c) Calculate the value of the voltage gain.
(d) If the MOSFET has λ = 0.1 V−1 , find ro at the bias point
and calculate the voltage gain.
D *7.26 An NMOS amplifier is to be designed to provide
a 0.20-V peak output signal across a 20-k load that can be used as a drain resistor. If a gain of at least 10 V/V is needed, what gm is required? Using a dc supply of 1.8 V, what values of ID and VOV would you choose? What W/L ratio is required if μnCox = 200 μA/V2? If Vt = 0.4 V, find VGS.
D *7.27 In this problem we investigate an optimum design of the CS amplifier circuit of Fig. 7.10. First, use the voltage gain expression Av = −gm RD together with Eq. (7.42) for gm to show that
A =−2IDRD =−2VDD−VDS v VOV VOV
Voltages (V) Type I (mA) V V
Next, let the maximum positive input signal be vˆi. To keep
the second-harmonic distortion to an acceptable level, we bias
the MOSFET to operate at an overdrive voltage V ≫ vˆ . Let OV i
VOV =mvˆi.Now,tomaximizethevoltagegainAv,wedesign
forthelowestpossibleVDS.ShowthattheminimumVDS thatis consistent with allowing a negative signal voltage swing at the
vˆi while maintaining saturation-mode operation
VDS=
Now,findVOV,VDS,Av,andvˆo forthecaseVDD =2.5V,vˆi = 20 mV, and m = 15. If it is desired to operate this transistor at ID = 200 μA, find the values of RD and W/L, assuming that for this process technology kn′ = 100 μA/V2 .
7.28 In the table below, for MOS transistors operating under a variety of conditions, complete as many entries as possible. Although some data is not available, it is always possible to calculate gm using one of Eqs. (7.40), (7.41), or (7.42). Assume μn = 500 cm2/V· s, μp = 250 cm2/V · s, and Co x = 0.4 fF/μm2 .
drain of Av is given by
V +vˆ+2V vˆ/V OV i DD i OV
1+2vˆ/V i OV
CHAPTER 7 PROBLEMS
i P 10 jP10 kP lP
25
4
1303
5 0.08
Dimensions (μm) VWL
W/L k′(W/L)
g (mA/V) m
Case
aN132 1
b N 1 cN10 dN 0.5 eN 0.1 fN
0.7
0.5 50 21 0.5
D GS t OV
10 2 1.80.8 404
gP 0.5
hP31 0.5
4000 2
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7.29 An NMOS technology has μn Co x = 250 μA/V2 and
Vt = 0.5 V. For a transistor with L = 0.5 μm, find the value
ofWthatresultsing =2mA/VatI =0.25mA.Also,find
the required VGS .
7.30 For the NMOS amplifier in Fig. P7.30, replace the transistor with its T equivalent circuit, assuming λ = 0. Derive expressions for the voltage gains vs/vi and vd/vi.
Problems 485 7.32 For a 0.18-μm CMOS fabrication process: Vtn = 0.5 V,
Vtp = –0.5 V, μnCox = 400 μA/V2, μpCox = 100 μA/V2, C = 8.6 fF/μm2 , V (n-channel devices) = 5L (μm), and
CHAPTER 7 PROBLEMS
mD oxA
VA (p-channel devices) = 6L (μm). Find the small-signal
modelparameters(gm andro)forbothanNMOSandaPMOS transistor having W/L = 10 μm/0.5 μm and operating at ID = 100 μA. Also, find the overdrive voltage at which each device must be operating.
*7.33 Figure P7.33 shows a discrete-circuit amplifier. The input signal vsig is coupled to the gate through a very large capacitor (shown as infinite). The transistor source is connected to ground at signal frequencies via a very large capacitor (shown as infinite). The output voltage signal that develops at the drain is coupled to a load resistance via a very large capacitor (shown as infinite). All capacitors behave as short circuits for signals and as open circuits for dc.
Figure P7.30
7.31 In the circuit of Fig. P7.31, the NMOS transistor hasV=0.5VandV =50VandoperateswithV =1V.
become for I increased to 1 mA?
(a)
(b) (c)
(d)
Rsig = 200 k
vo
vsig
Figure P7.33
If the transistor has Vt = 1 V, and kn = 4 mA/V2 , verify that the bias circuit establishes VGS = 1.5 V, ID = 0.5 mA, and VD = +7.0 V. That is, assume these values, and verify that they are consistent with the values of the circuit components and the device parameters.
Findgm andro ifVA =100V.
Draw a complete small-signal equivalent circuit for the amplifier, assuming all capacitors behave as short circuits at signal frequencies.
Find Rin, vgs/vsig, vo/vgs, and vo/vsig.
tAD
What is the voltage gain vo/vi ? What do VD and the gain
15 V
10 M
vgs
Rin
16 k
7 k
vo 16 k
5 M
Figure P7.31
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
486 Chapter 7 Transistor Amplifiers
7.34 Consider a transistor biased to operate in the active mode at a dc collector current IC . Calculate the collector signal current as a fraction of IC (i.e., ic/IC)for input signals vbe of +1 mV, –1 mV, +2 mV, –2 mV, +5 mV, –5 mV, +8 mV, –8 mV, +10 mV, –10 mV, +12 mV, and –12 mV. In each case do the calculation two ways:
(a) using the exponential characteristic, and (b) using the small-signal approximation.
Present your results in the form of a table that includes a column for the error introduced by the small-signal approximation. Comment on the range of validity of the small-signal approximation.
7.35 An npn BJT with grounded emitter is operated with VBE = 0.700 V, at which the collector current is 0.5 mA. A 5-k resistor connects the collector to a +5-V supply. What is the resulting collector voltage VC ? Now, if a signal applied to thebaseraisesvBE to705mV,findtheresultingtotalcollector current iC and total collector voltage vC using the exponential iC–vBE relationship. For this situation, what are vbe and vc? Calculate the voltage gain vc/vbe. Compare with the value obtained using the small-signal approximation, that is, –gm RC .
7.36 A transistor with β = 100 is biased to operate at a dc collector current of 0.5 mA. Find the values of gm , rπ , and re . Repeat for a bias current of 50 μA.
7.37 A pnp BJT is biased to operate at IC = 1.0 mA. What is the associated value of gm? If β = 100, what is the value of the small-signal resistance seen looking into the emitter (re)? Into the base (rπ )? If the collector is connected to a 5-k load, with a signal of 5-mV peak applied between base and emitter, what output signal voltage results?
D 7.38 A designer wishes to create a BJT amplifier with a gm of 30 mA/V and a base input resistance of 3000 or more.
What collector-bias current should he choose? What is the minimum β he can tolerate for the transistor used?
7.39 A transistor operating with nominal gm of 40 mA/V has a β that ranges from 50 to 150. Also, the bias circuit, being less than ideal, allows a ±20% variation in IC . What are the extreme values found of the resistance looking into the base?
7.40 In the circuit of Fig. 7.20, VBE is adjusted so that VC = 1V.IfVCC =3V,RC =2k,andasignalvbe =0.005sinωt volts is applied, find expressions for the total instantaneous quantities iC(t), vC(t), and iB(t). The transistor has β = 100. What is the voltage gain?
D *7.41 We wish to design the amplifier circuit of Fig. 7.20 under the constraint that VCC is fixed. Let the input signal vbe = Vˆ be sin ωt, where Vˆ be is the maximum value for acceptable linearity. For the design that results in the largest signal at the collector, without the BJT leaving the active region, show that
Vˆbe RCIC = VCC −0.3 1+ VT
and find an expression for the voltage gain obtained. For VCC =3VandVˆbe =5mV,findthedcvoltageatthecollector, the amplitude of the output voltage signal, and the voltage gain.
7.42 Thetablebelowsummarizessomeofthebasicattributes of a number of BJTs of different types, operating as ampli- fiers under various conditions. Provide the missing entries. (Note: Isn’t it remarkable how much two parameters can reveal?)
7.43 A BJT is biased to operate in the active mode at a dc collector current of 1 mA. It has a β of 100 and VA of 100 V. Give the four small-signal models (Figs. 7.25 and 7.27) of the BJT complete with the values of their parameters.
CHAPTER 7 PROBLEMS
Transistor a b c d e f g
α 1.000
β 100 ∞
0.90 5
IC (mA) 1.00 IE (mA)
IB (mA)
gm (mA/V)
re () rπ ()
1.00
1.00 0.020
25
100 10.1k
1.10 700
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CHAPTER 7 PROBLEMS
7.44 Using the T model of Fig. 7.26(a), show that the input resistance between base and emitter, looking into the base, is equal to rπ .
7.45 Show that the collector current provided by the model of Fig. 7.26(b) is equal to that provided by the model in Fig. 7.26(a).
7.46 Show that the hybrid-π model of Fig. 7.24(b) is the incremental version of the large-signal model of Fig. 6.5(d).
7.47 ShowthattheTmodelofFig.7.26(b)istheincremental version of the large-signal model of Fig. 6.5(b).
7.48 The transistor amplifier in Fig. P7.48 is biased with a current source I and has a very high β. Find the dc voltage at the collector, VC. Also, find the value of re. Replace the transistor with the T model of Fig. 7.26(b) (note that the dc current source I should be replaced with an open circuit). Hence find the voltage gain vc/vi.
input, v π /v sig , and v o /v π . Use these to is given by
Rsig
vsig
Rin Figure P7.50
vsig
rπ +Rsig
RC
Problems 487 the voltage gain from base to collector,
show that the overall voltage gain v o /v sig vo =− βRC
ib
v
vo
3
10 k
I
0.2 mA
7.51 Figure P7.51 shows a transistor with the collector connected to the base. The bias arrangement is not shown. SinceazerovBC impliesoperationintheactivemode,theBJT can be replaced by one of the small-signal models of Figs. 7.24 and 7.26. Use the model of Fig. 7.26(b) and show that the resulting two-terminal device, known as a diode-connected transistor, has a small-signal resistance r equal to re.
ix
r = vx ix
7.52 Figure P7.52 shows a particular configuration of BJT amplifiers known as “emitter follower.” The bias arrangement is not shown. Replace the BJT with its T equivalent-circuit
Figure P7.48
vx
7.49 For the conceptual
RC = 2 k, gm = 50 mA/V, and β =100. If a peak-to-peak output voltage of 1 V is measured at the collector, what are the peak-to-peak values of vbe and ib?
7.50 Figure P7.50 shows the circuit of an amplifier fed with a signal source v sig with a source resistance Rsig . The bias circuitry is not shown. Replace the BJT with its hybrid-π equivalent circuit of Fig. 7.24(a). Find the input resistance Rin ≡ v π /ib , the voltage transmission from source to amplifier
circuit
shown
in Fig. 7.23,
Figure P7.51
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
488 Chapter 7 Transistor Amplifiers model of Fig. 7.26(b). Show that
R ≡vi =(β+1)r+R ini ee
7.54 In the circuit shown in Fig. P7.54, the transistor has a β
of 200. What is the dc voltage at the collector? Replacing the
BJT with one of the hybrid-π models (neglecting ro ), draw the
b vR
equivalent circuit of the amplifier. Find the input resistances
o=e
vi Re +re
R and R and the overall voltage gain v /v . For an output ib in osig
ib 1.5V
10 k
10 mA
signal of ±0.4 V, what values of vsig and vb are required? 5V
CHAPTER 7 PROBLEMS
vi Re
R vsig R
Rsig vb
vo
in C
1k
Figure P7.54
vo 100
Figure P7.52
7.53 For the circuit shown in Fig. P7.53, draw a complete
small-signal equivalent circuit utilizing an appropriate T
model for the BJT (use α=0.99). Your circuit should show
the values of all components, including the model parameters.
WhatistheinputresistanceR ?Calculatetheoverallvoltage
Rin Rib
in
5V
RC
7.55 Consider the augmented hybrid-π model shown in Fig. 7.25(a). Disregarding how biasing is to be done, what is the largest possible voltage gain available for a signal source connected directly to the base and a very-high-resistance load? Calculate the value of the maximum possible gain for VA =25VandVA =125V.
D 7.56 Redesign the circuit of Fig. 7.30(a) by raising the resistor values by a factor n to increase the resistance seen by the input vi to 75 . What value of voltage gain results?
gain vo/vsig .
12 k
Q1 C1
Rin
C2
RL
12 k
vo Grounded-base circuits of this kind are used in systems such as cable TV, in which, for highest-quality signaling, load resistances need to be “matched” to the equivalent resistances of the interconnecting cables.
D *7.57 Design an amplifier using the configuration of Fig. 7.30(a). The power supplies available are ±5 V. The input signal source has a resistance of 50 , and it is required that the amplifier input resistance match this value. (Note that Rin = re ∥ RE ≃ re .) The amplifier is to have the greatest possible voltage gain and the largest possible output signal but retain small-signal linear operation (i.e., the signal component across the base–emitter junction should be limited to no more
Rsig
75
vsig
0.33 mA
Figure P7.53
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
CHAPTER 7 PROBLEMS
than 10 mV). Find appropriate values for RE and RC . What is the value of voltage gain realized from signal source to output?
*7.58 The transistor in the circuit shown in Fig. P7.58 is biased to operate in the active mode. Assuming that β is very large, find the collector bias current IC . Replace the transistor with the small-signal equivalent-circuit model of Fig. 7.26(b) (remember to replace the dc power supply with a short circuit). Analyze the resulting amplifier equivalent circuit to show that
Problems 489 D 7.60 Specify the parameters Rin , Av o , and Ro of an
amplifier that is to be connected between a 100-k source and a 2-k load and is required to meet the following specifications:
(a) No more than 5% of the signal strength is lost in the connection to the amplifier input;
(b) If the load resistance changes from the nominal value of 2 k to a low value of 1 k, the change in output voltage is limited to 5% of nominal value; and
(c) The nominal overall voltage gain is 10 V/V.
7.61 Figure P7.61 shows an alternative equivalent-circuit representation of an amplifier. If this circuit is to be equivalent to that in Fig. 7.34(b) show that Gm = Av o /Ro . Also convince yourself that the transconductance Gm is defined as
vo1 = RE
vi RE +re
vo2 = −αRC
vi 5V
RE +re
3.3
3.6
i Gm = o
vi RL=0
and hence is known as the short-circuit transconductance.
Now, if the amplifier is fed with a signal source (v sig , Rsig )
and is connected to a load resistance R show that the gain of
L
the amplifier proper Av is given by Av = Gm Ro ∥ RL and the
overall voltage gain Gv is given by
G = Rin G R ∥R
vi Rin Gmvi Ro vo
Figure P7.61
7.62 An alternative equivalent circuit of an amplifier fed with a signal source (v sig , Rsig ) and connected to a load RL is shown in Fig. P7.62. Here Gv o is the open-circuit overall voltage gain,
vR+RmoL in sig
Figure P7.58
Io
Find the values of these voltage gains (for α ≃ 1). Now, if the terminal labeled vo1 is connected to ground, what does the voltage gain vo2/vi become?
Section 7.3: Basic Configurations
7.59 An amplifier with an input resistance of 100 k, an open-circuit voltage gain of 100 V/V, and an output resistance of 100 is connected between a 20-k signal source and a 2-k load. Find the overall voltage gain Gv . Also find the current gain, defined as the ratio of the load current to the current drawn from the signal source.
G v o = v o
vsig RL =∞ = Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
490 Chapter 7 Transistor Amplifiers
and Rout is the output resistance with vsig set to zero. This is
Evaluate Rin, Avo, and Ro for the case R1 = 100 k, Rf = 1M,gm=100mA/V,R2=100,andRL=1k. Which of the amplifier characteristic parameters is most affected by Rf (that is, relative to the case with Rf = ∞)? For Rsig = 100 k determine the overall voltage gain, Gv , with and without Rf present.
7.64 Calculate the overall voltage gain of a CS amplifier fed with a 1-M source and connected to a 10-k load. The MOSFET has gm = 2 mA/V, and a drain resistance RD = 10 k is utilized.
7.65 A CS amplifier utilizes a MOSFET with μn Co x = 400μA/V2 andW/L=10.ItisbiasedatID =320μAanduses RD =10k.FindRin,Avo,andRo.Also,ifaloadresistanceof 10 k is connected to the output, what overall voltage gain Gv is realized? Now, if a 0.2-V peak sine-wave signal is required at the output, what must the peak amplitude of vsig be?
7.66 A common-source amplifier utilizes a MOSFET oper- ated at VOV = 0.25 V. The amplifier feeds a load resistance RL = 15 k. The designer selects RD = 2RL . If it is required to realize an overall voltage gain Gv of −10 V/V what gm is needed? Also specify the bias current ID. If, to increase the output signal swing, RD is reduced to RD = RL , what does Gv become?
different than Ro. Show that
Gvo = where R = R .
**7.63 Most practical amplifiers have internal feedback that make them non-unilateral. In such a case, Rin depends on RL . To illustrate this point we show in Fig. P7.63 the equivalent circuit of an amplifier where a feedback resistance Rf models the internal feedback mechanism that is present in this amplifier. It is Rf that makes the amplifier non-unilateral. Show that
i in RL=∞
G=G RL
v vo RL +Rout
Ri
Avo
Ri +Rsig
Also show that the overall voltage gain is
CHAPTER 7 PROBLEMS
Rf + R2∥RL Rin=R1∥ 1+gR∥R
Avo=−gmR2 Ro =R2∥Rf
vi
ii
m2L
1−1/g R m f
1+ R2/Rf
Rsig
vsig Figure P7.62
Rsig
Rout
io
Rin
Gv ovsig
Rf
RL vo
vsigviR1gmvi R2RLvo
Rin Figure P7.63
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
CHAPTER 7 PROBLEMS
7.67 Two identical CS amplifiers are connected in cascade.
The first stage is fed with a source vsig having a resistance
Rsig = 200 k. A load resistance RL = 10 k is connected
to the drain of the second stage. Each MOSFET is biased
at I = 0.3 mA and operates with V = 0.2 V. Each stage D OV
utilizes a drain resistance RD = 10 k.
(a) Sketch the equivalent circuit of the two-stage amplifier.
(b) Calculate the overall voltage gain Gv .
7.68 A CE amplifier utilizes a BJT with β = 100 biased at IC = 0.5 mA; it has a collector resistance RC = 10 k. Find Rin , Ro , and Av o . If the amplifier is fed with a signal source havingaresistanceof10k,andaloadresistanceRL =10k is connected to the output terminal, find the resulting Av and Gv . If the peak voltage of the sine wave appearing between base and emitter is to be limited to 5 mV, what vˆsig is allowed, and what output voltage signal appears across the load?
D *7.69 In this problem we investigate the effect of the inevitable variability of β on the realized gain of the CE amplifier. For this purpose, use the overall gain expression in Eq. (7.114).
R′ Gv= L
Problems 491 (a) Sketch the equivalent circuit of the two-stage amplifier.
(b) Find the overall voltage gain, v o2 /v sig .
7.71 A MOSFET connected in the CS configuration has a transconductance gm = 5 mA/V. When a resistance Rs is connected in the source lead, the effective transconductance is reduced to 2 mA/V. What do you estimate the value of Rs to be?
7.72 A CS amplifier using an NMOS transistor with gm = 2 mA/V is found to have an overall voltage gain of −10 V/V. What value should a resistance Rs inserted in the source lead have to reduce the overall voltage gain to −5 V/V?
7.73 The overall voltage gain of a CS amplifier with a resistance Rs = 0.5 k in the source lead was measured and found to be −10 V/V. When Rs was shorted, but the circuit operation remained linear, the gain doubled. What must gm be? What value of Rs is needed to obtain an overall voltage gain of −16 V/V?
7.74 A CE amplifier utilizes a BJT with β = 100 biased at IC = 0.5 mA and has a collector resistance RC = 12 k and a resistance Re = 250 connected in the emitter. Find Rin , Av o , and Ro . If the amplifier is fed with a signal source having a resistance of 10 k, and a load resistance RL = 12 k is connected to the output terminal, find the resulting Av and Gv . If the peak voltage of the sine wave appearing between
base and emitter is to be limited to 5 mV, what vˆ
and what output voltage signal appears across the load?
D 7.75 Design a CE amplifier with a resistance Re in the emitter to meet the following specifications:
(i) Input resistance R = 15 k. in
(ii) When fed from a signal source with a peak amplitude of 0.15 V and a source resistance of 30 k, the peak amplitude of vπ is 5 mV.
Specify Re and the bias current IC . The BJT has β = 74. If the total resistance in the collector is 6 k, find the overall voltage gain Gv and the peak amplitude of the output signal v o .
D 7.76 Inclusion of an emitter resistance Re reduces the variability of the gain Gv due to the inevitable wide variance in the value of β . Consider a CE amplifier operating between a signal source with Rsig = 10 k and a total collector resistance RC∥RL of10k.TheBJTisbiasedatIC =1mAanditsβ is specified to be nominally 100 but can lie in the range of 50 to 150. First determine the nominal value and the range of
Rsig/β + 1/gm ConsiderthecaseR′ =10kandR =10k,andlet
whereRL′ =RL∥RC.
theBJTbebiasedatIC =1mA.TheBJThasanominalβ of
100.
(a) What is the nominal value of G ?
L sig
is allowed,
(b) If β can be anywhere between 50 and 150, what is the corresponding range of G ?
(c) If in a particular design, it is required to maintain G v
within ±20% of its nominal value, what is the maximum
allowable range of β?
(d) If it is not possible to restrict β to the range found in (c),
v
and the designer has to contend with β in the range 50 to 150, what value of bias current I would result in G
Cv falling in a range of ±20% of a new nominal value? What
is the nominal value of G in this case? v
v
sig
7.70 Two identical CE amplifiers are connected in cascade. The first stage is fed with a source vsig having a resistance Rsig = 10 k. A load resistance RL = 10 k is connected to the collector of the second stage. Each BJT is biased at IC = 0.25 mA and has β = 100. Each stage utilizes a collector resistance RC = 10 k.
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
492 Chapter 7 Transistor Amplifiers
G without resistance R . Then select a value for R that will what are the corresponding amplitudes of v
v e e sig ensure that G be within ±20% of its new nominal value. α≃1.
the expected range of Gv .
v
Specify the value of R , the new nominal value of G , and ev
7.77 A CG amplifier using an NMOS transistor for which gm = 2 mA/V has a 5-k drain resistance RD and a 5-k load resistance RL. The amplifier is driven by a voltage source having a 750- resistance. What is the input resistance of the amplifier? What is the overall voltage gain Gv ? By what factor must the bias current ID of the MOSFET be changed so that Rin matches Rsig?
7.78 A CG amplifier when fed with a signal source having Rsig = 100 is found to have an overall voltage gain of 12 V/V. When a 100- resistance was added in series with the signal generator the overall voltage gain decreased to 10 V/V. Whatmustgm oftheMOSFETbe?IftheMOSFETisbiasedat ID = 0.25 mA, at what overdrive voltage must it be operating?
D 7.79 A CB amplifier is operating with RL = 10 k, RC = 10 k, and Rsig = 50 . At what current IC should the transistor bebiasedfortheinputresistanceRin toequalthatofthesignal source? What is the resulting overall voltage gain? Assume α ≃ 1.
7.80 For the circuit in Fig. P7.80, let Rsig ≫ re and α ≃ 1. Find vo.
and v ? Assume o
7.82 A source follower is required to connect a high-resistance source to a load whose resistance is nominally 2 k but can be as low as 1.5 k and as high as 5 k. What is the maximum output resistance that the source follower must have if the output voltage is to remain within ±10% of nominal value? If the MOSFET has kn = 2.5 mA/V2 , at what current ID must it be biased? At what overdrive voltage is the MOSFET operating?
D 7.83 A source follower is required to deliver a 0.5-V peak sinusoid to a 2-k load. If the peak amplitude of vgs is to be limited to 50 mV, and the MOSFET transconductance parameter kn is 5 mA/V2 , what is the lowest value of ID at which the MOSFET can be biased? At this bias current, what are the maximum and minimum currents that the MOSFET will be conducting (at the positive and negative peaks of the output sine wave)? What must the peak amplitude of vsig be?
D 7.84 An emitter follower is required to deliver a 0.5-V peak sinusoid to a 2-k load. If the peak amplitude of vbe is to be limited to 5 mV, what is the lowest value of IE at which the BJT can be biased? At this bias current, what are the maximum and minimum currents that the BJT will be conducting (at the positive and negative peaks of the output sine wave)? If the resistance of the signal source is 200 k, what value of Gv is obtained? Thus determine the required amplitude of vsig. Assume β = 100.
7.85 An emitter follower with a BJT biased at IC = 2 mA and having β=100 is connected between a source with Rsig =10kandaloadRL =0.5k.
(a) Find Rin, vb/vsig, and vo/vsig.
(b) If the signal amplitude across the base–emitter junction
is to be limited to 10 mV, what is the corresponding
amplitude of vsig and vo?
(c) Find the open-circuit voltage gain Gvo and the output
resistance Rout . Use these values first to verify the value of Gv obtained in (a), then to find the value of Gv obtained withRL reducedto250.
7.86 An emitter follower is operating at a collector bias current of 0.5 mA and is used to connect a 10-k source to a 1-k load. If the nominal value of β is 100, what output resistance Rout and overall voltage gain Gv result? Now if
CHAPTER 7 PROBLEMS
RC vo
isig Rsig
Figure P7.80
7.81 ACBamplifierisbiasedatIE =0.2 mAwithRC =RL = 10 k and is driven by a signal source with Rsig = 0.5 k. Find the overall voltage gain Gv . If the maximum signal amplitude of the voltage between base and emitter is limited to 10 mV,
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
CHAPTER 7 PROBLEMS
transistor β is specified to lie in the range 50 to 150, find the correspondingrangeofRout andGv.
7.87 An emitter follower, when driven from a 5-k source, was found to have an output resistance Rout of 150. The output resistance increased to 250 when the source resistance was increased to 10 k. Find the overall voltage gain when the follower is driven by a 10-k source and loaded by a 1-k resistor.
7.88 For the general amplifier circuit shown in Fig. P7.88 neglect the Early effect.
(a) Find expressions for vc/vsig and ve/vsig.
(b) If vsig is disconnected from node X, node X is grounded,
Problems 493 D 7.91 In this problem, we investigate the effect of changing
the bias current IC on the overall voltage gain Gv of a CE amplifier. Consider the situation of a CE amplifier operating with a signal source having Rsig = 10 k and having RC ||RL = 10k.TheBJTisspecifiedtohaveβ=100andVA =25V.
and node Y is disconnected from ground and connected to vsig, find the new expression for vc/vsig.
1.0 mA, and 1.25 mA. Observe the effect of r on limiting o
Gv as IC is increased. Find the value of IC that results in Gv=50V/V.
Section 7.4: Biasing
D 7.92 Consider the classical biasing scheme shown in Fig.7.48(c),usinga9-Vsupply.FortheMOSFET,Vt =1V, λ = 0, and kn = 2 mA/V2. Arrange that the drain current is 1 mA, with about one-third of the supply voltage across each of RS and RD. Use 22 M for the larger of RG1 and RG2. What are the values of RG1 , RG2 , RS , and RD that you have chosen? Specify them to two significant digits. For your design, how far is the drain voltage from the edge of saturation?
D 7.93 Using the circuit topology displayed in Fig. 7.48(e), arrange to bias the NMOS transistor at ID = 0.5 mA with VD midway between cutoff and the beginning of triode operation. The available supplies are ±5 V. For the NMOS transistor, Vt = 1.0 V, λ = 0, and kn = 1 mA/V2. Use a gate-bias resistor of 10 M. Specify RS and RD to two significant digits.
D *7.94 In an electronic instrument using the biasing scheme shown in Fig. 7.48(c), a manufacturing error reduces RS tozero.LetVDD =15V,RG1 =10M,andRG2 =5.1M. What is the value of VG created? If supplier specifications allow kn to vary from 0.2 to 0.3 mA/V2 and Vt to vary from 1.0 V to 1.5 V, what are the extreme values of ID that may result? What value of RS should have been installed to limit the maximum value of ID to 1.5 mA? Choose an appropriate standard 5% resistor value (refer to Appendix J). What extreme values of current now result?
7.95 An NMOS transistor is connected in the bias circuit of
Fig. 7.48(c), with VG = 5 V and RS = 3 k. The transistor
has Vt = 1 V and kn = 2 mA/V2 . What bias current results?
Ifatransistorforwhichk is50%higherisused,whatisthe n
resulting percentage increase in ID?
7.96 The bias circuit of Fig. 7.48(c) is used in a
ic
ve
vc
Use Eq. (7.114) (with r included in parallel with R and R in oCL
the numerator) to find Gv at IC = 0.1 mA, 0.2 mA, 0.5 mA,
i XRB b
vsig
RC
ie
RE
Y
Figure P7.88
7.89 When the Early effect is neglected, the overall voltage gain of a CE amplifier with a collector resistance RC = 10 k is calculated to be −100 V/V. If the BJT is biased at IC = 1 mA and the Early voltage is 100 V, provide a better estimate of the voltage gain Gv .
*7.90 Show that when ro is taken into account, the voltage gain of the source follower becomes
G≡vo= RL∥ro
v vsig R ∥r + 1
L o gm
Now,withRL removed,thevoltagegainiscarefullymeasured andfoundtobe0.98.Then,whenRL isconnectedanditsvalue is varied, it is found that the gain is halved at RL = 500 . If the amplifier remained linear throughout this measurement, what must the values of gm and ro be?
design with VG = 5V and RS = 2k. For a MOSFET with = Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
494 Chapter 7 Transistor Amplifiers
kn = 2 mA/V2 , the source voltage was measured and found
to be 2 V. What must Vt be for this device? If a device for which Vt is 0.5 V less is used, what does VS become? What bias current results?
D 7.97 Design the circuit of Fig. 7.48(e) for a MOSFET havingVt =1Vandkn =4mA/V2.LetVDD =VSS =5V. Design for a dc bias current of 0.5 mA and for the largest possible voltage gain (and thus the largest possible RD) consistent with allowing a 2-V peak-to-peak voltage swing at the drain. Assume that the signal voltage on the source terminal of the FET is zero.
D 7.98 Design the circuit in Fig. P7.98 so that the transistor operates in saturation with VD biased 1 V from the edgeofthetrioderegion,withID =1mAandVD =3V,for each of the following two devices (use a 10-μA current in the voltage divider):
(a) V=1Vandk′ W/L=0.5mA/V2 t p
and its value, when multiplied by the variability (or tolerance) of K, provides the corresponding expected variability of ID,
I K D =SID
IKK D
The purpose of this problem is to investigate the use of the sensitivity function in the design of the bias circuit of Fig. 7.48(e).
(a) Show that for Vt constant,
SID=1 1+2KIR KDS
(b) ForaMOSFEThavingK=100μA/V2 withavariability of ±10% and Vt = 1 V, find the value of RS that would result in ID = 100 μA with a variability of ±1%. Also, findVGS andtherequiredvalueofVSS.
(c) If the available supply VSS = 5 V, find the value of RS for ID = 100 μA. Evaluate the sensitivity function, and give the expected variability of ID in this case.
D **7.100 The variability (△ID /ID ) in the bias current ID due to the variability (△Vt /Vt ) in the threshold voltage Vt can be evaluated from
t
CHAPTER 7 PROBLEMS
(b) Vt =2Vandkp′ W/L=1.25mA/V2
For each case, specify the values of VG, VD, VS, R1, R2, RS,
and RD.
10 V
△I △V
D =SID
I Vt V
Dt
where SID , the sensitivity of I relative to V , is defined as
R1RS VtDt
VG
Figure P7.98
VS
VD
(a)
(b)
ID ∂ID Vt SVt =∂Vt ID
ForthecaseofaMOSFETbiasedwithafixedVGS,show that
SID =−2Vt Vt VOV
and find the variability in ID for Vt = 0.5 V and △Vt /Vt = ±5%. Let the MOSFET be biased at VOV = 0.25 V. ForthecaseofaMOSFETbiasedwithafixedgatevoltage VG and a resistance RS included in the source lead, show that
ID 2Vt
SVt =−V +2IR
For the same parameters given in (a), find the required value of (ID RS ) and VG to limit △ID /ID to ±5%. What value of RS is needed if ID is 100 μA?
R2 RD
D **7.99 A very useful way to characterize the stability of the bias current ID is to evaluate the sensitivity of ID relative to a particular transistor parameter whose variability might be large. The sensitivity of ID relative to the MOSFET parameter K ≡ 1 k′(W/L) is defined as
2
SID ≡∂ID/ID =∂ID K K ∂K/K ∂K ID
OV DS
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
CHAPTER 7 PROBLEMS
7.101 In the circuit of Fig. 7.50, let RG = 10 M, RD = 10 k, and VDD = 10 V. For each of the following two transistors, find the voltages VD and VG.
(a) Vt =1Vandkn =0.5mA/V2 (b) Vt =2Vandkn =1.25mA/V2
D 7.102 Using the feedback bias arrangement shown in Fig. 7.50 with a 5-V supply and an NMOS device for which Vt = 1V and kn = 10mA/V2, find RD to establish a drain current of 0.2 mA.
D 7.103 Figure P7.103 shows a variation of the feedback-bias circuit of Fig. 7.50. Using a 5-V supply with an NMOS transistor for which Vt = 0.8 V, kn = 8 mA/V2 , and λ = 0, provide a design that biases the transistor at ID = 1 mA, with VDS large enough to allow saturation operation for a 2-V negative signal swing at the drain. Use 22 M as the largest resistor in the feedback-bias network. What values of RD, RG1, and RG2 have you chosen? Specify all resistors to two significant digits.
Problems 495 the range obtained for VCE ? Comment on the efficacy of this
biasing arrangement.
D 7.105 It is required to bias the transistor in the circuit of
Fig. 7.51(b) at I = 1 mA. The transistor β is specified to be C
nominally 100, but it can fall in the range of 50 to 150. For VCC =+3 V and RC =2 k, find the required value of RB to achieve IC = 1 mA for the “nominal” transistor. What is the expected range for IC and VCE ? Comment on the efficacy of this bias design.
D 7.106 Consider the single-supply bias network shown in Fig. 7.52(a). Provide a design using a 9-V supply in which the supply voltage is equally split between RC , VCE , and RE with a collector current of 0.6 mA. The transistor β is specified to have a minimum value of 90. Use a voltage-divider current of IE/10, or slightly higher. Since a reasonable design should operate for the best transistors for which β is very high, do your initial design with β = ∞. Then choose suitable 5% resistors (see Appendix J), making the choice in a way that will result in a VBB that is slightly higher than the ideal value. Specify the values you have chosen for RE, RC, R1, and R2. Now, find VB, VE, VC, and IC for your final design using β = 90.
D 7.107 Repeat Problem 7.106, but use a voltage-divider current that is IE /2. Check your design at β = 90. If you have the data available, find how low β can be while the value of IC does not fall below that obtained with the design of Problem 7.106 for β = 90.
D *7.108 It is required to design the bias circuit of Fig. 7.52 for a BJT whose nominal β = 100.
(a) Find the largest ratio RB/RE that will guarantee IE remains within ±5% of its nominal value for β as low as 50 and as high as 150.
(b) If the resistance ratio found in (a) is used, find an
expressionforthevoltageVBB ≡VCCR2/ R1 +R2 thatwill
result in a voltage drop of VCC /3 across RE .
(c) For VCC = 5 V, find the required values of R1, R2, and RE to obtain IE = 0.5 mA and to satisfy the requirement for
stabilityofIE in(a).
(d) Find RC so that VCE = 1.0 V for β equal to its nominal
value.
Check your design by evaluating the resulting range
VDD
RD
RG1
RG2
Figure P7.103
D 7.104 For the circuit in Fig. 7.51(a), neglect the base current IB in comparison with the current in the voltage divider. It is required to bias the transistor at IC = 1 mA, which requires selecting RB1 and RB2 so that VBE = 0.710 V. If VCC = 3 V, what must the ratio RB1 /RB2 be? Now, if RB1 and RB2 are1%resistors,thatis,eachcanbeintherangeof0.99to 1.01 of its nominal value, what is the range obtained for VBE ? What is the corresponding range of IC ? If RC = 2 k, what is
ofIE.
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
496 Chapter 7 Transistor Amplifiers
D *7.109 Consider the two-supply bias arrangement shown in Fig. 7.53 using ±5-V supplies. It is required to design the circuit so that IC = 0.5 mA and VC is placed 2 V above VE .
(a) For β = ∞, what values of RE and RC are required?
(b) If the BJT is specified to have a minimum β of 50, find the largest value for RB consistent with the need to limit the voltage drop across it to one-tenth the voltage drop
across RE .
(c) Whatstandard5%resistorvalues(seeAppendixJ)would
you use for RB , RE , and RC ? In making your selection, use somewhat lower values in order to compensate for the low-β effects.
Design this circuit for β = 100. Use a current through RB2 equal to the base current. Now, what values of VC and IC result with β = ∞?
VCC
RC
VC
IC
RB1 (d) Forthevaluesyouselectedin(c),findIC,VB,VE,andVC
CHAPTER 7 PROBLEMS
for β = ∞ and for β = 50.
D *7.110 Utilizing ±3-V power supplies, it is required to design a version of the circuit in Fig. 7.53 in which the signal will be coupled to the emitter and thus RB can be set to zero. Find values for RE and RC so that a dc emitter current of 0.4 mA is obtained and so that the gain is maximized while allowing ±1 V of signal swing at the collector. If temperature increases from the nominal value of 25°C to 125°C, estimate the percentage change in collector bias current. In addition to the –2 mV/°C change in VBE , assume that the transistor β changes over this temperature range from 50 to 150.
D 7.111 Using a 3-V power supply, design a version of the circuit of Fig. 7.54 to provide a dc emitter current of 0.5 mA and to allow a ±1-V signal swing at the collector. The BJT has a nominal β=100. Use standard 5% resistor values (see Appendix J). If the actual BJT used has β = 50, what emitter current is obtained? Also, what is the allowable signal swing at the collector? Repeat for β = 150.
D *7.112 (a) Using a 3-V power supply, design the feedback bias circuit of Fig. 7.54 to provide IC = 1 mA and VC =VCC/2forβ=100. (b)Selectstandard5%resistorvalues,andreevaluateVC and IC forβ=100.
(c)FindVC andIC forβ=∞.
(d) To improve the situation that obtains when high-β transistors are used, we have to arrange for an additional current to flow through RB. This can be achieved by connecting a resistor between base and emitter, as shown in Fig. P7.112.
RB2
Figure P7.112
D 7.113 A circuit that can provide a very large voltage gain for a high-resistance load is shown in Fig. P7.113. Find the valuesofIandRB tobiastheBJTatIC =1mAandVC = 1.5V.Letβ=100.
RB
VCC
I
VC
IC
Figure P7.113
7.114 The circuit in Fig. P7.114 provides a constant cur- rent IO as long as the circuit to which the collector is
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
CHAPTER 7 PROBLEMS
connected maintains the BJT in the active mode. Show that
V R/R+R−V CC212 BE
Problems 497 and keeping the current in each junction the same, the current
IO will be
IO=α
R + R ∥R /(β+1)
I=
O 2R
VCC
E12
which is independent of VBE . What must the relationship of RE toR1 andR2 be?ForVCC =10VandVBE =0.7V,design the circuit to obtain an output current of 0.5 mA. What is the lowest voltage that can be applied to the collector of Q3?
D7.116 ForthecircuitinFig.P7.116findthevalueofRthat will result in I ≃ 0.5 mA. What is the largest voltage that can
O
be applied to the collector? Assume
Figure P7.116
Section 7.5: Discrete-Circuit Amplifiers
7.117 Calculate the overall voltage gain Gv of a common-source amplifier for which gm = 3 mA/V, ro = 100k,RD =10k,andRG =10M.Theamplifierisfed from a signal source with a The ́venin resistance of 1 M, and the amplifier output is coupled to a load resistance of 20 k.
7.118 The NMOS transistor in the CS amplifier shown inFig.P7.118hasVt =0.7VandVA =50V.
(a) Neglecting the Early effect, verify that the MOSFET is operating in saturation with ID = 0.5 mA and VOV = 0.3 V. What must the MOSFET’s kn be? What is the dc voltage at the drain?
(b) FindRin andGv.
(c) If vsig is a sinusoid with a peak amplitude vˆsig, find the
maximum allowable value of vˆsig for which the tran- sistor remains in saturation. What is the corresponding amplitude of the output voltage?
E
Figure P7.114
D *7.115 For the circuit in Fig. P7.115, assuming all transistors to be identical with β infinite, derive an expression for the output current IO, and show that by selecting
R1 =R2
Figure P7.115
VBE = 0.7 V.
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
498 Chapter 7
Transistor Amplifiers
5 V
120 k
vsig
Rin
Figure P7.118
CC1
300 k
200 k
5 k
2 k
CC2
5 k
CS
vo
CHAPTER 7 PROBLEMS
(d) What is the value of resistance Rs
inserted in series with capacitor CS in order to allow us to double the input signal vˆsig ? What output voltage now results?
D *7.119 The PMOS transistor in the CS amplifier of Fig. P7.119 has V = −0.7 V and a very large V .
(c) Find the largest sinusoid vˆsig that the amplifier can handle while remaining in the saturation region. What is the corresponding signal at the output?
(d) If to obtain reasonably linear operation, vˆsig is limited to 50 mV, what value can RD be increased to while maintaining saturation-region operation? What is the new value of Gv ?
that needs to be
tp A
(a) Select a value for RS to bias the transistor at ID = 7.120 Figure P7.120 shows a scheme for coupling and
0.3mA and V =0.3V. Assume v to have a zero OV sig
dc component.
(b) Select a value for RD that results in Gv = −10 V/V.
amplifying a high-frequency pulse signal. The circuit utilizes
2.5 V RS
RD
2.5 V
CS CC
VDD
RD
vo
Rsig
Figure P7.119
vd1
50- coaxial cable Q2
id
vsig
vo
Q Ri2 = 50 i1
v
5 mV
Figure P7.120
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
CHAPTER 7 PROBLEMS
two MOSFETs whose bias details are not shown and a 50- coaxial cable. Transistor Q1 operates as a CS amplifier and Q2 as a CG amplifier. For proper operation, transistor Q2 is required to present a 50- resistance to the cable. This situation is known as “proper termination” of the cable and ensures that there will be no signal reflection coming back on the cable. When the cable is properly terminated, its input resistance is 50 . What must gm2 be? If Q1 is biased at the same point as Q2, what is the amplitude of the current pulses in the drain of Q1 ? What is the amplitude of the voltage pulses at the drain of Q1? What value of RD is required to provide 1-V pulses at the drain of Q2?
D *7.121 The MOSFET in the circuit of Fig. P7.121 has Vt =0.8V,kn =5mA/V2,andVA =40V.
(a) Find the values of RS, RD, and RG so that ID = 0.4 mA, the largest possible value for RD is used while a maximum signal swing at the drain of ±0.8 V is possible, and the input resistance at the gate is 10 M. Neglect the Early effect.
(b) Find the values of gm and ro at the bias point.
(c) If terminal Z is grounded, terminal X is connected to a signal source having a resistance of 1 M, and terminal Y is connected to a load resistance of 10 k, find the
voltage gain from signal source to load.
(d) If terminal Y is grounded, find the voltage gain from X
to Z with Z open-circuited. What is the output resistance of the source follower?
(e) If terminal X is grounded and terminal Z is connected to a current source delivering a signal current of 50 μA and having a resistance of 100 k, find the voltage signal that can be measured at Y. For simplicity, neglect the effect of ro .
*7.122
(a) The NMOS transistor in the source-follower circuit of Fig. P7.122(a) has gm = 10 mA/V and a large ro . Find the open-circuit voltage gain and the output resistance.
(b) The NMOS transistor in the common-gate amplifier of Fig. P7.122(b) has gm = 10 mA/V and a large ro . Find the input resistance and the voltage gain.
(c) If the output of the source follower in (a) is connected to the input of the common-gate amplifier in (b), use the results of (a) and (b) to obtain the overall voltage gain vo/vi.
Problems 499
vi
vo1
10 k
(a)
5 V
RD
5 k
Y
vi2 Z
10 k
Figure P7.122
vo 2 k
X
RG
RS
5 V
(b)
Figure P7.121
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
500 Chapter 7 Transistor Amplifiers
D **7.123 The MOSFET in the amplifier circuit of Fig.P7.123hasVt =0.6V,kn =5mA/V2,andVA =60V. The signal vsig has a zero average.
(a) It is required to bias the transistor to operate at an overdrive voltage VOV = 0.2 V. What must the dc voltage at the drain be? Calculate the dc drain current ID taking into account VA. Now, what value must the drain resistance RD have?
(b) Calculate the values of gm and ro at the bias point established in (a).
(c) Using the small-signal equivalent circuit of the amplifier, show that the voltage gain is given by
vo =− R2/R1
vsig 1+ 1+R2/R1
gm(RD ∥ro ∥R2)(1−1/gmR2) and find the value of the gain.
D **7.124 The MOSFET in the amplifier circuit of Fig. P7.124 has Vt = 0.6 V and kn = 5 mA/V2. We shall assume that VA is sufficiently large so that we can ignore the Early effect. The input signal vsig has a zero average.
(a) It is required to bias the transistor to operate at an overdrive voltage VOV = 0.2 V. What must the dc voltage at the drain be? Calculate the dc drain current ID. What value must RD have?
(b) Calculate the value of gm at the bias point.
(c) Use the small-signal equivalent circuit of the amplifier to
show that
and
where
vo = 1+(R2/R1) vsig 1+ (1+R2/R1)
g m R D′
Rin = 1 (1+gmRD′ R1 ) gm R1 +R2
CHAPTER 7 PROBLEMS
VDD = + 10 V
RD
R2 v
RD′ =RD∥(R1+R2) (d) Evaluate vo/vsig and Rin.
VDD = + 10 V
2 M
o
R1
500 k
v R2v
RD
sig
Figure P7.123
P.S. This feedback amplifier and the gain expression should remind you of an op amp utilized in the inverting configura- tion. We shall study feedback formally in Chapter 11.
0.5 M
0.5 M
o
R1
vsig Rin
Figure P7.124
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
CHAPTER 7 PROBLEMS
P.S. This feedback amplifier circuit and the gain formula should remind you of an op amp connected in the nonin- verting configuration. We shall study feedback formally in Chapter 11.
7.125 For the common-emitter amplifier shown in Fig. P7.125, let VCC =15 V, R1 =27 k, R2 =15 k, RE = 2.4 k, and RC = 3.9 k. The transistor has β = 100. Calculate the dc bias current IC. If the amplifier operates between a source for which Rsig = 2 k and a load of 2 k, replace the transistor with its hybrid-π model, and find the values of Rin, and the overall voltage gain vo/vsig.
D 7.126 Using the topology of Fig. P7.125, design an amplifier to operate between a 2-k source and a 2-k load with a gain v o /v sig of –40 V/V. The power supply available is 15V. Use an emitter current of approxi- mately 2mA and a current of about one-tenth of that in the voltage divider that feeds the base, with the dc voltage at the base about one-third of the supply. The transistor available has β=100. Use standard 5% resistors (see Appendix J).
Figure P7.125
D 7.127 A designer, having examined the situation described in Problem 7.125 and estimating the available gain to be approximately –36.3V/V, wants to explore the possibility of improvement by reducing the loading
of the source by the amplifier input. As an experiment, the designer varies the resistance levels by a factor of approximately 3: R1 to 82 k, R2 to 47 k, RE to 7.2 k, and RC to 12 k (standard values of 5%-tolerance resistors). With VCC =15 V, Rsig =2 k, RL =2 k, and β=100, what does the gain become? Comment.
D 7.128 The CE amplifier circuit of Fig. P7.128 is biased with a constant-current source I. It is required to design the circuit (i.e., find values for I, RB , and RC ) to meet the following specifications:
(a) Rin ≃ 10 k.
(b) The dc voltage drop across RB is approximately 0.2 V. (c) The open-circuit voltage gain from base to collector is
the maximum possible, consistent with the requirement that the collector voltage never fall by more than approximately 0.4 V below the base voltage with the signal between base and emitter being as high as 5 mV.
Assume that vsig is a sinusoidal source, the available supply VCC = 5 V, and the transistor has β = 100. Use standard 5% resistance values, and specify the value of I to one significant digit. What base-to-collector open-circuit voltage gain does your design provide? If Rsig = RL = 20 k, what is the overall voltage gain?
Figure P7.128
Problems 501
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
502 Chapter 7 Transistor Amplifiers
D 7.129 In the circuit of Fig. P7.129, v sig is a small sine-wave
signal with zero average. The transistor β is 100.
(a) Find the value of RE to establish a dc emitter current of
(b) Find RC to establish a dc collector voltage of about +0.5 V.
(c) For RL = 10 k, draw the small-signal equivalent circuit of the amplifier and determine its overall voltage gain.
*7.130 TheamplifierofFig.P7.130consistsoftwoidentical common-emitter amplifiers connected in cascade. Observe that the input resistance of the second stage, Rin2, constitutes the load resistance of the first stage.
(a) For VCC =15 V, R1 =100 k, R2 =47 k, RE =3.9 k, RC = 6.8 k, and β = 100, determine the dc col- lector current and dc collector voltage of each transistor.
(b) Draw the small-signal equivalent circuit of the entire amplifier and give the values of all its components.
(c) Find Rin1 and vb1/vsig for Rsig = 5 k.
(d) Find Rin2 and vb2/vb1.
(e) ForRL =2k,findvo/vb2.
(f) Find the overall voltage gain vo/vsig.
about 0.5 mA.
3V
CHAPTER 7 PROBLEMS
Rsig
vsig
2.5 k
Figure P7.129
3V
Rsig
in
Figure P7.130
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
vsig
in
CHAPTER 7 PROBLEMS
7.131 In the circuit of Fig. P7.131, the BJT is biased with a constant-current source, and vsig is a small sine-wave signal. Find Rin and the gain v o /v sig . Assume β = 100. If the amplitude of the signal vbe is to be limited to 5 mV, what is the largest signal at the input? What is the corresponding signal at the output?
Figure P7.131
*7.132 The BJT in the circuit of Fig. P7.132 has β = 100.
(a) Find the dc collector current and the dc voltage at the collector.
(b) Replacing the transistor by its T model, draw the small-signal equivalent circuit of the amplifier. Ana- lyze the resulting circuit to determine the voltage gain vo/vi.
7.133 For the circuit in Fig. P7.133, find the input resistance Rin and the voltage gain v o /v sig . Assume that the source provides a small signal v sig and that β = 100.
Problems 503
0.5 mA
Rsig 50
vsig
Rin
5k
Figure P7.133
7.134 Fortheemitter-followercircuitshowninFig.P7.134, the BJT used is specified to have β values in the range of 50 to 200 (a distressing situation for the circuit designer).
+ 3V
Figure P7.132
Figure P7.134
vsig
in
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
504 Chapter 7 Transistor Amplifiers
For the two extreme values of β (β=50 and β=200),
find:
(a) IE, VE, and VB
(b) the input resistance Rin (c) the voltage gain vo/vsig
7.135 For the emitter follower in Fig. P7.135, the signal source is directly coupled to the transistor base. If the dc component of vsig is zero, find the dc emitter current. Assume β=100. Neglecting ro, find Rin, the voltage gain vo/vsig, the current gain io/ii, and the output resistance Rout.
CHAPTER 7 PROBLEMS
3
vsig
Figure P7.135
Rin
Rout
2
Figure P7.136
**7.137 ForthefollowercircuitinFig.P7.137,lettransistor Q1 have β = 50 and transistor Q2 have β = 100, and neglect the effect of ro. Use VBE = 0.7 V.
5
**7.136 ForthecircuitinFig.P7.136,calledabootstrapped follower:
(a) Find the dc emitter current and gm , re , and rπ . Use β = 100.
(b) Replace the BJT with its T model (neglecting ro), and analyze the circuit to determine the input resistance Rin Rin and the voltage gain vo/vsig.
(c) Repeat (b) for the case when capacitor CB is
open-circuited. Compare the results with those obtained
in (b) to find the advantages of bootstrapping. Figure P7.137
50 A
5 mA
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
CHAPTER 7 PROBLEMS
(a) Find the dc emitter currents of Q1 and Q2. Also, find the dc voltages VB1 and VB2.
(b) If a load resistance RL = 1 k is connected to the output terminal, find the voltage gain from the base to the emitter
of Q2 , v o /v b2 , and find the input resistance Rib2 looking into the base of Q2. (Hint: Consider Q2 as an emitter
follower fed by a voltage v
(c) Replacing Q2 with its input resistance Rib2 found in (b),
analyze the circuit of emitter follower Q1 to determine its input resistance Rin, and the gain from its base to its emitter, ve1/vb1.
(d) If the circuit is fed with a source having a 100-k resistance,findthetransmissiontothebaseofQ1, vb1/vsig.
b2
at its base.)
a higher 3-dB frequency fH = 500 kHz. In Chapter 10 we will learnthatconnectingaresistanceR intheemitteroftheBJT
(e) Find the overall voltage gain vo/vsig.
D 7.138 A CE amplifier has a midband voltage gain of
A = 100 V/V, a lower 3-dB frequency of f = 100 Hz, and ML
e results in lowering fL and raising fH by the factor 1 + gm Re .
If the BJT is biased at IC = 1 mA, find Re that will result in fH at least equal to 2 MHz. What will the new values of fL and AM be?
Problems 505
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
PART II
Integrated-Circuit Amplifiers
CHAPTER 8
BuildingBlocksofIntegrated-CircuitAmplifiers 508
CHAPTER 9
DifferentialandMultistageAmplifiers 594
CHAPTER 10
FrequencyResponse 696
CHAPTER 11
Feedback 806
CHAPTER 12
OutputStagesandPowerAmplifiers 920
CHAPTER 13
Operational-AmplifierCircuits 994
Having studied the MOSFET and the BJT and become familiar with their basic circuit applications, we are now ready to consider their use in the design of practical amplifier circuits that can be fabricated in integrated-circuit (IC) form. Part II is devoted
to this rich subject. Its six chapters constitute a coherent treatment of IC amplifier design and can thus serve as a second course in electronic circuits.
Beginning with a brief introduction to the philosophy of IC design, Chapter 8 presents the basic circuit building blocks that are utilized in the design of IC amplifiers. However, the most important building block of all, the differential-pair configuration, is deferred to Chapter 9, where it is the main topic. Chapter 9 also considers the design of amplifiers that require a number of cascaded stages.
As mentioned at various points in Part I, amplifiers have finite bandwidths. Chapter 10 is devoted to the frequency-response analysis of amplifiers; it provides a comprehensive study of the mechanisms that limit the bandwidth and the tools and methods that are utilized to estimate it for a wide variety of amplifier circuit configurations. While the study of the first half or so of Chapter 10 is essential, some of its later sections can be postponed until a later point in the course or even to subsequent courses.
An essential tool in amplifier design is the judicious use of feedback. Chapter 11 deals with this exceedingly important subject. A thorough understanding of feedback concepts, insight into feedback configurations, and proficiency in the use of the feedback-analysis method are invaluable to the serious circuit designer.
In Chapter 12, we switch gears from dealing with primarily small-signal amplifiers to studying those that are required to handle large signals and large amounts of power. Finally, Chapter 13 brings together all the topics of Part II in an important application: namely, the design of operational-amplifier circuits. We will then have come full circle, from considering the op amp as a black box in Chapter 2 to understanding what is inside the box in Chapter 13.
Throughout Part II, MOSFET and BJT circuits are treated side by side. Because over 90% of ICs today employ the MOSFET, its circuits are presented first. Nevertheless, BJT circuits are presented with equal depth, although sometimes somewhat more briefly. In this regard, we draw the reader’s attention to Appendix G (on the website), which presents a valuable compilation of the properties of transistors of both types, allowing interesting comparisons to be made. As well, typical device parameter values are provided in Appendix K for a number of CMOS and bipolar fabrication process technologies.
507
CHAPTER 8
Building Blocks of Integrated-Circuit Amplifiers
Introduction 509
8.1 IC Design Philosophy 510
8.2 IC Biasing–Current Sources, Current Mirrors, and Current-Steering Circuits 511
8.3 The Basic Gain Cell 525
8.4 The Common-Gate and Common-Base Amplifiers 537
8.5 The Cascode Amplifier 546
8.6 Current-Mirror Circuits with Improved
Performance 559
8.7 Some Useful Transistor Pairings 567
Summary 575 Problems 576
IN THIS CHAPTER YOU WILL LEARN
1. The basic integrated-circuit (IC) design philosophy and how it differs from that for discrete-circuit design.
2. How current sources are used to bias IC amplifiers and how the use of current mirrors allows the replication of the reference current generated in one location at various other locations on the IC chip.
3. The basic gain cells of IC amplifiers, namely, the CS and CE amplifiers with current-source loads.
4. How the CG and CB amplifiers act as current buffers.
5. How to increase the gain realized in the basic gain cells by employing the principle of
cascoding.
6. Analysis and design of the cascode amplifier and the cascode current source in both their MOS and bipolar forms.
7. Some ingenious analog circuit-design techniques that result in current mirrors with vastly improved characteristics.
8. How to pair transistors to realize amplifiers with characteristics superior to those obtained from a single-transistor stage.
Introduction
Having studied the two major transistor types, the MOSFET and the BJT, and their basic discrete-circuit amplifier configurations, we are now ready to begin the study of integrated-circuit (IC) amplifiers. This chapter is devoted to the design of the basic building blocks of IC amplifiers.
We begin with a brief section on the design philosophy of integrated circuits and how it differs from that of discrete circuits. This is followed by the study of IC biasing in Section 8.2, highlighting the design of current sources and current mirrors. The current mirror is one of the most important building blocks of analog integrated circuits. More advanced mirror circuits are presented in Section 8.6.
The heart of this chapter is the material in Sections 8.3 to 8.5. In Section 8.3 we present the basic gain cell of IC amplifiers, namely, the current-source-loaded common-source (common-emitter) amplifier. Then, in determining how to increase its gain, we discover the
509
510 Chapter 8
Building Blocks of Integrated-Circuit Amplifiers
need for current buffers. The two amplifier configurations capable of implementing a current buffer, the common-gate and common-base amplifiers, are studied in Section 8.4. This study differs from that in Chapter 7 in that ro of the transistor is included, as must always be the case in integrated circuits. The study of the CG and CB leads naturally and seamlessly to the principle of cascoding and its applications in amplifier design: namely, the cascode amplifier and the cascode current source, which are very important building blocks of IC amplifiers.
The chapter concludes with the presentation in Section 8.7 of an interesting and useful collection of amplifier configurations, each utilizing a pair of transistors. Throughout this chapter, MOS and bipolar circuits are presented side by side, which allows a certain economy in presentation and, more important, provides an opportunity to compare and contrast the two circuit types.
8.1 IC Design Philosophy
Integrated-circuit fabrication technology (Appendix A) imposes constraints on and provides opportunities to the circuit designer. To cope with the constraints and take advantage of the opportunities, IC designers have over the years invented (and continue to invent) many ingenious techniques, and a distinct philosophy has emerged for the design of integrated circuits. In the following we provide a brief summary of the important constraints and opportunities and the major features of the IC design philosophy.
1. Resistors. To minimize the chip area, large and even moderate-size resistors are to be avoided. As well, economic considerations discourage the use of resistors of precise values. On the other hand, transistors can be made small and cheaply, and the designer is encouraged to use transistors in preference to resistors wherever possible. As a result, the classical biasing arrangement, popular in discrete-circuit amplifier design, is abandoned in IC amplifiers in favor of biasing with constant-current sources implemented with transistors operating in the active mode. As well, the collector and drain resistors in amplifiers are replaced with constant-current sources that have much higher incremental resistance, thus providing larger gains.
2. Capacitors. Chip-area considerations also make it impossible to fabricate large-valued capacitors such as those employed for signal coupling and bypass in discrete-circuit amplifiers. As a result, IC amplifiers are all direct coupled and utilize clever techniques, which we will study in this chapter and the next.
Small-size capacitors, in the picofarad and fraction-of-a-picofarad range, are easy to fabricate in IC MOS technology. Such capacitors can be combined with MOS amplifiers and MOS switches to realize a wide variety of signal-processing functions, both analog (Chapter 17) and digital (Chapter 15).
3. Power Supplies. To pack a large number of devices on the same IC chip, and thus reduce system cost and increase reliability, the trend has been to reduce the device dimensions. (For a discussion of Moore’s law and device scaling, see Section 14.5.) By 2014, CMOS process technologies capable of producing devices with a 14-nm channel length were in use. To avoid breaking down the thin oxide layers (less than 1 nm) used in these devices, power supplies are limited to 1 V or so. Low power-supply voltages help with another major design challenge; namely, keeping the power dissipated in the chip within acceptable limits. However, the use of such low dc power-supply voltages presents the circuit designer with a host of challenges. For instance, MOS
8.2 IC Biasing—Current Sources, Current Mirrors, and Current-Steering Circuits 511
transistors must be operated with overdrive voltages of only 0.1 V to 0.2 V. In our
study of MOS amplifiers, we will frequently comment on such issues.
4. Device Variety. Unlike the designer of discrete circuits, who is limited to available off-the-shelf transistors, the IC designer has the freedom to specify the device dimensions and to utilize device matching and arrays of devices having dimensions with specified ratios. For instance, one can utilize an array of bipolar transistors whose emitter–base–junction areas have binary-weighted ratios. CMOS technology provides even more flexibility, with the W and L values of MOS transistors selected
to fit a very wide range of design requirements.
5. Bipolar Technology. BJTs are still used in special analog applications, such as
high-quality general-purpose op-amp packages that are intended for assembly on printed-circuit (PC) boards (as opposed to being part of a system-on-a-chip). Bipolar circuits can also be combined with CMOS circuits in innovative and exciting ways in what is known as BiCMOS technology.
6. CMOS Technology. Currently the vast majority of analog integrated circuits are designed using CMOS technology. This practice was initially motivated by the need to be compatible with digital circuits, which have become predominantly CMOS. Now, however, the richness and the versatility that CMOS provides the analog designer is an even stronger reason for its dominance. We hope that the reader will come to appreciate this point in Chapters 8 and 9.
SOLID CIRCUITS WITH “FLYING WIRES”:
As the importance of transistors grew during the 1950s, packaging became a problem. While it was possible to create smaller and smaller active devices, individual transistor packages had to be large enough to be held in the assembly of an electronic system. As one solution to this problem, Texas Instruments (TI) initiated a program of package modular electronics in the creation, on a ceramic substrate, of larger, more functional system elements. Employed to work in this direction, Jack Kilby believed it was necessary to go one step further and design the multiplicity of active and passive elements on a single piece of semiconductor. Thus, in 1958 he created the first “solid circuit,” incorporating many transistors and resistors formed on a single slab of germanium and coupled by “flying wire” interconnections to form system elements such as oscillators and amplifiers. In 1959 TI began to use this technique to manufacture the 507 Binary Flip-Flop. While the approach was successful in producing small space-efficient modules, it was not suited for mass production. In 2000 Kilby received the Nobel Prize in Physics, in recognition of his part in the invention of the integrated circuit.
8.2 IC Biasing—Current Sources, Current Mirrors, and Current-Steering Circuits
Biasing in integrated-circuit design is based on the use of constant-current sources. On an IC chip with a number of amplifier stages, a constant dc current (called a reference current) is generated at one location and is then replicated at various other locations for biasing the various amplifier stages through a process known as current steering. This approach has the advantage that the effort expended on generating a predictable and stable reference current,
512 Chapter 8
Building Blocks of Integrated-Circuit Amplifiers
usually utilizing a precision resistor external to the chip or a special circuit on the chip, need not be repeated for every amplifier stage. Furthermore, the bias currents of the various stages track each other in case of changes in power-supply voltage or in temperature.
In this section we study circuit building blocks and techniques employed in the bias design of IC amplifiers. These current-source circuits are also utilized as amplifier load elements, as will be seen in Sections 8.3 and 8.4.
8.2.1 The Basic MOSFET Current Source
Figure 8.1 shows the circuit of a simple MOS constant-current source. The heart of the circuit is transistor Q1, the drain of which is shorted to its gate,1 thereby forcing it to operate in the
saturation mode with
W
ID1 = 1kn′ (VGS −Vtn)2 (8.1)
2L1
where we have neglected channel-length modulation. The drain current of Q1 is supplied by VDD through resistor R, which in most cases would be outside the IC chip. Since the gate currents are zero,
ID1 = IREF = VDD − VGS (8.2) R
where the current through R is considered to be the reference current of the current source and is denoted IREF . Equations (8.1) and (8.2) can be used to determine the value required for R.
NowconsidertransistorQ2:IthasthesameVGS asQ1;thus,ifweassumethatitisoperating in saturation, its drain current, which is the output current IO of the current source, will be
W
IO =ID2 = 1kn′ (VGS−Vtn)2 (8.3)
2L2
where we have neglected channel-length modulation. Equations (8.1) and (8.3) enable us to
relate the output current IO to the reference current IREF as follows:
IO IREF
= (W/L)2 (W/L)1
(8.4)
IREF
ID1
VDD
R
0 0
0
IO
VO
Q2
Q1
VGS
Figure 8.1 Circuit for a basic MOSFET constant- current source. For proper operation, the output terminal, that is, the drain of Q2, must be connected to a circuit that ensures that Q2 operates in saturation.
1Such a transistor is said to be diode connected.
IREF
8.2 IC Biasing—Current Sources, Current Mirrors, and Current-Steering Circuits 513
IO
Q Q2 VO
1
VGS
Figure 8.2 Basic MOSFET current mirror.
This is a simple and attractive relationship: The special connection of Q1 and Q2 provides an output current IO that is related to the reference current IREF by the aspect ratios of the transistors. In other words, the relationship between IO and IREF is solely determined by the geometries of the transistors. In the special case of identical transistors, IO = IREF , and the circuit simply replicates or mirrors the reference current in the output terminal. This has given the circuit composed of Q1 and Q2 the name current mirror, a name that is used irrespective of the ratio of device dimensions.
Figure 8.2 depicts the current-mirror circuit with the input reference current shown as being supplied by a current source for both simplicity and generality. The current gain or current transfer ratio of the current mirror is given by Eq. (8.4).
Effect of VO on IO In the description above for the operation of the current source of Fig. 8.1, we assumed Q2 to be operating in saturation. This is essential if Q2 is to supply a constant-current output. To ensure that Q2 is saturated, the circuit to which the drain of Q2 is to be connected must establish a drain voltage VO that satisfies the relationship
VO ≥VGS −Vtn (8.5) or, equivalently, in terms of the overdrive voltage VOV of Q1 and Q2,
VO ≥VOV (8.6)
In other words, the current source will operate properly with an output voltage VO as low as VOV , which is a few tenths of a volt.
Although thus far neglected, channel-length modulation can have a significant effect on the operation of the current source. Consider, for simplicity, the case of identical devices Q1 and Q2. The drain current of Q2, IO, will equal the current in Q1, IREF, at the value of VO that causes the two devices to have the same VDS , that is, at VO = VGS . As VO is increased above this value, IO will increase according to the incremental output resistance ro2 of Q2. This is illustrated in Fig. 8.3, which shows IO versus VO . Observe that since Q2 is operating at a constantVGS (determinedbypassingIREF throughthematcheddeviceQ1),thecurveinFig.8.3 is simply the iD−vDS characteristic curve of Q2 for vGS equal to the particular value VGS.
In summary, the current source of Fig. 8.1 and the current mirror of Fig. 8.2 have a finite output resistance Ro,
Ro≡VO =ro2=VA2 (8.7) IO IO
514 Chapter 8
Building Blocks of Integrated-Circuit Amplifiers
IO
I REF
Slope r1o
0VVV GS tn GS
VOV
VO
Figure 8.3 Output characteristic of the current source in Fig. 8.1 and the current mirror of Fig. 8.2 for the case of Q2 matched to Q1.
where IO is given by Eq. (8.3) and VA2 is the Early voltage of Q2 . Also, recall that for a given process technology, VA is proportional to the transistor channel length; thus, to obtain high output-resistance values, current sources are usually designed using transistors with relatively long channels. Finally, note that we can express the current IO as
(W/L) V−V IO= 2IREF 1+O GS
(8.8)
Example 8.1
Given VDD = 3 V and using IREF = 100 μA, design the circuit of Fig. 8.1 to obtain an output current whose nominal value is 100 μA. Find R if Q1 and Q2 are matched and have channel lengths of 1 μm, channel widths of 10 μm, Vt = 0.7 V, and kn′ = 200 μA/V2 . What is the lowest possible value of VO ? Assuming thatforthisprocesstechnology,theEarlyvoltageVA′ =20V/μm,findtheoutputresistanceofthecurrent source. Also, find the change in output current resulting from a +1-V change in VO .
Solution
Thus,
I =I =1k′ W V2 D1 REF 2n L OV
(W/L)1 VA2
1 2 OV
100 = 1 × 200 × 10 V 2 VOV =0.316V
and
8.2 IC Biasing—Current Sources, Current Mirrors, and Current-Steering Circuits 515
VGS =Vt +VOV =0.7+.316≃1V R=VDD−VGS = 3−1 =20k
IREF 0.1 mA VOmin =VOV ≃0.3V
For the transistors used, L = 1 μm. Thus,
VA =20×1=20V
ro2 = 20V =0.2M 100 μA
The output current will be 100 μA at VO = VGS = 1 V. If VO changes by +1 V, the corresponding change in IO will be
IO=VO= 1V =5μA ro2 0.2 M
EXERCISE
D8.1 In the current source of Example8.1, it is required to reduce the change in output current, IO, corresponding to a change in output voltage, VO , of 1 V to 1% of IO . What should the dimensions of Q1 and Q2 be changed to? Assume that Q1 and Q2 are to remain matched.
Ans. L=5μm;W=50μm
8.2.2 MOS Current-Steering Circuits
As mentioned earlier, once a constant current has been generated, it can be replicated to provide dc bias or load currents for the various amplifier stages in an IC. Current mirrors can obviously be used to implement this current-steering function. Figure 8.4 shows a simple current-steering circuit. Here Q1 together with R determine the reference current IREF. Transistors Q1, Q2, and Q3 form a two-output current mirror,
I =I (W/L)2 (8.9) 2 REF (W/L)1
I =I (W/L)3 (8.10) 3 REF (W/L)1
516 Chapter 8
Building Blocks of Integrated-Circuit Amplifiers
VDD
VSG5
+
–
Q4
I4
Q5 I5
IREF R
I2
I3 Q1 Q2 Q3
+
VGS1 –
VSS
Figure 8.4 A current-steering circuit.
To ensure operation in the saturation region, the voltages at the drains of Q2 and Q3 are
constrained as follows: or, equivalently,
VD2,VD3 ≥−VSS +VGS1 −Vtn (8.11) VD2,VD3 ≥−VSS +VOV1 (8.12)
where VOV 1 is the overdrive voltage at which Q1 , Q2 , and Q3 are operating. In other words, the drains of Q2 and Q3 will have to remain higher than −VSS by at least the overdrive voltage, which is usually a few tenths of a volt.
Continuing our discussion of the circuit in Fig. 8.4, we see that current I3 is fed to the input side of a current mirror formed by PMOS transistors Q4 and Q5. This mirror provides
I =I (W/L)5 5 4 (W/L)4
where I4 = I3 . To keep Q5 in saturation, its drain voltage should be VD5 ≤VDD −|VOV5|
(8.13)
(8.14)
where VOV 5 is the overdrive voltage at which Q5 is operating.
The constant current I2 generated in the circuit of Fig.8.4 can be used to bias a
source-follower amplifier such as that implemented by transistor Q6 in Fig. 8.5(a). Similarly, the constant current I5 can be used as the load for a common-source amplifier such as that implemented with transistor Q7 in Fig. 8.5(b). We will discuss the use of current sources as load elements for CS amplifiers in Section 8.3.
Finally, an important point to note is that in the circuit of Fig. 8.4, while Q2 pulls its current I2 from a circuit (not shown in Fig. 8.4), Q5 pushes its current I5 into a circuit (not shown in Fig. 8.4). Thus Q5 is appropriately called a current source, whereas Q2 should more properly be called a current sink. In an IC, both current sources and current sinks are usually needed. The difference between a current source and a current sink is further illustrated in Fig. 8.6, where VCSmin denotes the minimum voltage needed across the current source (or sink) for its proper operation.
8.2
VDD
Q6
I2 Q2
VSS (a)
IC Biasing—Current Sources, Current Mirrors, and Current-Steering Circuits 517 VDD
vi6
Q5 I5
Q7
VSS (b)
vo6
vo7
vi7
Figure 8.5 Application of the constant currents I2 and I5 generated in the current-steering circuit of Fig. 8.4. Constant-current I2 is the bias current for the source follower Q6, and constant-current I5 is the load current for the common-source amplifier Q7.
VDD
VCSmin I
I
VO ≥ VSS VCSmin
VCSmin
(b)
VO ≤ VDDVCSmin
VSS Figure 8.6 (a) A current source; and (b) a current sink.
EXERCISE
(a)
D8.2 ForthecircuitofFig.8.4,letVDD =VSS =1.5V,Vtn =0.6V,Vtp =−0.6V,allchannellengths=1μm, kn′ = 200 μA/V2, kp′ = 80 μA/V2, and λ = 0. For IREF = 10 μA, find the widths of all transistors to obtain I2 = 60 μA, I3 = 20 μA, and I5 = 80 μA. It is further required that the voltage at the drain of Q2 be allowed to go down to within 0.2 V of the negative supply and that the voltage at the drain of Q5 be allowed to go up to within 0.2 V of the positive supply.
Ans. W1 =2.5μm;W2 =15μm;W3 =5μm;W4 =12.5μm;W5 =50μm
518 Chapter 8
Building Blocks of Integrated-Circuit Amplifiers
IREF
IO
VO
Q1 Q2
VBE
8.2.3 BJT Circuits
Figure 8.7 The basic BJT current mirror.
The basic BJT current mirror is shown in Fig. 8.7. It works in a fashion very similar to that of the MOS mirror. However, there are two important differences: First, the nonzero base current of the BJT (or, equivalently, the finite β) causes an error in the current transfer ratio of the bipolar mirror. Second, the current transfer ratio is determined by the relative areas of the emitter–base junctions of Q1 and Q2.
Let us first consider the case of β sufficiently high that we can neglect the base currents. The reference current IREF is passed through the diode-connected transistor Q1 and thus establishes a corresponding voltage VBE, which in turn is applied between base and emitter of Q2. Now, if Q2 is matched to Q1 or, more specifically, if the EBJ area of Q2 is the same as that of Q1, and thus Q2 has the same scale current IS as Q1, then the collector current of Q2 will be equal to that of Q1; that is,
IO = IREF (8.15)
Forthistohappen,however,Q2 mustbeoperatingintheactivemode,whichinturnisachieved as long as the collector voltage VO is 0.3 V or so higher than that of the emitter.
To obtain a current transfer ratio other than unity, say m, we simply arrange that the area of the EBJ of Q2 is m times that of Q1. In this case,
IO = mIREF (8.16) In general, the current transfer ratio is given by
IO = IS2 = Areaof EBJof Q2 (8.17) IREF IS1 Area of EBJ of Q1
Alternatively, if the area ratio m is an integer, one can think of Q2 as equivalent to m transistors, each matched to Q1 and connected in parallel.
Next we consider the effect of finite transistor β on the current transfer ratio. The analysis for the case in which the current transfer ratio is nominally unity—that is, for the case in which Q2 is matched to Q1 —is illustrated in Fig. 8.8. The key point here is that since Q1 and Q2 are matched and have the same VBE , their collector currents will be equal. The rest of the analysis is straightforward. A node equation at the collector of Q1 yields
2 IREF =IC +2IC/β=IC 1+β
8.2
IC Biasing—Current Sources, Current Mirrors, and Current-Steering Circuits 519
IREF IC
2ICb ICb
VO IO = IC
Q Q2
I C 1 b1 I C 1 b1
1
ICb
Figure 8.8 Analysis of the current mirror tak- ing into account the finite β of the BJTs.
Finally, since IO = IC , the current transfer ratio can be found as
IO = IC = 1 (8.18) IREF I 1+ 2 1+ 2
Cββ
Note that as β approaches ∞, IO /IREF approaches the nominal value of unity. For typical values of β, however, the error in the current transfer ratio can be significant. For instance, β = 100 results in a 2% error in the current transfer ratio. Furthermore, the error due to the finite β increases as the nominal current transfer ratio is increased. The reader is encouraged to show that for a mirror with a nominal current transfer ratio m—that is, one in which IS2 = mIS1—the actual current transfer ratio is given by
IO = m (8.19) IREF 1+m+1
β
In common with the MOS current mirror, the BJT mirror has a finite output resistance Ro, Ro ≡ VO = ro2 = VA2 (8.20)
IO IO
where VA2 and ro2 are the Early voltage and the output resistance, respectively, of Q2. Thus, even if we neglect the error due to finite β, the output current IO will be at its nominal value only when Q2 has the same VCE as Q1, namely, at VO = VBE. As VO is increased, IO will correspondingly increase. Taking both the finite β and the finite Ro into account, we can express the output current of a BJT mirror with a nominal current transfer ratio m as
mV−V
IO=IREF 1+ O BE (8.21)
1+m+1 VA2 β
where we note that the error term due to the Early effect is expressed in a form that shows that it reduces to zero for VO = VBE .
520 Chapter 8 Building Blocks of Integrated-Circuit Amplifiers
EXERCISE
8.3 Consider a BJT current mirror with a nominal current transfer ratio of unity. Let the transistors have IS =10−15A,β=100,andVA =100V.ForIREF =1mA,findIO whenVO =5V.Also,findtheoutput resistance.
Ans. 1.02 mA; 100 k
A Simple Current Source In a manner analogous to that in the MOS case, the basic BJT current mirror can be used to implement a simple current source, as shown in Fig. 8.9. Here the reference current is
IREF = VCC−VBE (8.22) R
where VBE is the base–emitter voltage corresponding to the desired value of IREF. The output
current IO is given by
IV−V IO= REF 1+ O BE
1+(2/β) VA The output resistance of this current source is ro of Q2,
Ro = ro2 ≃ VA ≃ VA IO IREF
Figure 8.9 A simple BJT current source.
(8.23)
(8.24)
EXERCISE
D8.4 Assuming the availability of BJTs with scale currents IS = 10−15A, β = 100, and VA = 50 V, design the current-source circuit of Fig. 8.9 to provide an output current IO = 0.5 mA at VO = 2 V. The power supply VCC = 5 V. Give the values of IREF, R, and VOmin. Also, find IO at VO = 5 V.
Ans. 0.497 mA; 8.71 k; 0.3 V; 0.53 mA
8.2 IC Biasing—Current Sources, Current Mirrors, and Current-Steering Circuits 521
Figure 8.10 Generation of a number of constant currents of various magnitudes.
Current Steering To generate bias currents for different amplifier stages in an IC, the current-steering approach described for MOS circuits can be applied in the bipolar case. As an example, consider the circuit shown in Fig. 8.10. The dc reference current IREF is generated in the branch that consists of the diode-connected transistor Q1, resistor R, and the diode-connected transistor Q2:
IREF = VCC + VEE − VEB1 − VBE2 (8.25) R
Now, for simplicity, assume that all the transistors have high β and thus that the base currents are negligibly small. We will also neglect the Early effect. The diode-connected transistor Q1 forms a current mirror with Q3; thus Q3 will supply a constant current I1 equal to IREF. Transistor Q3 can supply this current to any load as long as the voltage that develops at the collector does not exceed (VCC − 0.3 V); otherwise Q3 would enter the saturation region.
To generate a dc current twice the value of IREF , two transistors, Q5 and Q6 , each of which is matched to Q1, are connected in parallel, and the combination forms a mirror with Q1. Thus I3 = 2IREF . Note that the parallel combination of Q5 and Q6 is equivalent to a transistor with an EBJ area double that of Q1, which is precisely what is done when this circuit is fabricated in IC form.
TransistorQ4 formsamirrorwithQ2;thusQ4 providesaconstantcurrentI2 equaltoIREF. Note that while Q3 sources its current to parts of the circuit whose voltage should not exceed (VCC − 0.3 V), Q4 sinks its current from parts of the circuit whose voltage should not decrease below (−VEE +0.3V). Finally, to generate a current three times IREF, three transistors, Q7, Q8, and Q9, each of which is matched to Q2, are connected in parallel, and the combination is placed in a mirror configuration with Q2. Again, in an IC implementation, Q7, Q8, and Q9 would be replaced with a transistor having a junction area three times that of Q2.
522 Chapter 8 Building Blocks of Integrated-Circuit Amplifiers
EXERCISE
8.5 Figure E8.5 shows an N-output current mirror. Assuming that all transistors are matched and have finite β and ignoring the effect of finite output resistances, show that
I1 =I2 =···=IN = IREF 1+(N +1)/β
For β = 100, find the maximum number of outputs for an error not exceeding 10%.
IREF I1 I2 IN
QREF
Figure E8.5
Ans. 9
Q1 Q2
VEE
QN
A Bipolar Mirror with Base-Current Compensation
Figure 8.11 shows a bipolar current mirror with a current transfer ratio that is much less dependent on β than that of the simple current mirror. The reduced dependence on β is achieved by including transistor Q3, the emitter of which supplies the base currents of Q1 and Q2. The sum of the base currents is then divided by (β3 + 1), resulting in a much smaller error current that has to be supplied by IREF. Detailed analysis is shown on the circuit diagram; it is based on the assumption that Q1 and Q2 are matched and thus have equal collector currents, IC . A node equation at the node
labeled x gives
Since
2 IREF=IC 1+β(β+1)
IO =IC
8.2 IC Biasing—Current Sources, Current Mirrors, and Current-Steering Circuits 523
IREF
x Q3 2IC
2IC b
I =I O C
Q2
IC
Q1
b(b1)
ICb ICb
Figure 8.11 A current mirror with base-current compensation.
the current transfer ratio of the mirror will be
IO= 1
IREF 1+2/(β2 +β)
≃ 1 (8.26) 1+2/β2
which means that the error due to finite β has been reduced from 2/β in the simple mirror to 2/β2, a tremendous improvement. Unfortunately, however, the output resistance remains approximately equal to that of the simple mirror, namely ro. Finally, note that if a reference current IREF is not available, we simply connect node x to the power supply, VCC , through a resistance R. The result is a reference current given by
IREF = VCC −VBE1 −VBE3 (8.27) R
8.2.4 Small-Signal Operation of Current Mirrors
In addition to their use in biasing, current mirrors are sometimes employed as current amplifiers. It is therefore useful to derive the small-signal parameters of the current mirror, that is, Rin, Ais, and Ro.
Figure 8.12(a) shows a MOS current mirror biased with a dc input current ID1 and fed with a small-signal input current ii . Note that VGS and ID2 are the resulting dc quantities, while vgs and io are signal quantities. Although we are not showing the circuit to which the output terminalisconnected,weareassumingthatthevoltageatthedrainofQ2 exceedstheminimum required to keep Q2 in saturation.
Replacing Q1 and Q2 with their small-signal models results in the circuit in Fig. 8.12(b). Observe that the controlled current source gm1 vgs appears across its control voltage vgs and thus can be replaced by a resistance, 1/gm1, as shown in Fig. 8.12(c). For the latter circuit we can obtain
(8.28) (8.29)
1 1
Rin=ro1g ≃g m1
m1
Ro=ro2
Ais ≡io =gm2vgs ≃gm2ii/gm1 ii vd2=0 ii ii
524 Chapter 8 Building Blocks of Integrated-Circuit Amplifiers
ID1 ii
ID2 io
Q1
Q2
VGS vgs
(a)
D1,G1,2
D io 2
gm2vgs ro2
D2
gm2vgs ro2
ii ro1
gm1vgs vgs
(b)
vgs
D1, G1,2
io = gm2vgs
ii
ro1
Thus,
1 gm1
output short-circuit
Rin =ro1g1 g1 m1 m1
Ro =ro2 Figure 8.12 Obtaining the small-signal parameters of the MOS current mirror as a current amplifier.
(c)
Ais = gm2 gm1
(8.30) Substituting for gm1,2 = μn Cox (W/L)1,2 VOV , where VOV is the overdrive voltage at which Q1
and Q2 are operating, yields for the short-circuit current gain
Ais = (W/L)2 (8.31)
(W/L)1
which is equal to the dc or large-signal current transfer function—a clear indication of the excellent linearity of the current mirror.
We conclude that the current mirror is an excellent current amplifier: It has a relatively low input resistance (1/gm1), a relatively high output resistance (ro2), and a gain determined
8.3 The Basic Gain Cell 525 by the aspect ratios of the MOSFETs. Finally, a similar development can be used to obtain
the small-signal parameters of the bipolar mirror.
EXERCISE
D8.6 The MOSFETs in the current mirror of Fig. 8.12(a) have equal channel lengths, μn Cox = 400 μA/V2 , andVA′ =20V/μm.Iftheinputbiascurrentis100μA,findW1,W2,L1,andL2 toobtainashort-circuit current gain of 5, an input resistance of 1 k, and an output resistance of 40 k.
Ans. 12.5 μm; 62.5 μm; 1 μm; and 1 μm
THE INTEGRATED CIRCUIT:
In 1959, at the same time that Kilby and TI applied for a patent on “miniaturized electronic circuits,” Robert Noyce (a cofounder of Fairchild Semiconductor and later of Intel) filed a patent on the “monolithic silicon-based integrated circuit.” He later acknowledged the critical importance of Kurt Lehovac’s idea of using reverse-biased junctions to isolate multiple devices on a single die. Lehovac, of Sprague Electric Company, also filed a patent in 1959. Regrettably, Noyce, who died in 1990, did not live to share in the Nobel Prize with Kilby.
8.3 The Basic Gain Cell
8.3.1 The CS and CE Amplifiers with Current-Source Loads
The basic gain cell in an IC amplifier is a common-source (CS) or common-emitter (CE) transistor loaded with a constant-current source, as shown in Fig. 8.13(a) and (b). These circuits are similar to the CS and CE amplifiers studied in Section 7.3, except that here we have replaced the resistances RD and RC with constant-current sources. This is done for two reasons: First, as mentioned in Section 8.1, it is difficult in IC technology to implement resistances with reasonably precise values; rather, it is much easier to use current sources, which are implemented using transistors. Second, by using a constant-current source we are in effect operating the CS and CE amplifiers with a very high (ideally infinite) load resistance; thus we can obtain a much higher gain than if a finite RD or RC is used. This is particularly the case because, even if passive resistances were available, they would have very small values because the dc power supplies are now limited to only 1 V to 2 V. These voltages, however, do allow the use of current sources that have large output resistances. The circuits in Fig. 8.13(a) and (b) are said to be current-source loaded or active loaded.
Before we consider the small-signal analysis of the active-loaded CS and CE amplifiers, a word on their dc bias is in order. Obviously, in each circuit Q1 is biased at ID = I and IC = I . But what determines the dc voltages at the drain (collector) and at the gate (base)? Usually, these gain cells will be part of larger circuits in which negative feedback is utilized to fix the values ofVDS andVGS (VCE andVBE).InthenextchapterwewillbegintoseecompleteICamplifiers including biasing. For the time being, however, we shall assume that the MOS transistor in
526 Chapter 8
Building Blocks of Integrated-Circuit Amplifiers
VDD VCC II
Q1
vo o
vi vi
(a) (b)
vi vo vi vo
(c) (d)
Figure 8.13 The basic gain cells of IC amplifiers: (a) current-source- or active-loaded common-source amplifier; (b) current-source- or active-loaded common-emitter amplifier; (c) small-signal equivalent circuit of (a); and (d) small-signal equivalent circuit of (b).
Fig. 8.13(a) is biased to operate in the saturation region and that the BJT in Fig. 8.13(b) is biased to operate in the active region. We will often refer to both the MOSFET and the BJT as operating in the “active region.”
Small-signal analysis of the current-source-loaded CS and CE amplifiers can be performed by utilizing their equivalent-circuit models, shown respectively in Fig. 8.13(c) and (d). Observe that since the current-source load is assumed to be ideal, it is represented in the models by an infinite resistance. Practical current sources have finite output resistance, as we have seen in the previous section. For the time being, however, note that the CS and CE amplifiers of Fig. 8.13 are in effect operating in an open-circuit fashion. The only resistance between their output node and ground is the output resistance of the transistor itself, ro. Thus the voltage gain obtained in these circuits is the maximum possible for a CS or a CE amplifier.
Q1 v
vgs
rv
gvr mo
gmvgs ro
From Fig. 8.13(c) we obtain for the active-loaded CS amplifier: Rin =∞
Avo =−gmro Ro =ro
(8.32) (8.33) (8.34)
Similarly, from Fig. 8.13(d) we obtain for the active-loaded CE amplifier:
Rin = rπ
Avo =−gmro
Ro =ro
(8.35) (8.36) (8.37)
8.3 The Basic Gain Cell 527
Thus both circuits realize a voltage gain of magnitude gmro. Since this is the maximum gain obtainable in a CS or CE amplifier, we refer to it as the intrinsic gain and give it the symbol A0. Furthermore, it is useful to examine the nature of A0 in a little more detail.
8.3.2 The Intrinsic Gain
For the BJT, we can derive a formula for the intrinsic gain A0 = gm ro by using the following formulas for gm and ro:
The result is
gm = IC VT
ro = VA IC
A0=gmro=VA VT
(8.38) (8.39)
(8.40)
Thus A0 is simply the ratio of the Early voltage VA, which is a technology-determined parameter, and the thermal voltage VT , which is a physical parameter (approximately 0.025 V at room temperature). The value of VA ranges from 5 V to 35 V for modern IC fabrication processes to 100 V to 130 V for the older, so-called high-voltage processes (see Appendix G). As a result, the value of A0 will be in the range of 200 V/V to 5000 V/V, with the lower values characteristic of modern small-feature-size devices. It is important to note that for a given bipolar-transistor fabrication process, A0 is independent of the transistor junction area and of its bias current. This is not the case for the MOSFET, as we shall now see.
Recall from our study of the MOSFET gm in Section 7.2 that there are three possible expressions for gm. Two of these are particularly useful for our purposes here:
gm= ID VOV/2
(8.41) (8.42)
gm =
2μn Cox (W/L) 1D
For the MOSFET ro we have
where VA is the Early voltage and VA′ is the technology-dependent component of the Early volt-
ro = VA = VA′ L ID ID
(8.43) age.Utilizingeachofthegm expressionstogetherwiththeexpressionforro,weobtainforA0,
A0= VA (8.44) VOV/2
which can be expressed in the alternate forms
A0 = 2VA′ L (8.45) VOV
528 Chapter 8
Building Blocks of Integrated-Circuit Amplifiers
and
VA′ 2(μnCox)(WL)
A0 =
The expression in Eq. (8.44) is the one most directly comparable to that of the BJT (Eq. 8.40).
Here, however, we note the following:
1. The quantity in the denominator is VOV /2, which is a design parameter. Although the valueofVOV thatdesignersuseformodernsubmicrontechnologieshasbeensteadily decreasing, it is still about 0.15 V to 0.3 V. Thus VOV /2 is 0.075 V to 0.15 V, which is 3 to 6 times higher than VT . Furthermore, there are reasons for selecting higher values forVOV (tobediscussedinlaterchapters).
2. The numerator quantity is both process dependent (through VA′ ) and device dependent (through L), and its value has been steadily decreasing with the scaling down of the technology (see Appendix K).
3. From Eq. (8.45) we see that for a given technology (i.e., a given value of VA′ ) the intrinsic gain A0 can be increased by using a longer MOSFET and operating it at a lower VOV . As usual, however, there are design trade-offs. For instance, we will see inChapter10thatincreasingLandloweringVOV result,independently,indecreasing the amplifier bandwidth.
As a result, the intrinsic gain realized in a MOSFET fabricated in a modern short-channel technology is only 10 V/V to 40 V/V, an order of magnitude lower than that for a BJT.
a typical plot for A0 versus the bias current ID . The plot confirms that the gain increases as the bias current is lowered. The gain, however, levels off at very low currents. This is because the MOSFET enters the subthreshold region of operation (Section 5.1.9), where it becomes very much like a BJT with an exponential current–voltage characteristic. The intrinsic gain then becomes constant, just like that of a BJT. Note, however, that although higher gain is
The alternative expression for the MOSFET A0 given in Eq.(8.46) reveals a very interesting fact: For a given process technology (V ′ and μ C ) and a given device (W and L),
A nox
the intrinsic gain is inversely proportional to ID . This is illustrated in Fig. 8.14, which shows
ID
(8.46)
A0 (log scale)
1000 100 10 1
′ 2′D
aplotofA0 =VA 2μnCoxWL/ID forthecase:μnCox =20μA/V ,VA =20V/μm,L=2μm,andW=20μm.
Subthreshold region
Strong inversion region
Slope = 12
106 105 104 103 102
Figure8.14 TheintrinsicgainoftheMOSFETversusbiascurrentI .Outsidethesubthresholdregion,thisis
ID (A) (log scale)
8.3 The Basic Gain Cell 529 obtained at lower values of ID , the price paid is a lower gm (Eq. 8.42) and less ability to drive
capacitive loads, and thus a decrease in bandwidth. This point will be studied in Chapter 10.
Example 8.2
We wish to compare the values of gm, Rin, Ro, and A0 for a CS amplifier that is designed using an NMOS transistor with L = 0.4 μm and W = 4 μm and fabricated in a 0.25-μm technology specified to have μn Cox = 267 μA/V2 and VA′ = 10 V/μm, with those for a CE amplifier designed using a BJT fabricated in a process with β = 100 and VA = 10 V. Assume that both devices are operating at a drain (collector) current of 100 μA.
Solution
For simplicity, we shall neglect the Early effect in the MOSFET in determining VOV ; thus,
resulting in
W ID = 1 μnCox
V2OV 1 42
2L 100=2×267× 0.4 VOV
For the CE amplifier we have
VOV =0.27V
gm = 2ID = 2×0.1 =0.74mA/V
VOV 0.27 Rin =∞
ro = VA′ L = 10 × 0.4 = 40 k ID 0.1
Ro =ro =40k
A0 =gmro =0.74×40=29.6V/V
gm = IC = 0.1mA =4mA/V VT 0.025 V
Rin = rπ = β = 100 = 25 k gm 4
ro=VA =10=100k IC 0.1
Ro =ro =100k
A0 =gmro =4×100=400V/V
530 Chapter 8 Building Blocks of Integrated-Circuit Amplifiers
EXERCISE
8.7 A CS amplifier utilizes an NMOS transistor with L = 0.36 μm and W/L = 10; it was fabricated in a 0.18-μm CMOS process for which μn Cox = 387 μA/V2 and VA′ = 5 V/μm. Find the values of gm and A0 obtained at ID = 10 μA, 100 μA, and 1 mA.
Ans. 0.28 mA/V, 50 V/V; 0.88 mA/V, 15.8 V/V; 2.78 mA/V, 5 V/V
8.3.3 Effect of the Output Resistance of the Current-Source Load
The current-source load of the CS amplifier in Fig. 8.13(a) can be implemented using a PMOS transistor biased in the saturation region to provide the required current I, as shown in Fig. 8.15(a). We can use the large-signal MOSFET model (Section 5.2, Fig. 5.18) to model
VDD
VDD
VG Q2
Q1 vo
Q1 v o
vi
vi vgs1 gm1vgs1 ro1
vi
(a) (b)
ro2 vo
(c)
Figure 8.15 (a) The CS amplifier with the current-source load implemented with a p-channel MOSFET Q2; (b) the circuit with Q2 replaced with its large-signal model; and (c) small-signal equivalent circuit of the amplifier.
I ro2
Q2 as shown in Fig. 8.15(b), where
8.3 The Basic Gain Cell 531
and
I=1μCWV −V−V2 2 p ox L DD G tp
2
ro2 = |VA2| I
(8.47)
(8.48)
Thus the current-source load no longer has an infinite resistance; rather, it has a finite output resistance ro2 . This resistance will in effect appear in parallel with ro1 , as shown in the amplifier equivalent-circuit model in Fig. 8.15(c), from which we obtain
A ≡vo =−g (r ∥r ) (8.49) vvi m1o1o2
Thus, not surprisingly, the finite output resistance of the current-source load reduces the magnitude of the voltage gain from (gm1ro1) to gm1(ro1 ∥ro2). This reduction can be substantial. For instance, if Q2 has an Early voltage equal to that of Q1, ro2 = ro1 and the gain is reduced by half,
Av =−1gmro (8.50) 2
Finally, we note that a similar development can be used for the bipolar case.
Example 8.3
A practical circuit implementation of the common-source amplifier is shown in Fig. 8.16(a). Here the current-source transistor Q2 is the output transistor of a current mirror formed by Q2 and Q3 and fed with a reference current IREF . The NMOS version of this current source was studied in Section 8.1. Assume that Q2 and Q3 are matched. To be able to clearly see the region of vI over which the circuit operates as an almost-linearamplifier,determinethevoltage-transfercharacteristic(VTC),thatis,vO versusvI.
vo
VOV2
(b)
Figure 8.16 Practical implementation of the common-source amplifier: (a) circuit; (b) i–v characteristic of the active-load Q2 ; (c) graphical construction to determine the transfer characteristic; (d) transfer characteristic.
532
Chapter 8 Building Blocks of Integrated-Circuit Amplifiers
Example 8.3 continued
VOA VDD VOV2
Figure 8.16 continued Solution
(c)
VOA
VDD VOV2
VOB Vtn
First we concern ourselves with the current mirror, with the objective of determining the i–v characteristic ofthecurrentsourceQ2.Towardthatend,wenotethatthecurrentIREF flowsthroughthediode-connected transistor Q3 and thus determines VSG of Q3, which is in turn applied between the source and the gate of Q2. Thus, the i–v characteristic of the current source Q2 will be the iD–vSD characteristic curve of Q2 obtained for vSG = VSG. This is shown in Fig. 8.16(b), where we note that i will be equal to IREF at one point only, namely, at vSD2 = VSG, this being the only point at which the two matched transistors Q2 and Q3 have identical operating conditions. We also observe the effect of channel-length modulation in Q2 (the Early effect), which is modeled by the finite output resistance ro2. Finally, note that Q2 operates as
a current source when v is equal to or greater than V = V − V . This in turn is obtained when OV2 SG tp
v O ≤ VDD − VOV 2 . This is the maximum permitted value of the output voltage v O .
Now, with the i–v characteristic of the current-source load Q2 in hand, we can proceed to determine vO versus vI . Figure 8.16(c) shows a graphical construction for doing this. It is based on the graphical analysis method employed in Section 7.1.6 except that here the load line is not a straight line but is the i–v characteristic curve of Q2 shifted along the vO axis by VDD volts and “flipped around.” The reason for
this is that
vO =VDD −v
The term VDD necessitates the shift, and the minus sign of v gives rise to the “flipping around” of the load curve.
The graphical construction of Fig. 8.16(c) can be used to determine vO for every value of vI , point by point:ThevalueofvI determinestheparticularcharacteristiccurveofQ1 onwhichtheoperatingpointlies. The operating point will be at the intersection of this particular graph and the load curve. The horizontal coordinate of the operating point then gives the value of vO.
Proceeding in the manner just explained, we obtain the VTC shown in Fig. 8.16(d). As indicated, it has four distinct segments, labeled I, II, III, and IV. Each segment is obtained for one of the four combinations of the modes of operation of Q1 and Q2, which are also indicated in the diagram. Note that we have labeled two important break points on the transfer characteristic (A and B) in correspondence with the intersection points (A and B) in Fig. 8.16(c). We urge the reader to carefully study the transfer characteristic and its various details.
Not surprisingly, segment III is the one of interest for amplifier operation. Observe that in region
III the transfer curve is almost linear and is very steep, indicating large voltage gain. In region III both
the amplifying transistor Q and the load transistor Q are operating in saturation. The end points of 1 2
region III are A and B: At A, defined by vO = VDD − VOV2 , Q2 enters the triode region, and at B, defined by vO = vI − Vtn, Q1 enters the triode region. When the amplifier is biased at a point in region III, the small-signal voltage gain can be determined as we have done in Fig. 8.15(c). The question remains as to how we are going to guarantee that the dc component of vI will have such a value that will result in operation in region III. That is why overall negative feedback is needed, as will be demonstrated later.
Before leaving this example it is useful to reiterate that the upper limit of the amplifier region (i.e., point A)isdefinedbyV =V −V andthelowerlimit(i.e.,pointB)isdefinedbyV =V ,whereV
OA DD OV2 OB OV1 OV1 can be approximately determined by assuming that ID1 ≃ IREF . A more precise value for VOB can be obtained
by taking into account the Early effect in both Q1 and Q2, as will be demonstrated in the next example.
Example 8.4
Consider the CMOS common-source amplifier in Fig. 8.16(a) for the case V = 3 V, V = V = 0.6 V, DD tn tp
μ C = 200μA/V2, and μ C = 65μA/V2. For all transistors, L = 0.4μm and W = 4μm. Also, n ox p ox
VAn = 20 V, VAp = 10 V, and IREF = 100 μA. Find the small-signal voltage gain. Also, find the coordinates of the extremities of the amplifier region of the transfer characteristic— that is, points A and B.
8.3 TheBasicGainCell 533
534
Chapter 8 Building Blocks of Integrated-Circuit Amplifiers
Example 8.4 continued Solution
gm1= 2kn′ W IREF
L1
= 2×200× 4 ×100=0.63mA/V 0.4
Thus,
ID2 0.1 mA
Av =−gm1 ro1∥ro2 =−0.63(mA/V)×(200∥100)(k)=−42V/V
ro1=VAn = 20V =200k ID1 0.1 mA
V 10V
ro2= Ap = =100k
Approximate values for the extremities of the amplifier region of the transfer characteristic [region
III in Fig. 8.16(d)] can be determined as follows: Neglecting the Early effect, all three transistors are
carrying equal currents I , and thus we can determine the overdrive voltages at which they are operating. REF
Transistors Q2 and Q3 will have equal overdrive voltages, VOV 3 , determined from I =I ≃1μCWV 2
D3 REF 2 p ox L
Substituting IREF = 100 μA, μpCox = 65 μA/V2, (W/L)3 = 4/0.4 = 10 results in
Thus,
Next we determine V
OA DD
OV3
OV3
V =V −V =2.45V
from
SubstitutingIREF =100μA,μnCox =200μA/V2,(W/L)1 =4/0.4=10resultsin
OV1
V =0.55V OV3
VOV1 =0.32V VOB =VOV1 =0.32V.
I ≃I ≃1μC
D1 REF 2 n ox L
V2 OV1
W
3
Thus,
More precise values for VOA and VOB can be determined by taking the Early effect in all transistors into account as follows.
1
First, we determine VSG of Q2 and Q3 corresponding to ID3 = IREF = 100 μA using
8.3
The Basic Gain Cell 535
Thus,
I =1k′ W V −V2 1+VSD D32pLSGtp V
3 Ap
100=1×65 4 V 2 1+0.6+VOV3
(8.51) whereV isthemagnitudeoftheoverdrivevoltageatwhichQandQareoperating,andwehave
2 0.4 OV3 10
OV3 32
used the fact that, for Q3 , VSD = VSG . Equation (8.51) can be manipulated to the form 0.29 = V 2 1 + 0.09V
OV3
which by a trial-and-error process yields
V = 0.526 V
OV3
OV3
Thus,
and
Noting that in region III, Q1 and Q2 are in saturation and obviously conduct equal currents, we can write
(8.52)
VSG =0.6+0.526=1.126V
VOA = VDD−VOV3 = 2.47 V
To find the corresponding value of v I , VIA , we derive an expression for v O versus v I in region III.
iD1 = iD2
1′W 2 vO 1′W 2 VDD−vO 2kn L vI−Vtn 1+V =2kp L VSG−Vtp 1+ V
1 An 2 Ap Substituting numerical values, we obtain
8.55vI − 0.62 = 1 − 0.08vO 1 + 0.05vO
This is the equation of segment III of the transfer characteristic. Although it includes v2I , the reader should not be alarmed: Because region III is very narrow, vI changes very little, and the characteristic is nearly linear. Substituting vO = 2.47 V gives the corresponding value of vI ; that is, VIA = 0.89 V. To determine the coordinates of B, we note that they are related by VOB = VIB − Vt n . Substituting in Eq. (8.52) and solving by trial and error gives VIB = 0.935 V and VOB = 0.335 V. The width of the amplifier region is therefore
vI =VIB −VIA =0.045V vO =VOB −VOA =−2.135V
and the corresponding output range is
536
Chapter 8 Building Blocks of Integrated-Circuit Amplifiers
Example 8.4 continued
Thus, the “large-signal” voltage gain is
vO =−2.135 =−47.4V/V v I 0.045
which is reasonably close to the small-signal value of –42, indicating that segment III of the transfer characteristic is quite linear.
EXERCISES
8.8 ACMOScommon-sourceamplifiersuchasthatinFig.8.16(a),fabricatedina0.18-μmtechnology,
has W/L = 7.2 μm/0.36 μm for all transistors, kn′ = 387 μA/V2 , kp′ = 86 μA/V2 , IREF = 100 μA,
V′ =5V/μm,and|V′ |=6V/μm.Findg ,r ,r ,andthevoltagegain. An Ap m1 o1 o2
Ans. 1.24 mA/V; 18 k; 21.6 k; –12.2 V/V
8.9 Consider the active-loaded CE amplifier when the constant-current source I is implemented with a
pnp transistor. Let I = 0.1 mA, V = 50 V (for both the npn and the pnp transistors), and β = 100. A
Find Rin, ro (for each transistor), gm, A0, and the amplifier voltage gain. Ans. 25 k; 0.5 M; 4 mA/V; 2000 V/V; –1000 V/V
8.3.4 Increasing the Gain of the Basic Cell
We conclude this section by considering a question: How can we increase the voltage gain obtained from the basic gain cell? The answer lies in finding a way to raise the level of the output resistance of both the amplifying transistor and the load transistor. That is, we seek a circuit that passes the current gmvi provided by the amplifying transistor right through, but increases the resistance from ro to a much larger value. This requirement is illustrated in Fig. 8.17. Figure 8.17(a) shows the CS amplifying transistor Q1 together with its output equivalent circuit. Note that for the time being we are not showing the load device. In Fig. 8.17(b) we have inserted a shaded box between the drain of Q1 and a new output terminal labeled d2. Here again we are not showing the load to which d2 will be connected. Our “black box” takes in the output current of Q1 and passes it to the output; thus at its output we have the equivalent circuit shown, consisting of the same controlled source gm1vi but with the output resistance increased by a factor K.
Now, what does the black box really do? Since it passes the current but raises the resistance level, it is a current buffer. It is the dual of the voltage buffer (the source and emitter followers), which passes the voltage but lowers the resistance level.
Now searching our repertoire of transistor amplifier configurations studied in Section 7.3, the only candidate for implementing this current-buffering action is the common-gate (or common-base in bipolar) amplifier. Indeed, recall that the CG and CB circuits have a unity current gain. What we have not yet investigated, however, is their resistance transformation property. We shall do this in the next section.
8.4
The Common-Gate and Common-Base Amplifiers 537
d1
To Load ro1
Q1
d2
d1
d1
gm1vi
ro1
vi
Out
In
To Load Kro1
(a)
d2
Kro1
gm1vi
vi
ro1 Q1
Figure 8.17 To increase the voltage gain realized in the basic gain cell shown in (a), a functional block, shown as a black box in (b), is connected between d1 and the load. This new block is required to pass the current gm1vi right through but raise the resistance level by a factor K. The functional block is a current buffer and can be realized with a common-gate transistor, as demonstrated in the next section.
8.4 The Common-Gate and Common-Base Amplifiers
In this section we study the IC versions of the CG and CB amplifier configurations. This study differs in a significant way from that of the discrete-circuit versions (Section 7.3.5) because here we have to take into account the output resistance of the transistor, ro. In the following, we show that both the CG and CB configurations provide excellent implementations of the current buffer discussed in the previous section.
8.4.1 The CG Circuit
Figure 8.18(a) shows a CG amplifier with the biasing arrangement shown only partially. The amplifier is fed with a signal source vsig having a resistance Rs, and it has a load resistance RL . The latter is usually implemented using a PMOS current source, as discussed earlier.
To characterize the signal performance of the CG amplifier, we show in Fig. 8.18(b) the circuit with the dc voltages eliminated. Observe that because the gate current is zero, the input
(b)
538 Chapter 8
Building Blocks of Integrated-Circuit Amplifiers
VDD
i
RL
VG Q Q
vo RL
Rout
Rs
0
i Rs vsig
vsig
Rin
Figure 8.18 (a) A CG amplifier with the bias arrangement only partially shown. (b) The circuit with the dc
sources eliminated.
current i passes through to the drain and on to the load—the first requirement of a current buffer.
Input Resistance The input resistance Rin can be found using the circuit of Fig. 8.19. Here we have employed the T model of the MOSFET and applied a test voltage vx to the input.
The input resistance is given by
Rin ≡ vx ix
(a)
(b)
D ix gmvgs
ix
vx
0
vgs
Rin ≡ vx ix
G ro RL gmvgs
1
gm
S
ix gmvgs
Figure 8.19 Determining resistance Rin of the CG amplifier.
input
the
The analysis proceeds as follows.
A node equation at the input yields the current in ro as (ix + gm vgs ). A node equation at the
output shows that the current through RL is ix . Next, a loop equation for the loop comprising vx, ro, and RL gives
vx =(ix +gmvgs)ro +ixRL
Since the voltage at the source node vx is equal to −vgs, we can replace vgs by −vx and
rearrange terms to obtain Rin ≡ vx /ix ,
Forgmro ≫1,
Rin = ro +RL 1+gmro
Rin ≃ 1 + RL gm gmro
(8.53)
(8.54)
8.4 The Common-Gate and Common-Base Amplifiers 539
This is a very interesting result. First, it shows that if ro is infinite, as was the case in our analysis of the discrete CG amplifier in Section 7.3.5, then Rin reduces to 1/gm, verifying the result we found there. If ro cannot be neglected, as is always the case in IC amplifiers, we see that the input resistance depends on RL in an interesting fashion: The load resistance RL is transformed to the input by dividing it by the intrinsic gain A0 = gm ro . Thus, even as RL is increased, this impedance transformation property ensures that Rin remains relatively low, an important characteristic of a current buffer.
Output Resistance To obtain the output resistance Rout we utilize the circuit shown in Fig. 8.20. Here we have short circuited vsig but left the source resistance Rs , and applied a test voltage vx to the output. The output resistance is given by
D
Rout = vx ix
ix
0
ixgmvgs G ro
1
gm
gmvgs
vx
gmvgs
vgs
S
i
Rout ≡ vx x ix
Rs
Figure 8.20 Determining the output resistance Rout of the CG amplifier.
540 Chapter 8
Building Blocks of Integrated-Circuit Amplifiers
The analysis proceeds as follows.
A node equation at the drain gives the current through ro as (ix − gm vgs ). A node equation
at the source gives the current in Rs as ix . Next, a loop equation for the loop comprising vx , ro, and Rs gives
vx =(ix −gmvgs)ro +ixRs (8.55) Finally,weobservethatthevoltageatthesourceterminalis−vgs andcanalsobeexpressed
as ixRs, thus
Substituting this value for vgs into Eq. (8.55) and rearranging terms to obtain Rout ≡ vx /ix
yields
which can be written in the alternate form
vgs =−ixRs
Forgmro ≫1,
and if we also have gmRs ≫ then
Rout =ro +Rs +gmroRs Rout =ro +(1+gmro)Rs
Rout ≃ro +(gmro)Rs Rout ≃(gmro)Rs
(8.56)
(8.57)
(8.58)
(8.59)
Equation (8.58) indicates that the output resistance of the CG amplifier includes, in addition to the transistor’s ro , a component related to the resistance in the source load Rs . The significant point is that the CG amplifier transforms the source resistance Rs to the output by multiplying it by the intrinsic gain A0 = gm ro . This impedance transformation is the inverse to that observed from output to input. Now, if Rs is large then the output resistance of the CG circuit can be very large; this also is an important characteristic of a current buffer.
To summarize: the CG circuit has a unity current gain; a low input resistance, obtained by dividing RL by gmro; and a high output resistance, obtained by multiplying Rs by gmro. Thus it makes for an excellent current buffer and can be used to implement the shaded functional box in Fig. 8.17. As a useful summary, Fig. 8.21 illustrates the impedance transformation properties of the common-gate amplifier.
RL
Rs
Rout =roRsgmroRs ro (gm ro)Rs
r o R L Rin= 1gmro
Figure 8.21 The impedance transformation
properties of the common-gate amplifier.
Depending on the values of Rs and RL, we
cansometimeswriteR ≃R /(g r )andR ≃ inLmo o
(gm ro )Rs . However, such approximations are not always justified.
1 RL
gm gm ro
can be neglected, resulting in
8.4 The Common-Gate and Common-Base Amplifiers 541
EXERCISES
8.10 For the CG amplifier in Fig. 8.18, show that the voltage gain is given by vo = RL
vsig Rs +Rin
8.11 For a CG amplifier for which gm ro ≫ 1, find Rin for the following cases: RL = 0; ro ; (gm ro )ro ; ∞.
Ans. 1; 2;ro;∞ gm gm
8.12 For a CG amplifier for which gm ro ≫ 1, find Rout for the following cases: Rs = 0; ro ; (gm ro )ro ; ∞. Ans. ro; (gmro)ro; (gmro)2 ro; ∞
8.4.2 Output Resistance of a CS Amplifier with a Source Resistance
In Section 7.3.4 we discussed some of the benefits that are obtained when a resistance Rs is included in the source lead of a CS amplifier, as in Fig. 8.22. Such a resistance is referred to as a source-degeneration resistance because of its action in reducing the effective transconductance of the CS stage to gm/(1 + gmRs), that is, by a factor (1 + gmRs). This also is the factor by which a number of performance parameters are increased, such as linearity and bandwidth (as will be seen in Chapter 10). At this juncture we simply wish to point out that the expression we derived above for the output resistance of the CG amplifier applies directly to the case of a source-degenerated CS amplifier. This is because when we determine Ro , we ground the input terminal, making transistor Q appear as a CG transistor. Thus Ro is given by Eq. (8.56), namely,
Ro =ro +Rs +gmroRs (8.60) Since gm ro ≫ 1, the second term on the right-hand side will be much lower than the third and
Ro ≃(1+gmRs)ro
(8.61)
Ro
Q
vi Rs
Figure8.22 TheoutputresistanceexpressionoftheCGamplifiercanbe used to find the output resistance of a source-degenerated common-source amplifier. Here, a useful interpretation of the result is that Rs increases the output resistance by the factor (1 + gm Rs ).
Ro = Rs ro gm ro Rs
R (1 g R ) r o m s o
542 Chapter 8 Building Blocks of Integrated-Circuit Amplifiers
Thus source degeneration increases the output resistance of the CS amplifier from ro to (1+gmRs)ro,againbythesamefactor(1+gmRs).InChapter11,wewillfindthatRs introduces negative (degenerative) feedback of an amount (1 + gm Rs ).
EXERCISE
8.13 Given that source degeneration reduces the transconductance of a CS amplifier from g to
m approximately gm/ 1+gmRs and increases its output resistance by approximately the same factor,
what happens to the open-circuit voltage gain Avo? Now, find an expression for Av when a load resistanceRL isconnectedtotheoutput.
Ans. Av o remains constant at gm ro :
A = g r RL (E.8.13) v m o RL+1+gmRs ro
8.4.3 The Body Effect
Since in the CG amplifier the source cannot be connected to the substrate, the body effect (see Section 5.4) plays a role in the operation of the CG amplifier. It turns out, however, that taking the body effect into account in the analysis of the CG circuit is a very simple matter. To see how this can be done, refer to Fig. 8.23(a) and recall that the body terminal acts as another gate for the MOSFET. Thus, just as a signal voltage vgs between the gate and the source gives
i
i
Dv1
D
ro
G, B
GB
gs
S
gm (lx)
vgs
vbs = vgs
(a)
Figure 8.23 The body effect can be easily taken into account in the analysis of the CG circuit by replacing gm by(1+χ)gm,whereχ=gmb/gm =0.1to0.2.
vbs
S
i = gmvgs gmbvbs = (gmgmb)vgs = gm(1x)vgs
(b)
risetoadraincurrentsignalgmvgs,asignalvoltagevbs betweenthebodyandthesourcegives rise to a drain current signal gmbvbs. Thus the drain signal current becomes (gmvgs +gmbvbs), where the body transconductance gmb is a small fraction χ of gm ; gmb = χ gm and χ = 0.1 to 0.2. For the CG circuit, vbs = vgs , thus the two current signals can be combined as (gm + gmb )vgs or gm(1+χ)vgs. Thus, the body effect can be taken into account by simply replacing gm by gm (1 + χ ) as illustrated in the T equivalent model shown in Fig. 8.23(b). Normally, however, we will not bother with the factor (1 + χ ) in our calculations.
8.4.4 The CB Circuit
Analysis of the CB amplifier parallels that of the CG amplifier except it is a little more involved because of the finite base current. Figure 8.24(a) shows a CB amplifier with the bias details only partially shown and with a load resistance RL that is normally implemented with a pnp current source. The circuit, prepared for small-signal analysis, is shown in Fig. 8.24(b). Note that since α ≃ 1 the current gain is nearly unity, an important characteristic of a current buffer.
Input Resistance The circuit for determining the input resistance Rin is shown in Fig. 8.25,
which also shows the currents in all branches, obtained by writing node equations for the three
nodes. Of special note is the use of the identity gm + 1 = 1 to obtain the current in the base rπ re
8.4 The Common-Gate and Common-Base Amplifiers 543
asvπ/rπ.Writingaloopequationfortheloopcomprisingvx,ro,andRL,andreplacingvπ by −vx , results in the following expression for Rin ≡ vx /ix ,
Rin = ro +RL 1+ro+ RL
re (β + 1)re
where we have utilized the relationship rπ = (β + 1)re . Since ro ≫ re ,
(8.62)
(8.63)
VCC
R ≃r ro+RL in e RL
ro + β + 1
(1a)i
Re i
Rin
ai
Rout
RL
vo RL
VB
Re
vsig
(a)
Figure 8.24 (a) A CB amplifier with the bias arrangement only partially shown. (b) The circuit with the dc sources eliminated.
vsig
(b)
544 Chapter 8
Building Blocks of Integrated-Circuit Amplifiers
i vp B ro
C
i vp x rp
g v
mp xre
RL
vp/rp
ix
vp
vp/re re
ix (vp/re)
Rin ≡ vx /ix
the input
E
vx
Figure 8.25 Determining resistance Rin of the CB amplifier.
Note that setting ro = ∞ yields Rin = re , which is consistent with the case of the discrete-circuit CB amplifier studied in Section 7.3.5. Also, for RL = 0, Rin = re. The value of Rin increases as RL is raised, reaching a maximum of
R =(β+1)r =r ,forR =∞ inmax eπL
that is, for the amplifier operating open circuited. Finally, for RL β+1
approximated by
Rin ≃ re + RL gm ro
which is very similar to the case of the MOSFET (Eq. 8.54). We conclude by noting that the impedance transformation property of the CB circuit ensures that its input resistance is kept small, an important characteristic of a current buffer.
Output Resistance The determination of the output resistance Rout of the CB amplifier is illustrated in Fig. 8.26. The result is
Rout =ro +(Re∥rπ)+(Re∥rπ)gmro (8.66)
which is very similar to the corresponding expression for the MOSFET case (Eq. 8.56) except that Rs is replaced by (Re ∥ rπ ). The expression in Eq. (8.66) can be written in the alternate form
(8.64)
≪ ro, Eq. (8.63) can be (8.65)
Forgmro ≫1,
Rout =ro +(1+gmro)(Re∥rπ) (8.67) Rout ≃ro +(gmro)(Re∥rπ) (8.68)
Thus, similar to the CG amplifier, the CB amplifier exhibits an impedance transformation property that raises the output resistance. Unlike the CG case, however, the output resistance of the CB circuit has an absolute maximum value obtained by setting Re = ∞ as
R =r+grr=(β+1)r (8.69) out max o m o π o
C
ix
8.4 The Common-Gate and Common-Base Amplifiers 545
ixgmvp mp
vp/rp
B ro vp/re
g v
vx
(i vp ) x rp
Rout ≡ vx /ix
vp re
ixgmvp E
Re
RL
r o R L
Re
gmro
Figure 8.27 The impedance transformation properties of the CB amplifier. Note that for β = ∞, these formulas reduce to those for the MOSFET case (Fig. 8.21).
We conclude that the CB circuit has a current gain of nearly unity, a low input resistance, and a high output resistance; thus it makes for an excellent current buffer. The impedance transformation properties of the CB circuit are summarized in Fig. 8.27.
EXERCISES
Figure 8.26 Determining resistance Rout of the CB amplifier.
the output
R
=r(Rr)g r(Rr) outo e moe
r (g r )(R r ) omoe
Rin re
o
RL r
b1
re RL , for RL bro
8.14 For a CB amplifier, find approximate values for Rin for the following cases: RL = 0; ro ; (β + 1)ro ; ∞. Ans. r ; 2r ; 1 r ; r
ee2ππ
8.15 For a CB amplifier, find approximate values for Rout for the following cases: Re = 0; re ; rπ ; ro ; ∞.
Ans. r ;2r ;(1β+1)r ;(β+1)r ;(β+1)r oo2ooo
546 Chapter 8
Building Blocks of Integrated-Circuit Amplifiers
8.4.5 Output Resistance of an Emitter-Degenerated CE Amplifier
As we have done in the MOS case, we shall adapt the expression for Ro derived for the CB amplifier (Eq. 8.68) for the case of a CE amplifier with a resistance Re connected in its emitter,
as shown in Fig. 8.28(a),
which can be written in the alternate form
Ro≃ro+gmro Re∥rπ
Ro = 1+gm Re∥rπ ro (8.70) Thus, emitter degeneration multiplies the transistor output resistance r by the factor
o
1+gm Re∥rπ .Notethatthisfactorhasamaximumvalueof(1+gmrπ)or(β+1),obtained
when Re ≫ rπ . Thus the theoretical maximum output resistance realized is (β + 1)ro and is achieved when the emitter is open circuited.
R=r(Rr)g r(Rr) ooemoe
ro[1 gm(Re rp)]
vi Re
Figure 8.28 Output resistance of a CE amplifier with an emitter resistance Re.
EXERCISE
8.16 Find the output resistance of a CE amplifier biased at IC = 1 mA and having a resistance of 500 connected in its emitter. Let β = 100 and VA = 10 V. What is the value of the output resistance without degeneration?
Ans. 177 k; 10 k
8.5 The Cascode Amplifier 8.5.1 Cascoding
Cascoding refers to the use of a transistor connected in the common-gate (or the common-base) configuration to provide current buffering for the output of a common-source (or a common-emitter) amplifying transistor. Figure 8.29 illustrates the technique for the MOS case. Here the CS transistor Q1 is the amplifying transistor and Q2, connected in the CG
d2
To Load Kro1
8.5 The Cascode Amplifier 547
VG2
Q2
d2 To Load
gm1vi
Kro1
vi
ro1 Q1
Figure 8.29 The current-buffering action of Fig. 8.17(b) is implemented using a transistor Q2 connected in the CG configuration. Here VG2 is a dc bias voltage. The output equivalent circuit indicates that the CG transistor passes the current gm1vi through but raises the resistance level by a factor K. Transistor Q2 is called a cascode transistor.
configuration with a dc bias voltage VG2 (signal ground) at its gate, is the cascode transistor.2 A similar arrangement applies for the bipolar case and will be considered later.
From our study of the CG amplifier characteristics, we can see that the cascode transistor passes the current gm1vi to the output node while multiplying the resistance in its source (ro1 of Q1 ) by a factor K. The result is the equivalent circuit of Fig. 8.29, which can be utilized to determine the voltage gain of the cascode amplifier for various load resistances. We shall consider the MOS cascode amplifier in detail next.
EXERCISE
8.17 Give an approximate value of the factor K of the circuit in Fig. 8.29. Ans. K ≃ gm2 ro2
8.5.2 The MOS Cascode Amplifier
The Ideal Case Figure 8.30(a) shows a MOS cascode amplifier loaded with an ideal constant-current source. The voltage gain realized can be found from the equivalent circuit in Fig. 8.30(b). Since the load is an ideal constant-current source, the load resistance is infinite. That is, the amplifier is operating with an open-circuit load, and the gain is
A ≡vo =−g R (8.71) vovi m1o
2 The name cascode is a carryover from the days of vacuum tubes and is a shortened version of “cascaded cathode”; in the tube version, the anode of the amplifying tube (corresponding to the drain of Q1) feeds the cathode of the cascode tube (corresponding to the source of Q2).
548 Chapter 8
Building Blocks of Integrated-Circuit Amplifiers
I
VG2
vi
Q2
r vo
o1
Q1
Ro (gm2ro2)ro1
vo
Rin = ∞
Figure 8.30 (a) A MOS cascode amplifier with an ideal current-source load; (b) equivalent circuit
representation of the cascode output.
Now, since Rs of Q2 is ro1, the output resistance Ro is given by the approximate expression
(a)
(b)
Ro ≃(gm2ro2)ro1
Substituting in Eq. (8.71) results in
Avo =−(gm1ro1)(gm2ro2)
For the case gm1 =gm2 =gm and ro1 =ro2 =ro,
Avo =−(gmro)2
= − A 20
Thus cascoding increases the gain magnitude from A0 to A20.
Implementation of the Constant-Current Source Load
(8.72)
(8.73)
( 8 . 7 4 )
If the current source load is implemented with a PMOS transistor (which can be part of a PMOS current mirror) as shown
in Fig. 8.31(a), the load resistance RL will be equal to the output resistance of Q3, ro3, RL =ro3
and the voltage gain of the cascode amplifier will be Av =−gm1(Ro∥RL)
= −gm1 (gm2 ro2 ro1 ∥ ro3 ) (8.75)
from which we can readily see that since RL ≪ Ro , the total resistance will be approximately equal to ro3 and the gain will be
Av ≃ −gm1ro3 (8.76)
gm1vi
Ro
VG3
VG2
VDD
Q3
Q2
Q1
(a)
RL = ro3
8.5 The Cascode Amplifier 549
Ro vo
gm1vi
Ro RL vo
(b)
vi
Figure8.31 (a)AMOScascodeamplifierloadedinasimplePMOScurrentsourceQ3.(b)Equivalentcircuit at the amplifier output.
Thus the gain magnitude will be back to A0 , of the same order as that realized by a CS amplifier. In other words, the use of a simple current-source load with a relatively low output resistance has in effect destroyed the cascoding advantage of increased output resistance. Nevertheless, it turns out that this cascode amplifier, whose gain is of the same order as that of a CS amplifier, does in fact have a major advantage over the CS circuit: It exhibits a much wider bandwidth. We will demonstrate this point in Chapter 10.
The Use of a Cascode Current Source To realize a gain of the order of A20, the load resistance RL must be of the same order as Ro of the cascode amplifier. This can be achieved by using a cascode current source such as that shown in Fig. 8.32. Here Q4 is the current-source transistor, and Q3 is the CG cascode transistor. Voltages VG3 and VG4 are dc bias voltages. The cascode transistor Q3 multiplies the output resistance of Q4, ro4 by (gm3ro3) to provide an
VDD
VG4
VG3
Q4
Q3
ro4 (gm3ro3)ro4
Figure 8.32 Employing a cascode transistor Q3 to raise the output resistance of the current source Q4.
550 Chapter 8
Building Blocks of Integrated-Circuit Amplifiers
VG4
VG3
VDD
Q3
Q4
ro4
Rop = (gm3ro3) ro4
V
Ron = (gm2ro2) ro1 G2 Q2vo
ro1
Q1 vi
(a)
Figure 8.33 A cascode amplifier with a cascode current-source load.
output resistance for the cascode current source of
Ro = (gm3ro3)ro4
(b)
vo
(8.77)
gm1 vi
Combining a cascode amplifier with a cascode current source results in the circuit of Fig. 8.33(a). The equivalent circuit at the output side is shown in Fig. 8.33(b), from which the voltage gain can be easily found as
Av = −gm1{[(gm2ro2)ro1]∥[(gm3ro3)ro4]} For the case in which all transistors are identical,
Av =−1(gmro)2 =−1A20 22
(8.78)
(8.79)
A =vo =−g R ∥R v v m1 on op
i
Thus,
By comparison to the gain expression in Eq. (8.50), we see that using the cascode configuration for both the amplifying transistor and the current-source load transistor results in an increase in the magnitude of gain by a factor equal to A0.
Ron Rop
resistance of 500 k. Assume the availability of a 0.18-μm CMOS technology for which V = 1.8 V, 2′ DD
Vtp =−0.5V, μpCox =90μA/V , and VA =−5V/μm. Use VOV each transistor, and the values of the bias voltages VG3 and VG4.
=0.3V and determine L and W/L for
Solution
The output resistance Ro is given by
Assuming Q3 and Q4 are identical,
Ro = gm3ro3 ro4
Ro = gmro ro
V V = A × A VOV /2 ID
= 0.3 V, we write Thus we require
VA 500 k = ×
VA 0.1 mA
8.5 The Cascode Amplifier 551
Example 8.5
It is required to design the cascode current source of Fig. 8.32 to provide a current of 100 μA and an output
Using V OV
Now, since V = V ′ L we need to use a channel length of AA
L= 2.74 =0.55μm 5
which is about three times the minimum channel length. With V = 0.5 V and V
t OV
VSG4 =0.5+0.3=0.8V VG4 =1.8−0.8=1.0V
= 0.3 V,
0.15
V =2.74V
A
and thus,
To allow for the largest possible signal swing at the output terminal, we shall use the minimum required
voltage across Q , namely, V or 0.3 V. Thus, 4 OV
VD4 =1.8−0.3=1.5V Since the two transistors are identical and are carrying equal currents,
Thus,
VSG3 =VSG4 =0.8V VG3 =1.5−0.8=+0.7V
552
Chapter 8 Building Blocks of Integrated-Circuit Amplifiers
Example 8.5 continued
We note that the maximum voltage allowed at the output terminal of the current source will be constrained
by the need to allow a minimum voltage of V across Q ; thus; OV 3
vD3max =1.5−0.3=+1.2V To determine the required W/L ratios of Q3 and Q4, we use
which yields
EXERCISES
1 W2 VSD
ID = 2 μpCox L VOV 1+ V
A
100=1×90× W ×0.32 1+0.3 2 L 2.74
W =22.3 L
D8.18 If in Example 8.5, L of each of Q3 and Q4 is halved while W/L is changed to allow ID and VOV to remainunchanged,findthenewvaluesofR andW/L.[Hint:Incomputingtherequired(W/L),note
o
Ans. 125 k; 20.3
8.19 Consider the cascode amplifier of Fig. 8.33 with the dc component at the input, VI = 0.7 V, VG2 =
1.0V, V =0.8V, V =1.1V, and V =1.8V. If all devices are matched (i.e., if k =k = G3 G4 DD n1 n2
kp3 = kp4 ), and have equal Vt of 0.5 V, what is the overdrive voltage at which the four transistors are operating? What is the allowable voltage range at the output?
Ans. 0.2V;0.5Vto1.3V
that V has changed.] A
8.20 The cascode amplifier in Fig. 8.33 is operated at a current of 0.2 mA with all devices operating at V = 0.2 V. All devices have V = 2 V. Find g , the output resistance of the amplifier, R ,
OV A m1 on and the output resistance of the current source, Rop. Also find the overall output resistance and the
voltage gain realized.
Ans. 2 mA/V; 200 k, 200 k; 100 k; −200 V/V
8.5.3 Distribution of Voltage Gain in a Cascode Amplifier
It is often useful to know how much of the overall voltage gain of a cascode amplifier is realized in each of its two stages: the CS stage Q1, and the CG stage Q2. For this purpose, consider the cascode amplifier shown in Fig. 8.34(a). Here, for generality we have included
8.5 The Cascode Amplifier 553
vi
g1
(gm2 ro2)ro1 Q2 RL vo
Rin2
d1 vo1
ro1 Q1
(a)
d1
vi
Rd1
Figure8.34 (a)The cascode amplifier with a load resistance RL. Only signal quantities are shown.
(b) Determining vo1.
a load resistance RL, which represents the output resistance of the current-source load plus any additional resistance that may be connected to the output node. The voltage gain Av of the amplifier can be found as
Av =−gm1(Ro∥RL)
gm vi
ro1 Rin2 vo1
(b)
Thus,
The overall gain Av can be expressed as the product of the voltage gains of Q1 and Q2 as
vo1vo
Av =Av1Av2 = v v (8.81)
i o1
To obtain Av1 ≡ vo1/vi we need to find the total resistance between the drain of Q1 and ground.
Av =−gm1(gm2ro2ro1∥RL) (8.80)
Referring to Fig. 8.34(b) and denoting this resistance Rd1, we can express Av1 as
A =vo1 =−g R (8.82)
v1vi m1d1
Observe that Rd1 is the parallel equivalent of ro1 and Rin2, where Rin2 is the input resistance of
the CG transistor Q2 . From Eq. (8.54), we can write
Rin2≃RL +1 (8.83) gm2 ro2 gm2
554 Chapter 8
Building Blocks of Integrated-Circuit Amplifiers
Table 8.1
Case
Gain Distribution in the MOS Cascode Amplifier for Various Values of RL
RL Rin2 Rd1 Av1 Av2 Av
∞ ∞ r −gr gr −gr2 omomomo
grr r r/2 −1gr gr −1gr2 moooo2momo2mo
r 2 2 −2 1gr −gr ogmgm 2momo
1 2 3
4
0 1 1 −1 0 0 gm gm
Now we can obtain Rd1 as
and Av1 as
Rd1 = ro1 ∥Rin2
Av1 = −gm1Rd1 = −gm1(ro1 ∥Rin2)
(8.84)
(8.85)
Finally, we can obtain Av2 by dividing the total gain Av given by Eq. (8.80) by Av1. To provide insight into the effect of the value of RL on the overall gain of the cascode as well as on how this gain is distributed among the two stages of the cascode amplifier, we provide in Table 8.1 approximate values for the case ro1 = ro2 = ro and for four different values of RL : (1) RL = ∞, obtained with an ideal current-source load; (2) RL = (gmro)ro, obtained with a cascode current-source load; (3) RL = ro , obtained with a simple current-source load; and (4) for completeness, RL = 0, that is, a signal short circuit at the output.
Observe that while case 1 represents an idealized situation, it is useful in that it provides the theoretical maximum voltage gain achievable in a MOS cascode amplifier. Case 2, which assumes a cascode current-source load with an output resistance equal to that of the cascode amplifier, provides a realistic estimate of the gain achieved if one aims to maximize the realized gain. In certain situations, however, that is not our objective. This point is important, for as we shall see in Chapter 10, there is an entirely different application of the cascode amplifier: namely, to obtain wideband amplification by extending the upper-3-dB frequency fH . As will be seen, for such an application one opts for the situation represented by case 3, where the gain achieved in the CS amplifier is only −2 V/V, and of course the overall gain is now only −(gm ro ). However, as will be seen in Chapter 10, this trade-off of the overall gain to obtain extended bandwidth is in some cases a good bargain!
EXERCISE
8.21 Consider a cascode amplifier for which the CS and CG transistors are identical and are biased to operateatID =0.1mAwithVOV =0.2V.AlsoletVA =2V.FindAv1,Av2,andAv fortwocases:(a) RL =20kand(b)RL =400k.
Ans. (a) –1.82 V/V, 10.5 V/V, –19.0 V/V; (b) –10.2 V/V, 19.6 V/V, –200 V/V
8.5.4 Double Cascoding
If a still higher output resistance and correspondingly higher gain are required, it is possible to add another level of cascoding, as illustrated in Fig. 8.35. Observe that Q3 is the second cascode transistor, and it raises the output resistance by (gm3ro3). For the case of identical transistors, the output resistance will be (gm ro )2 ro and the voltage gain, assuming an ideal current-source load, will be (gmro)3 orA30. Of course, we have to generate another dc bias voltage for the second cascode transistor, Q3.
A drawback of double cascoding is that an additional transistor is now stacked between the power-supply rails. Furthermore, to realize the advantage of double cascoding, the current-source load will also need to use double cascoding with an additional transistor. Since for proper operation each transistor needs a certain minimum vDS (at least equal to VOV ), and recalling that modern MOS technology utilizes power supplies in the range of 1 V to 2 V, we see that there is a limit on the number of transistors in a cascode stack.
VDD
I
8.5 The Cascode Amplifier 555
VG3 Q3
vo
(gm3ro3)(gm2ro2)ro1 = A20 ro
(gm2ro2)ro1
VG2 Q2
ro1
vi Q1
8.5.5 The Folded Cascode
Figure 8.35 Double cascoding.
To avoid the problem of stacking a large number of transistors across a low-voltage power supply, one can use a PMOS transistor for the cascode device, as shown in Fig. 8.36. Here, as before, the NMOS transistor Q1 is operating in the CS configuration, but the CG stage is implemented using the PMOS transistor Q2. An additional current source I2 is needed to bias Q2 and provide it with its active load. Note that Q1 is now operating at a bias current of (I1 −I2). Finally, a dc voltage VG2 is needed to provide an appropriate dc level for the gate of the cascode transistor Q2. Its value has to be selected so that Q2 and Q1 operate in the saturation region.
The small-signal operation of the circuit in Fig. 8.36 is similar to that of the NMOS cascode. The difference here is that the signal current gmvi is folded down and made to flow
556 Chapter 8
Building Blocks of Integrated-Circuit Amplifiers
VDD
I1
gmvi
vi Q1
Q2
VG2
vo I2
Figure 8.36 The folded cascode.
into the source terminal of Q2, which gives the circuit the name folded cascode.3 The folded cascode is a very popular building block in CMOS amplifiers.
EXERCISE
D8.22 Consider the folded-cascode amplifier of Fig. 8.36 for the following case: VDD = 1.8 V, kn′ = 4kp′ , andVtn =−Vtp =0.5V.TooperateQ1 andQ2 atequalbiascurrentsI,I1 =2IandI2 =I.While current source I1 is implemented using the simple circuit studied in Section 8.2, current source I2 is realized using a cascoded circuit (i.e., the NMOS version of the circuit in Fig. 8.32). The transistor W/L ratios are selected so that each operates at an overdrive voltage of 0.2 V.
(a) What must the relationship of (W/L)2 to (W/L)1 be?
(b) What is the minimum dc voltage required across current source I1 for proper operation? Now, if
a 0.1-V peak-to-peak signal swing is to be allowed at the drain of Q1, what is the highest dc bias
voltage that can be used at that node?
(c) What is the value of VSG of Q2, and hence what is the largest value to which VG2 can be set?
(d) What is the minimum dc voltage required across current-source I2 for proper operation?
(e) Given the results of (c) and (d), what is the allowable range of signal swing at the output?
Ans. (a)(W/L)2 =4(W/L)1;(b)0.2V,1.55V;(c)0.7V,0.85V;(d)0.4V;(e)0.4Vto1.35V
3The circuit itself can be thought of as having been folded. In this same vein, the regular cascode is sometimes referred to as a telescopic cascode because the stacking of transistors resembles the extension of a telescope.
8.5.6 The BJT Cascode
Figure 8.37(a) shows the BJT cascode amplifier with an ideal current-source load. Voltage VB2 is a dc bias voltage for the CB cascode transistor Q2. The circuit is very similar to the MOS cascode, and the small-signal analysis will follow in a parallel fashion. First, note that the input resistance of the bipolar cascode amplifier is finite,
Rin =rπ1 (8.86)
Second, recall that the current signal in the collector of Q2 will be approximately equal to gm1 vi. Thus, the equivalent circuit of the output of the cascode amplifier will be that shown in Fig. 8.37(b). To obtain Ro we use the formula in Eq. (8.68) and note that the resistance Re in the emitter of Q2 is ro1, thus
Ro ≃ro2 +(gm2ro2) ro1∥rπ2 (8.87) Since gm2 ro1 ∥ rπ 2 ≫ 1, we can neglect the first term on the right-hand side of Eq. (8.87),
Ro ≃ (gm2ro2) ro1 ∥rπ2 (8.88) This result is similar but certainly not identical to that for the MOS cascode. Here, because of
will always be lower than
rπ2, it follows that the maximum possible value of Ro is R = g r r
= gm2rπ2 ro2 =β2ro2
Thus the maximum output resistance realizable by cascoding is β2ro2. This means that unlike
8.5 The Cascode Amplifier 557
the finite β of the BJT, we have r appearing in parallel with r . This poses a very significant
π2
constraint on Ro of the BJT cascode. Specifically, because
o1 ro1 ∥ rπ 2
o max m2 o2 π2
(8.89)
the MOS case, double cascoding with a BJT would not be useful.
I
c2
Q2
r vo
o1
Ro (gm2 ro2) (ro1 rp2)
Q1
Figure 8.37 (a) A BJT
equivalent-circuit representation of the output of the cascode amplifier.
VB2
Rr
c2
vi
gm1 vi
Ro
in 1
(a)
(b)
load;
cascode
amplifier
with an
ideal
current-source
(b) small-signal,
558 Chapter 8
Building Blocks of Integrated-Circuit Amplifiers
The open-circuit voltage gain of the bipolar cascode can be found using the equivalent circuit of Fig. 8.37(b) as
Thus,
A =vo =−g R vovi m1o
Avo = −gm1(gm2ro2) ro1 ∥rπ2 For the case gm1 = gm2, ro1 = ro2,
is obtained when ro ≫ rπ and is given by
A =βgr=βA (8.92)
(8.90)
(8.91) which will be less than (gmro)2 in magnitude. In fact, the maximum possible gain magnitude
Avo = −(gmro) gm ro ∥rπ
vo max m o 0
Finally, we note that to be able to realize gains approaching this level, the current-source load must also be cascoded. Figure 8.38 shows a cascode BJT amplifier with a cascode current-source load.
VCC
VB4
VB3
VB2
vi
Rin = r1
Q4
Q3
R =(g r )(r r ) op m3o3o43
Q2 vo
Q1
R =(g r )(r r ) on m2o2o12
Av = gm1(Ron Rop)
Figure 8.38 A BJT cascode amplifier with a cascode current source.
8.6 Current-Mirror Circuits with Improved Performance 559
EXERCISES
find Ron, Rop, and Av. Also use the result of Exercise 8.23 to determine the maximum achievable gain.
Ans. 1.67 M; 0.762 M; −4186 V/V; −5714 V/V
8.6 Current-Mirror Circuits with Improved Performance
As we have seen throughout this chapter, current sources play a major role in the design of IC amplifiers: The constant-current source is used both in biasing and as active load. Simple forms of both MOS and bipolar current sources and, more generally, current mirrors were studied in Section 8.2. The need to improve the characteristics of the simple sources and mirrors has already been demonstrated.
Specifically, three performance parameters need to be addressed:
1. The accuracy of the current transfer ratio of the mirror. For bipolar mirrors, this parameter is primarily affected by the transistor β. For both bipolar and MOS mirrors, the Early effect affects the current transfer ratio.
2. The output resistance, Ro . The need to increase the output resistance of current sources is motivated by the need to increase the voltage gain achievable in an amplifier stage. While simple bipolar and MOS mirrors have output resistances equal to ro , cascoding can be used to increase the output resistance.
3. The minimum dc voltage required across the current source. The need to keep this voltage as small as possible stems from the low dc voltage supplies employed in modern IC technologies. Simple BJT and MOS sources can operate with dc voltages in the range of 0.2 V to 0.3 V. More elaborate mirror circuits usually require higher voltages.
In this section we study MOS and bipolar current mirrors that feature improvements in one or more of these characteristics.
8.6.1 Cascode MOS Mirrors
The use of cascoding in the design of current sources was presented in Section 8.5. Figure 8.39 shows the basic cascode current mirror. Observe that in addition to the diode-connected transistor Q1, which forms the basic mirror Q1–Q2, another diode-connected transistor, Q4, is used to provide a suitable bias voltage for the gate of the cascode transistor Q3. To determine the output resistance of the cascode mirror at the drain of Q3, we assume that the voltages
8.23 Find an expression for the maximum voltage gain achieved in the amplifier of Fig. 8.38. Ans. A =g βr ∥βr
vmax m1 2 o2 3 o3
8.24 Consider the BJT cascode amplifier of Fig. 8.38 when biased at a current of 0.2 mA. Assuming that
npntransistorshaveβ=100andV =5Vandthatpnptransistorshaveβ=50andV=4V, AA
560 Chapter 8
Building Blocks of Integrated-Circuit Amplifiers
R
VO
o
Figure 8.39 A cascode MOS current mirror.
across Q1 and Q4 are constant, and thus the signal voltages at the gates of Q2 and Q3 will be
zero. Thus Ro will be that of the cascode current source formed by Q2 and Q3,
Ro ≃ gm3ro3ro2 (8.93)
Thus, as expected, cascoding raises the output resistance of the current source by the factor (gm3ro3), which is the intrinsic gain of the cascode transistor.
A drawback of the cascode current mirror is that it consumes a relatively large portion of the steadily shrinking supply voltage VDD. While the simple MOS mirror operates properly with avoltageaslowasVOV acrossitsoutputtransistor,thecascodecircuitofFig.8.39requiresa minimum voltage of Vt + 2VOV . This is because the gate of Q3 is at 2VGS = 2Vt + 2VOV . Thus the minimum voltage required across the output of the cascode mirror is 1 V or so. This obviously limits the signal swing at the output of the mirror (i.e., at the output of the amplifier that utilizes this current source as a load). In Chapter 13 we shall study a wide-swing cascode mirror.
EXERCISE
8.25 For a cascode MOS mirror utilizing devices with Vt = 0.5 V, μn Cox = 387 μA/V2 , VA′ = 5 V/μm, W/L = 3.6 μm/0.36 μm, and IREF = 100 μA, find the minimum voltage required at the output and the output resistance.
Ans. 0.95 V; 285 k
8.6.2 The Wilson Current Mirror
A simple but ingenious modification of the basic bipolar mirror results in both reducing the β dependence and increasing the output resistance. The resulting circuit, known as the Wilson mirror after its inventor George Wilson, an IC design engineer working for Tektronix, is shown in Fig. 8.40(a). The analysis to determine the effect of finite β on the current transfer
8.6 Current-Mirror Circuits with Improved Performance 561 ix
vx IREF i232
(1 2b)b IO=IC b1
bi
I 112b C b1
Q3 b1
Q3 ro3
IC
1 2b
Ro =vxix
I C 1 b2
I2ICI
i2 i1
CbC Q2 Q1
ro2
Q2 Q1 ro1 vi1re1
ICb ICb
VEE
Figure8.40 TheWilsonbipolarcurrentmirror:(a)circuitshowinganalysistodeterminethecurrenttransfer
ratio; (b) determining the output resistance.
ratio is shown in Fig. 8.40(a), from which we can write
2
I IC 1+ββ(β+1)
O =
(a)
(b)
IREF
IC 1+ 1+2 (β+1) β
=β+2=β+2 β+1+β+2 β+2+2
=1 1+2
Ro =vx/ix
ββ
β(β+2)
≃ 1 (8.94)
1+2/β2
which is much less dependent on β than in the case of the simple current mirror.
This analysis assumes that Q1 and Q2 conduct equal collector currents. There is, however, a slight problem with this assumption: The collector-to-emitter voltages of Q1 and Q2 are not equal, which introduces a current offset or a systematic error. The problem can be solved by adding a diode-connected transistor in series with the collector of Q2 , as we shall shortly
show for the MOS version.
To determine the output resistance of the Wilson mirror, we set IREF = 0 and apply a
test voltage vx to the output node, as shown in Fig. 8.40(b). Our purpose is to determine the current ix and hence Ro as
562 Chapter 8
Building Blocks of Integrated-Circuit Amplifiers
Rather than replacing each transistor with its hybrid-π model, we shall do the analysis directly on the circuit diagram. For this purpose, we have “pulled ro out” of each transistor and shown it separately.
Observe that transistor Q3, viewed as a supernode (highlighted in color), has a current ix entering it and two currents i1 and i2 exiting it; thus,
i1 + i2 = ix
Next note that the action of current mirror Q1–Q2 forces i2 to be approximately equal to i1;
thus,
i2 ≃i1 =ix/2
Currenti2 flowsintothebaseofQ3 andthusgivesrisetoacollectorcurrentβ3i2 inthedirection indicated. We are now in a position to write a node equation at the collector of Q3 and thus determine the current through ro3 as ix + β3 i2 = ix + β3 (ix /2) = ix (β3 /2 + 1). Finally, we can express the voltage between the collector of Q3 and ground as the sum of the voltage drop across ro3 and the voltage v across Q1,
Sincero ≫re andβ3 ≫2
and
β
v=i 3+1r+ir
x x 2 o3 1e1 β i
=i3+1r+xr
x 2 o3 2 e1
β v≃i3r
x x 2 o3
Ro = β3ro3/2
Thus the Wilson current mirror has an output resistance ( 1 β3 ) times higher than that of
(8.95)
2
Q3 alone. This is a result of the negative feedback obtained by feeding the collector current
of Q2 (i2) back to the base of Q3. As can be seen from the above analysis, this feedback results in increasing the current through ro3 to approximately 1 β3 ix , and thus the voltage
2
across ro3 and the output resistance increase by the same factor, 1 β3 . Finally, note that the 2
factor 1 is because only half of ix is mirrored back to the base of Q3. 2
The Wilson mirror is preferred over the cascode circuit because the latter has the same dependence on β as the simple mirror. However, like the cascode mirror, the Wilson mirror requires an additional VBE drop for its operation; that is, for proper operation we must allow for 1 V or so across the Wilson mirror output.
8.6 Current-Mirror Circuits with Improved Performance 563
EXERCISE
8.26 For β = 100 and ro = 100 k, contrast the Wilson mirror and the simple mirror by evaluating the transfer-ratio error due to finite β, and the output resistance.
Ans. Transfer-ratio error: 0.02% for Wilson as opposed to 2% for the simple circuit; Ro = 5 M for Wilson compared to 100 k for the simple circuit
8.6.3 The Wilson MOS Mirror
Figure 8.41(a) shows the MOS version of the Wilson mirror. Obviously there is no β error to reduce here, and the advantage of the MOS Wilson lies in its enhanced output resistance.
To determine the output resistance of the Wilson MOS mirror, we set IREF = 0, and apply a test voltage vx to the output node, as shown in Fig. 8.41(b). Our purpose is to determine the current ix and hence Ro as
Ro =vx/ix
Rather than replacing each transistor with its hybrid-π equivalent-circuit model, we shall perform the analysis directly on the circuit. For this purpose, we have “pulled ro out” of each transistor and shown it separately.
ix
0
id3
Q3
vx
ro3
VO
(ixro2)
Ro = vx ix
ix
ix i x
ix
ro2
Q2 Q1
(b)
ro1 vixgm1
Q2
Q1
(a)
Figure 8.41 The Wilson MOS mirror: (a) circuit; (b) analysis to determine output resistance; (c) modified circuit.
564 Chapter 8
Building Blocks of Integrated-Circuit Amplifiers
VO
Q2
Q1
(c)
Figure 8.41 continued
Observe that the current ix that enters the drain of Q3 must exit at its source. Thus the current that feeds the input side of the Q1–Q2 mirror is equal to ix. Most of this current will flow in the drain proper of Q1 (i.e., only a very small fraction flows through ro1) and will give risetoavoltagev≃ix/gm1,where1/gm1 istheapproximateresistanceofthediode-connected transistor Q1. The current-mirror action of (Q1, Q2) forces a current equal to ix to flow through the drain proper of Q2. Now, since the current in the drain of Q2 is forced (by the connection to the gate of Q3) to be zero, all of ix must flow through ro2, resulting in a voltage −ixro2. This is the voltage fed back to the gate of Q3. The drain current of Q3 can now be found as
id3 = gm3vgs3
=gm3 vg3−vs3 =gm3(−ixro2 −ix/gm1)
≃ −gm3 ro2 ix
A node equation at the drain of Q3 gives the current through ro3 as (ix − id3) = ix + gm3ro2ix ≃ gm3ro2ix. Finally, we can express vx as the sum of the voltage drop across ro3 and the voltage v across Q1,
and obtain
vx =gm3ro2ixro3 +v =(gm3ro3ro2)ix +(ix/gm1)
≃ gm3ro3ro2ix
Ro = vx = (gm3ro3)ro2
ix
Thus, the Wilson MOS mirror exhibits an increase of output resistance by a factor (gm3ro3), an identical result to that achieved in the cascode mirror. Here the increase in Ro , as demonstrated in the analysis above, is a result of the negative feedback obtained by connecting the drain of Q2 to the gate of Q3. Finally, to balance the two branches of the mirror and thus avoid the systematic current error resulting from the difference in VDS between Q1 and Q2, the circuit can be modified as shown in Fig. 8.41(c).
(8.96)
and
I VBE1 = VT ln REF
IS I
I VBE1−VBE2 = VT ln REF
IO VBE1 =VBE2 +IORE
I IORE=VTln REF
IO
(8.97)
(8.98) where we have assumed that Q1 and Q2 are matched devices. Combining Eqs. (8.97) and
8.6 Current-Mirror Circuits with Improved Performance 565
Figure 8.42 The Widlar current source.
8.6.4 The Widlar Current Source4
Our final current-source circuit, known as the Widlar current source, is shown in Fig. 8.42. Itdiffersfromthebasiccurrent-mirrorcircuitinanimportantway:AresistorRE isincluded in the emitter lead of Q2. Neglecting base currents we can write
VBE2 = VT ln O IS
(8.98) gives
But from the circuit we see that
Thus,
(8.99)
(8.100)
(8.101)
The design and advantages of the Widlar current source are illustrated in the following example.
4Named after Robert Widlar, a pioneer in analog IC design.
566 Chapter 8 Building Blocks of Integrated-Circuit Amplifiers
Example 8.6
The two circuits for generating a constant current IO = 10 μA shown in Fig. 8.43 operate from a 10-V supply.Determinethevaluesoftherequiredresistors,assumingthatVBE is0.7Vatacurrentof1mAand neglecting the effect of finite β.
(a) (b)
Figure 8.43 Circuits for Example 8.6.
Solution
For the basic current-source circuit in Fig. 8.43(a) we choose a value for R1 to result in IREF = 10 μA. At this current, the voltage drop across Q1 will be
10μA VBE1=0.7+VTln 1mA =0.58V
Thus,
For the Widlar circuit in Fig. 8.43(b) we must first decide on a suitable value for IREF . If we select IREF =
1mA,thenVBE1 =0.7VandR2 isgivenby
R2 = 10−0.7 =9.3k
1
The value of R3 can be determined using Eq. (8.101) as follows:
10×10−6R3 =0.025ln 1mA 10 μA
R3 =11.5k
R1 = 10−0.58 =942k 0.01
From the above example we observe that using the Widlar circuit allows the generation of a small constant current using relatively small resistors. This is an important advantage that results in considerable savings in chip area. In fact the circuit of Fig. 8.43(a), requiring a 942-k resistance, is totally impractical for implementation in IC form because of the very high value of resistor R1.
Another important characteristic of the Widlar current source is that its output resistance is high. The increase in the output resistance, above that achieved in the basic current source, is due to the emitter-degeneration resistance RE . To determine the output resistance of Q2 , we assume that since the base of Q2 is connected to ground via the small resistance re of Q1, the incremental voltage at the base will be small. Thus we can use the formula in Eq. (8.70) and adapt it for our purposes here as follows:
Rout ≃ 1+gm RE∥rπ ro (8.102) Thus the output resistance is increased above ro by a factor that can be significant.
EXERCISE
8.27 Find the output resistance of each of the two current sources designed in Example 8.6. Let VA = 100 V and β = 100.
Ans. 10 M; 54 M
8.7 Some Useful Transistor Pairings
The cascode configuration studied in Section 8.5 combines CS and CG MOS transistors (CE and CB bipolar transistors) to great advantage. The key to the superior performance of the resulting combination is that the transistor pairing is done in a way that maximizes the advantages and minimizes the shortcomings of each of the two individual configurations. In this section we present a number of other such transistor pairings. In each case the transistor pair can be thought of as a compound device; thus the resulting amplifier may be considered as a single stage.
8.7.1 The CC–CE, CD–CS, and CD–CE Configurations
Figure 8.44(a) shows an amplifier formed by cascading a common-collector (emitter-follower) transistor Q1 with a common-emitter transistor Q2 . This circuit has two main advantages over the CE amplifier. First, the emitter follower increases the input resistance by a factor equal to (β1 + 1). As a result, the overall voltage gain is increased, especially if the resistance of the signal source is large. Second, it will be shown in Chapter 10 that the CC–CE amplifier can exhibit much wider bandwidth than that obtained with the CE amplifier.
The MOS counterpart of the CC–CE amplifier, namely, the CD–CS configuration, is shown in Fig. 8.44(b). Here, since the CS amplifier alone has an infinite input resistance, the
8.7 Some Useful Transistor Pairings 567
568 Chapter 8
Building Blocks of Integrated-Circuit Amplifiers
VCC
I2
VDD
I2
Q2
Q1
Q2
Q1
(b)
I1
I1
(a)
Q1
I1
I2
Q2
Figure8.44 (a)CC–CEamplifier;(b)CD–CSamplifier;(c)CD–CEamplifier.
(c)
sole purpose for adding the source-follower stage is to increase the amplifier bandwidth, as will be seen in Chapter 10. Finally, Fig. 8.44(c) shows the BiCMOS version of this circuit type. Compared to the bipolar circuit in Fig. 8.44(a), the BiCMOS circuit has an infinite input resistance. Compared to the MOS circuit in Fig. 8.44(b), the BiCMOS circuit typically has a higher gm2.
The IC Source Follower Since a number of the circuit configurations discussed in this section utilize an input source follower, we digress briefly to consider the IC source follower (the discrete-circuit source follower was studied in Section 7.3.6). Figure 8.45(a) shows a source follower formed by transistor Q1 and biased by a constant-current supplied by the current mirror Q2−Q3. Observe that since the source of Q1 cannot be connected to the body (which is at signal ground potential) a voltage signal vbs develops between body and source and gives rise to a current signal gmbvbs, as indicated in the equivalent circuit in Fig. 8.45(b). The equivalent circuit shows also the output resistance ro3 of the bias current source Q3 , which acts as a load resistance for the follower Q1.
An important observation to make from the equivalent circuit is that the controlled source (gmb vbs ) appears across its control voltage vbs . Thus we can use the source-absorption theorem (Appendix G) to replace the controlled source with a resistance 1/gmb . Next, note that the three
VDD
Q1
G
B vgs
8.7
Some Useful Transistor Pairings 569 D, B
gmbvbs
gmvgs ro1
vi I REF
Q2
vi
vo S
ro3
Q3
ro3 vo
(b)
(a)
Figure 8.45 (a) A source follower biased with a current mirror Q2−Q3 and with the body terminal indicated. Note that the source cannot be connected to the body and thus the body effect should be taken into account. (b) Equivalent circuit.
resistances 1/gmb, ro1, and ro3 appear in parallel between the source and ground. If we denote their parallel equivalent RL , we can easily show that the voltage gain of the source follower
is given by
where
In cases where
and
1 ≪ ro1,ro3, gmb
vo = RL
vi RL + 1
gm
RL =ro1∥ro3∥ 1 gmb
RL ≃ 1 gmb
vo ≃ gmb
vi gm +gmb
(8.103)
(8.104)
(8.105)
Substituting for gmb = χ gm where χ = 0.1 to 0.2, vo ≃ 1
(8.106) This is the maximum possible gain obtained from an IC source follower. The actual gain
vi 1+χ
realized will usually be lower because of the effect of ro1 and ro3.
EXERCISE
8.28 ForthesourcefollowerinFig.8.45(a),letthebiascurrentofQ1 be200μAandassumeQ1 isoperating at VOV = 0.2 V. If VA = 5 V and χ = 0.2, find the voltage gain of the source follower.
Ans. 0.81 V/V
570 Chapter 8 Building Blocks of Integrated-Circuit Amplifiers
Example 8.7
For the CC–CE amplifier in Fig. 8.44(a) let I1 = I2 = 1 mA and assume identical transistors with β = 100. Find the input resistance Rin and the overall voltage gain obtained when the amplifier is fed with a signal source having Rsig = 4 k and loaded with a resistance RL = 4 k. Compare the results with those obtained with a common-emitter amplifier operating under the same conditions. Ignore ro.
Solution
At an emitter current of 1 mA, Q1 and Q2 have
gm =40mA/V
Q1
vo
re =25
rπ = β = 100 = 2.5 k
gm
40
Rsig
vb1
re1 vb2 L
Rin Rin2 (c)
Figure 8.46 Circuit for Example 8.7. Referring to Fig. 8.46 we can find
Rin2 =rπ2 =2.5k
Rin=β1+1 re1+Rin2
= 101(0.025 + 2.5) = 255 k
vsig
Q2
R
vb1 v sig
vb2 vb1
vo vb2
= Rin = 255 =0.98V/V Rin +Rsig 255+4
= Rin2 = 2.5 =0.99V/V Rin2 +re1 2.5+0.025
=−g R =−40×4=−160V/V m2 L
Thus,
G = vo =−160×0.99×0.98=−155V/V v vsig
For comparison, a CE amplifier operating under the same conditions will have Rin =rπ =2.5k
G = Rin −g R vR+RmL
= 2.5 (−40×4) 2.5+4
= −61.5 V/V
in sig
8.7 Some Useful Transistor Pairings 571
EXERCISE
8.29 Repeat Example 8.7 for the CD–CE configuration of Fig. 8.44(c). Let I1 = I2 = 1 mA, β2 = 100, RL = 4 k, and kn1 = 8 mA/V2; neglect the body effect in Q1 and ro of both transistors. Find Rin and Gv when Rsig = 4 k (as in Example 8.7) and Rsig = 400 k. What would Gv of the CC–CE amplifier in Example 8.7 become for Rsig = 400 k?
Ans. Rin = ∞; Gv = −145.5 V/V, independent of Rsig ; −61.7 V/V
8.7.2 The Darlington Configuration5
Figure 8.47(a) shows a popular BJT circuit known as the Darlington configuration. It can be thought of as a variation of the CC–CE circuit with the collector of Q1 connected to that of Q2. Alternatively, the Darlington pair can be thought of as a composite transistor with β = β1β2. It can therefore be used to implement a high-performance voltage follower, as illustrated in Fig.8.47(b). Note that in this application the circuit can be considered as the cascade connection of two common-collector transistors (i.e., a CC–CC configuration).
Since the transistor β depends on the dc bias current, it is possible that Q1 will be operating at a very low β, rendering the β-multiplication effect of the Darlington pair rather ineffective. A simple solution to this problem is to provide a bias current for Q1 , as shown in Fig. 8.47(c).
5Named after Sidney Darlington, a pioneer in filter design and transistor circuit design.
572 Chapter 8 Building Blocks of Integrated-Circuit Amplifiers
C
VCC
Rsig
B Q1 Q1
Q2 vsig
Rin
Q2
vo RE
Rout
Q1
I
VCC
Q2
RE
VEE
Figure 8.47 (a) The Darlington configuration; (b) voltage follower using the Darlington configuration;
(a) (b)
(c) the Darlington follower with a bias current I supplied to Q1 to ensure that its β remains high.
EXERCISE
8.30 For the Darlington voltage follower in Fig. 8.47(b), show that:
Rin = β1+1 re1+ β2+1 re2+RE
Rout=RE∥ re2+re1+Rsig/β1+1 β2 +1
vo= RE vsig RE+re2+ re1+Rsig/β1+1 /β2+1
EvaluateRin,Rout,andvo/vsig forthecaseIE2 =5mA,β1 =β2 =100,RE =1k,andRsig =100k. Ans. 10.3 M; 20 ; 0.98 V/V
8.7.3 The CC–CB and CD–CG Configurations
Cascading an emitter follower with a common-base amplifier, as shown in Fig. 8.48(a), results in a circuit with a low-frequency gain approximately equal to that of the CB but with the problem of the low input resistance of the CB solved by the buffering action of the CC stage. It will be shown in Chapter 10 that this circuit exhibits wider bandwidth than that obtained with a CE amplifier of the same gain. Note that the biasing current sources shown in Fig. 8.48(a) ensure that each of Q1 and Q2 is operating at a bias current I. We are not showing, however, how the dc voltage at the base of Q1 is set, nor do we show the circuit that determines the
VEE (c)
E
8.7
Some Useful Transistor Pairings 573
VCC
Q1 Q2
2I
I
vi
VCC
Q1
Q2
VDD
Q Q
2I
I
vo
vo
Rin
vi
VBIAS vi
12
vo
Rin
I
Rin
VEE (a)
VSS (c)
VEE
Figure 8.48 (a) A CC–CB amplifier. (b) Another version of the CC–CB circuit with Q2 implemented using
a pnp transistor. (c) The MOSFET version of the circuit in (a).
dc voltage at the collector of Q2. Both issues are usually looked after in the larger circuit of which the CC–CB amplifier is a part.
An interesting version of the CC–CB configuration is shown in Fig. 8.48(b). Here the CB stage is implemented with a pnp transistor. Although only one current source is now needed, observe that we also need to establish an appropriate bias voltage at the base of Q2 . This circuit is part of the internal circuit of the popular 741 op amp, which will be studied in Chapter 13.
The MOSFET version of the circuit in Fig. 8.48(a) is the CD–CG amplifier shown in Fig. 8.48(c).
Example 8.8
(b)
For the CC–CB amplifiers in Fig. 8.48(a) and (b), find Rin, vo/vi, and vo/vsig when each amplifier is fed with asignalsourcehavingaresistanceRsig,andaloadresistanceRL isconnectedattheoutput.Forsimplicity, neglect ro.
Solution
The analysis of both circuits is illustrated in Fig. 8.49. Observe that both amplifiers have the same Rin and vo/vi. The overall voltage gain vo/vsig can be found as
vo = Rin α2RL vsig Rin +Rsig 2re
574
Chapter 8 Building Blocks of Integrated-Circuit Amplifiers
Example 8.8 continued
RL
2i 2L a v v = a R v 2r o2ri
Q2 re
Rsigve e
i
Q1
re
vsig
vi 2re Rin = (b11)(2re)
(a)
vi
Q1
Rsig
re
re
Q2 a2vi
2 r e
(b)
vsig
Rin = (b11)(2re)
vi2re
RL
v = a R v
2L
o 2r i e
Figure 8.49 Circuits for Example 8.8.
EXERCISES
8.31 For the amplifiers in Example 8.8 find Rin, vo/vi, and vo/vsig for the case I = 1 mA, β = 100. RL =Rsig =5k.
Ans. 5.05 k; 100 V/V; 50 V/V
D8.32 (a) Neglecting ro1 and the body effect, show that the voltage gain vo/vi of the CD–CG amplifier shown earlier in Fig. 8.48(c) is given by
vo = IRL v i VOV
whereRL isaloadresistanceconnectedattheoutputandVOV istheoverdrivevoltageatwhicheach of Q1 and Q2 is operating.
(b) For I =0.1mA and RL =20k, find W/L for each of Q1 and Q2 to obtain a gain of 10V/V. Assumekn′ =200μA/V2.
Summary 575
Ans. (b) W/L = 25
Summary
Integrated-circuit fabrication technology offers the circuit designer many exciting opportunities, the most important of which is the large number of inexpensive small-area MOS transistors. An overriding concern for IC designers, however, is the minimization of chip area or “silicon real estate.” As a result, large-valued resistors and capacitors are virtually absent.
Biasing in integrated circuits utilizes current sources. As well, current sources are used as load devices. Typically an accurate and stable reference current is generated and then replicated to provide bias currents for the various amplifier stages on the chip. The heart of the current-steering circuitry utilized to perform this function is the current mirror.
The MOS current mirror has a current transfer ratio of (W/L) /(W/L) . For a bipolar mirror, the ratio is I /I .
a MOSFET, A0 is inversely proportional to ID (see Eq. 8.46).
Simple current-source loads reduce the gain realized in the basic gain cell because of their finite output resistance (usually comparable to the value of ro of the amplifying transistor).
To raise the output resistance of the CS or CE transistor, we stack a CG or CB transistor on top. This is cascoding.
The CG and CB amplifiers act as current buffers. They have a short-circuit current gain of unity or, equivalently, a short-circuit transconductance equal to
gm of the transistor. For the CG: Rin = ro + RL and gm ro
R =R+r+grR.FortheCB:R =r ro+RL out s o mos in e R
21 S2S1 ro+L
Bipolar mirrors suffer from the finite β, which reduces the accuracy of the current transfer ratio.
Both bipolar and MOS mirrors of the basic type have a finite output resistance equal to ro of the output device. Also, for proper operation, a voltage of at least 0.3 V is required across the output transistor of a simple bipolar mirror (V for the MOS case).
OV
The basic gain cell of IC amplifiers is the CS (CE) ampli- fier with a current-source load. For an ideal current-source load (i.e., one with infinite output resistance), the transistor operates in an open-circuit fashion and thus provides the maximum gain possible, Av o = −gm ro = −A0 .
β+1 The CG or CB transistor in the cascode passes the current
TheintrinsicgainA isgivenbyA =V /V foraBJTand
gain as high as 1 A2 can be obtained. 20
Double cascoding is possible in the MOS case only. However, the large number of transistors in the
andRout =(Re∥rπ)+ro +gmro(Re∥rπ).
g v provided by the CS or CE transistor to the output but
m1i increases the resistance at the output from r to g r r
o1 m2o2o1 in the MOS case [gm2 ro2 ro1 ∥ rπ 2 in the bipolar case]. The
maximum output resistance achieved in the bipolar case is β2ro2.
A MOS cascode amplifier operating with an ideal current-source load achieves a gain of g r 2 = A2 .
mo0
To realize the full advantage of cascoding, the load current-source must also be cascoded, in which case a
00AT
A0 =VA/ VOV/2 foraMOSFET.ForaBJT,A0 isconstant
independent of bias current and device dimensions. For
576 Chapter 8 Building Blocks of Integrated-Circuit Amplifiers
stack between the power-supply rails results in the disadvantage of a severely limited output-signal swing. The folded-cascode configuration helps resolve this issue.
A CS amplifier with a resistance Rs in its source lead has an
output resistance Ro ≃ 1 + gm Rs ro . The corresponding
formula for the BJT case is Ro = 1+gm Re ∥rπ ro.
Cascoding can be applied to current mirrors to increase
their output resistances. An alternative that also solves the
β problem in the bipolar case is the Wilson circuit. The
The Widlar current source provides an area-efficient way to implement a low-valued constant-current source that also has a high output resistance.
Preceding the CE (CS) transistor with an emitter follower (a source follower) results in increased input resistance in the BJT case and wider bandwidth in both the BJT and MOS cases.
Preceding the CB (CG) transistor with an emitter follower (a source follower) solves the low-input-resistance problem of the CB and CG configurations.
The Darlington configuration results in an equivalent BJT with a current gain approaching β2.
assume that the nominal value of the output current is obtained at VO ≃ VGS . It is further required that the circuit operate for VO in the range of 0.3 V to VDD and that the change in IO over this range be limited to 10% of the nominal value of IO. Find the required value of R and the device dimensions. For the fabrication-process technology utilized, μnCox = 400 μA/V2, VA′ = 10 V/μm, and Vt = 0.5 V.
D 8.3 Sketch the p-channel counterpart of the current-source
circuit of Fig. 8.1. Note that while the circuit of Fig. 8.1 should
MOS Wilson mirror has an output resistance of gmro ro, and the BJT version has an output resistance of 1 βr .
2o Both the cascode and Wilson mirrors require at least 1 V
or so for proper operation.
PROBLEMS
Computer Simulation Problems
Problems identified by the multisim/PSpice icon are intended to demonstrate the value of using SPICE simulation to verify hand analysis and design, and to investigate important issues such as allowable signal swing and amplifier nonlinear distortion. Instructions to assist in setting up PSpice and Multism simulations for all the indicated problems can be found in the corresponding files on the website. Note that if a particular parameter value is not specified in the problem statement, you are to make a reasonable assumption.
Section 8.2: IC Biasing—Current Sources, Current Mirrors, and Current-Steering Circuits
D 8.1 For VDD = 1.3 V and using IREF = 100 μA, it is required to design the circuit of Fig. 8.1 to obtain an output current whose nominal value is 100 μA. Find R if Q1 and Q2 are matched with channel lengths of 0.5 μm, channel widths of 5μm, Vt = 0.4V, and kn′ = 500μA/V2. What is the lowest possible value of VO? Assuming that for this process technology the Early voltage VA′ = 5 V/μm, find the output resistance of the current source. Also, find the change in output current resulting from a +0.5-V change in VO .
D 8.2 Using VDD = 1.8 V and a pair of matched MOSFETs, design the current-source circuit of Fig. 8.1 to provide an output current of 150-μA nominal value. To simplify matters,
more appropriately be called a current sink, the corresponding
PMOS circuit is a current source. Let V = 1.3 V, V = DD t
0.4 V, Q1 and Q2 be matched, and μp Cox = 80 μA/V2 . Find the device W/L ratios and the value of the resistor that sets the value of IREF so that a nominally 80-μA output current is obtained. The current source is required to operate for VO as high as 1.1 V. Neglect channel-length modulation.
8.4 Consider the current-mirror circuit of Fig. 8.2 with two transistors having equal channel lengths but with Q2 having a width five times that of Q1. If IREF is 20μA and the transistors are operating at an overdrive voltage of 0.2 V, what IO results? What is the minimum allowable value of VO for proper operation of the current source? If Vt = 0.5 V, at what value of VO will the nominal value of IO be obtained? If VO increases by 1 V, what is the corresponding increase in IO?LetVA=20V.
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
Problems 577 8.5 For the current-steering circuit of Fig. P8.5, find I in outputs. All transistors have V = 0.6 V, k′ = 100 μA/V2,
CHAPTER 8 PROBLEMS
terms of IREF and device W/L ratios. VDD
IREF Q3 Q4
Otp
and L = 1.0 μm but three different widths, namely, 10 μm,
Q1
Figure P8.5
IO
20 μm, and 40 μm. When the diode-connected transistor is supplied from a 100-μA source, how many different output currents are available? Repeat with two of the transistors diode connected and the third used to provide current output. For each possible input-diode combination, give the values of the output currents and of the VSG that results.
8.8 Consider the basic bipolar current mirror of Fig. 8.7 for the case in which Q1 and Q2 are identical devices having IS =10−17A.
(a) Assuming the transistor β is very high, find the range of VBE and IO corresponding to IREF increasing from 10 μA to 10 mA. Assume that Q2 remains in the active mode, and neglect the Early effect.
(b) Find the range of IO corresponding to IREF in the range of 10 μA to 10 mA, taking into account the finite β. Assume that β remains constant at 100 over the current range0.1mAto5mAbutthatatIC ≃10mAandatIC ≃ 10 μA, β = 50. Specify IO corresponding to IREF = 10 μA, 0.1 mA, 1 mA, and 10 mA. Note that β variation with cur- rent causes the current transfer ratio to vary with current.
8.9 Consider the basic BJT current mirror of Fig. 8.7 for the caseinwhichQ2 hasmtimestheareaofQ1.Showthatthecur- rent transfer ratio is given by Eq. (8.19). If β is specified to be a minimum of 80, what is the largest current transfer ratio pos- sible if the error introduced by the finite β is limited to 10%?
8.10 Give the circuit for the pnp version of the basic current mirror of Fig. 8.7. If β of the pnp transistor is 50, what is the current gain (or transfer ratio) IO /IREF for the case of identical transistors, neglecting the Early effect?
8.11 Consider the basic BJT current mirror of Fig. 8.7 when Q1 and Q2 are matched and IREF = 1 mA. Neglecting the effect of finite β, find the change in IO, both as an absolute value and as a percentage, corresponding to VO changing from 1 V to 10 V. The Early voltage is 90 V.
Q2
D 8.6 The current-steering circuit of Fig. P8.6 is fabricated in
a CMOS technology for which μnCox = 400 μA/V2, μpCox =
100μA/V2, V =0.5V V =−0.5V, V′ = 5V/μm, and tn tp An
|V′ | = 5 V/μm. If all devices have L = 0.5 μm, design the Ap
circuit so that IREF =20μA, I2 =100μA, I3 =I4 = 40μA, and I5 = 80 μA. Use the minimum possible device widths needed to achieve proper operation of the current source Q2 for voltages at its drain as high as +0.8 V and proper operation of the current sink Q5 with voltages at its drain as low as –0.8 V. Specify the widths of all devices and the value of R. Find the output resistance of the current source Q2 and the output resistance of the current sink Q5.
1.0 V
Q1 Q2 Q3 I3
IREF R
Figure P8.6
I2
I4
1.0 V
I5 Q5
Q4
*8.7 A PMOS current mirror consists of three PMOS transistors, one diode connected and two used as current
output current IO = 1 mA at VO = 1 V. What values of IREF and R are needed? What is the maximum allowed value of VO while the current source continues to operate properly? What change occurs in IO corresponding to VO changing from the
D8.12 Thecurrent-sourcecircuitofFig.P8.12utilizesapair of matched pnp transistors having I = 10−15A, β = 50, and
S
VA = 50 V. It is required to design the circuit to provide an
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
578 Chapter 8 VCC 3 V
Q1
IREF R
Figure P8.12
Building Blocks of Integrated-Circuit Amplifiers
Q2
IO
8.14 For the circuit in Fig. P8.14, let V = 0.7 V and BE
β=∞.FindI,V1,V2,V3,V4,andV5 for(a)R=10k and (b) R = 100 k.
+ 2.7 V
VO
CHAPTER 8 PROBLEMS
maximum positive value to –5 V? Hint: Adapt Eq. (8.21) for
this case as:
⎡3−V−V⎤ 1+ O EB
I=I⎢ |VA|⎥ O REF⎣ 1+2 ⎦
β
8.13 Find the voltages at all nodes and the currents through
all branches in the circuit of Fig. P8.13. Assume V = 0.7 V – 2.7 V
BE
and β = ∞. Figure P8.14 10 V 5 V
Figure P8.13
R4 5 k
5 V
R3 3.6 k
R5 10 k R2 8 k
R1 20 k
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CHAPTER 8 PROBLEMS
D 8.15 Using the ideas embodied in Fig. 8.10, design a
multiple-mirror circuit using power supplies of ±5 V to create
source currents of 0.2 mA, 0.4 mA, and 0.8 mA and sink
Problems 579 to obtain a short-circuit current gain of 4, an input resistance
of 500 , and an output resistance of 20 k.
8.19 Figure P8.19 shows an amplifier utilizing a current
mirrorQ2–Q3.HereQ1 isacommon-sourceamplifierfedwith
v = V + v , where V is the gate-to-source dc bias voltage IGSi GS
of Q1 and vi is a small signal to be amplified. Find the signal component of the output voltage v O and hence the small-signal voltage gain v o /v i . Also, find the small-signal resistance of the diode-connected transistor Q2 in terms of gm2, and hence the total resistance between the drain of Q1 and ground. What is the voltage gain of the CS amplifier Q1? Neglect all ro’s.
VDD
currents of 0.5 mA, 1 mA, and 2 mA. Assume that the BJTs
have V ≃ 0.7 V and large β. What is the total power BE
dissipated in your circuit?
*8.16 The circuit shown in Fig. P8.16 is known as a current
conveyor. YX
Q2 Q1
Z
Q Q3 Q 45
VEE
Figure P8.16
(a) Assuming that Y is connected to a voltage V , a current I is forced into X, and terminal Z is connected to a voltage that keeps Q5 in the active region, show that a current equal to I flows through terminal Y, that a voltage equal to V appears at terminal X, and that a current equal to I flows through terminal Z. Assume β to be large; corresponding transistors are matched, and all transistors are operating in the active region.
(b) With Y connected to ground, show that a virtual ground appears at X. Now, if X is connected to a +5-V supply through a 10-k resistor, what current flows through Z?
8.17 TheMOSFETsinthecurrentmirrorofFig.8.12(a)have equal channel lengths of 0.5 μm, W1 = 10 μm, W2 = 50 μm, μn Cox = 500 μA/V2 , and VA′ = 10 V/μm. If the input bias current is 100 μA, find Rin, Ais, and Ro.
D 8.18 The MOSFETs in the current mirror of Fig. 8.12(a) have equal channel lengths, μn Cox = 400 μA/V2 and VA′ = 20 V/μm. If the input bias current is 200 μA, find W1 , W2 , and L
Q3 W3 vO
W2Q2 LL
vI Q1 RL
Figure P8.19
*8.20 Figure P8.20 shows a current-mirror circuit prepared for small-signal analysis. Replace the BJTs with their hybrid- π models and find expressions for Rin, io/ii, and Ro, where io is the output short-circuit current. Assume ro ≫ rπ .
ii Rin
Q1
Figure P8.20
i Ro o
Q2
8.21 It is required to find the incremental (i.e., small-signal) resistance of each of the diode-connected transistors shown in
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580 Chapter 8 Building Blocks of Integrated-Circuit Amplifiers
Fig. P8.21. Assume that the dc bias current I = 0.1 mA. For the MOSFET, let μnCox = 200 μA/V2 and W/L = 10. Neglect ro for both devices.
8.26 Consider the CE amplifiers of Fig. 8.13(b) for the case ofI=0.5mA,β=100,andVA =100V.FindRin,Avo,andRo. If it is required to raise Rin by a factor of 5 by changing I, what value of I is required, assuming that β remains unchanged? What are the new values of Avo and Ro? If the amplifier is fed with a signal source having Rsig = 5 k and is connected to a load of 100-k resistance, find the overall voltage gain,
vo/vsig.
8.27 FindtheintrinsicgainofanNMOStransistorfabricated in a process for which kn′ = 400 μA/V2 and VA′ = 10 V μm. The transistor has a 0.5-μm channel length and is operated at VOV =0.2V.Ifa2-mA/Vtransconductanceisrequired,what must ID and W be?
8.28 An NMOS transistor fabricated in a certain process is found to have an intrinsic gain of 50 V/V when operated at an ID of 100 μA. Find the intrinsic gain for ID = 25 μA and ID = 400 μA. For each of these currents, find the factor by which gm changes from its value at ID = 100 μA.
D 8.29 Consider an NMOS transistor fabricated in a 0.18-μm technology for which kn′ = 400 μA/V2 and VA′ = 5 V/μm. It is required to obtain an intrinsic gain of 20 V/V and a gm of 2 mA/V. Using VOV = 0.2 V, find the required values of L, W/L, and the bias current I.
D 8.30 Sketch the circuit for a current-source-loaded CS
amplifier that uses a PMOS transistor for the amplifying
I
I
CHAPTER 8 PROBLEMS
(a) (b) Figure P8.21
8.22 For the base-current-compensated mirror of Fig. 8.11, let the three transistors be matched and specified to have a collector current of 1 mA at VBE = 0.7 V. For IREF of 100 μA and assuming β = 100, what will the voltage at node x be? If IREF is increased to 1 mA, what is the change in Vx ? What is the value of IO obtained with VO = Vx in both cases? Give the percentage difference between the actual and ideal value of IO. What is the lowest voltage at the output for which proper current-source operation is maintained?
D 8.23 Extend the current-mirror circuit of Fig. 8.11 to n outputs. What is the resulting current transfer ratio from the input to each output, IO /IREF ? If the deviation from unity is to be kept at 0.2% or less, what is the maximum possible number of outputs for BJTs with β = 150?
*8.24 Forthebase-current-compensatedmirrorofFig.8.11, show that the incremental input resistance (seen by the reference current source) is approximately 2VT /IREF . Evaluate Rin for IREF = 100 μA. (Hint: Q3 is operating at a current IE3 = 2IC/β, where IC is the operating current of each of Q1 and Q2. Replace each transistor with its T model and neglect r0 .)
Section 8.3: The Basic Gain Cell
8.25 Find gm, rπ, ro, and A0 for the CE amplifier of Fig. 8.13(b) when operated at I = 10 μA, 100 μA, and 1 mA. Assume β = 100 and remains constant as I is varied, and that VA = 10 V. Present your results in a table.
device. Assume the availability of a single +1.8-V dc
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
supply. If the transistor is operated with V = 0.2 V, OV
what is the highest instantaneous voltage allowed at the drain?
8.31 AnNMOStransistoroperatedwithanoverdrivevoltage of 0.25 V is required to have a gm equal to that of an npn transistor operated at IC = 0.1 mA. What must ID be? What value of gm is realized?
8.32 For an NMOS transistor with L = 1 μm fabricated in the 0.5-μm process specified in Table J.1 in Appendix J, find gm, ro, and A0 if the device is operated with VOV = 0.5 V and ID = 100 μA. Also, find the required device width W.
8.33 For an NMOS transistor with L = 0.3 μm fabricated in the 0.18-μm process specified in Table J.1 in Appendix J, find gm, ro, and A0 obtained when the device is operated at ID =100μAwithVOV =0.2V.Also,findW.
CHAPTER 8 PROBLEMS
8.34 Fill in the table below. For the BJT, let β = 100 and VA = 100 V. For the MOSFET, let μnCox = 200 μA/ V2, W/L=40,andVA =10V.
Problems 581 current-source-loaded CS amplifier for operation at I =
50 μA with VOV = 0.2 V. The amplifier is to have an open-circuit voltage gain of −100 V/V. Assume that the current-source load is ideal. Specify L and W/L.
D 8.41 The circuit in Fig. 8.15(a) is fabricated in a 0.18-μm
Bias Current
=20 V/μm, Vtn = −Vtp = 0.5 V, and VDD = 2.5 V. The two transistors have L=0.5μmandaretobeoperatedatID =100μAand|VOV|= 0.3 V. Find the required values of VG , (W/L)1 , (W/L)2 , and Av .
BJT Cell
MOSFET Cell
D8.40 ThecircuitinFig.8.15(a)isfabricatedinaprocessfor
whichμ C =2μ C =200 μA/V2,V′ =V′ n ox p ox An Ap
8.35 A CS amplifier utilizes an NMOS transistor with
L = 0.54 μm and W/L = 8. It was fabricated in a 0.18-μm
CMOS process for which μ C = 400 μA/V2 and V′ = n ox A
5 V/μm. What is the bias current of the transistor for which A =18V/V?
0
8.36 A CS amplifier utilizes an NMOS transistor with L =
0.36 μm and W/L = 8. It was fabricated in a 0.18-μm CMOS
process for which μn Cox = 400 μA/V2 and VA′ = 5 V/μm.
Find the values of g and A obtained at I = 25 μA, 250 μA, m0D
and 2.5 mA.
D 8.37 An NMOS transistor is fabricated in the 0.18-μm pro- cess whose parameters are given in Table J.1 in Appendix J. The device has a channel length twice the minimum and is operated at VOV = 0.25 V and ID = 10 μA.
(a) What values of gm, ro, and A0 are obtained?
(b) If ID is increased to 100 μA, what do VOV , gm, ro, and A0
become?
(c) If the device is redesigned with a new value of W so that
itoperatesatVOV =0.25VforID =100μA,whatdogm,
ro, and A0 become?
(d) If the redesigned device in (c) is operated at 10 μA, find
VOV , gm, ro, and A0.
(e) Which designs and operating conditions produce the
lowest and highest values of A0? What are these values? In each of these two cases, if W/L is held at the same value but L is made 10 times larger, what gains result?
D8.38 FindA0 foranNMOStransistorfabricatedinaCMOS process for which kn′ = 400 μA/V2 and VA′ = 6 V/μm. The transistor has a 0.5-μm channel length and is operated with an overdrive voltage of 0.15 V. What must W be for the NMOS transistor to operate at ID = 100 μA? Also, find the values of gm and ro.
D 8.39 Using a CMOS technology for which kn′ = 200 μA/V2 and VA′ = 20 V/μm, design a
CMOS technology for which μ C = 400 μA/V2 , μ C = n ox p ox
100μA/V2, V = −V = 0.5V, V′ = 5V/μm, V′ = tn tp An Ap
5 V/μm, and VDD = 1.8 V. It is required to design the circuit to obtain a voltage gain A = −40 V/V. Use devices of
v
equal length L operating at I = 100 μA and VOV = 0.25 V.
Determine the required values of VG, L, (W/L)1, and (W/L)2.
8.42 Figure P8.42 shows an IC MOS amplifier formed
by cascading two common-source stages. Assuming that
V = V and that the biasing current sources have output An Ap
resistances equal to those of Q1 and Q2 , find an expression for the overall voltage gain in terms of gm and ro of Q1 and Q2. If Q1 and Q2 are to be operated at equal overdrive voltages, |VOV |, find the required value of |VOV | if |VA| = 5 V and the gain required is 400 V/V.
Figure P8.42
*8.43 The NMOS transistor in the circuit of Fig. P8.43 has Vt =0.5V,kn′W/L=2mA/V2,andVA =20V.
(a)
Neglecting the dc current in the feedback network and the effect of ro, find VGS. Then find the dc current in the feedback network and VDS . Verify that you were justified in neglecting the current in the feedback network when you found VGS .
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582 Chapter 8
Building Blocks of Integrated-Circuit Amplifiers
vi Rin
**8.48 The MOSFETs in the circuit of Fig. P8.48 are matched, having k′ (W/L) = k′ (W/L) = 1 mA/V2 and V =
3 M
2 M
200 A
vo
(b) What are the extreme values of vO for which Q1 and Q2 just remain in saturation?
(c) What is the large-signal voltage gain?
(d) FindtheslopeofthetransfercharacteristicatvO =VDD/2.
(e) For operation as a small-signal amplifier around a bias
point at vO = VDD/2, find the small-signal voltage gain and output resistance.
n1p2 t 0.5 V. The resistance R = 1 M.
CHAPTER 8 PROBLEMS
Figure P8.43
(a) ForGandDopen,whatarethedraincurrentsID1 andID2? (b) For ro = ∞, what is the voltage gain of the amplifier from G to D? (Hint: Replace the transistors with their
small-signal models.)
(c) For finite r (V = 20 V), what is the voltage gain from
oA
G to D and the input resistance at G?
(d) IfGisdriven(throughalargecouplingcapacitor)froma
(b) Find the small-signal voltage gain, vo/vi. What is the peak of the largest output sine-wave signal that is possible while the NMOS transistor remains in saturation? What is the corresponding input signal?
(c) Find the small-signal input resistance Rin .
D 8.44 Consider the CMOS amplifier of Fig. 8.16(a) when
fabricated with a process for which k′ = 4k′ = 400 μA/V2, n p
Vt =0.5V,and VA =5V.FindIREF and(W/L)1 toobtaina voltage gain of –40 V/V and an output resistance of 100 k. Recall that Q2 and Q3 are matched. If Q2 and Q3 are to be operated at the same overdrive voltage as Q1 , what must their W/L ratios be?
8.45 Consider the CMOS amplifier analyzed in Example 8.4. IfvI consistsofadcbiascomponentonwhichissuperimposed a sinusoidal signal, find the value of the dc component that will result in the maximum possible signal swing at the output with almost-linear operation. What is the amplitude of the output sinusoid resulting? (Note: In practice, the amplifier would have a feedback circuit that caused it to operate at a point near the middle of its linear region.)
8.46 The power supply of the CMOS amplifier analyzed in Example 8.4 is increased to 5 V. What will the extent of the linear region at the output become?
**8.47 Consider the circuit shown in Fig. 8.16(a), using a
source vsig having a resistance of 20 k, find the voltage gainv/v .
d sig
(e) For what range of output signals do Q1 and Q2 remain in
the saturation region?
1.0 V
Q2 R
GD
Q1
1.0 V Figure P8.48
8.49 Transistor Q1 in the circuit of Fig. P8.49 is operating as
a CE amplifier with an active load provided by transistor Q2 ,
which is the output transistor in a current mirror formed by
3.3-V supply and transistors for which Vt = 0.8 V and L =
shown.)
(a) Neglecting the finite base currents of Q2 and Q3 and
assuming that their VBE ≃ 0.7 V and that Q2 has five times
the area of Q , find the value of I.
3
(b) If Q1 and Q2 are specified to have VA = 30 V, find ro1 and ro2 and hence the total resistance at the collector of Q1 .
1μm.ForQ ,k′ =100μA/V2,V =100V,andW=20μm.
1nA
For Q2 and Q3, kp′ = 50μA/V2 and VA = 50V. For Q2,
W = 40 μm. For Q3, W = 10 μm.
(a) If Q1 is to be biased at 100 μA, find IREF . For simplicity,
Q and Q . (Note that the biasing arrangement for Q is not 2 3 1
ignore the effect of VA.
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CHAPTER 8 PROBLEMS
(c) Find rπ 1 and gm1 assuming that β1 = 50. (d) Find Rin, Av, and Ro.
Problems 583 what percentage does the current gain change? Can you see
the effectiveness of the CG as a current buffer?
D8.53 ItisrequiredtodesignthecurrentsourceinFig.P8.53 to deliver a current of 0.2 mA with an output resistance of 500 k. The transistor has VA = 20 V and Vt = 0.5 V. Design for VOV =0.2VandspecifyRs andVBIAS.
vi 3 V
46 k
Q3
Figure P8.49
VCC 3 V
Q1
vo
Q2
VBIAS
Figure P8.53
IO
Rs
I
D 8.50 It is required to design the CMOS amplifier of Fig. 8.16(a) utilizing a 0.18-μm process for which k ′ =
D 8.54 Figure P8.54 shows a current source realized using a
current mirror with two matched transistors Q1 and Q2. Two
equal resistances R are inserted in the source leads to increase s
the output resistance of the current source. If Q is operating at 2
gm = 1 mA/V and has VA = 10 V, and if the maximum allowed dc voltage drop across Rs is 0.3 V, what is the maximum avail- able output resistance of the current source? Assume that the voltage at the common-gate node is approximately constant.
100 A
Rout Q1 Q2
Rs Rs
Figure P8.54
8.55 In the common-gate amplifier circuit of Fig. P8.55, Q2 and Q3 are matched. kn′ (W/L)n = kp′ (W/L)p = 4 mA/V2 , and all transistors have |Vt| = 0.8 V and |VA| = 20 V.
n 387μA/V2,k′ =86μA/V2,V =−V =0.5V,V =1.8V,
must be able to swing to within approximately 0.2 V of the power-supply rails (i.e., from 0.2 V to 1.6 V), and the voltage gain must be at least 10 V/V. Design for a dc bias current of 50 μA, and use devices with the same channel length. If the channel length is an integer multiple of the minimum 0.18 μm, what channel length is needed and what W/L ratios are required? If it is required to raise the gain by a factor of 2, what channel length would be required, and by what factor does the total gate area of the circuit increase?
Section 8.4: The CG and CB Amplifiers
8.51 A CG amplifier operating with gm = 2 mA/V and ro =20kisfedwithasignalsourcehavingRs =1kandis loadedinaresistanceRL =20k.FindRin,Rout,andvo/vsig.
8.52 A CG amplifier operating with gm = 2 mA/V and ro = 20 k is fed with a signal source having a Norton equivalent composed of a current signal isig and a source resistance Rs = 20 k. The amplifier is loaded in a resistance RL = 20 k. Find Rin and io /isig , where io is the current through the load RL. If RL increases by a factor of 10, by
′ p ′ tn tp DD
VAn = 5 V/μm, and VAp = −6 V/μm. The output voltage
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
584 Chapter 8
Building Blocks of Integrated-Circuit Amplifiers
Q3
100 A
Figure P8.55
3.3 V
VBIAS
50 vi
vsig Rin
Q2
Q1
v RL o Rout
it to the collector and supplies the output collector current at a high output resistance. Figure P8.59 shows a CB amplifier fed with a signal current isig having a source resistance Rsig = 10k.TheBJTisspecifiedtohaveβ=100andVA =50V. (Note that the bias arrangement is not shown.) The output at the collector is represented by its Norton equivalent circuit. Find the value of the current gain k and the output resistance Rout . Note that k is the short-circuit current gain and should be evaluated using the T model of the transistor with the collector short-circuited to ground.
CHAPTER 8 PROBLEMS
0.1 mA
C
Rsig = 10 k
8.60 For the constant-current source circuit shown in Fig. P8.60, find the collector current I and the output resistance. The BJT is specified to have β = 100, VBE = 0.7 V, and VA = 100 V. If the collector voltage undergoes a change of 10 V while the BJT remains in the active mode, what is the corresponding change in collector current?
C
Rout
The signal vsig is a small sinusoidal signal with no dc component.
(a) Neglecting the effect of VA, find the dc drain current of Q1 and the required value of VBIAS.
(b) Find the values of gm1 and ro for all transistors.
(c) Find the value of Rin.
(d) Find the value of Rout.
(e) Calculate the voltage gains vo/vi and vo/vsig.
(f) How large can vsig be (peak-to-peak) while maintaining saturation-mode operation for Q1 and Q2?
8.56 For the CB amplifier, use Eq. (8.63) to explore the variation of the input resistance Rin with the load resistance RL . Specifically, find Rin as a multiple of re for RL /ro = 0, 1, 10, 100, 1000, and ∞. Let β = 100. Present your results in tabular form.
8.57 What value of load resistance RL causes the input resistance of the CB amplifier to be approximately double the value of re?
8.58 Show that for the CB amplifier, Rout ≃1+ β(Re/re)
ro β+1+(Re/re)
Generate a table for Rout as a multiple of ro versus Re as a multiple of re with entries for Re = 0, re, 2re, 10re, (β/2)re, β re, and 1000re. Let β = 100.
8.59 Asmentionedinthetext,theCBamplifierfunctionsasa current buffer. That is, when fed with a current signal, it passes
kisig
isig
Figure P8.59
5V
Figure P8.60
I
4.3 k
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
CHAPTER 8 PROBLEMS
8.61 Find the value of the resistance R , which, when e
connected in the emitter lead of a CE BJT amplifier, raises the output resistance by a factor of (a) 5, (b) 10, and (c) 50. What is the maximum possible factor by which the output resistance can be raised, and at what value of Re is it achieved? Assume theBJThasβ=100andisbiasedatIC =0.5mA.
Section 8.5: The Cascode Amplifier
D8.62 InaMOScascodeamplifier,thecascodetransistoris required to raise the output resistance by a factor of 50. If the transistor is operated at VOV = 0.2 V, what must its VA be? If the process technology specifies VA′ as 5 V/μm, what channel length must the transistor have?
D8.63 ForacascodecurrentsourcesuchasthatinFig.8.32,
show that if the two transistors are identical, the current I
Now consider the case of a 0.18-μm technology for which ′
VA = 5 V/μm and let the transistors be operated at
VOV = 0.2 V. Find the figure-of-merit IRo for the three cases of L equal to the minimum channel length, twice the minimum, and three times the minimum. Complete the entries of the table at the bottom of the page. Give W/L and the area 2WL in terms of n, where n is the value of W/L for the case I = 0.01 mA. In the table, Av denotes the gain obtained in a cascode amplifier such as that in Fig. 8.33 that utilizes our current source as load and which has the same values of gm and Ro as the current-source transistors.
(a) For each current value, what is price paid for the increase in Ro and Av obtained as L is increased?
(b) For each value of L, what advantage is obtained as I is increased, and what is the price paid? (Hint: We will see in Chapter 10 that the amplifier bandwidth increases with gm .)
(c) Contrast the performance obtained from the circuit with the largest area with that obtained from the circuit with the smallest area.
D 8.65 Design the cascode amplifier of Fig. 8.30(a) to obtain gm1 = 2 mA/V and Ro = 200 k. Use a 0.18-μm technology for which Vtn = 0.5 V, VA′ = 5 V/μm, and kn′ = 400 μA/V2. Determine L, W/L, VG2, and I. Use identical transistors operated at VOV = 0.25 V, and design for the maximum possible negative signal swing at the output. What is the value of the minimum permitted output voltage?
8.66 The cascode amplifier of Fig. 8.33 is operated at a
supplied by the current source and the output resistance R
2 o
are related by IR =2 V / V . Now consider the case of o A OV
transistors that have VA = 4 V and are operated at VOV of
0.2 V. Also, let μpCox = 100 μA/V2. Find the W/L ratios
required and the output resistance realized for the two cases:
(a) I =0.1mA and (b) I =0.5mA. Assume that V for the SD
two devices is the minimum required (i.e., VOV ).
D *8.64 For a cascode current source, such as that in Fig.8.32, show that if the two transistors are identical, the current I supplied by the current source and the output resistance Ro are related by
2 V ′ 2 A2
IRo= L VOV
= 0.20 V.
Problems 585
current of 0.2 mA with all devices operating at VOV
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
586 Chapter 8 Building Blocks of Integrated-Circuit Amplifiers
All devices have V = 4 V. Find g , the output resistance of A m1
the amplifier, Ron , the output resistance of the current source, Rop , the overall output resistance, Ro , and the voltage gain, Av .
D8.67 Design the CMOS cascode amplifier in Fig.8.33
for the following specifications: gm1 = 1 mA/V and Av =
two circuits shown in Fig. P8.70(b) and (c). The circuit in Fig. P8.70(b) is a CS amplifier in which the channel length has been quadrupled relative to that of the original CS amplifier in Fig. P8.70(a) while the drain bias current has been kept constant.
−280 V/V. Assume that for the available fabrication process,
VA′ = 5 V/μm for both NMOS and PMOS devices and that
μn Cox = 4 μp Cox = 400 μA/V2 . Use the same channel length
II
L for all devices and operate all four devices at V = 0.25 V. OV
Determine the required channel length L, the bias current I,
and the W/L ratio for each of four transistors. Assume that
suitable bias voltages have been chosen, and neglect the Early vi WL effect in determining the W/L ratios.
vo
vo
vi
W4L
CHAPTER 8 PROBLEMS
D 8.68 Design the circuit of Fig. 8.32 to provide an output current of 100 μA. Use VDD = 3.3 V, and assume the PMOS
transistors to have μ C = 60 μA/V2 , V = −0.8 V, and (a) p ox tp
VA = 5 V. The current source is to have the widest possible signalswingatitsoutput.DesignforVOV =0.2V,andspecify the values of the transistor W/L ratios and of VG3 and VG4. What is the highest allowable voltage at the output? What is the value of Ro?
(b)
I
vo
8.69 The cascode transistor can be thought of as providing
a “shield” for the input transistor from the voltage variations VBIAS WL at the output. To quantify this “shielding” property of the
cascode, consider the situation in Fig. P8.69. Here we have
grounded the input terminal (i.e., reduced vi to zero), applied vi asmallchangevx totheoutputnode,anddenotedthevoltage
change that results at the drain of Q1 by vy. By what factor is
vy smallerthanvx?
WL
ix
v Q2 x
vy Q1
(c)
Figure P8.70
Figure P8.69
(a) Show that for this circuit VOV is double that of the original circuit, gm is half that of the original circuit, and vo is
vi
double that of the original circuit.
(b) Compare these values to those of the cascode circuit in
Fig. P8.70(c), which is operating at the same bias current and has the same minimum voltage requirement at the drain as in the circuit of Fig. P8.70(b).
8.71 Consider the cascode amplifier of Fig. 8.33 with the dc
componentattheinputVI =0.6V,VG2 =0.9V,VG3 =0.4V,
V = 0.7 V, and V = 1.3 V. If all devices are matched, G4 DD
that is, kn1 =kn2 =kp3 =kp4, and have equal Vt of 0.4V, what is the overdrive voltage at which the four transistors are operating? What is the allowable voltage range at the output?
*8.70 In this problem we investigate whether, as an alterna- tive to cascoding, we can simply increase the channel length L of the CS MOSFET. Specifically, we wish to compare the
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
8.72 A CMOS cascode amplifier such as that in Fig. 8.34(a) has identical CS and CG transistors that have W/L = 5.4 μm/0.36 μm and biased at I = 0.2 mA. The fabrication process has μnCox = 400 μA/V2, and VA′ = 5 V/μm. At what value of RL does the gain become –100 V/V? What is the voltage gain of the common-source stage?
8.73 The purpose of this problem is to investigate the signal currents and voltages at various points throughout a cascode
amplifier circuit. Knowledge of this signal distribution is very useful in designing the circuit so as to allow for the required signal swings. Figure P8.73 shows a CMOS cascode amplifier with all dc voltages replaced with signal grounds. As well, we have explicitly shown the resistance ro of each of the four transistors. For simplicity, we are assuming that the four transistors have the same gm and ro. The amplifier is fed with a signal vi.
(a) Determine R1, R2, and R3. Assume gmro ≫ 1.
(b) Determinei1,i2,i3,i4,i5,i6,andi7,allintermsofvi.(Hint:
Use the current-divider rule at the drain of Q1.)
(c) Determine v1, v2, and v3, all in terms of vi.
(d) If vi is a 5-mV peak sine wave and gmro = 20, sketch and
clearly label the waveforms of v1, v2, and v3.
D 8.74 Design the double-cascode current source shown in
Fig. P8.74 to provide I = 0.2 mA and the largest possible sig-
nal swing at the output; that is, design for the minimum allow-
able voltage across each transistor. The 0.13-μm CMOS fab-
rication process available has Vt p = −0.4 V, VA′ = −6 V/μm,
and μ C = 100 μA/V2. Use devices with L = 0.4 μm, and p ox
operate at VOV = 0.2 V. Specify VG1, VG2, VG3, and the W/L ratios of the transistors. What is the value of Ro achieved?
VDD = 1.8 V
Problems 587
CHAPTER 8 PROBLEMS
Q4 ro i6 i7
i5
v
3
R1
Q3 ro
i R2vVG1 Q1 42
Q2 ro
VG2 Q2
R VG3 Q3 i3 3
v1 I Figure P8.74
Ro
i1
i2
Q1
ro
vi
Figure P8.73
*8.75 FigureP8.75showsafolded-cascodeCMOSamplifier utilizing a simple current source Q2, supplying a current 2I, and a cascoded current source (Q4, Q5) supplying a current I. Assume, for simplicity, that all transistors have equal parameters gm and ro .
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
588
Chapter 8
Building Blocks of Integrated-Circuit Amplifiers
VDD
(d) Find the overall voltage gain v o /v i and evaluate its value forthecasegm1 =2mA/VandA0 =30.
8.76 Acascodecurrentsourceformedoftwopnptransistors forwhichβ=50andVA =5Vsuppliesacurrentof0.2mA. What is the output resistance?
8.77 Use Eq. (8.88) to show that for a BJT cascode current source utilizing identical pnp transistors and supplying a current I,
VG2
vi
Q2
Q1
Ro2 Ro1
Rin3
Q3
VG3
V o3 A
R
vo Ro4
Ro5
IRo = V V +(1/β)
TA
CHAPTER 8 PROBLEMS
= 5 V and β=50.NowfindRo forthecasesofI=0.1,0.5,and1.0mA.
VG4 VG5
Q4 Q5
Ro
8.78 ConsidertheBJTcascodeamplifierofFig.8.38forthe case all transistors have equal β and ro . Show that the voltage gain Av can be expressed in the form
Evaluate the figure-of-merit IRo for the case VA
V /V 1AT
Av =−2V V +(1/β) TA
Figure P8.75
EvaluateA forthecaseV=5Vandβ=50.Notethat vA
except for the fact that β depends on I as a second-order effect, the gain is independent of the bias current I!
(a) Give approximate expressions for all the resistances indicated.
(b) Find the amplifier output resistance Ro.
(c) Show that the short-circuit transconductance Gm is
8.79 A bipolar cascode amplifier has a current-source load with an output resistance βr . Let β = 50, V = 100 V, and
approximately equal to gm1. Note that the short-circuit transconductance is determined by short-circuiting vo to ground and finding the current that flows through the short
oA I = 0.2 mA. Find the voltage gain Av .
circuit, G v .
D *8.80 Figure P8.80 shows four possible realizations of the
folded cascode amplifier. Assume that the BJTs have β = 100
and that both the BJTs and the MOSFETs have V = 5 V. miA
2I
2I
Q2
Q2
VBIAS
v
Figure P8.80
v
VBIAS
vo
I Q1
I Q1
(a)
vo II
(b)
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
Problems 589
CHAPTER 8 PROBLEMS
2I
vI Q1 Q2
(c)
2I
vI
Q1
Q2
VBIAS
VBIAS
vo II
(d)
vo
Figure P8.80 continued
Let I = 100 μA, and assume that the MOSFETs are operating
VDD
I
Q2
Q1
at V = 0.2 V. Assume the current sources are ideal. For OV
each circuit determine Rin, Ro, and Avo. Comment on your results.
8.81 Inthisproblem,wewillexplorethedifferencebetween
using a BJT as cascode device and a MOSFET as cascode device. Refer to Fig. P8.81. Given the following data, calculate Gm, Ro, and Avo for the circuits (a) and (b): VG2
I=100μA,β=125,μnCox =400μA/V2,W/L=25, VA =1.8V
VDD
I
VB2 Q2
vi Q1
(a)
Figure P8.81
vo
vi
vo
Figure P8.81 continued
(b)
Section 8.6: Current-Mirror Circuits with Improved Performance
8.82 In a particular cascoded current mirror, such as that shown in Fig. 8.39, all transistors have Vt = 0.6 V, μnCox = 160μA/V2, L = 1μm, and VA = 10V. Width W1 =W4 =4μm,andW2 =W3 =40μm.Thereference current IREF is 20 μA. What output current results? What are the voltages at the gates of Q2 and Q3? What is the lowest voltage at the output for which current-source operation is possible? What are the values of gm and
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
590 Chapter 8 Building Blocks of Integrated-Circuit Amplifiers ro of Q2 and Q3? What is the output resistance of the
mirror?
8.83 Findtheoutputresistanceofthedouble-cascodecurrent mirror of Fig. P8.83.
Figure P8.83
8.84 Consider the Wilson current-mirror circuit of Fig. 8.40 when supplied with a reference current IREF of 1mA. What is the change in IO corresponding to a change of +10 V in the voltage at the collector of Q3 ? Give both the absolute value and the percentage change. Let β = 100 and VA = 100 V.
D 8.85 (a) The circuit in Fig. P8.85 is a modified version of the Wilson current mirror. Here the output transistor is “split” into two matched transistors, Q3 and Q4. Find IO1 and IO2 in terms of IREF. Assume all transistors to be matched with current gain β.
(b) Use this idea to design a circuit that generates currents of 0.1 mA, 0.2 mA, and 0.4 mA, using a reference current source of 0.7 mA. What are the actual values of the currents generated for β = 50?
Figure P8.85
D 8.86 Use the pnp version of the Wilson current mirror to design a 0.1-mA current source. The current source is required to operate with the voltage at its output terminal as low as –2.5 V. If the power supplies available are ±2.5 V, what is the highest voltage possible at the output terminal?
*8.87 For the Wilson current mirror of Fig. 8.40, show that theincrementalinputresistanceseenbyIREF isapproximately 2VT/IREF. (Neglect the Early effect in this derivation and assume a signal ground at the output.) Evaluate Rin for IREF = 0.2 mA.
*8.88 Consider the Wilson MOS mirror of Fig. 8.41(a) for the case of all transistors identical, with W/L = 10, μnCox = 400 μA/V2, Vtn =0.5V, and VA =18V. The mirror is fed with IREF = 180 μA.
(a) Obtain an estimate of VOV and VGS at which the three transistors are operating, by neglecting the Early effect.
(b) Noting that Q1 and Q2 are operating at different VDS , obtain an approximate value for the difference in their currents and hence determine IO .
(c) To eliminate the systematic error between IO and IREF caused by the difference in VDS between Q1 and Q2, a diode-connected transistor Q4 can be added to the circuit
CHAPTER 8 PROBLEMS
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
CHAPTER 8 PROBLEMS
as shown in Fig. 8.41(c). What do you estimate IO now
to be?
(d) What is the minimum allowable voltage at the output
node of the mirror?
(e) Convince yourself that Q4 will have no effect on the
output resistance of the mirror. Find Ro.
(f) What is the change in IO (both absolute value and
percentage) that results from VO = 1 V?
8.89 Showthattheincrementalinputresistance(seenbyIREF) for the Wilson MOS mirror of Fig. 8.41(a) is 2/gm . Assume that all three transistors are identical and neglect the Early effect. Also, assume a signal ground at the output. (Hint: Replace all transistors by their T model and remember that Q1 is equivalent to a resistance 1/gm .)
D 8.90 (a) Utilizing a reference current of 200 μA, design a Widlar current source to provide an output current of 20 μA. Assume β to be high.
(b) If β=200 and VA =50V, find the value of the output resistance, and find the change in output current corresponding to a 5-V change in output voltage.
D 8.91 Design three Widlar current sources, each having a 100-μA reference current: one with a current transfer ratio of 0.8, one with a ratio of 0.10, and one with a ratio of 0.01, all assuming high β. For each, find the output resistance, and contrast it with ro of the basic unity-ratio source that is providing the desired current and for which RE = 0. Use β=∞andVA =50V.
D 8.92 (a) For the circuit in Fig. P8.92, assume BJTs with highβ andvBE =0.7Vat1mA.FindthevalueofRthatwill result in IO = 10 μA.
(b) For the design in (a), find Ro assuming β = 100 and VA =40V.
D 8.93 If the pnp transistor in the circuit of Fig. P8.93 is characterized by its exponential relationship with a scale current IS, show that the dc current I is determined by IR = VT ln(I/IS). Assume Q1 and Q2 to be matched and Q3, Q4, and Q5 to be matched. Find the value of R that yields a current I = 200 μA. For the BJT, VEB = 0.7 V atIE =1mA.
Figure P8.93
Section 8.7: Some Useful Transistor Pairings
8.94 Use the source-follower equivalent circuit in Fig. 8.45(b) to show that its output resistance is given by
Ro =ro3∥ro1∥ 1 ≃ 1
gm +gmb gm +gmb
Problems 591
Ro
Q1
Q3
20V/μm,χ=0.2,L=0.5μm,W=20μm,andVt =0.6V is required to provide a dc level shift (between input and output of 0.9 V.) What must the bias current be? Find gm, gmb, ro, Avo, and Ro. Assume that the bias current source has an output resistance equal to ro. Also find the voltage gain when a load resistance of 2 k is connected to the output.
8.96 ThetransistorsinthecircuitofFig.P8.96haveβ=100 andVA =50V.
10 A
8.95 A source follower for which k′ = 200 μA/V2, V′ = IO nA
Q2 R
Figure P8.92
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
592 Chapter 8 Building Blocks of Integrated-Circuit Amplifiers
(a) Find Rin and the overall voltage gain.
(b) What is the effect of increasing the bias currents by a
factor of 10 on Rin , Gv , and the power dissipation? 5V
200 A Rsig 500 k v
(d)
(e)
Noting that RG is connected between the input node where the voltage is vi and the output node where the voltage is Av v i , find Rin and hence the overall voltage gain vo/vsig.
To considerably reduce the effect of RG on Rin and hence on Gv, consider the effect of adding another 10-M resistor in series with the existing one and placing a large bypass capacitor between their joint node and ground. What will Rin and Gv become?
vsig
Rin
Figure P8.96
Q1 o Q2
8.98 The BJTs in the Darlington follower of Fig. P8.98 have β = 100. If the follower is fed with a source having a 100-k resistance and is loaded with 1 k, find the input resistance and the output resistance (excluding the load). Also find the overall voltage gain, both open-circuited and with load. Neglect the Early effect.
Figure P8.98
8.99 For the amplifier in Fig. 8.48(a), let I = 0.5 mA and β = 100, and neglect ro. Assume that a load resistance of 10 k is connected to the output terminal. If the amplifier is fed with a signal vsig having a source resistance Rsig = 10 k, find Gv .
8.100 Consider the CD–CG amplifier of Fig. 8.48(c) for the case gm = 5mA/V, Rsig = 500k, and RL = 10k. Neglecting ro , find Gv .
**8.101 In each of the six circuits in Fig. P8.101, let β = 100, and neglect ro. Calculate the overall voltage gain.
CHAPTER 8 PROBLEMS
200 A
D *8.97 Consider the BiCMOS amplifier shown in Fig.P8.97.TheBJThasVBE =0.7Vandβ=200.The MOSFET has Vt = 1 V and kn = 2 mA/V2. Neglect the Early effect in both devices.
5 V
Q2
3 k C2
RG 10 M
∞
Q1
(a) Consider the dc bias circuit. Neglect the base current in Q2 in determining the current in Q1 . Find the dc bias currents in Q1 and Q2 and show that they are approximately 100 μA and 1 mA, respectively.
(b) Evaluatethesmall-signalparametersofQ1 andQ2 attheir bias points.
(c) Determine the voltage gain Av = v o /v i . For this purpose
you can neglect RG .
500 k C1 vi ∞
vo 1 k
Vsig Figure P8.97
6.8 k
Rin
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
vo
Problems 593
CHAPTER 8 PROBLEMS
vo
vo
vsig
vsig
vsig
(a)
(b)
(c)
vo
vo
vsig
vsig
vo
vsig
(d)
Figure P8.101
(e)
(f)
CHAPTER 9
Differential and Multistage Amplifiers
Introduction 595 9.5 9.1 The MOS Differential Pair 596
The Differential Amplifier with a Current-MirrorLoad 644
9.2 The BJT Differential Pair 614
9.3 Common-Mode Rejection 627
9.4 DC Offset 637
9.6 Multistage Amplifiers 659 Summary 672
Problems 674
IN THIS CHAPTER YOU WILL LEARN
1. The essence of the operation of the MOS and the bipolar differential amplifiers: how they reject common-mode noise or interference and amplify differential signals.
2. The analysis and design of MOS and BJT differential amplifiers.
3. Differential-amplifier circuits of varying complexity; utilizing passive resistive loads,
current-source loads, and cascodes—the building blocks we studied in Chapter 8.
4. An ingenious and highly popular differential-amplifier circuit that utilizes a current-mirror load.
5. The structure, analysis, and design of amplifiers composed of two or more stages in cascade. Two practical examples are studied in detail: a two-stage CMOS op amp and a four-stage bipolar op amp.
Introduction
The differential-pair or differential-amplifier configuration is the most widely used building block in analog integrated-circuit design. For instance, the input stage of every op amp is a differential amplifier. Also, the BJT differential amplifier is the basis of a very-high-speed logic-circuit family, studied in Chapter 15, called emitter-coupled logic (ECL).
Initially invented in the 1940s for use with vacuum tubes, the basic differential-amplifier configuration was subsequently implemented with discrete bipolar transistors. However, it was the advent of integrated circuits that has made the differential pair extremely popular in both bipolar and MOS technologies. There are two reasons why differential amplifiers are so well suited for IC fabrication: First, as we shall shortly see, the performance of the differential pair depends critically on the matching between the two sides of the circuit. Integrated-circuit fabrication is capable of providing matched devices whose parameters track over wide ranges of changes in environmental conditions. Second, by their very nature, differential amplifiers utilize more components (approaching twice as many) than single-ended circuits. Here again, the reader will recall from the discussion in Section 8.1 that a significant advantage of integrated-circuit technology is the availability of large numbers of transistors at relatively low cost.
We assume that the reader is familiar with the basic concept of a differential amplifier as presented in Section 2.1. Nevertheless it is worthwhile to answer the question: Why dif- ferential? Basically, there are two reasons for using differential in preference to single-ended amplifiers. First, differential circuits are much less sensitive to noise and interference than
595
596 Chapter 9
Differential and Multistage Amplifiers
single-ended circuits. To appreciate this point, consider two wires carrying a small differential signal as the voltage difference between the two wires. Now, assume that there is an interference signal that is coupled to the two wires, either capacitively or inductively. As the two wires are physically close together, the interference voltages on the two wires (i.e., between each of the two wires and ground) will be equal. Since, in a differential system, only the difference signal between the two wires is sensed, it will contain no interference component!
The second reason for preferring differential amplifiers is that the differential configuration enables us to bias the amplifier and to couple amplifier stages together without the need for bypass and coupling capacitors such as those utilized in the design of discrete-circuit amplifiers (Section 7.5). This is another reason why differential circuits are ideally suited for IC fabrication where large capacitors are impossible to fabricate economically.
The major topic of this chapter is the differential amplifier in both its MOS and bipolar implementations. As will be seen, the design and analysis of differential amplifiers makes extensive use of the material on single-stage amplifiers presented in Chapters 7 and 8. We will follow the study of differential amplifiers with examples of practical multistage amplifiers, again in both MOS and bipolar technologies.
9.1 The MOS Differential Pair
Figure 9.1 shows the basic MOS differential-pair configuration. It consists of two matched transistors, Q1 and Q2, whose sources are joined together and biased by a constant-current source I. The latter is usually implemented by a MOSFET circuit of the type studied in Sections 8.2 and 8.5. For the time being, we assume that the current source is ideal and that it has infinite output resistance. Although each drain is shown connected to the positive supply through a resistance RD, in most cases active (current-source) loads are employed, as will be seen shortly. For the time being, however, we will explain the essence of the differential-pair operation utilizing simple resistive loads. Whatever type of load is used, it is essential that the MOSFETs not enter the triode region of operation.
VDD
RD
RD
vD1
iD1 iD1
iD2 iD2
vD2
Q1
Q2
vG1
vG2
I
VSS
Figure 9.1 The basic MOS differential-pair configuration.
9.1.1 Operation with a Common-Mode Input Voltage
To see how the differential pair works, consider first the case when equal voltages, VCM , are applied to the two gate terminals. That is, as shown in Fig. 9.2, vG1 = vG2 = VCM . Since VCM is common to the two input terminals, it is called common-mode voltage. Since Q1 and Q2 are matched, the current I will divide equally between the two transistors. Thus, iD1 = iD2 = I/2, and the voltage at the sources, VS , will be
VS =VCM −VGS (9.1) where VGS is the gate-to-source voltage corresponding to a drain current of I/2. Neglecting
channel-length modulation, VGS and I/2 are related by
I = 1 kn′ W (VGS − Vt )2
22L or in terms of the overdrive voltage VOV ,
(9.2)
(9.3) (9.4) (9.5)
(9.6)
9.1 The MOS Differential Pair 597
The voltage at each drain will be
VOV =VGS −Vt
I = 1k′ W V2
2 2 n L OV
VOV = I/kn′(W/L) vD1 = vD2 = VDD − I RD
2
Thus, the difference in voltage between the two drains will be zero.
Now, let us vary the value of the common-mode voltage VCM . We see that, as long as Q1
and Q2 remain in the saturation region, the current I will divide equally between Q1 and Q2 and the voltages at the drains will not change. Thus the differential pair does not respond to (i.e., it rejects) common-mode input signals.
VDD
RD
RD
vVIR I2I2 vVIR
D1 DD 2D
D2 DD 2D
QQ
12
I2 I2
VCM
VGS
VGS
VVV VCM S CM GS
VGS Vt VOV
VIkW tnL
VSS
I
Figure9.2 TheMOSdifferentialpairwithacommon-modeinputvoltageVCM.
598 Chapter 9
Differential and Multistage Amplifiers
An important specification of a differential amplifier is its input common-mode range. ThisistherangeofVCM overwhichthedifferentialpairoperatesproperly.Thehighestvalue of VCM is limited by the requirement that Q1 and Q2 remain in saturation, thus
VCMmax = Vt + VDD − I RD (9.7) 2
ThelowestvalueofVCM isdeterminedbytheneedtoallowforasufficientvoltageacrossthe currentsourceIforittooperateproperly.IfavoltageVCS isneededacrossthecurrentsource, then
VCMmin =−VSS +VCS +Vt +VOV
(9.8)
Example 9.1
For the MOS differential pair with a common-mode voltage VCM applied, as shown in Fig. 9.2, let VDD = VSS = 1.5 V, kn′ (W/L) = 4 mA/V2, Vt = 0.5 V, I = 0.4 mA, and RD = 2.5 k, and neglect channel-length modulation. Assume that the current source I requires a minimum voltage of 0.4 V to operate properly.
(a) Find VOV and VGS for each transistor.
(b) For VCM = 0, find VS, ID1, ID2, VD1, and VD2. (c) Repeat (b) for VCM = +1 V.
(d) Repeat (b) for VCM = − 0.2 V.
(e) What is the highest permitted value of VCM ?
(f) What is the lowest value allowed for VCM ? Solution
(a) With vG1 = vG2 = VCM , we see that VGS1 = VGS2. Now, since the transistors are matched, I will divide equally between the two transistors,
Thus,
which results in and thus,
ID1 = ID2 = I 2
I =1k′(W/L)V2 22n OV
0.4 = 1 ×4V2 2 2 OV
VOV =0.316V
VGS =Vt +VOV =0.5+0.316≃0.82 V
9.1
The MOS Differential Pair 599
2.5 k
1 V
0.82 V
1.5 V
0.2 0.2 mA mA
2.5 k
2.5 k
1 V
1.5 V
0.2 0.2 mA mA
2.5 k
1 V
1 V
Q1 Q2 1 V Q1 Q2 1 V
0.2 0.2 mA mA
0.82 V
0.4 mA
0.82 V
0.2 0.2 0.82 V mA mA
0.82 V
1.5 V
(a)
0.18 V
0.4 mA
1.5 V
(b)
1.5 V
2.5 k
1 V
0.2 V Q1 0.82 V
0.2 mA
0.2 mA
0.2 mA
2.5 k
0.82 V
1 V
0.2 V
Q2 1.02 V
0.2 mA
0.4 mA
1.5 V
(c)
Figure 9.3 Circuits for Example 9.1. Effects of varying VCM on the operation of the differential pair. (b) The analysis for the case VCM = 0 is shown in Fig. 9.3(a) from which we see that
VS =VG −VGS =0−0.82=−0.82V
ID1 =ID2 = I =0.2mA 2
600
Chapter 9 Differential and Multistage Amplifiers
Example 9.1 continued
VD1 = VD2 = VDD − I RD 2
=1.5−0.2×2.5=1V
(c) The analysis for the case VCM = +1 V is shown in Fig. 9.3(b) from which we see that
VS =VG −VGS =1−0.82=+0.18V ID1 =ID2 = I =0.2mA
2
VD1 =VD2 =VDD − I RD =1.5−0.2×2.5=+1V 2
Observe that the transistors remain in the saturation region as assumed. Also observe that ID1, ID2, VD1, and VD2 remain unchanged even though the common-mode voltage VCM changed by 1 V.
(d) The analysis for the case VCM = −0.2 V is shown in Fig. 9.3(c), from which we see that VS =VG −VGS =−0.2−0.82=−1.02V
It follows that the current source I now has a voltage across it of
VCS =−VS − −VSS =−1.02+1.5=0.48V
which is greater than the minimum required value of 0.4 V. Thus, the current source is still operating
properly and delivering a constant current I = 0.4 mA and hence ID1 =ID2 = I =0.2mA
2
VD1 = VD2 = VDD − I RD = +1 V 2
So, here again the differential circuit is not responsive to the change in the common-mode voltage VCM . (e) The highest permitted value of VCM is that which causes Q1 and Q2 to leave saturation and enter the
triode region. Thus,
VCMmax =Vt +VD =0.5+1=+1.5V
(f) The lowest value allowed for VCM is that which reduces the voltage across the current source I to the minimum required of VCS = 0.4 V. Thus,
VCMmin =−VSS +VCS +VGS =−1.5+0.4+0.82=−0.28V
Thus, the input common-mode range is
−0.28V≤VCM ≤+1.5V
9.1 The MOS Differential Pair 601
EXERCISE
9.1 For the amplifier in Example 9.1, find the input common-mode range for the case in which the two drain resistances RD are increased by a factor of 2.
Ans. −0.28 V to 1.0 V
9.1.2 Operation with a Differential Input Voltage
NextweapplyadifferenceordifferentialinputvoltagebygroundingthegateofQ2 (i.e.,setting vG2 = 0) and applying a signal vid to the gate of Q1, as shown in Fig. 9.4. We can see that since vid = vGS1 – vGS2, if vid is positive, vGS1 will be greater than vGS2 and hence iD1 will be greater than iD2 and the difference output voltage (vD2 – vD1) will be positive. On the other hand, when vid is negative, vGS1 will be lower than vGS2, iD1 will be smaller than iD2, and correspondingly v D1 will be higher than v D2 ; in other words, the difference or differential output voltage (vD2 – vD1) will be negative.
From the above, we see that the differential pair responds to difference-mode or differential input signals by providing a corresponding differential output signal between thetwodrains.Atthispoint,itisusefultoinquireaboutthevalueofvid thatcausestheentire bias current I to flow in one of the two transistors. In the positive direction, this happens when vGS1 reaches the value that corresponds to iD1 = I, and vGS2 is reduced to a value equal to the thresholdvoltageVt,atwhichpointvS =−Vt.ThevalueofvGS1 canbefoundfrom
I =
1 W kn′
2L
(vGS1 −Vt)2
VDD
RD
RD
vD1 iD1 QQ
vD2
iD2
vid
vGS1
vGS2
12
vS
I
VSS
Figure 9.4 The MOS differential pair with a differential input signal v i d applied. With vid positive: vGS1 > vGS2, iD1 > iD2, and vD1 < vD2; thus (vD2 – vD1) willbepositive.Withvid negative:vGS1 < vGS2, iD1 < iD2, and vD1 > vD2; thus (vD2 – vD1) will be negative.
602 Chapter 9
Differential and Multistage Amplifiers
as
vGS1 =Vt +√2I/kn′(W/L)
=Vt+ 2VOV (9.9)
whereVOV istheoverdrivevoltagecorrespondingtoadraincurrentofI/2(Eq.9.5).Thus,the value of vid at which the entire bias current I is steered into Q1 is
vidmax =vGS1 +vS √
=Vt+ 2VOV−Vt √
= 2VOV √√
(9.10) 2VOV , iD1 remains equal to I, vGS1 remains equal to (Vt + 2VOV ),
If vid is increased beyond
and v rises correspondingly, thus keeping Q off. In a similar manner we can show that in
S√2
the negative direction, as vid reaches − 2VOV , Q1 turns off and Q2 conducts the entire bias
current I. Thus the current I can be steered from one transistor to the other by varying vid in the range
√√
− 2VOV≤vid≤ 2VOV
which defines the range of differential-mode operation. Finally, observe that we have assumed that Q1 and Q2 remain in saturation even when one of them is conducting the entire current I.
EXERCISE
9.2 FortheMOSdifferentialpairspecifiedinExample9.1find(a)thevalueofvid thatcausesQ1 toconduct the entire current I, and the corresponding values of vD1 and vD2; (b) the value of vid that causes Q2 to conduct the entire current I, and the corresponding values of vD1 and vD2; (c) the corresponding range of the differential output voltage (vD2 – vD1).
Ans. (a)+0.45V,0.5V,1.5V;(b)–0.45V,1.5V,0.5V;(c)+1Vto–1V
To use the differential pair as a linear amplifier, we keep the differential input signal vid small. As a result, the current in one of the transistors (Q1 when vid is positive) will increase by an increment I proportional to v i d , to (I /2 + I ). Simultaneously, the current in the other transistor will decrease by the same amount to become (I/2 – I). A voltage signal –IRD develops at one of the drains and an opposite-polarity signal, IRD , develops at the other drain. Thus the output voltage taken between the two drains will be 2I RD, which is proportional to the differential input signal vid. The small-signal operation of the differential pair will be studied in detail in Section 9.1.4.
9.1.3 Large-Signal Operation
We shall now derive expressions for the drain currents iD1 and iD2 in terms of the input differential signal vid ≡ vG1 – vG2. The derivation assumes that the differential pair is perfectly
Q1 Q2
9.1 The MOS Differential Pair 603
matched and neglects channel-length modulation (λ = 0 or VA = ∞). Thus these expressions do not depend on the details of the circuit to which the drains are connected, and we do not show these connections in Fig. 9.5; we simply assume that the circuit maintains Q1 and Q2 in the saturation region of operation at all times.
To begin with, we express the drain currents of Q1 and Q2 as iD1 = 1kn′ W(vGS1 −Vt)2
2L
iD2 = 1kn′ W(vGS2 −Vt)2
2L
Taking the square roots of both sides of each of Eqs. (9.11) and (9.12), we obtain
(9.11) (9.12)
(9.13)
(9.14)
(9.15)
(9.16)
Figure 9.5 The MOSFET differen- tial pair for the purpose of deriving the transfer characteristics, iD1 and iD2 versusvid =vG1 –vG2.
1W iD1 = kn′
2L
1W iD2 = kn′
(vGS1 −Vt) (vGS2 −Vt)
2L Subtracting Eq. (9.14) from Eq. (9.13) and substituting
results in
vGS1 −vGS2 =vG1 −vG2 =vid 1 W
iD1−iD2= kn′ vid 2L
The constant-current bias imposes the constraint
iD1 + iD2 = I
(9.17) Equations (9.16) and (9.17) are two equations in the two unknowns iD1 and iD2 and can be
solved as follows: Squaring both sides of Eq. (9.16) and substituting for iD1 + iD2 = I gives
2 i D 1 i D 2 = I − 1 k n′ W v 2i d 2L
604 Chapter 9
Differential and Multistage Amplifiers
Substituting for iD2 from Eq. (9.17) as iD2 = I − iD1 and squaring both sides of the resulting equation provides a quadratic equation in iD1 that can be solved to yield
I W v (v /2)2 iD1=±kn′ Iid1−id
2 L 2 I/kn′W L
Now, since the increment in iD1 above the bias value of I/2 must have the same polarity as vid, only the root with the “+” sign in the second term is physically meaningful; thus,
(9.18)
(9.19)
(9.20)
(9.21)
(9.22) to express
(9.23)
(9.24)
I W v (v /2)2 iD1=+kn′ Iid1−id
2 L 2 I/kn′W L
The corresponding value of iD2 is found from iD2 = I − iD1 as
I W v (v /2)2
iD2=−kn′ Iid1−id
2 L 2 I/kn′W
At the bias (quiescent) point, vid = 0, leading to
iD1 = iD2 = I
L
Correspondingly,
where
vGS1 =vGS2 =VGS I=1k′W(V −V)2=1k′WV2
2
22nLGS t 2nLOV
This relationship enables us to replace k′ (W/L) in Eqs. (9.18) and (9.19) with I/V2
iD1 and iD2 in the alternative form I
I vid V 2
OV
I vid V 2
OV
vid/22 V
vid/22 V
iD1 = 2 + I
1 −
n OV
OV
iD2 = 2 −
1 −
These two equations describe the effect of applying a differential input signal vid on the
currents iD1 and iD2. They can be used to obtain the normalized plots, iD1/I and iD2/I versus
vid /VOV , shown in Fig. 9.6. Note that at vid = 0, the two currents are equal to I/2. Making vid
positive causes i to increase and i to decrease by equal amounts, to keep the sum constant,
D1 D2
iD1 + iD2 = I . The current is steered entirely into Q1 when v i d reaches the value
√
2VOV , as we
OV
found out earlier. For v
iD2. In this case, vid = − 2VOV steers the current entirely into Q2. Finally, note that the plots in Fig. 9.6 are universal, as they apply to any MOS differential pair.
negative, identical statements can be made by interchanging i and
id D1 √
9.1 The MOS Differential Pair 605
VOV
VOV VOV
Figure 9.6 Normalized plots of the currents in a MOSFET differential pair. Note that VOV is the overdrive voltage at which Q1 and Q2 operate when conducting drain currents equal to I/2, the equilibrium situation. Note that these graphs are universal and apply to any MOS differential pair.
The transfer characteristics of Eqs. (9.23) and (9.24) and Fig. 9.6 are obviously nonlinear. This is due to the term involving v 2i d . Since we are interested in obtaining linear amplification from the differential pair, we will strive to make this term as small as possible. For a given value of VOV, the only thing we can do is keep (vid/2) much smaller than VOV, which is the condition for the small-signal approximation. It results in
I Ivid iD1≃2+ VOV 2
(9.25)
and
I Ivid iD2≃2− VOV 2
(9.26) which, as expected, indicate that iD1 increases by an increment id , and iD2 decreases by the
sameamount,id,whereid isproportionaltothedifferentialinputsignalvid, I vid
id= VOV 2 (9.27)
Recalling from our study of the MOSFET amplifier in Chapter 7 (also refer to Table G.3 in AppendixG),thataMOSFETbiasedatacurrentID hasatransconductancegm =2ID/VOV, we recognize the factor (I /VOV ) in Eq. (9.27) as gm of each of Q1 and Q2 , which are biased at ID = I /2. Now, why v i d /2? Simply because v i d divides equally between the two devices with vgs1 = vid /2 and vgs2 = −vid /2, which causes Q1 to have a current increment id and Q2 to have a current decrement id . We shall analyze the small-signal operation of the MOS differential pair
606 Chapter 9
Differential and Multistage Amplifiers
VOV VOV VOV
0.2 V 0.3 V 0.4 V
iD I
1.0 iD2 0.9 I 0.8 0.7
0.5
0.3 0.2 0.1
iD1 I
VOV 0.2 V VOV 0.3 V VOV 0.4 V
500 vid (mV) Figure 9.7 The linear range of operation of the MOS differential pair can be extended by operating the
transistor at a higher value of VOV .
shortly. At this time, however, we wish to return to Eqs. (9.23) and (9.24) and note that for a givenvid,linearitycanbeincreasedbyincreasingtheoverdrivevoltageVOV atwhicheachof Q1 and Q2 is operating. This can be done by using smaller W/L ratios. The price paid for the increasedlinearityisareductioningm andhenceareductioningain.Inthisregard,weobserve that the normalized plot of Fig. 9.6, though compact, masks this design degree of freedom. Figure 9.7 shows plots of the transfer characteristics iD1,2/I versus vid for various values of VOV . These graphs clearly illustrate the linearity–transconductance trade-off obtained by changing the value of VOV : The linear range of operation can be extended by operating the MOSFETs at a higher VOV (by using smaller W/L ratios) at the expense of reducing gm and hence the gain. This trade-off is based on the assumption that the bias current I is being kept constant. The bias current can, of course, be increased to obtain a higher gm. The expense for doing this, however, is increased power dissipation, a serious limitation in IC design.
500 400
300 200
100
0
100 200
300
400
EXERCISE
9.3 A MOS differential pair is operated at a bias current I of 0.4 mA. If μn Cox = 0.2 mA/V2 , find the
required values of W/L and the resulting g if the MOSFETs are operated at V = 0.2, 0.3, and 0.4 V. m 2 OV
For each value, give the maximum v i d for which the term involving v i d in Eqs. (9.23) and (9.24), namely, v /2/V 2, is limited to 0.1.
Ans.
id OV
VOV(V) 0.2 0.3 0.4
50 22.2 12.5 2 1.33 1 126 190 253
W/L
g (mA/V)
m
vid max (mV)
9.1.4 Small-Signal Operation
In this section we build on the understanding gained of the basic operation of the differential pair and consider in some detail its operation as a linear amplifier.
Differential Gain Figure9.8(a) shows the MOS differential amplifier with input voltages
Here,VCM denotesacommon-modedcvoltagewithintheinputcommon-moderangeofthe differential amplifier. It is needed in order to set the dc voltage of the MOSFET gates. Typically
VDD
9.1 The MOS Differential Pair 607
and
vG1 =VCM +1vid 2
vG2 =VCM −1vid 2
(9.28) (9.29)
RD
RD
vod
vV1v vV1v
vD1
Q1
Q2
vD2 G2
G1
CM
2 id
CM
2 id
vG1
vG2
I
VSS
(a)
RD
RD
RD
RD
vo2 gm(vid 2)
vgs2 vid
vo1 gmRD(vid 2)
gm(vid 2) vod gmRDvid gm(vid 2)
vo1 gmRD(vid 2) gm(vid 2)
vid 2
vgs1 vid
gmRD(vid 2)
vid 2 2
vo2 gmRD(vid 2)
vod gmRDvid
1 1 gm gm
0V
(c)
vid 2
vgs1 vid 2
Q1
Q2
vid 2 vgs2 vid 2
Biased at I 2
0 V
(b)
2
Figure 9.8 Small-signal analysis of the MOS differential amplifier. (a) The circuit with a common-mode voltageappliedtosetthedcbiasvoltageatthegatesandwithvid appliedinacomplementary(orbalanced) manner. (b) The circuit prepared for small-signal analysis. (c) The circuit in (b), with the MOSFETs replaced with T models.
608 Chapter 9
Differential and Multistage Amplifiers
VCM isatthemiddlevalueofthepowersupply.Thus,forourcase,wheretwocomplementary suppliesareutilized,VCM istypically0V.
The differential input signal vid is applied in a complementary (or balanced) manner; that is, vG1 is increased by vid/2 and vG2 is decreased by vid/2. This would be the case, for instance, if the differential amplifier were fed from the output of another differential-amplifier stage. Sometimes, however, the differential input is applied in a single-ended fashion, as we saw earlier in Fig. 9.4. The difference in the performance resulting is too subtle a point for our current needs.
As indicated in Fig. 9.8(a) the amplifier output can be taken either between one of the
drains and ground or between the two drains. In the first case, the resulting single-ended
outputs v and v will be riding on top of the dc voltages at the drains, V − I R . o1 o2 DD2D
This is not the case when the output is taken between the two drains; the resulting differential output vod (having a 0-V dc component) will be entirely a signal component. We will see shortly that there are other significant advantages to taking the output voltage differentially.
Our objective now is to analyze the small-signal operation of the differential amplifier of Fig.9.8(a) to determine its voltage gain in response to the differential input signal vid. Toward that end we show in Fig. 9.8(b) the circuit with the power supplies grounded, the bias current source I removed, and VCM eliminated; that is, only signal quantities are indicated. For the time being we will neglect the effect of the MOSFET ro. Finally note that each of Q1 and Q2 is biased at a dc current of I/2 and is operating at an overdrive voltage VOV .
From the symmetry of the circuit and because of the balanced manner in which vid is applied, we observe that the signal voltage at the joint source connection must be zero, acting as a sort of virtual ground. Thus Q1 has a gate-to-source voltage signal v gs1 = v i d /2 and Q2 hasvgs2 =−vid/2.Assumingvid/2≪VOV,theconditionforthesmall-signalapproximation, the changes resulting in the drain currents of Q1 and Q2 will be proportional to vgs1 and vgs2, respectively. Thus Q1 will have a drain current increment gm(vid/2) and Q2 will have a drain current decrement gm(vid/2), where gm denotes the equal transconductances of the two devices,
gm = 2ID = 2(I/2) = I (9.30) VOV VOV VOV
These results correspond to those obtained earlier using the large-signal transfer characteristics and imposing the small-signal condition, Eqs. (9.25) to (9.27). To further illustrate the small-signal operation of the differential amplifier, we show in Fig. 9.8(c) its equivalent circuit obtained by replacing each of the MOSFETs with the corresponding T model. The reader is urged to study the correspondence between the elements and qualities in Fig. 9.8(b) and 9.8(c).
It is useful at this point to observe again that a signal ground is established at the source terminals of the transistors without resorting to the use of a large bypass capacitor, clearly a major advantage of the differential-pair configuration.
The essence of differential-pair operation is that it provides complementary current signals in the drains; what we do with the resulting pair of complementary current signals is, in a sense, a separate issue. Here, of course, we are simply passing the two current signals through a pair of matched resistors, RD, and thus obtaining the drain voltage signals
v =−gvidR (9.31) o1 m2D
and
v =+gvidR o2 m2D
If the output is taken in a single-ended fashion, the resulting gain becomes vo1 =−1g R
(9.32)
(9.33)
(9.34)
(9.35)
9.1
The MOS Differential Pair 609
or
vid 2mD vo2 = 1g R
vid 2mD
Alternatively, if the output is taken differentially, the gain becomes
A ≡vod =vo2−vo1 =g R dvid vid mD
Thus another advantage of taking the output differentially is an increase in gain by a factor of 2 (6 dB). It should be noted, however, that although differential outputs are preferred, a single-ended output is needed in some applications. We will have more to say about this later.
An alternative and useful way of viewing the operation of the differential pair in response toadifferentialinputsignalvid isillustratedinFig.9.9.Herewearemakinguseofthefact that the resistance between gate and source of a MOSFET, looking into the source, is 1/gm . As a result, between G1 and G2 we have a total resistance, in the source circuit, of 2/gm . It follows that we can obtain the current id simply by dividing vid by 2/gm, as indicated in the figure.
The Differential Half-Circuit When a symmetrical differential amplifier is fed with a differential signal in a balanced manner, as in the case in Fig. 9.8, the performance can be determined by considering only half the circuit. The equivalent differential half-circuit is shown in Fig. 9.10. It has a grounded source, a result of the virtual ground that appears on the common sources’ terminal of the MOSFETs in the differential pair. Note that Q1 is operating at a drain bias current of (I/2) and an overdrive voltage VOV .
RD RD
RD
vo1
id
RD
id
vo1
id
vod
vo2 id
vod
vo2
gm
id
0
0
G1 Q1 Q2 vid
1id=vid1
gm
v
2gm gm
vid 1 gm
G2
(2gm)
(a)
1
Figure 9.9 An alternative view of the small-signal differential operation of the MOS differential pair: (a) analysis done directly on the circuit; (b) analysis using equivalent-circuit models.
(b)
610 Chapter 9
Differential and Multistage Amplifiers
RD
Q1
vod 2
vid 2
Figure 9.10 The equivalent differential half-circuit of the differentialamplifierofFig.9.8.HereQ1 isbiasedatI/2and is operating at VOV . This circuit can be used to determine the differential voltage gain of the differential amplifier Ad = vod /vid .
ThedifferentialgainAd canbedetermineddirectlyfromthehalf-circuit.Forinstance,if we wish to take ro of Q1 and Q2 into account, we can use the half-circuit with the following result:
Ad =gm(RD∥ro) (9.36) More significantly, the frequency response of the differential gain can be determined by
analyzing the half-circuit, as we shall do in Chapter 10.
Example 9.2
Give the differential half-circuit of the differential amplifier shown in Fig. 9.11(a). Assume that Q1 and Q2 areperfectlymatched.Neglectingro,determinethedifferentialvoltagegainAd ≡vod/vid.
RD
VDD
RL
vod
RD
RD
V vid CM 2
Q1
Q2 vod vid
VCM 2 RR2R
ss vidQL 212
I
VSS
(a)
Rs
Figure 9.11 (a) Differential amplifier for Example 9.2. (b) Differential half-circuit.
(b)
Solution
Sincethecircuitissymmetricalandisfedwithvid inabalancedmanner,thedifferentialhalf-circuitwill be as shown in Fig. 9.11(b). Observe that because the line of symmetry passes through the middle of RL , the half-circuit has a resistance RL /2 connected between drain and ground. Also note that the virtual ground appears on the node between the two resistances Rs . As a result, the half-circuit has a source-degeneration resistance Rs.
Now, neglecting ro of the half-circuit transistor Q1, we can obtain the gain as the ratio of the total resistance in the drain to the total resistance in the source as
with the result that
EXERCISE
−vod/2=−RD∥ RL/2 vid/2 1/gm +Rs
A ≡vod =RD∥ RL/2 d vid 1/gm +Rs
(9.37)
9.1 The MOS Differential Pair 611
9.4 AMOSdifferentialamplifierisoperatedatatotalcurrentof0.8mA,usingtransistorswithaW/Lratio of100,μnCox =0.2mA/V2,VA =20V,andRD =5k.FindVOV,gm,ro,andAd.
Ans. 0.2 V; 4 mA/V; 50 k; 18.2 V/V
9.1.5 The Differential Amplifier with Current-Source Loads
To obtain higher gain, the passive resistances RD can be replaced with current sources, as shown in Fig. 9.12(a). Here the current sources are realized with PMOS transistors Q3 and Q4, and VG is a dc bias voltage that ensures that Q3 and Q4 each conducts a current equal to I/2. The differential voltage gain Ad can be found from the differential half-circuit shown in Fig. 9.12(b) as
A ≡vod =g (r ∥r ) d vid m1 o1 o3
EXERCISE
for each of Q1, Q2, Q3, and Q4, and determine the differential voltage gain Ad. Ans. (W/L)1,2 = 12.5; (W/L)3,4 = 50; Ad = 18 V/V
9.5 The differential amplifier of Fig. 9.12(a) is fabricated in a 0.18-μm CMOS technology for which μC =4μC =400μA/V2,V=0.5V,andV′=10V/μm.IfthebiascurrentI=200μAand
n ox p ox t A
all transistors have a channel length twice the minimum and are operating at VOV = 0.2 V, find W/L
612 Chapter 9
Differential and Multistage Amplifiers
VDD
Q3
VG Q4
vod
Q3
Q1
Q2
v v vod
VCM id VCM id
22
I
VSS
2
vid 2
Q1
(b)
(a)
Figure 9.12 (a) Differential amplifier with current-source loads formed by Q3 and Q4 . (b) Differential half-circuit of the amplifier in (a).
THE LONG-TAILED PAIR:
This idea using vacuum tubes was first documented by B. C. P. Matthews in 1934 in the Proceedings of the Physical Society, and was further developed by others in the late 1930s. The topology is simply that of a differential pair, where the term “long-tailed” refers to the biasing current source, which originally used a large-valued (hence long) resistor. Interestingly enough, the first application in measuring biological potentials in an electrically noisy environment continues to be an important one in modern medical instruments that utilize MOS devices.
9.1.6 Cascode Differential Amplifier
The gain of the differential amplifier can be increased by utilizing the cascode configuration studied in Section 8.5. Figure 9.13(a) shows a CMOS differential amplifier with cascoding applied to the amplifying transistors Q1 and Q2 via transistors Q3 and Q4, and to the current-source transistors Q7 and Q8 via transistors Q5 and Q6. The differential voltage gain can be found from the differential half-circuit shown in Fig. 9.13(b) as
A ≡vod =g R ∥R (9.38) d vid m1 on op
VDD
9.1
The MOS Differential Pair 613
VG3
VG2
VG1
Q8
Q6
Q4
Q7
Q7
Q5
vod
Q5
Ron
Q3
Q1 Q2
Rop vod 2
VCM vid I2
Q3
Q1
(b)
VCM
vid 22
– VSS
(a)
vid
Figure 9.13 (a) Cascode differential amplifier; and (b) its differential half-circuit. where
and,
EXERCISE
Ron = (gm3ro3)ro1 Rop = (gm5ro5)ro7
(9.39)
(9.40)
9.6 TheCMOScascodedifferentialamplifierofFig.9.13(a)isfabricatedina0.18-μmtechnologyforwhich μC =4μC =400μA/V2,V=0.5V,andV′=10V/μm.IfthebiascurrentI=200μA,and
n ox p ox t A
all transistors have a channel length twice the minimum and are operating at VOV = 0.2 V, find W/L
foreachofQ1 toQ8,anddeterminethedifferentialvoltagegainAd. Ans. (W/L)1,2,3,4 = 12.5; (W/L)5,6,7,8 = 50; Ad = 648 V/V
614 Chapter 9
Differential and Multistage Amplifiers
++ ––
Figure 9.14 The basic BJT differential-pair configuration.
9.2 The BJT Differential Pair
Figure 9.14 shows the basic BJT differential-pair configuration. It is very similar to the MOSFET circuit and consists of two matched transistors, Q1 and Q2, whose emitters are joined together and biased by a constant-current source I. The latter is usually implemented by a transistor circuit of the type studied in Sections 8.2 and 8.6. Although each collector is shown connected to the positive supply voltage VCC through a resistance RC, this connection is not essential to the operation of the differential pair—that is, in some applications the two collectors may be connected to current sources rather than resistive loads. It is essential, though, that the collector circuits be such that Q1 and Q2 never enter saturation.
9.2.1 Basic Operation
To see how the BJT differential pair works, consider first the case of a common-mode voltage
VCM applied to the two input terminals. That is, as shown in Fig. 9.15(a), vB1 = vB2 = VCM .
Since Q1 and Q2 are matched, and assuming an ideal bias current source I with infinite
output resistance, it follows that the current I will remain constant and, from symmetry, that
I will divide equally between the two devices. Thus iE1 = iE2 = I/2, and the voltage at the
emitters will be VCM − VBE , where VBE is the base–emitter voltage [assumed in Fig 9.15(a)
to be approximately 0.7 V] corresponding to an emitter current of I/2. The voltage at each
collector will be VCC − 1 αIRC , and the difference in voltage between the two collectors will 2
be zero.
Now let us vary the value of the common-mode input voltage VCM . Obviously, as long as
Q1 and Q2 remain in the active region, and the current source I has sufficient voltage across it to operate properly, the current I will still divide equally between Q1 and Q2, and the voltages at the collectors will not change. Thus the differential pair does not respond to (i.e., it rejects) changes in the common-mode input voltage.
Asanotherexperiment,letthevoltagevB2 besettoaconstantvalue,say,zero(bygrounding B2), and let vB1 = +1 V [see Fig. 9.15(b)]. With a bit of reasoning it can be seen that Q1 will be on and conducting all of the current I and that Q2 will be off. For Q1 to be on (with
9.2 The BJT Differential Pair 615
VEE
(a)
VEE VEd (c) (d)
Figure 9.15 Different modes of operation of the BJT differential pair: (a) the differential pair with a common-mode input voltage VCM ; (b) the differential pair with a “large” differential input signal; (c) the differential pair with a large differential input signal of polarity opposite to that in (b); (d) the differential pair with a small differential input signal vi. Note that we have assumed the bias current source I to be ideal (i.e., it has an infinite output resistance) and thus I remains constant with the change in the voltage across it.
VBE1 = 0.7 V), the emitter has to be at approximately +0.3 V, which keeps the EBJ of Q2 reverse-biased. The collector voltages will be vC1 = VCC − αIRC and vC2 = VCC .
Let us now change vB1 to –1 V [Fig. 9.15(c)]. Again with some reasoning it can be seen that Q1 will turn off, and Q2 will carry all the current I. The common emitter will be at –0.7 V,
616 Chapter 9
Differential and Multistage Amplifiers
which means that the EBJ of Q1 will be reverse biased by 0.3 V. The collector voltages will bevC1 =VCC andvC2 =VCC −αIRC.
From the foregoing, we see that the differential pair certainly responds to difference-mode (or differential) signals. In fact, with relatively small difference voltages we are able to steer the entire bias current from one side of the pair to the other. This current-steering property of the differential pair allows it to be used in logic circuits, as will be demonstrated in Chapter 15.
To use the BJT differential pair as a linear amplifier, we apply a very small differential signal (a few millivolts), which will result in one of the transistors conducting a current of I /2 + I ; the current in the other transistor will be I /2 − I , with I being proportional to the difference input voltage (see Fig. 9.15(d)). The output voltage taken between the two collectors will be 2αIRC, which is proportional to the differential input signal vi. The small-signal operation of the differential pair will be studied shortly.
EXERCISE
9.7 Find v , v , and v in the circuit of Fig. E9.7. Assume that v of a conducting transistor is
EC1 C2 approximately 0.7 V and that α ≃1.
BE
5V
1k
vE
0.5 V
vC1 1k
Q1 Q2
vC2
1 k
Ans. +0.7 V; −5 V; −0.7 V
5 V
Figure E9.7
9.2.2 Input Common-Mode Range
RefertothecircuitinFig.9.15(a).TheallowablerangeofVCM isdeterminedattheupperend by Q1 and Q2 leaving the active mode and entering saturation. Thus
VCMmax ≃VC +0.4=VCC −αIRC +0.4 (9.41) 2
9.2 The BJT Differential Pair 617 The lower end of the VCM range is determined by the need to provide a certain minimum
voltage VCS across the current source I to ensure its proper operation. Thus,
VCMmin =−VEE +VCS +VBE (9.42)
EXERCISE
9.8 Determine the input common-mode range for a bipolar differential amplifier operating from ±2.5-V power supplies and biased with a simple current source that delivers a constant current of 0.4 mA and requires a minimum of 0.3 V for its proper operation. The collector resistances RC = 5 k.
Ans. −1.5 V to +1.9 V
9.2.3 Large-Signal Operation
We now present a general analysis of the BJT differential pair of Fig. 9.14. If we denote the voltageatthecommonemitterbyvE andneglecttheEarlyeffect,theexponentialrelationship applied to each of the two transistors may be written
iE1 = IS e(vB1 −vE )/VT α
iE2 = IS e(vB2 −vE )/VT α
These two equations can be combined to obtain
iE1 =e(vB1−vB2)/VT
iE2 which can be manipulated to yield
iE1 = 1
iE1 + iE2 1 + e(vB2 −vB1 )/VT
iE2 = 1
iE1 + iE2 1 + e(vB1 −vB2 )/VT
The circuit imposes the additional constraint
iE1 +iE2 =I
(9.43) (9.44)
(9.45) (9.46)
(9.47) Using Eq. (9.47) together with Eqs. (9.45) and (9.46) and substituting vB1 − vB2 = vid gives
iE1 = I (9.48) 1+e−vid /VT
iE2 = I (9.49) 1+evid /VT
618 Chapter 9
Differential and Multistage Amplifiers
The collector currents iC1 and iC2 can be obtained simply by multiplying the emitter currents in Eqs. (9.48) and (9.49) by α, which is normally very close to unity.
The fundamental operation of the differential amplifier is illustrated by Eqs. (9.48) and (9.49). First, note that the amplifier responds only to the difference voltage vid. That is, if vB1 = vB2 = VCM , the current I divides equally between the two transistors irrespective of the value of the common-mode voltage VCM . This is the essence of differential-amplifier operation, which also gives rise to its name.
Anotherimportantobservationisthatarelativelysmalldifferencevoltagevid willcause
the current I to flow almost entirely in one of the two transistors. Figure 9.16 shows a plot
of the two collector currents (assuming α ≃ 1) as a function of the differential input signal.
This is a normalized plot that can be used universally. Observe that a difference voltage of
about4V (≃100mV)issufficienttoswitchthecurrentalmostentirelytoonesideoftheBJT
T
(Chapter 15).
The nonlinear transfer characteristics of the differential pair, shown in Fig. 9.16, will not be
utilized any further in this chapter. Rather, in the following we shall be interested specifically in the application of the differential pair as a small-signal amplifier. For this purpose, the difference input signal is limited to less than about VT /2 in order that we may operate on a linear segment of the characteristics around the midpoint x (in Fig. 9.16).
Before leaving the large-signal operation of the differential BJT pair, we wish to point out an effective technique frequently employed to extend the linear range of operation. It consists of including two equal resistances Re in series with the emitters of Q1 and Q2, as
vid VT
Figure 9.16 Transfer characteristics of the BJT differential pair of Fig. 9.14 assuming α ≃1.
√
2 VOV . The fact that such a small signal can switch the current from one side of the BJT differential pair to the other means that the BJT differential pair can be used as a fast current switch
pair. Note that this is much smaller than the corresponding voltage for the MOS pair,
iC I
VCC
9.2
The BJT Differential Pair 619
vC1
RC
Re
iC1 Q1
iC2 Q2
RC
Re
vC2
vB1
vB2
I
(a)
1.0 0.8 0.6 0.4 0.2
0
iC2 I
iC1 I
IRe IRe
IRe IRe
IRe 20VT 10VT
0
0
10VT
IRe 20VT
vid VT Figure 9.17 The transfer characteristics of the BJT differential pair (a) can be linearized (b) (i.e., the linear
range of operation can be extended) by including resistances in the emitters.
shown in Fig. 9.17(a). The resulting transfer characteristics for three different values of Re are sketched in Fig. 9.17(b). Observe that expansion of the linear range is obtained at the expense of reduced Gm (which is the slope of the transfer curve at vid = 0) and hence reduced gain. This result should come as no surprise; Re here is performing in exactly the same way as the emitter resistance Re does in the CE amplifier with emitter degeneration (see Section 7.3.4). Finally, we also note that this linearization technique is in effect the bipolar counterpart of the technique employed for the MOS differential pair (Fig. 9.7). In the latter case, however, VOV was varied by changing the transistors’ W/L ratio, a design tool with no counterpart in the BJT.
24 20 16 12
8 4 0 4 8
12 16 20 24
(b)
Normalized collector current, iC I
620 Chapter 9 Differential and Multistage Amplifiers
EXERCISE
9.9 For the BJT differential pair of Fig. 9.14, find the value of input differential signal that is sufficient to cause iE1 = 0.99I.
Ans. 115 mV
9.2.4 Small-Signal Operation
In this section we study the application of the BJT differential pair in small-signal amplification. Figure 9.18 shows the BJT differential pair with a difference voltage signal vid applied between the two bases. Implied is that the dc level at the input—that is, the common-mode input voltage—has been somehow established. For instance, one of the two inputterminalscanbegroundedandvid appliedtotheotherinputterminal.Alternatively,the differential amplifier may be fed from the output of another differential amplifier. In the latter case, the voltage at one of the input terminals will be VCM + v i d /2 while that at the other input terminal will be VCM − vid /2.
The Collector Currents When vid Is Applied For the circuit of Fig. 9.18, we may use Eqs. (9.48) and (9.49) to write
iC1 = iC2 =
αI 1+e−vid /VT
αI 1+evid /VT
v
(9.50) (9.51)
vid vid
vid
vid
id
vid
vid
vid
Figure9.18 Thecurrentsandvoltagesinthedifferentialamplifierwhenasmalldifferentialinputsignalvid is applied.
9.2 The BJT Differential Pair 621 Multiplying the numerator and the denominator of the right-hand side of Eq. (9.50) by evid /2VT
gives
αIevid /2VT
iC1 = evid /2VT + e−vid /2VT
Assume that vid ≪ 2VT . We may thus expand the exponential e±vid /2VT only the first two terms:
in a series and retain
(9.52)
(9.53)
iC1 ≃
αI(1+vid/2VT) 1+vid/2VT +1−vid/2VT
iC1 = αI + αI vid 2 2VT 2
Thus
Similar manipulations can be applied to Eq. (9.51) to obtain iC2 = αI − αI vid
2 2VT 2
Equations (9.52) and (9.53) tell us that when v i d = 0, the bias current I divides equally between the two transistors of the pair. Thus each transistor is biased at an emitter current of I /2. When a “small-signal”vid isapplieddifferentially(i.e.,betweenthetwobases),thecollectorcurrent of Q1 increases by an increment ic and that of Q2 decreases by an equal amount. This ensures that the sum of the total currents in Q1 and Q2 remains constant, as constrained by the current-source bias. The incremental (or signal) current component ic is given by
ic = αI vid (9.54) 2VT 2
Equation (9.54) has an easy interpretation. First, note from the symmetry of the circuit (Fig. 9.18) that the differential signal vid should divide equally between the base–emitter junctions of the two transistors. Thus the total base–emitter voltages will be
v =V +vid BEQ1 BE 2
v =V −vid BE Q2 BE 2
where VBE is the dc BE voltage corresponding to an emitter current of I/2. Therefore, the collector current of Q1 will increase by gmvid/2 and the collector current of Q2 will decrease bygmvid/2.Heregm denotesthetransconductanceofQ1 andofQ2,whichareequalandgivenby
gm = IC = αI/2 (9.55) VT VT
ThusEq.(9.54)simplystatesthatic =gmvid/2.
An Alternative Viewpoint There is an extremely useful alternative interpretation of the results above. Assume the current source I to be ideal. Its incremental resistance then will be infinite. Thus the voltage vid appears across a total resistance of 2re, where
re = VT = VT (9.56) IE I/2
622
Chapter 9
Differential and Multistage Amplifiers
avid 2re
avid 2re
RC
aie ib
RC
aie
RC
RC
avid R 2re C
v
avid R 2re C
avid
2r RC
avid
2r RC
od
v
od ee
i vid
b
Rid
(b
1)2re
Q1
Q2 VT
ie = vid
vid reI2re2rere
vid
2re
(a)
vid
ib
ib
ib = (1–a)ie = vid
Figure 9.19 A simple technique for determining the signal currents in a differential amplifier excited by a differential voltage signal v i d ; dc quantities are not shown. While Fig. 9.19(a) utilizes the BJT T model implicitly, the T model of both BJTs are shown explicitly in Fig. 9.19(b).
Correspondingly there will be a signal current ie , as illustrated in Fig. 9.19, given by
ie = vid (9.57)
2re
Thus the collector of Q1 will exhibit a current increment ic and the collector of Q2 will exhibit
(b + 1)2re Rid = 2(b+1)re = 2rp
(b)
a current decrement ic:
i =αi =αvid =g vid (9.58) c e 2r m2
e
Note that in Fig. 9.19(a) we have shown signal quantities only. It is implied, of course, that each transistor is biased at an emitter current of I/2. For greater emphasis, we show in Fig. 9.20(b) the equivalent circuit obtained by replacing each BJT with its T model.
This method of analysis is particularly useful when resistances are included in the emitters, as shown in Fig. 9.20. For this circuit we have
ie = vid (9.59) 2re +2Re
Input Differential Resistance Unlike the MOS differential amplifier, which has an infinite input resistance, the bipolar differential pair exhibits a finite input resistance, a result of the finite β of the BJT.
The input differential resistance is the resistance seen between the two bases; that is, it is the resistance seen by the differential input signal vid. For the differential amplifier in Figs. 9.18 and 9.19 it can be seen that the base current of Q1 shows an increment ib and the base current of Q2 shows an equal decrement,
ib = ie = vid/2re (9.60) β+1 β+1
9.2 The BJT Differential Pair 623
avid 2(re
aRC
2(re Re) vid
Re)
avid 2(re Re)
aRC
2(re Re) vid
RC
2re
vid 1) (re
ThusthedifferentialinputresistanceRid isgivenby
Rid ≡ vid =(β+1)2re =2rπ (9.61)
ib
This result is just a restatement of the familiar resistance-reflection rule: namely, the resistance seen between the two bases is equal to the total resistance in the emitter circuit multiplied by (β + 1). We can employ this rule to find the input differential resistance for the circuit in Fig. 9.20 as
Rid = (β + 1)(2re + 2Re) (9.62) Differential Voltage Gain We have established that for small difference input voltages
RC
vod
ib
2(b
vid 1) (re
vid
Re)
Q1
Q2 Re
vid
2Re
Re
Rid
ib
2(b
Figure 9.20 A differential amplifier with emitter resistances. Only signal quantities are shown (in color).
Re)
(vid ≪ 2 VT ; i.e., vid smaller than about 20 mV), the collector currents are given by i=I+gvid
(9.63) (9.64)
(9.65)
(9.66) (9.67)
where
Thus the total voltages at the collectors will be
C1 C m2 i=I−gvid
C2 C m2 IC = αI
2
v =(V −IR)−gRvid C1 CC CC mC2
v =(V −IR)+gRvid C2 CC CC mC2
The quantities in parentheses are simply the dc voltages at each of the two collectors.
624 Chapter 9
Differential and Multistage Amplifiers
As in the MOS case, the output voltage signal of a bipolar differential amplifier can be taken differentially (i.e., between the two collectors, vod = vc2 – vc1). The differential gain of the differential amplifier will be
A =vod =g R (9.68) d vid mC
For the differential amplifier with resistances in the emitter leads (Fig.9.20), the differential gain is given by
Ad = α(2RC) ≃ RC (9.69) 2re +2Re re +Re
This equation is a familiar one: It states that the voltage gain is equal to the ratio of the total resistance in the collector circuit (2RC ) to the total resistance in the emitter circuit (2re + 2Re ).
The Differential Half-Circuit As in the MOS case, the differential gain of the BJT differential amplifier can be obtained by considering its differential half-circuit. Figure 9.21(a) showsadifferentialamplifierfedbyadifferentialsignalvid thatisappliedinacomplementary (push–pullorbalanced)manner.Thatis,whilethebaseofQ1 israisedbyvid/2,thebaseof Q2 is lowered by vid/2. We have also included the output resistance REE of the bias current source. From symmetry, it follows that the signal voltage at the emitters will be zero. Thus the circuit is equivalent to the two common-emitter amplifiers shown in Fig. 9.21(b), where each of the two transistors is biased at an emitter current of I/2. Note that the finite output resistanceREE ofthecurrentsourcewillhavenoeffectontheoperation.Theequivalentcircuit in Fig. 9.21(b) is valid for differential operation only.
In many applications the differential amplifier is not fed in a complementary fashion; rather, the input signal may be applied to one of the input terminals while the other terminal is
RC
RC
RC RC
vod
vidQQvid2 2
vo1 2122
REE
Figure 9.21 Equivalence of the BJT differential amplifier in (a) to the two common-emitter amplifiers in (b). This equivalence applies only for differential input signals. Either of the two common-emitter amplifiers in (b) can be used to find the differential gain, differential input resistance, frequency response, and so on, of the differential amplifier.
vo2
vo1 = vod
vid Q Q vid
vo2 =vod 2122
0V
Biased at 2I (a) (b)
9.2 The BJT Differential Pair 625
vo1
RC
Q1
vod
RC
Q2
vo2
vid vid 2 2
vid
ve vid 2
i ve 0 REE REE re REE
Figure 9.22 The differential amplifier fed in a single-ended fashion.
grounded, as shown in Fig. 9.22. In this case the signal voltage at the emitters will not be zero, and thus the resistance REE will have an effect on the operation. Nevertheless, if REE is large (REE ≫ re), as is usually the case,1 then vid will still divide equally (approximately) between the two junctions, as shown in Fig. 9.22. Thus the operation of the differential amplifier in this case will be almost identical to that in the case of symmetric feed, and the common-emitter equivalence can still be employed.
Since in Fig. 9.21, vo2 = −vo1 = vod /2, the two common-emitter transistors in Fig. 9.21(b) yield similar results about the performance of the differential amplifier. Thus only one is needed to analyze the differential small-signal operation of the differential amplifier, and it is known as the differential half-circuit. If we take the common-emitter transistor fed with +vid/2 as the differential half-circuit and replace the transistor with its low-frequency, hybrid-π , equivalent-circuit model, the circuit in Fig. 9.23 results. In evaluating the model parameters rπ , gm , and ro , we must recall that the half-circuit is biased at I/2. The voltage gain of the differential amplifier is equal to the voltage gain of the half-circuit—that is, v o1 /(v i d /2). Here, we note that including ro will modify the gain expression in Eq. (9.68) to
Ad = gm(RC ∥ro) (9.70)
The input differential resistance of the differential amplifier is twice that of the half-circuit—that is, 2rπ . Finally, we note that the differential half-circuit of the amplifier of Fig. 9.20 is a common-emitter transistor with a resistance Re in the emitter lead.
vo1 = vod 2
vid 2
Figure 9.23 Equivalent-circuit model of the differential half-circuit formed by Q1 in Fig. 9.22(b). 1Note that REE appears in parallel with the much smaller re of Q2.
626 Chapter 9 Differential and Multistage Amplifiers
Example 9.3
The differential amplifier in Fig. 9.24 uses transistors with β = 100. Evaluate the following: (a) The input differential resistance Rid.
(b) The overall differential voltage gain vod/vsig (neglect the effect of ro).
vod
+ –
+ –
vid Rid
Figure 9.24 Circuit for Example 9.3.
Solution
(a) Each transistor is biased at an emitter current of 0.5 mA. Thus re1 =re2 = VT = 25mV =50
IE 0.5 mA The input differential resistance can now be found as
Rid =2(β+1) re +RE
= 2 × 101 × (50 + 150) ≃ 40 k
(b) The voltage gain from the signal source to the bases of Q1 and Q2 is vid = Rid
5+5+40 The voltage gain from the bases to the output is
vsig Rsig +Rid
= 40 = 0.8 V/V
vod ≃ Total resistance in the collectors vid Total resistance in the emitters
= 2RC = 2×10 =50V/V 2 re +RE 2(50+150)×10−3
The overall differential voltage gain can now be found as
A =vod =vid vod =0.8×50=40V/V
EXERCISE
9.10 ForthecircuitinFig.9.18,letI=1mA,VCC =15V,RC =10k,withα=1,andlettheinput voltages be vB1 = 5 + 0.005 sin 2π × 1000t, volts, and vB2 = 5 − 0.005 sin 2π × 1000t, volts. (a) If the BJTs are specified to have vBE of 0.7 V at a collector current of 1 mA, find the voltage at the emitters. (b) Find gm for each of the two transistors. (c) Find iC for each of the two transistors. (d) FindvC foreachofthetwotransistors.(e)Findthevoltagebetweenthetwocollectors.(f)Findthe gain experienced by the 1000-Hz signal.
Ans. (a)4.317V;(b)20mA/V;(c)iC1 =0.5+0.1sin2π ×1000t,mAandiC2 =0.5–0.1sin2π × 1000t,mA;(d)vC1 =10–1sin2π ×1000t,VandvC2 =10+1sin2π ×1000t,V;(e)vC2 –vC1 = 2 sin 2π × 1000t, V; (f) 200 V/V
9.3 Common-Mode Rejection
Thus far, we have seen that the differential amplifier responds to a differential input signal and completely rejects a common-mode signal. This latter point was made very clearly at the outset of our discussion of differential amplifiers and was illustrated in Example 9.1, where wesawthatchangesinVCM overawiderangeresultedinnochangeinthevoltageateitherof the two drains. The same phenomenon was demonstrated for the BJT differential amplifier in Section 9.2.1. This highly desirable result is, however, a consequence of our assumption that the current source that supplies the bias current I is ideal. As we shall now show, if we
d vsig vsig vid
9.3 Common-Mode Rejection 627
628 Chapter 9
Differential and Multistage Amplifiers
consider the more realistic situation of the current source having a finite output resistance, the common-mode gain will no longer be zero.
9.3.1 The MOS Case
Figure 9.25(a) shows a MOS differential amplifier biased with a current source having an output resistance RSS . As before, the dc voltage at the input is defined by VCM . Here, however, we also have an incremental signal vicm applied to both input terminals. This common-mode input signal can represent an interference signal or noise that is picked up by both inputs and is clearly undesirable. Our objective now is to find how much of vicm makes its way to the output of the amplifier.
Before we determine the common-mode gain of the amplifier, we wish to address the question of the effect of RSS on the bias current of Q1 and Q2. That is, with vicm set to zero, the bias current in each of Q1 and Q2 will no longer be I/2 but will be larger than I/2 by an amount determinedbyVCM andRSS.However,sinceRSS isusuallyverylarge,thisadditionaldccurrent in each of Q1 and Q2 is usually small and we shall neglect it, thus assuming that Q1 and Q2 continue to operate at a bias current of I/2. The reader might also be wondering about the effect of RSS on the differential gain. The answer here is very simple: The virtual ground that develops on the common-source terminal when a differential input signal is applied results in azerosignalcurrentthroughRSS;henceRSS hasnoeffectonthevalueofAd.
To determine the response of the differential amplifier to the common-mode input signal vicm, consider the circuit in Fig. 9.25(b), where we have replaced each of VDD and VSS by a short circuit and I by an open circuit. The circuit is obviously symmetrical, and thus the two transistors will carry equal signal currents, denoted i. The value of i can be easily determined byreplacingeachofQ1 andQ2 withitsTmodeland,forsimplicity,neglectingro.Theresulting equivalent circuit is shown in Fig. 9.25(c), from which we can write
Thus,
vicm = i + 2iRSS gm
i = vicm 1/gm +2RSS
(9.71)
(9.72)
(9.73)
The voltages at the drain of Q1 and Q2 can now be found as vo1 =vo2 =−RDi
resulting in
vo1 = vo2 = − RD vicm 1/gm +2RSS
It follows that both vo1 and vo2 will be corrupted by the common-mode signal vicm and will be given approximately by
vo1 = vo2 ≃ − RD (9.74) v icm v icm 2RSS
where we have assumed that 2RSS ≫ 1/gm. Nevertheless, because vo1 = vo2, the differential outputvoltagevod willremainfreeofcommon-modeinterference:
vod =vo2 −vo1 =0 (9.75)
VDD
9.3 Common-Mode Rejection 629
RD
RD
VD
VCM
vo1 vicm
VD vo2
Q1Q2 RDiiRD
vod
VCM
vicm
vo1 vod
vo2
vicm
vicm
Q2 ii
2i
RSS
(b)
Q1
RSS
I
RD
VSS
(a)
vod
RD
vo1
g1
vo2
g2
RD
vo1
RD
i
i
i
1
gm
i
1
gm
vicm
vicm
vo2
v Q1 Q2
icm i i vicm
2i
RSS
2RSS
2RSS
(c)
Biased at I/2
(d)
Figure 9.25 (a) A MOS differential amplifier with a common-mode input signal vicm superimposed on the input dc common-mode voltage VCM . (b) The amplifier circuit prepared for small-signal analysis. (c) The amplifier circuit with the transistors replaced with their T model and ro neglected. (d) The circuit in (b) split into its two halves; each half is said to be a “CM half-circuit.”
630 Chapter 9
Differential and Multistage Amplifiers
Thus the circuit still rejects common-mode signals! Unfortunately, however, this will not be the case if the circuit is not perfectly symmetrical, as we shall now show.
Before proceeding further, it is useful to observe that all the above results can be obtained by considering only half the differential amplifier. Figure 9.25(d) shows the two half-circuits of the differential amplifier that apply for common-mode analysis. To see the equivalence, observe that each of the two half-circuits indeed carries a current i given by Eq. (9.72) and the voltages at the source terminals are equal (vs = 2iRSS). Thus the two sources can be joined, returning the circuit to the original form in Fig. 9.25(b). Each of the circuits in Fig. 9.25(d) is known as the common-mode half-circuit. Note the difference between the CM half-circuit and the differential half-circuit.
Effect of RD Mismatch When the two drain resistances exhibit a mismatch RD , as they inevitably do, the common-mode voltages at the two drains will no longer be equal. Rather, if the load of Q1 is RD and that of Q2 is (RD + RD ) the drain signal voltages arising from v icm will be
and
Thus,
vo1 ≃ − RD vicm 2RSS
vo2 ≃ − RD +RD vicm 2RSS
vod =vo2 −vo1 =−RD vicm 2RSS
(9.76)
(9.77)
(9.78)
(9.79)
(9.80)
and we can find the common-mode gain Acm as
A ≡vod =−RD
cm vicm 2RSS
which can be expressed in the alternate form
R R Acm =− D D
2RSS RD
It follows that a mismatch in the drain resistances causes the differential amplifier to have a finite common-mode gain. Thus, a portion of the interference or noise signal vicm will appear as a component of vod . A measure of the effectiveness of the differential amplifier in amplifying differential-mode signals and rejecting common-mode interference is the ratio of the magnitude of its differential gain |Ad| to the magnitude of its common-mode gain |Acm|. This ratio is termed common-mode rejection ratio (CMRR). Thus,
and is usually expressed in decibels,
CMRR≡ |Ad| |Acm|
(9.81)
(9.82)
CMRR(dB) = 20 log |Ad | |Acm|
9.3 Common-Mode Rejection 631 For the case of a MOS differential amplifier with drain resistances RD that exhibit a mismatch
RD, the CMRR can be found as the ratio of Ad in Eq. (9.35) to Acm in Eq. (9.79), thus R
CMRR = (2gm RSS ) D (9.83) RD
It follows that to obtain a high CMRR, we should utilize a bias current source with a high output resistance RSS , and we should strive to obtain a high degree of matching between the drain resistances (i.e., keep RD/RD small).
EXERCISE
9.11 AMOSdifferentialpairoperatedatabiascurrentof0.8mAemploystransistorswithW/L=100and μn Cox = 0.2 mA/V2 , using RD = 5 k and RSS = 25 k. Find the differential gain, the common-mode gain when the drain resistances have a 1% mismatch, and the CMRR.
Ans. 20 V/V; 0.001 V/V; 86 dB
Effect of gm Mismatch on CMRR Another possible mismatch between the two halves of the MOS differential pair is a mismatch in gm of the two transistors. For the purpose of finding the effect of a gm mismatch on CMRR, let
That is,
gm1 = gm + 1 gm 2
gm2 = gm − 1 gm 2
gm1 − gm2 = gm
(9.84) (9.85)
(9.86)
Since the circuit is no longer symmetrical, we cannot employ the common-mode half-circuit. Rather, we need to return to the original circuit of Fig. 9.25(a) and replace each of Q1 and Q2 with its T equivalent-circuit model. We shall skip the analysis and simply present the result,
and the corresponding CMRR will be
CMRR = (2gm RSS ) m
R g Acm ≃ D m
(9.87)
(9.88)
2RSS gm g
Note that both expressions have exactly the same form as the corresponding expressions for the case of RD mismatch.
Thus, as in that case, to keep CMRR high, we have to use a biasing current source with a highoutputresistanceRSS and,ofcourse,strivetomaintainahighdegreeofmatchingbetween Q1 andQ2.
gm
632 Chapter 9 Differential and Multistage Amplifiers
EXERCISE
9.12 FortheMOSamplifierspecifiedinExercise9.11,computetheCMRRresultingfroma1%mismatch in gm.
Ans. 86 dB
Example 9.4
In this example we consider the design of the current source that supplies the bias current of a MOS differential amplifier. Let it be required to achieve a CMRR of 100 dB and assume that the only source of mismatch between Q1 and Q2 is a 2% mismatch in their W/L ratios. Let I = 200 μA and assume that all transistors are to be operated at VOV = 0.2 V. For the 0.18-μm CMOS fabrication process available, VA′ = 5 V/μm. If a simple current source is utilized for I, what channel length is required? If a cascode current source is utilized, what channel length is needed for the two transistors in the cascode?
Solution
A mismatch in W/L results in a gm mismatch that can be found from the expression of gm:
g CMRR= 2g R m
Now, a 100-dB CMRR corresponds to a ratio of 105; thus,
105 =2g R /0.01
The value of gm can be found from
Substituting in Eq. (9.90) gives
g = 2μ C W I m noxLD
(9.89)
It can be seen that an error of 2% in W/L will result in an error in gm of 1%. That is, the 2% mismatch in the W/L ratios of Q1 and Q2 will result in a 1% mismatch in their gm values. The resulting CMRR can be found from Eq. (9.88), repeated here:
mSS gm
m SS
gm=2ID =2×(I/2) VOV VOV
= 2×0.1 =1mA/V 0.2
(9.90)
RSS =500k
Now if the current source is implemented with a single transistor, its ro must be
ro =RSS =500k
Thus,
VA =500k I
9.3 Common-Mode Rejection 633
Substituting I = 200 μA, we find the required value of VA as VA = 100 V
Since VA = VA′ L = 5L, the required value of L will be
L = 20 μm
which is very large!
Using a cascode current source, we have
where
Thus,
and the required VA now becomes
RSS = gmro ro
gm = 2I = 2 × 0.2 = 2 mA/V
VOV 0.2 500=2×ro2
ro = 15.81 k
15.81 = VA = VA I 0.2
VA =3.16 V
which implies a channel length for each of the two transistors in the cascode of
L= 3.16 = 3.16 =0.63μm VA′ 5
a considerable reduction from the case of a simple current source, and indeed a practical value.
Differential versus Single-Ended Output The above study of common-mode rejection was predicated on the assumption that the output of the differential amplifier is taken differentially, that is, between the drains of Q1 and Q2. In some cases one might decide to take the output single-endedly; that is, between one of the drains and ground. If this is done, the CMRR is reduced dramatically. This can be seen from the above analysis, where the common-mode gain in the absence of mismatches is zero if the output is taken differentially and finite (Eq. 9.74) if the output is taken single-endedly. When mismatches are taken into account, the CM gain for the differential-output case departs from zero but remains much lower than the value obtained for single-ended output (Eq. 9.74).
634 Chapter 9 Differential and Multistage Amplifiers
We conclude that to obtain a large CMRR, the output of the differential amplifier must be taken differentially. The subject of converting the output signal from differential to single-ended without loss of CMRR will be studied in Section 9.5.
EXERCISE
9.13 Show that if the output of the MOS differential amplifier is taken single-endedly, the CMRR is given by:
CMRR = gm RSS
9.3.2 The BJT Case
An exactly similar development applies for studying the common-mode rejection of the BJT differential amplifier. Figure 9.26 shows a bipolar differential amplifier with an input common-mode signal vicm. Here REE is the output resistance of the bias current source I. We wish to find the voltages that result from v icm at the collectors of Q1 and Q2 , v o1 and v o2 , and between the two collectors, vod. Toward that end, we make use of the common-mode half-circuits shown in Fig. 9.26(b). The signal vo1 that appears at the collector of Q1 in response to vicm will be
vo1 =−
vo2 vicm
αRC vicm re +2REE
(9.91)
RC
RC
vo1 vicm
vod Q1
REE
(a)
RC
Q1
RC
Q2
vo1 vicm
2REE
Figure 9.26 (a) The differential amplifier fed by a common-mode input signal vicm. (b) Equivalent “half-circuits” for common-mode calculations.
vod
vo2
Q2 vicm
Biased
at I 2 2REE
(b)
Similarly, vo2 will be
vo2 =− αRC vicm re +2REE
(9.92)
A ≡ vod =− αRC cm vicm 2REE +re
Since α ≃ 1, re ≪ 2REE , Eq. (9.93) can be approximated and written in the form R R
Acm ≃ − C C 2REE RC
The common-mode rejection ratio can now be found from CMRR= |Ad|
|Acm| together with using Eqs. (9.68) and (9.94), with the result that
R
(9.93)
(9.94)
9.3 Common-Mode Rejection 635
where we have neglected the transistor ro, for simplicity. The differential output signal vod can be obtained as
vod =vo2 −vo1 =0
Thus, while the voltages at the two collectors will contain common-mode noise or interference components, the output differential voltage will be free from such interference. This condition, however, is based on the assumption of perfect matching between the two sides of the differentialamplifier.Anymismatchwillresultinvod acquiringacomponentproportionalto vicm.Forexample,amismatchRC betweenthetwocollectorresistancesresultsin
CMRR = (2gm REE )
C
(9.95)
which is similar in form to the expression for the MOS pair [Eq. (9.83)]. Thus, to obtain a highCMRR,wedesignthecurrentsourcetohavealargeoutputresistanceREE andstrivefor close matching of the collector resistances.
Common-Mode Input Resistance The definition of the common-mode input resistance Ricm is illustrated in Fig. 9.27(a). Figure 9.27(b) shows the equivalent common-mode half-circuit; its input resistance is 2Ricm. The value of 2Ricm can be determined by analyzing the circuit of Fig. 9.27(b) while taking ro into account (because REE and RC can be equal to, or larger than, ro). The analysis is straightforward but tedious and can be shown (Problem 9.79) to yield the following result
R ≃βR 1+RC/βro (9.96) icm EE RC +2REE
RC
1+ ro
636 Chapter 9
Differential and Multistage Amplifiers
Q1
REE
Q2 vicm
vicm +–
2REE
2Ricm
Figure 9.27 (a) Definition of the input common-mode resistance Ricm. (b) The equivalent common-mode
half-circuit.
Example 9.5
For the differential amplifier analyzed in Example 9.3, let the bias-current source have an output resistance REE = 200 k. Evaluate:
(a) the worst-case common-mode gain if the two collector resistances are accurate to within ±1%. (b) the CMRR in dB.
(c) the input common-mode resistance (assuming the Early voltage VA = 100 V).
Solution
FirstweobservethatthetwoemitterresistancesRE willhavenegligibleeffectonAcm. (a) Using Eq. (9.94),
|Acm|= RC △RC 2REE RC
where △RC = 0.02 RC in the worst case. Thus,
|Acm|= 10 ×0.02=5×10−4 V/V
Ricm
(b)
(b)
2×200
CMRR=20log |Ad| |Acm|
where from Example 9.3, |Ad | = 40, thus
CMRR = 20 log 40 = 98 dB 5×10−4
(c)
EXERCISE
ro=VA =100=200k I/2 0.5
Rin =6.6M
Using Eq. (9.96),
9.4 DC Offset 637
9.14 Abipolardifferentialamplifierutilizesasimple(i.e.,asingleCEtransistor)currentsourcetosupplya
bias current I of 200 μA, and simple current-source loads formed by pnp transistors. For all transistors,
β=100andV =10V.Findg ,R ,A ,R ,R ,CMRR(ifthetwoloadtransistorsexhibita1% A m C d id EE
mismatch in their ro’s), and Ricm. Hint: Remember to take into account ro1 and ro2. Ans. 4 mA/V; 100 k; 200 V/V; 50 k, 50 k; 86 dB; 1.67 M
9.4 DC Offset
Because differential amplifiers are directly coupled and have finite gain at dc, they suffer from a number of dc problems. In this section we study some of these.
9.4.1 Input Offset Voltage of the MOS Differential Amplifier
Consider the basic MOS differential amplifier with both inputs grounded, as shown in Fig. 9.28(a). If the two sides of the differential pair were perfectly matched (i.e., Q1 and Q2 identical and RD1 = RD2 = RD ), then current I would split equally between Q1 and Q2 , and VO would be zero. But practical circuits exhibit mismatches that result in a dc output voltage VO even with both inputs grounded. We call VO the output dc offset voltage. More commonly, we divide VO by the differential gain of the amplifier, Ad , to obtain a quantity known as the input offset voltage, VOS ,
VOS =VO/Ad (9.97)
Wecanseethatifweapplyavoltage−VOS betweentheinputterminalsofthedifferential amplifier, then the output voltage will be reduced to zero [see Fig. 9.28(b)]. This observation gives rise to the usual definition of the input offset voltage. It should be noted, however, that since the offset voltage is a result of device mismatches, its polarity is not known a priori.
Three factors contribute to the dc offset voltage of the MOS differential pair: mismatch in load resistances, mismatch in W/L, and mismatch in Vt. We shall consider the three contributing factors one at a time.
638 Chapter 9
Differential and Multistage Amplifiers
RD1
VDD
0V
I
RD2
Q1
Q2
VOS
(a)
(b)
Figure 9.28 (a) The MOS differential pair with both inputs grounded. Owing to device and resistor mismatches, a finite dc output voltage VO results. (b) Application of a voltage equal to the input offset voltage VOS to the input terminals with opposite polarity reduces VO to zero.
For the differential pair shown in Fig. 9.28(a) consider first the case where Q1 and Q2 are perfectly matched but RD1 and RD2 show a mismatch RD; that is,
RD1 = RD + RD (9.98) 2
RD2 = RD − RD (9.99) 2
Because Q1 and Q2 are matched, the current I will split equally between them. Nevertheless, because of the mismatch in load resistances, the output voltages VD1 and VD2 will be
I R VD1 = VDD − RD + D
22 Thus the differential output voltage VO will be
VO = VD2 − VD1 I
= 2 RD
(9.100)
2 2 VD2=VDD−I RD−RD
The corresponding input offset voltage is obtained by dividing VO by the gain gmRD and substituting for gm from Eq. (9.30). The result is
V R
VOS = OV D (9.101) 2 RD
Thus the offset voltage is directly proportional to VOV and, of course, to RD/RD. As an example, consider a differential pair in which the two transistors are operating at an overdrive voltage of 0.2 V and each drain resistance is accurate to within ±1%. It follows that the worst-case resistor mismatch will be
RD =0.02 RD
and the resulting input offset voltage will be |VOS|=0.1×0.02=2mV
=L+2 L (9.102)
=W−1 W (9.103) L2L2L
Such a mismatch causes the current I to no longer divide equally between Q1 and Q2. Rather, because VGS1 = VGS2, the current conducted by each of Q1 and Q2 will be proportional to its
9.4 DC Offset 639
Next, consider the effect of a mismatch in the W/L ratios of Q1 and Q2, expressed as W W 1W
L
1 W
W/L ratio, and we can easily show that
I (W/L)
I1 = 2 1 + 2(W/L) I (W/L)
I (W/L)
(9.104) (9.105)
(9.106)
HereagainwenotethatVOS,resultingfroma(W/L)mismatch,isproportionaltoVOV and,as expected, (W/L).
Finally,weconsidertheeffectofamismatchVt betweenthetwothresholdvoltages,
I2 = 2 1 − 2(W/L)
Dividing the current difference,
2 (W/L)
by gm gives the input offset voltage (due to the mismatch in W/L values).2 Thus
V (W/L) VOS = OV
2 (W/L)
Vt1 = Vt + Vt 2
Vt2 = Vt − Vt 2
(9.107) (9.108)
The current I1 will be given by
1 W V2 I1=kn′ VGS−Vt− t
2L2
1W V2 =kn′(VGS−Vt)21− t
2 L 2(VGS−Vt)
2We are skipping a step in the derivation: Rather than multiplying the current difference by RC and dividing the resulting output offset by Ad = gm RC , we are simply dividing the current difference by gm .
640 Chapter 9
Differential and Multistage Amplifiers
which,forVt ≪2(VGS –Vt)(thatis,Vt ≪2VOV),canbeapproximatedas
Similarly,
We recognize that
2L2 and the current increment (decrement) in Q2 (Q1) is
I = I Vt = I Vt 2 VGS − Vt 2 VOV
Dividing the current difference 2I by gm gives the input offset voltage (due to Vt ). Thus, VOS =Vt (9.109)
a very logical result! For modern MOS technology Vt can be as high as a few mV. Finally, we note that since the three sources for offset voltage are not correlated, an estimate of the total input offset voltage can be found as
1W V I1≃kn′ (VGS−Vt)21− t
2L VGS−Vt
1W V I2≃kn′ (VGS−Vt)21+ t
2L VGS−Vt 1kn′ W(VGS −Vt)2 = I
V R 2 V (W/L)2 VOS = OV D + OV
2 RD 2 W/L
+(Vt)2 (9.110)
EXERCISE
9.15 For the MOS differential pair specified in Exercise 9.4, find the three components of the input offset voltage. Let RD /RD = 2%, (W/L )/(W/L ) = 2%, and Vt = 2 mV. Use Eq. (9.110) to obtain an estimate of the total VOS .
Ans. 2mV;2mV;2mV;3.5mV
9.4.2 Input Offset Voltage of the Bipolar Differential Amplifier
The offset voltage of the bipolar differential pair shown in Fig. 9.29(a) can be determined in a manner analogous to that used above for the MOS pair. Note, however, that in the bipolar casethereisnoanalogtotheVt mismatchoftheMOSFETpair.Heretheoutputoffsetresults from mismatches in the load resistances RC 1 and RC 2 and from junction area, β , and other mismatches in Q1 and Q2. Consider first the effect of the load mismatch. Let
RC1 = RC + RC (9.111) 2
RC2 = RC − RC (9.112) 2
VCC VCC
RC1 RC2 RC1 RC2
9.4 DC Offset 641
VO 0 V
B1
Q1 Q2
B2
Q1
Q2
VOS
II
(a)
(b)
Figure9.29 (a)TheBJTdifferentialpairwithbothinputsgrounded.Devicemismatchesresultinafinitedc outputVO.(b)ApplicationoftheinputoffsetvoltageVOS ≡VO/Ad totheinputterminalswithoppositepolarity reduces VO to zero.
and assume that Q1 and Q2 are perfectly matched. It follows that current I will divide equally between Q1 and Q2, and thus
αI R VC1 =VCC − RC + C
2 2 VC2=VCC− αI RC−RC
22
Thus the output voltage will be
VO=VC2−VC1=α 2 (RC)
and the input offset voltage will be
SubstitutingAd =gmRC and
gives
I VOS = α(I/2)(RC)
Ad
gm = αI/2 VT
(9.113)
(9.114)
R |V |=V C
OS T RC
An important point to note is that in comparison to the corresponding expression for the MOS
pair (Eq. 9.101) here the offset is proportional to VT rather than VOV /2. VT at 25 mV is 3 to 6 times lower than VOV /2. Hence bipolar differential pairs exhibit lower offsets than their MOS
642 Chapter 9
Differential and Multistage Amplifiers
counterparts. As an example, consider the situation of collector resistors that are accurate to within ±1%. Then the worst-case mismatch will be
RC = 0.02 RC
and the resulting input offset voltage will be |VOS|=25×0.02=0.5mV
Next consider the effect of mismatches in transistors Q1 and Q2. In particular, let the transistors have a mismatch in their emitter–base junction areas. Such an area mismatch gives rise to a proportional mismatch in the scale currents IS ,
IS1 = IS + IS (9.115) 2
IS2 = IS − IS (9.116) 2
Refer to Fig. 9.29(a) and note that VBE1 = VBE2. Thus, the current I will split between Q1 and Q2 in proportion to their IS values, resulting in
I I
IE1= 1+ S (9.117)
2 2IS
I I
IE2= 1− S (9.118)
2 2IS It follows that the output offset voltage will be
II VO=α SRC
2 IS and the corresponding input offset voltage will be
I
|V|=V S (9.119)
As an example, an area mismatch of 4% gives rise to IS /IS = 0.04 and an input offset voltage of 1 mV. Here again we note that the offset voltage is proportional to VT rather than to the much larger VOV , which determines the offset of the MOS pair due to (W/L) mismatch.
Since the two contributions to the input offset voltage are usually not correlated, an estimate of the total input offset voltage can be found as
(9.120)
There are other possible sources for input offset voltage such as mismatches in the values of β and ro. Some of these are investigated in the end-of-chapter problems. Finally, it should be noted that there is a popular scheme for compensating for the offset voltage. It involves introducing a deliberate mismatch in the values of the two collector resistances such that the differential output voltage is reduced to zero when both input terminals are grounded. Such an offset-nulling scheme is explored in Problem 9.81.
OS T IS
R2 I2 V=VC+VS
OS TR TI CS
R 2 I 2 =V C + S
T RC IS
9.4.3 Input Bias and Offset Currents of the Bipolar Differential Amplifier
In a perfectly symmetric bipolar differential pair, the two input terminals carry equal dc currents; that is,
IB1 = IB2 = I/2 (9.121) β+1
This is the input bias current of the differential amplifier.
Mismatches in the amplifier circuit and most importantly a mismatch in β make the two
input dc currents unequal. The resulting difference is the input offset current, IOS , given as
Let
then
Formally, the input bias current IB is defined as follows: IB≡IB1+IB2 = I
Thus
IOS =|IB1 −IB2| β1 = β + β
2
β2 = β − β 2
(9.122)
(9.123) (9.124) (9.125)
(9.126)
(9.127)
9.4 DC Offset 643
I 1 I1β IB1=2β+1+β/2≃2β+1 1−2β
I 1 I1β IB2=2β+1−β/2≃2β+1 1+2β
I β IOS=2(β+1) β
2 2(β+1) β
IOS =IB β
As an example, a 10% β mismatch results in an offset current that is one-tenth the value of the input bias current.
Finally note that a great advantage of the MOS differential pair is that it does not suffer from a finite input bias current or from mismatches thereof!
EXERCISE
9.16 For a BJT differential amplifier utilizing transistors having β = 100, matched to 10% or better, and areas that are matched to 10% or better, along with collector resistors that are matched to 2% or better, find VOS, IB, and IOS. The dc bias current I is 100 μA.
Ans. 2.55 mV; 0.5 μA; 50 nA
644 Chapter 9
Differential and Multistage Amplifiers
9.4.4 A Concluding Remark
We conclude this section by noting that the definitions presented here are identical to those presented in Chapter 2 for op amps. In fact, as will be seen in Chapter 13, it is the input differential stage in an op-amp circuit that primarily determines the op-amp dc offset voltage, input bias and offset currents, and input common-mode range.
9.5 The Differential Amplifier with a Current-Mirror Load
The differential amplifiers we have studied thus far have been of the differential output variety; that is, the output is taken between the two drains (or two collectors) rather than between one of the drains (collectors) and ground. Taking the output differentially has three major advantages:
1. It decreases the common-mode gain and thus increases the common-mode rejection ratio (CMRR). Recall that while the drain (collector) voltages change somewhat in response to a common-mode input signal, the difference between the drain (collector) voltages remains essentially zero except for a small change due to the mismatches inevitably present in the circuit.
2. It decreases the input offset voltage.
3. It increases the differential gain by a factor of 2 (6 dB) because the output is the
difference between two voltages of equal magnitude and opposite sign.
These advantages are sufficiently compelling that at least the first stage in an IC amplifier such as an op amp is differential-in, differential-out. The differential transmission of the signal on the chip also minimizes its susceptibility to corruption with noise and interference, which usually occur in a common-mode fashion. Nevertheless, it is usually required at some point to convert the signal from differential to single-ended; for instance, to connect it to an off-chip load. Figure 9.30 shows a block diagram of a three-stage amplifier in which the first two stages are of the differential-in, differential-out type, and the third has a single-ended output, that is, an output that is referenced to ground. We now address the question of conversion from differential to single-ended.
vid A1 A2 A3
vo
Figure 9.30 A three-stage amplifier consisting of two differential-in, differential-out stages, A1 and A2 , and a differential-in, single-ended-out stage A3.
9.5.1 Differential-to-Single-Ended Conversion
Figure 9.31 illustrates the simplest, most basic approach for differential-to-single-ended conversion. It consists of simply ignoring the drain current signal of Q1 and eliminating its drain resistor altogether, and taking the output between the drain of Q2 and ground. The
VDD
RD
vo
9.5 The Differential Amplifier with a Current-Mirror Load 645
vid 2 Q
Q
vid 2
12
I
VSS
Figure 9.31 A simple but inefficient approach for differential-to-single-ended conversion.
obvious drawback of this scheme is that we lose a factor of 2 (or 6 dB) in gain as a result of “wasting” the drain signal current of Q1. A much better approach would be to find a way of utilizing the drain current signal of Q1, and that is exactly what the circuit we are about to discuss accomplishes.
9.5.2 The Current-Mirror-Loaded MOS Differential Pair
Figure 9.32(a) shows a MOS differential pair formed by transistors Q1 and Q2 , loaded by a current mirror formed by transistors Q3 and Q4 . To see how this circuit operates, consider first the quiescent or equilibrium state with the two input terminals connected to a dc voltage equal to the common-mode equilibrium value, in this case 0 V, as shown in Fig. 9.32(b). Assuming perfect matching, the bias current I divides equally between Q1 and Q2. The drain current of Q1 , I /2, is fed to the input transistor of the mirror, Q3 . Thus, a replica of this current is provided by the output transistor of the mirror, Q4. Observe that at the output node the two currents I/2 balance each other out, leaving a zero current to flow out to the next stage or to a load (not shown). This is obviously the desired result! Further, if Q4 is perfectly matched to Q3 , its drain voltage will track the voltage at the drain of Q3; thus in equilibrium the voltage at the output will be VDD −VSG3. It should be noted, however, that in practical implementations, there will always be mismatches, resulting in a net dc current at the output. In the absence of a load resistance, this current will flow into the output resistances of Q2 and Q4 and thus can cause a large deviation in the output voltage from the ideal value. Therefore, this circuit is always designed so that the dc bias voltage at the output node is defined by a feedback circuit rather than by simply relying on the matching of Q4 and Q3. We shall see how this is done later.
Next,considerthecircuitwithadifferentialinputsignalvid appliedtotheinput,asshown in Fig. 9.32(c). Since we are now investigating the small-signal operation of the circuit, we have removed the dc supplies (including the current source I). Also, for the time being let us
ignorer ofalltransistors.AsFig.9.32(c)shows,acurrentiflowsthroughQ andQ,given o 2 1 2
. Thus, transistor Q1 will conduct a drain signal current i = gm1vid/2, and transistor Q2 will conduct an equal but opposite current i. The drain signal current i of Q1 is
by i = vid g
m
646
Chapter 9
Differential and Multistage Amplifiers
VDD
Q3
Q4
VDD
Q3 Q4 vO I2
VSG3
I2
Q1 Q2
I2 I2 I
VO VDD VSG3
vG1
vG2
I20
Q1 Q2
I
VSS
(a)
(b)
Q3
Q4
2i
i
i
i
Q1 Q2
vo
vid 2
vid 2
i=vid (g2) m
(c)
Figure 9.32 (a) The current-mirror-loaded MOS differential pair. (b) The circuit at equilibrium assuming perfect matching. (c) The circuit with a differential input signal applied and neglecting the ro of all transistors.
fedtotheinputoftheQ3−Q4 mirror,whichrespondsbyprovidingareplicainthedrainofQ4. Now, at the output node we have two currents, each equal to i, which sum together to provide an output current 2i. It is this factor of 2, which is a result of the current-mirror action, that makes it possible to convert the signal to single-ended form (i.e., between the output node and ground) with no loss of gain! If a load resistance is connected to the output node, the current 2i flows through it and thus determines the output voltage vo. In the absence of a load resistance, the output voltage is determined by the output current 2i and the output resistance of the circuit, as we shall shortly see.
Before immersing ourselves in detailed analysis of the circuit, it is important to understand the essence of its operation: For dc quantities and common-mode inputs, the current-mirror load produces an output current in the drain of Q4 that cancels the current of Q2. On the other hand, for differential input signals, the output current of the mirror adds to the current of Q2.
9.5 The Differential Amplifier with a Current-Mirror Load 647 9.5.3 Differential Gain of the Current-Mirror-Loaded MOS Pair
As we learned in Chapter 8, the output resistance ro of the transistor plays a significant role in the operation of active-loaded amplifiers. Therefore, we shall now take ro into account and derive an expression for the differential gain v o /v i d of the current-mirror-loaded MOS differential pair. Toward that end, we first observe that the circuit is not symmetrical: While the drain of Q1 sees the small resistance of the diode-connected transistor Q3 (approximately equal to 1/gm3), the drain of Q2 sees the much larger output resistance of Q4 (ro4). Thus, a virtual ground will not develop at the common sources3 and we cannot use the differential half-circuit technique.
Our approach will be to represent the output of the circuit in Fig. 9.32(c) by the general equivalent circuit shown in Fig. 9.33. Here Gm is the short-circuit transconductance and Ro is the output resistance. In the following, we will show that
Gm = gm1,2 (9.128) where gm1,2 is the transconductance of each of Q1 and Q2. We will also show that
Ro =ro2∥ro4 (9.129)
In other words, we shall have two intuitively appealing results: The short-circuit transcon- ductance of the circuit is equal to gm of each of the two transistors of the differential pair, and the output resistance is the parallel equivalent of the output resistances of Q2 and Q4. Thus, the open-circuit differential voltage gain can be found as
A≡vo=GR=g (r∥r) d vid m o m1,2 o2 o4
Writing gm1,2 simply as gm , and for the case ro2 = ro4 = ro , Ad = 1 gmro = 1 A0
22 where A0 is the intrinsic gain of the MOS transistor.
vo
(9.130)
(9.131)
Gm vid
Ro
Figure9.33 Outputequivalentcircuitoftheamplifierin Fig. 9.32(a) for differential input signals.
3The qualitative description of circuit operation above implied that a virtual ground develops at the MOSFET sources. That was the case because we were neglecting ro of all transistors.
648 Chapter 9 Differential and Multistage Amplifiers
EXERCISE
9.17 A current-mirror-loaded MOS differential amplifier of the type shown in Fig. 9.32(a) is specified as follows: (W/L)n = 100, (W/L)p = 200, μnCox = 2μpCox = 0.2 mA/V2, VAn = |VAp| = 20 V, and I = 0.8 mA. Calculate Gm, Ro, and Ad.
Ans. 4 mA/V; 25 k; 100 V/V
Derivation of the Short-Circuit Transconductance, Gm Figure 9.34(a) shows the current-mirror-loaded MOS amplifier with the output terminal short-circuited to ground. Our purpose is to determine the short-circuit transconductance
G ≡ io m vid
We note that short-circuiting the output terminal makes the circuit nearly balanced. This is because the drain of Q1 sees the small resistance of the diode-connected transistor Q3, and now the drain of Q2 sees a short circuit. It follows that the voltage at the MOSFET sources will be approximately zero. Now, replacing each of the four transistors with its hybrid-π model and noting that for the diode-connected transistor Q3, the model reduces to a resistance (1/gm3 ∥ ro3 ), we obtain the equivalent circuit shown in Fig. 9.34(b). The short-circuit output current io can be found by writing a node equation at the output and noting that the currents in ro2 and ro4 are zero; thus
vid
io = gm2 2 − gm4 vgs4
Next, we note that
and vgs3 can be obtained from a node equation at d1 as
(9.132) (9.133)
vgs3 =−gm1 2 g
1 ≪ ro3, ro1, reduces to
vgs4 = vgs3 vid 1
∥ro3∥ro1 gm1 vid
which for the usual case of
gm3
(9.134) Combining Eqs. (9.132) to (9.134) and substituting gm3 = gm4 and gm1 = gm2 = gm gives
m3
vgs3 ≃−gm3 2 io =gmvid
from which Gm is found to be as expected.
Gm =gm
Derivation of the Output Resistance Ro Figure 9.35 shows the circuit4 for determining
the output resistance Ro . Observe that we have set v i d to zero, resulting in the ground
4 Note that rather than replacing each transistor with its small-signal model, we are, for simplicity, using the models implicitly. Thus we have “pulled ro out” of each transistor and shown it separately so that the drain current becomes gmvgs.
9.5
The Differential Amplifier with a Current-Mirror Load 649
vgs3 = vgs4
Q3 Q4
io
vid 22
vid
Q1 Q
2
(g1 ro3) m3
0 V (a)
g3 ,g4
vgs3 = vgs4
gm4 vgs4
ro4 0
io
g1d1 g2 0
vid/2 g (vid) ro1 ro2 g (vid) vid/2 m1 2 m2 2
(b)
Figure 9.34 Derivation of the short-circuit transconductance Gm ≡ io /v i d .
connections at the gates of Q1 and Q2. We have applied a test voltage vx in order to
determine Ro,
Ro ≡ vx ix
Analysis of this circuit is considerably simplified by observing the current transmission around the circuit by simply following the circled numbers. The current i that enters Q2 must exit at its source. It then enters Q1, exiting at the drain to feed the Q3−Q4 mirror. Since for the diode-connected transistor Q3, 1/gm3 is much smaller than ro3, most of the current i flows into the drain proper of Q3. The mirror responds by providing an equal current i in the drain of Q4. The relationship between i and vx can be determined by observing that at the output node
i=vx/Ro2
650 Chapter 9
Differential and Multistage Amplifiers
ro3 Q3
1 gm3
Q4 ro4 i
ix i1
vx Ro
1 gm3
i4
5 i3 Ro2
Q1 ro1 ro2 Q2
i2
Rin1
Figure 9.35 Circuit for determining Ro. The circled numbers indicate the order of the analysis steps.
where Ro2 is the output resistance of Q2. Now, Q2 is a CG transistor and has in its source lead the input resistance Rin1 of the CG transistor Q1. Noting that the load resistance of Q1 is [(1/gm3)∥ro3], which is approximately 1/gm3, we can obtain Rin1 by using the expression for the input resistance of a CG transistor (Eq. 8.53),
Rin1 = ro1 +RL gm1 ro1
= 1 + 1/gm3 ≃ 1 gm1 gm1 ro1 gm1
We then use this value of Rin1 to determine Ro2 utilizing the expression in Eq. (8.60) as follows: Ro2 =Rin1 +ro2 +gm2ro2Rin1
(9.135)
g = 1 +ro2+ m2 ro2
gm1 gm1 which, for gm1 = gm2 = gm and gm2 ro2 ≫ 1, yields
Ro2 ≃ 2ro2
Returning to the output node, we write
ix =i+i+ vx ro4
=2i+vx =2vx +vx ro4 Ro2 ro4
Substituting for Ro2 from Eq. (9.135), we obtain
ix=2vx +vx 2ro2 ro4
Thus,
which is the result we stated earlier.
Ro≡vx =ro2∥ro4 (9.136) ix
9.5 The Differential Amplifier with a Current-Mirror Load 651
9.5.4 The Bipolar Differential Pair with a Current-Mirror Load
The bipolar version of the active-loaded differential pair is shown in Fig. 9.36(a). The circuit structure and operation are very similar to those of its MOS counterpart except that here we have to contend with the effects of finite β and the resulting finite input resistance at the base, rπ . For the time being, however, we shall ignore the effect of finite β on the dc bias of the four transistors and assume that in equilibrium all transistors are operating at a dc current of I/2.
Differential Gain To obtain an expression for the differential gain, we use an approach identical to that employed above for the MOS case. That is, we represent the output of the amplifier with the equivalent circuit shown in Fig. 9.36(b) and show that the short-circuit transconductance Gm is given by
Gm = gm1,2 (9.137) where gm1,2 denotes gm of each of Q1 and Q2, and that the output resistance Ro is given by
Ro =ro2∥ro4 (9.138) Both these results are identical to those for the MOS case and can be similarly derived.
VCC
Q3
Q4
Q2
vO
vB1
Q1
vB2
vo
I
VEE
(a)
Gm vid
Ro
Figure 9.36 (a) Current-mirror-loaded bipolar differential pair. (b) Small-signal equivalent circuit of the amplifier output when a differential signal vi d ≡ vB1 − vB2 is applied.
(b)
652 Chapter 9
Differential and Multistage Amplifiers
Equations (9.137) and (9.138) can now be combined to obtain the differential gain,
A ≡ vo =G R =g (r ∥r ) d vid m o m o2 o4
wheregm =gm1 =gm2 ≃ VT ,andsincero2 =ro4 =ro,wecansimplifyEq.(9.139)to I/2
Ad = 1gmro 2
(9.139)
(9.140)
Although this expression is identical to that found for the MOS circuit, the gain here is much larger because gmro for the BJT is more than an order of magnitude greater than gmro of a MOSFET. The downside, however, lies in the low input resistance of BJT amplifiers. Indeed, from the circuit in Fig. 9.36(a), we can see that the differential input resistance is equal to 2rπ ,
Rid =2rπ (9.141)
in sharp contrast to the infinite input resistance of the MOS amplifier. Thus, while the voltage gain realized in a current-mirror-loaded BJT amplifier stage is large, when a subsequent BJT stage is connected to the output, its inevitably low input resistance will drastically reduce the overall voltage gain.
EXERCISE
9.18 For the current-mirror-loaded BJT differential amplifier let I = 0.8 mA, VA = 100 V, and β = 160. Find Gm, Ro, Ad, and Rid.
Ans. 16 mA/V; 125 k; 2000 V/V; 20 k
Systematic Input Offset Voltage In addition to the random offset voltages that result from the mismatches inevitably present in the differential amplifier, the current-mirror-loaded bipolar differential pair suffers from a systematic offset voltage that has no counterpart in the MOS version. This is due to the error in the current transfer ratio of the current-mirror load caused by the finite β of the pnp transistors that make up the mirror. To see how this comes about, refer to Fig. 9.37. Here the inputs are grounded and the transistors are assumed to be perfectly matched. Thus, the bias current I will divide equally between Q1 and Q2, with the result that their two collectors conduct equal currents of αI/2. The collector current of Q1 is fed to the input of the current mirror. From Section 8.2 we know that the current transfer ratio of the mirror is
I4 = 1 (9.142) I3 1+2
βP
where βP is the value of β of the pnp transistors Q3 and Q4. Thus the collector current of Q4
will be
I4 = αI/2 (9.143)
1+2 βP
Q3
Q1
I
VCC
aI 2 2
1
Q4
Q2
9.5 The Differential Amplifier with a Current-Mirror Load 653
aI 2
bP aI 2
i
I2 I2
Figure9.37 Thecurrent-mirror-loadedBJTdif- ferential pair suffers from a systematic input offset voltage resulting from the error in the current transfer ratio of the current mirror.
which does not exactly balance the collector current of Q2 . It follows that the current difference i will flow into the output terminal of the amplifier with
i=αI− αI/2 21+2
βP = αI 2/βP
21+2 βP
VOS =−i Gm
Substituting for i from Eq. (9.144) and for Gm = gm = (αI/2)/VT , we obtain for the input offset voltage the expression
VOS=−αI/βP =−2VT (9.145) αI/2VT βP
As an example, for βP = 50, VOS = −1 mV. To reduce VOS , an improved current mirror such as the Wilson circuit studied in Section 8.6.2 should be used. Such a circuit provides the added advantage of increased output resistance and hence voltage gain. However, to realize the full advantage of the higher output resistance of the active load, the output resistance of the differential pair should be raised by utilizing a cascode stage. Figure 9.38 shows such an arrangement: A folded cascode stage formed by pnp transistors Q3 and Q4 is utilized to
≃ αI βP
(9.144) To reduce this output current to zero, an input voltage VOS has to be applied with a value of
654 Chapter 9
Differential and Multistage Amplifiers
VCC
II
Q1
vid
Q3
Q4
Q5
Q7
Q2
VBIAS
vo
I
Q6
VEE
Figure 9.38 An current-mirror-loaded bipolar differential amplifier employing a folded cascode stage (Q3 and Q4) and a Wilson current-mirror load (Q5, Q6, and Q7).
raise the output resistance looking into the collector of Q4 to β4ro4. A Wilson mirror formed by transistors Q5 , Q6 , and Q7 is used to implement the active load. From Section 8.6.2 we know that the output resistance of the Wilson mirror (i.e., looking into the collector of Q5) is β5(ro5/2). Thus the output resistance of the amplifier is given by
ro5
Ro = β4ro4∥β5 2 (9.146)
The transconductance Gm remains equal to gm of Q1 and Q2 . Thus the differential voltage gain
becomes
ro5
Ad =gm β4ro4∥β5 2 (9.147)
which can be very large. Further examples of improved-performance differential amplifiers will be studied in Chapter 13.
EXERCISE
9.19 Find Gm, Ro4, Ro5, Ro, and Ad for the differential amplifier in Fig. 9.38 under the following conditions: I=1mA,βP =50,βN =100,andVA =100V.
Ans. 20mA/V;10M;10M;5M;105 V/Vor100dB
9.5.5 Common-Mode Gain and CMRR
Although the output is single ended, the current-mirror-loaded differential amplifier has a low common-mode gain (ideally zero) and, correspondingly, a high CMRR (ideally infinite). This is due to the action of the current mirror, whose output current, for common-mode inputs, cancels the current of Q2 of the differential pair. We have, in fact, seen this in our initial qualitative description of circuit operation.
The current transfer ratio of the mirror, however, will never be exactly unity, and thus the current cancellation at the output node will never be perfect. As a result, the common-mode gain will be finite. We wish to derive an expression for Acm.
Figure 9.39(a) shows the circuit with vicm applied and with the power supplies eliminated except,ofcourse,fortheoutputresistanceRSS ofthebias-currentsourceI.Althoughthecircuit is not symmetrical and hence we cannot use the common-mode half-circuit, we can split RSS equally between Q1 and Q2 as shown in Fig. 9.39(b). It can now be seen that each of Q1 and Q2 is a CS transistor with a large source-degeneration resistance 2RSS .
Each of Q1 and Q2 together with their degeneration resistances can be replaced by equivalent circuits composed of a controlled source Gmcmvicm and an output resistance Ro1,2, as shown in Fig. 9.39(c). To determine Gmcm we short-circuit the drain to ground, as shown in Fig. 9.39(d) for Q1. Observe that 2RSS and ro1 appear in parallel. Thus the voltage at the source terminal can be found from the voltage divider consisting of 1/gm1 and (2RSS ∥ro1) as
v =v (2RSS∥ro1)
which leads to
2RSS G ≡ io
2RSS
= 1 (9.148)
s
icm (2RSS ∥ro1)+(1/gm1) ≃ vicm
The short-circuit drain current io can be seen to be equal to the current through 2RSS ; thus, io=vs ≃vicm
9.5 The Differential Amplifier with a Current-Mirror Load 655
mcm vicm
The output resistance Ro1 can be determined using the expression for Ro of a CS transistor
2RSS with an emitter-degeneration resistance (Eq. 8.60) to obtain
Ro1 =2RSS +ro1 +(gm1ro1)(2RSS) (9.149) Similar results can be obtained for Q2, namely, the same Gmcm and an output resistance Ro2
given by
Ro2 =2RSS +ro2 +(gm2ro2)(2RSS) (9.150)
Returning to the circuit in Fig. 9.39(c), we see that the current mirror is represented by its input resistance Rim , current gain Am , and output resistance Rom . This is a general representation that applies for any current mirror. As current mirrors have relatively low input resistances, Rim will be much lower than Ro1 with the result that the input current of the mirror i1 will be
ii ≃ Gmcmvicm (9.151) The output voltage can be obtained by writing a node equation at the output,
vo = (Amii − Gmcmvicm)(Rom ∥Ro2) (9.152)
656 Chapter 9
Differential and Multistage Amplifiers
Q3
Q4
Q3
Q4
vo vicm
Rim
2RSS
ii Q1
Rom vo
vicm
vicm
Q2
vicm
Q Q2
1
2RSS
RSS
(a)
(b)
1 gm1
io
Ro1
Rom
Current Mirror
Ro1
vicm
Q3
2RSS
ro1
vs
Rim
Amii
ii voio
Gmcmvicm
Gmcmvicm
(c)
Ro2
Figure 9.39 Analysis of the current-mirror-loaded MOS differential amplifier to determine its common-mode gain.
Substituting for ii from Eq. (9.151) results in the following expression for the common-mode gain:
Acm ≡ vo =−(1−Am)Gmcm(Rom∥Ro2) (9.153) vicm
This is a general expression that applies for any implementation of the current mirror. The expression makes clear that Acm results from the deviation from unity of the current gain of the mirror.
(d)
9.5 The Differential Amplifier with a Current-Mirror Load 657 For the simple current mirror utilized in the circuit of Fig. 9.39(a),
Rim = 1 ∥ro3 gm3
(9.154)
(9.155)
and
The current gain Am can be found as follows
but
Thus
Rom = ro4
Am ii = −gm4 vgs4 = −gm4 vgs3
vgs3 =−iiRim Am =gm4Rim
Substituting for Rim from (9.154) together with using gm4 = gm3 results in
m3 o3
from (9.155), and noting that ro4 ≪ Ro2, ro4 = ro3, and gmro3 ≪ 1, gives for Acm the expression, Acm ≃ − 1 (9.157)
2gm3 RSS
Since RSS is usually large, at least equal to ro, Acm will be small. The common-mode rejection
1 Am=1 1+g r
(9.156) Finally, substituting in Eq. (9.153) for Am from (9.156), for Gmcm from (9.148), and for Rom
ratio (CMRR) can now be obtained by utilizing Eqs. (9.130) and (9.157),
CMRR≡ |Ad| =[gm(ro2∥ro4)][2gm3RSS] (9.158)
|Acm|
which for ro2 = ro4 = ro and gm3 = gm simplifies to
CMRR = (gm ro )(gm RSS ) (9.159)
We observe that to obtain a large CMRR, we select an implementation of the biasing current source I that features a high output resistance. Such circuits include the cascode current source and the Wilson current source studied in Section 8.6.
EXERCISE
9.20 For the current-mirror-loaded MOS differential amplifier specified in Exercise 9.17, let R Calculate A and CMRR. Use the results of Exercise 9.17.
cm
Ans. 0.005 V/V; 20,000 or 86 dB
SS
= 25 k.
658 Chapter 9
Differential and Multistage Amplifiers
The Bipolar Case To obtain Acm and CMRR for the BJT circuit of Fig. 9.36(a) we can use the expression in Eq. (9.153) with
Gmcm= 1 2REE
Rim = 1 ∥rπ3∥ro3∥rπ4 gm3
which for ro3 ≫ rπ3 and rπ4 = rπ3 yields
Rim ≃ 1 ∥ 2
gm3 rπ3 Rom = ro4
(9.160) (9.161)
(9.162) (9.163) (9.164)
(9.165)
(9.166)
(9.167)
and
Assuming gm4 = gm3 and utilizing ro4 ≫ Ro2 , we obtain
2 Acm ≃− ro4 rπ3
2REE gm3 + 2 rπ3
≃− ro4 2 =− ro4 2REE β3 β3REE
UsingAd fromEq.(9.139)enablesustoobtaintheCMRRas
Am =gm4Rim
|A| CMRR ≡ d
|Ac m |
CMRR = 1β3gmREE
2
βR 3 EE
ro4
= gm(ro2 ∥ro4)
Forro2 =ro4 =ro,
from which we observe that to obtain a large CMRR, the circuit implementing the bias current source should have a large output resistance REE . This is possible with, say, a Wilson current mirror (Section 8.6.2).
In conclusion, it is useful to reflect once more on the origin of the finite common-mode gain: It is simply due to the current transmission error introduced by the current-mirror load. In the case of the MOS circuit, this error is due to the finite ro3; in the case of the bipolar mirror, the error is due to the finite β.
EXERCISE
9.21 Forthecurrent-mirror-loadedBJTdifferentialamplifierspecifiedinExercise9.18,findREE,Acm,and CMRR. Use the results of Exercise 9.18.
Ans. 125 k; 0.0125 V/V; 160,000, or 104 dB
9.6 Multistage Amplifiers
Practical transistor amplifiers usually consist of a number of stages connected in cascade. In addition to providing gain, the first (or input) stage is usually required to provide a high input resistance in order to avoid loss of signal level when the amplifier is fed from a high-resistance source. In a differential amplifier the input stage must also provide large common-mode rejection. The function of the middle stages of an amplifier cascade is to provide the bulk of the voltage gain. In addition, the middle stages provide such other functions as the conversion of the signal from differential mode to single-ended mode (unless, of course, the amplifier output also is differential) and the shifting of the dc level of the signal in order to allow the output signal to swing both positive and negative. These two functions and others will be illustrated later in this section and in greater detail in Chapter 13.
Finally, the main function of the last (or output) stage of an amplifier is to provide a low output resistance in order to avoid loss of gain when a low-valued load resistance is connected to the amplifier. Also, the output stage should be able to supply the current required by the load in an efficient manner—that is, without dissipating an unduly large amount of power in the output transistors. We have already studied one type of amplifier configuration suitable for implementing output stages, namely, the source follower and the emitter follower. It will be shown in Chapter 12 that the source and emitter followers are not optimum from the point of view of power efficiency and that other, more appropriate circuit configurations exist for output stages that are required to supply large amounts of output power. In fact, we will encounter some such output stages in the op-amp circuit examples studied in Chapter 13.
To illustrate the circuit structure and the method of analysis of multistage amplifiers, we will present two examples: a two-stage CMOS op amp and a four-stage bipolar op amp.
9.6 Multistage Amplifiers 659
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9.6.1 A Two-Stage CMOS Op Amp
Figure9.40 shows a popular structure for CMOS op amps known as the two-stage configuration. The circuit utilizes two power supplies, which can range from ±2.5 V for
660 Chapter 9
Differential and Multistage Amplifiers
I
CC
Figure 9.40 Two-stage CMOS op-amp configuration.
the 0.5-μm technology down to ±0.5 V for the 65-nm technology. A reference bias current IREF is generated either externally or using on-chip circuits. One such circuit will be discussed in Chapter 13. The current mirror formed by Q8 and Q5 supplies the differential pair Q1−Q2 with bias current. The W/L ratio of Q5 is selected to yield the desired value for the input-stage bias current I (or I/2 for each of Q1 and Q2). The input differential pair is actively loaded with the current mirror formed by Q3 and Q4. Thus the input stage is identical to that studied in Section 9.5 (except that here the differential pair is implemented with PMOS transistors and the current mirror with NMOS).
The second stage consists of Q6, which is a common-source amplifier loaded with the current-source transistor Q7. A capacitor CC is included in the negative-feedback path of the second stage. Its function will be explained in Chapter 13, when we study the frequency response of this amplifier.
A striking feature of the circuit in Fig. 9.40 is that it does not have a low-output-resistance stage. In fact, the output resistance of the circuit is equal to (ro6 ∥ ro7 ) and is thus rather high. This circuit, therefore, is not suitable for driving low-impedance loads. Nevertheless, the circuit is very popular and is used frequently for implementing op amps in VLSI circuits, where the op amp needs to drive only a small capacitive load, for example, in switched-capacitor circuits (Chapter 17). The simplicity of the circuit results in an op amp of reasonably good quality realized in a very small chip area.
Voltage Gain The voltage gain of the first stage was found in Section 9.5 to be given by A1 =−gm1(ro2∥ro4) (9.168)
D2 D6
where gm1 is the transconductance of each of the transistors of the first stage, that is, Q1 and Q2.
The second stage is a current-source-loaded, common-source amplifier whose voltage gain is given by
A2 =−gm6(ro6∥ro7)
The dc open-loop gain of the op amp is the product of A1 and A2.
Example 9.6
Consider the circuit in Fig. 9.40 with the following device geometries (in μm).
Transistor Q1 Q2 Q3 Q4 Q5 Q6
(9.169)
W/L
20/0.8 20/0.8 5/0.8 5/0.8 40/0.8 10/0.8
40/0.8
40/0.8
=90μA, V =0.7V, V =−0.8V, μC =160μA/V2, μC =40μA/V2, V (for all REF tn tp nox pox A
Let I
devices)=10V,VDD =VSS =2.5V.Foralldevices,evaluateID,VOV,VGS,gm,andro.AlsofindA1,A2, the dc open-loop voltage gain, the input common-mode range, and the output voltage range. Neglect the effect of VA on bias current.
Solution
RefertoFig.9.40.SinceQ8 andQ5 arematched,I=IREF.ThusQ1,Q2,Q3,andQ4 eachconductsacurrent equal to I/2 = 45 μA. Since Q7 is matched to Q5 and Q8, the current in Q7 is equal to IREF = 90 μA. Finally, Q6 conducts an equal current of 90 μA.
With ID of each device known, we use
I = 1(μC )(W/L)V2
9.6 Multistage Amplifiers 661
Q7 Q8
D2ox OV
to determine V for each transistor. Then we find V from V = V + V . The results are given
OV GS GS t OV
in Table 9.1.
The transconductance of each device is determined from
The value of ro is determined from
g = 2 I V m D OV
r = V I oAD
The resulting values of gm and ro are given in Table 9.1.
662
Chapter 9 Differential and Multistage Amplifiers
Example 9.6 continued Table 9.1
Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 I(μA) 45 45 45 45 90 90 90 90
D
VOV(V) 0.3 0.3 0.3 0.3 0.3 0.3 0.3 0.3
VGS(V) 1.1 1.1 1 1 1.1 1 1.1 1.1
gm (mA/V) 0.3 0.3 0.3 0.3 0.6 0.6 ro (k) 222 222 222 222 111 111
The voltage gain of the first stage is determined from
A1 =−gm1 ro2∥ro4
= −0.3(222 ∥ 222) = −33.3 V/V
The voltage gain of the second stage is determined from
A2 =−gm6 ro6∥ro7
= −0.6(111 ∥ 111) = −33.3V/V
Thus the overall dc open-loop gain is
A0 =A1A2 =(−33.3)×(−33.3)=1109V/V
0.6 0.6 111 111
or
The lower limit of the input common-mode range is the value of input voltage at which Q1 and Q2
20 log1109 = 61 dB leavethesaturationregion.ThisoccurswhentheinputvoltagefallsbelowthevoltageatthedrainofQ by
1
Vtp volts. Since the drain of Q1 is at −2.5 + 1 = −1.5 V, then the lower limit of the input common-mode
range is −2.3 V.
The upper limit of the input common-mode range is the value of input voltage at which Q5 leaves the
saturation region. Since for Q5 to operate in saturation the voltage across it (i.e., VSD5) should at least be equal to the overdrive voltage at which it is operating (i.e., 0.3 V), the highest voltage permitted at the drain of Q5 should be +2.2 V. It follows that the highest value of vICM should be
vICMmax =2.2−1.1=1.1V
The highest allowable output voltage is the value at which Q leaves the saturation region, which is
7
VDD − VOV 7 = 2.5 − 0.3 = 2.2 V. The lowest allowable output voltage is the value at which Q6 leaves
saturation, which is −VSS + VOV 6 = −2.5 + 0.3 = −2.2 V. Thus, the output voltage range is −2.2 V to +2.2 V.
Input Offset Voltage The device mismatches inevitably present in the input stage give rise to an input offset voltage. The components of this input offset voltage can be calculated using the methods developed in Section 9.4.1. Because device mismatches are random, the resulting offset voltage is referred to as random offset. This is to distinguish it from another type of input offset voltage that can be present even if all appropriate devices are perfectly matched. This predictable or systematic offset can be minimized by careful design. Although it occurs also in BJT op amps, and we have encountered it in Section 9.5.4, it is usually much more pronounced in CMOS op amps because their gain-per-stage is rather low.
To see how systematic offset can occur in the circuit of Fig. 9.40, let the two input terminals be grounded. If the input stage is perfectly balanced, then the voltage appearing at the drain of Q4 will be equal to that at the drain of Q3, which is (−VSS +VGS4). Now this is also the voltage that is fed to the gate of Q6. In other words, a voltage equal to VGS4 appears between gate and source of Q6. Thus the drain current of Q6, I6, will be related to the drain current of Q4, which is equal to I/2, by the relationship
I6 = (W/L)6 (I/2) (9.170) (W/L)4
In order for no offset voltage to appear at the output, this current must be exactly equal to the current supplied by Q7. The latter current is related to the current I of the parallel transistor
9.6 Multistage Amplifiers 663
Q5 by
Now, the condition for making I6 = I7 can be found from Eqs. (9.170) and (9.171) as
(W/L)6 =2(W/L)7 (W/L)4 (W/L)5
I7 = (W/L)7 I (W/L)5
(9.171)
(9.172)
If this condition is not met, a systematic offset will result. From the specification of the device geometries in Example 9.6, we can verify that condition (9.172) is satisfied, and, therefore, the op amp analyzed in that example should not exhibit a systematic input offset voltage.
EXERCISE
9.22 Consider the CMOS op amp of Fig. 9.40 when fabricated in a 0.8-μm CMOS technology for which μ C =3μ C =90μA/V2,V=0.8V,andV =V =2.5V.Foraparticulardesign,I=100μA,
nox pox t DD SS
(W/L)1 = (W/L)2 = (W/L)5 = 200, and (W/L)3 = (W/L)4 = 100.
(a) Findthe(W/L)ratiosofQ andQ sothatI =100μA. 6 7 6
(b) Find the overdrive voltage, VOV , at which each of Q1, Q2, and Q6 is operating.
(c) Findg forQ ,Q ,andQ .
m 12 6
(d) If VA = 10 V, find ro2, ro4, ro6, and ro7.
(e) Find the voltage gains A1 and A2, and the overall gain A.
Ans. (a) (W/L)6 = (W/L)7 = 200; (b) 0.129 V, 0.129 V, 0.105 V; (c) 0.775 mA/V, 0.775 mA/V, 1.90 mA/V; (d) 200 k, 200 k, 100 k, 100 k; (e) –77.5 V/V, –95 V/V, 7363 V/V
664 Chapter 9
Differential and Multistage Amplifiers
9.6.2 A Bipolar Op Amp
Our second example of multistage amplifiers is the four-stage bipolar op amp shown in Fig. 9.41. The circuit consists of four stages. The differential-in, differential-out input stage consists of transistors Q1 and Q2, which are biased by current source Q3. The second stage is also a differential-input amplifier, but its output is taken single-endedly at the collector of Q5. This stage is formed by Q4 and Q5, which are biased by the current source Q6. Note that the conversion from differential to single-ended as performed by the second stage results in a loss of gain by a factor of 2. In the more elaborate method for accomplishing this conversion studied in Section 9.5, a current mirror was used as an active load.
In addition to providing some voltage gain, the third stage, consisting of the pnp transistor Q7, provides the essential function of shifting the dc level of the signal. Thus, while the signal at the collector of Q5 is not allowed to swing below the voltage at the base of Q5 (+10 V), the signal at the collector of Q7 can swing negatively (and positively, of course). From our study of op amps in Chapter 2, we know that the output terminal of the op amp should be capable of both positive and negative voltage swings. Therefore every op-amp circuit includes a level-shifting arrangement. Although the use of the complementary pnp transistor provides a simple solution to the level-shifting problem, other forms of level shifter exist, one of which
Figure 9.41 A four-stage bipolar op amp.
will be discussed in Chapter 13. Furthermore, note that level shifting is accomplished in the CMOS op amp we have studied in Section 9.6.1 by using complementary devices for the two stages: that is, p-channel for the first stage and n-channel for the second stage.
The output stage of the op amp consists of emitter follower Q8. As we know from our study of op amps in Chapter 2, ideally the output operates around zero volts. This and other features of the BJT op amp will be illustrated in Example 9.7.
Example 9.7
In this example, we analyze the dc bias of the bipolar op-amp circuit of Fig. 9.41. Toward that end, Fig. 9.42 shows the circuit with the two input terminals connected to ground.
(a) Perform an approximate dc analysis (assuming β ≫ 1, V ≃ 0.7 V, and neglecting the Early effect) BE
to calculate the dc currents and voltages everywhere in the circuit. Note that Q6 has four times the area of each of Q9 and Q3.
(b) Calculate the quiescent power dissipation in this circuit.
(c) If transistors Q1 and Q2 have β = 100, calculate the input bias current of the op amp.
(d) What is the input common-mode range of this op amp?
Figure 9.42 Circuit for Example 9.7.
9.6 Multistage Amplifiers 665
666
Chapter 9 Differential and Multistage Amplifiers
Example 9.7 continued
Solution
(a) The values of all dc currents and voltages are indicated on the circuit diagram. These values were calculated by ignoring the base current of every transistor—that is, by assuming β to be very high. The analysis starts by determining the current through the diode-connected transistor Q9 to be 0.5 mA. Then we see that transistor Q3 conducts 0.5 mA and transistor Q6 conducts 2 mA. The current-source transistor Q3 feeds the differential pair (Q1, Q2) with 0.5 mA. Thus each of Q1 and Q2 will be biased at 0.25 mA. The collectors of Q1 and Q2 will be at [+15 – 0.25 × 20] = +10 V.
ProceedingtotheseconddifferentialstageformedbyQ4 andQ5,wefindthevoltageattheiremittersto be [+10 – 0.7] = 9.3 V. This differential pair is biased by the current-source transistor Q6 , which supplies a current of 2 mA; thus Q4 and Q5 will each be biased at 1 mA. We can now calculate the voltage at the collector of Q5 as [+15 – 1 × 3] = +12 V. This will cause the voltage at the emitter of the pnp transistor Q7 tobe+12.7V,andtheemittercurrentofQ7 willbe(+15−12.7)/2.3=1mA.
The collector current of Q7 , 1 mA, causes the voltage at the collector to be [–15 + 1 × 15.7] = +0.7 V. The emitter of Q8 will be 0.7 V below the base; thus output terminal 3 will be at 0 V. Finally, the emitter currentofQ8 canbecalculatedtobe[0–(–15)]/3=5mA.
(b) To calculate the power dissipated in the circuit in the quiescent state (i.e., with zero input signal) we simply evaluate the dc current that the circuit draws from each of the two power supplies. From the +15V supply the dc current is I+ =0.25+0.25+1+1+1+5=8.5mA. Thus the power supplied by the positive power supply is P+ = 15 × 8.5 = 127.5 mW. The –15-V supply provides a current I − given by I− =0.5+0.5+2+1+5=9mA. Thus the power provided by the negative supply is P− =15 × 9 = 135 mW. Adding P+ and P− provides the total power dissipated in the circuit PD : PD = P+ + P− = 262.5 mW.
(c) The input bias current of the op amp is the average of the dc currents that flow in the two input terminals(i.e.,inthebasesofQ1 andQ2).Thesetwocurrentsareequal(becausewehaveassumedmatched devices); thus the bias current is given by
IB = IE1 ≃2.5μA β+1
(d) The upper limit on the input common-mode voltage is determined by the voltage at which Q1 and Q2 leave the active mode and enter saturation. This will happen if the input voltage exceeds the collector voltage, which is +10 V, by about 0.4 V. Thus the upper limit of the common-mode range is +10.4 V.
The lower limit of the input common-mode range is determined by the voltage at which Q3 leaves the active mode and thus ceases to act as a constant-current source. This will happen if the collector voltage of Q3 goes below the voltage at its base, which is –14.3 V, by more than 0.4 V. It follows that the input common-mode voltage should not go lower than –14.7 + 0.7 = –14 V. Thus the common-mode range is –14 V to +10.4 V.
Example 9.8
Use the dc bias quantities evaluated in Example 9.7 to analyze the circuit in Fig. 9.41 to determine the input resistance, the voltage gain, and the output resistance.
Solution
TheinputdifferentialresistanceRid isgivenby
Rid =rπ1 +rπ2
Since each of Q1 and Q2 is operating at an emitter current of 0.25 mA, it follows that re1 =re2 = 25 =100
9.6 Multistage Amplifiers 667
Assume β = 100; then Thus,
0.25
rπ1 =rπ2 =101×100=10.1k
Rid =20.2k
To evaluate the gain of the first stage, we first find the input resistance of the second stage, Ri2,
Ri2 =rπ4 +rπ5
Q4 and Q5 are each operating at an emitter current of 1 mA; thus
re4 =re5 =25
rπ4 =rπ5 =101×25=2.525k
Thus Ri2 = 5.05 k. This resistance appears between the collectors of Q1 and Q2 , as shown in Fig. 9.43. Thus the gain of the first stage will be
A ≡ vo1 ≃ Total resistance in collector circuit
1 vid Total resistance in emitter circuit
=Ri2∥ R1+R2 re1 +re2
= 5.05 k∥40 k = 22.4 V/V 200
Figure 9.43 Equivalent circuit for calculating the gain of the input stage of the amplifier in Fig. 9.41.
668
Chapter 9 Differential and Multistage Amplifiers
Example 9.8 continued
R3
Q4 Q5
vo2 Ri3
vo1
Figure 9.44 Equivalent circuit for calculating the gain of the second stage of the amplifier in Fig. 9.41.
Figure 9.44 shows an equivalent circuit for calculating the gain of the second stage. As indicated, the input voltage to the second stage is the output voltage of the first stage, vo1. Also shown is the resistance Ri3, which is the input resistance of the third stage formed by Q7. The value of Ri3 can be found by multiplying thetotalresistanceintheemitterofQ7 by(β+1):
Ri3 =(β+1) R4 +re7 Since Q7 is operating at an emitter current of 1 mA,
re7 = 25 = 25 1
Ri3 =101×2.325=234.8k
We can now find the gain A2 of the second stage as the ratio of the total resistance in the collector circuit
to the total resistance in the emitter circuit:
A≡vo2 ≃−R3∥Ri3
2 vo1 re4 +re5
= −3 k∥234.8 k = −59.2 V/V
50
To obtain the gain of the third stage we refer to the equivalent circuit shown in Fig. 9.45, where Ri4 is the input resistance of the output stage formed by Q8. Using the resistance-reflection rule, we calculate
the value of Ri4 as
Ri4 =(β+1) re8 +R6
where
re8 = 25 = 5 5
9.6 Multistage Amplifiers 669
Ri4 =101(5+3000)=303.5k The gain of the third stage is given by
A ≡vo3 ≃−R5∥Ri4 3 vo2 re7 +R4
= −15.7 k∥303.5 k = −6.42 V/V 2.325 k
Figure 9.45 Equivalent circuit for evaluating the gain of the third stage in the amplifier circuit of Fig. 9.41.
Figure 9.46 Equivalent circuit of the output stage of the amplifier circuit of Fig. 9.41.
670
Chapter 9 Differential and Multistage Amplifiers
Example 9.8 continued
Finally, to obtain the gain A4 of the output stage we refer to the equivalent circuit in Fig. 9.46 and write
A≡vo= R6
4 vo3 R6 +re8
= 3000 =0.998≃1 3000+5
The overall voltage gain of the amplifier can then be obtained as follows: vo =AAAA=8513V/V
vid 1234
To obtain the output resistance Ro we “grab hold” of the output terminal in Fig. 9.41 and look back
or 78.6 dB.
into the circuit. By inspection we find
which gives
EXERCISE
Ro =R6∥[re8 +R5/(β+1)]
Ro =152
9.23 UsetheresultsofExample9.8tocalculatetheoverallvoltagegainoftheamplifierinFig.9.41when it is connected to a source having a resistance of 10 k and a load of 1 k.
Ans. 4943 V/V
Analysis Using Current Gains There is an alternative method for the analysis of bipolar multistage amplifiers that can be somewhat easier to perform in some cases. The method makes use of current gains or more appropriately current-transmission factors. In effect, one traces the transmission of the signal current throughout the amplifier cascade, evaluating all the current transmission factors in turn. We shall illustrate the method by using it to analyze the amplifier circuit of the preceding example.
9.6 Multistage Amplifiers 671
RR Ri3R 1 2 ib5 R3 4
Q7
ic2
i i
vid
ic1=ic2
Q1 Q2
ic5
Q4 Q5
ib7
ic7 ib8
ib4 ib5
Q8
ie8 vo
R6
R5
ii
Ri2
Ri4
Ri1
Figure9.47 ThecircuitofthemultistageamplifierofFig.9.41preparedforsmall-signalanalysis.Indicated
are the signal currents throughout the amplifier and the input resistances of the four stages.
Figure 9.47 shows the amplifier circuit prepared for small-signal analysis. We have indicated on the circuit diagram the signal currents through all the circuit branches. Also indicated are the input resistances of all four stages of the amplifier. These should be evaluated before commencing the following analysis.
The purpose of the analysis is to determine the overall voltage gain (vo/vid). Toward that end, we express vo in terms of the signal current in the emitter of Q8, ie8, and vid in terms of the input signal current ii, as follows:
vo =R6ie8 vid =Ri1ii
Thus, the voltage gain can be expressed in terms of the current gain (ie8/ii) as vo = R6 ie8
vid Ri1 ii
Next, we expand the current gain (ie8/ii) in terms of the signal currents throughout the circuit
as follows:
ie8 =ie8 ×ib8 ×ic7 ×ib7 ×ic5 ×ib5 ×ic2 ii ib8 ic7 ib7 ic5 ib5 ic2 ii
Each of the current-transmission factors on the right-hand side is either the current gain of a transistor or the ratio of a current divider. Thus, reference to Fig. 9.47 enables us to find these
672 Chapter 9
Differential and Multistage Amplifiers
factors by inspection:
ie8 =β8+1 ib8
ib8= R5
ic7 R5 +Ri4
ic7 =β7 ib7
ib7= R3
ic5 ic5 ib5 ib5 ic2 ic2 ii
R3 +Ri3 =β5
= (R1+R2) (R1 +R2)+Ri2
=β2
These ratios can be easily evaluated and their values used to determine the voltage gain. With a little practice, it is possible to carry out such an analysis very quickly, foregoing explicitly labeling the signal currents on the circuit diagram. One simply “walks through” the circuit, from input to output, or vice versa, determining the current-transmission factors one
at a time, in a chainlike fashion.
EXERCISE
9.24 Use the values of input resistance found in Example 9.8 to evaluate the seven current-transmission factors and hence the overall current gain and voltage gain.
Ans. The current-transmission factors in the order of their listing are 101, 0.0492, 100, 0.0126, 100, 0.8879, 100 A/A; the overall current gain is 55599 A/A; the voltage gain is 8257 V/V. This value differs slightly from that found in Example 9.8, because of the various approximations made in the example (e.g., α ≃ 1).
Summary
The differential-pair or differential-amplifier configura- tion is the most widely used building block in analog IC design. The input stage of every op amp is a differential amplifier.
There are two reasons for preferring differential to single-ended amplifiers: Differential amplifiers are insen- sitive to interference, and they do not need bypass and coupling capacitors.
For a MOS (bipolar) pair biased by a current source I, each device operates at a drain (collector, assuming α = 1) current of I/2 and a corresponding overdrive voltage VOV (no counterpart in bipolar). Each device has g = I/V
m OV (αI/2VT , for bipolar) and ro = VA /(I/2).
With the two input terminals connected to a suitable dc voltage VCM, the bias current I of a perfectly sym- metrical differential pair divides equally between the
two transistors of the pair, resulting in a zero voltage
difference between the two drains (collectors). To steer
the current completely to one side of the pair, a difference
Summary 673 Re in the two emitters. The latter action, however,
lowers Ad .
Mismatches between the two sides of a differential pair
result in a differential dc output voltage VO even when the two input terminals are tied together and connected to a dc voltage VCM . This signifies the presence of an input offset voltage VOS ≡ VO /Ad . In a MOS pair there are three main sources for VOS :
RD ⇒ VOS = VOV RD 2 RD
V (W/L) (W/L) ⇒ VOS = OV
2 W/L Vt ⇒VOS =Vt
For the bipolar pair there are two main sources:
RC RC⇒VOS=VT R
input voltage vid of at least 2VOV (4VT for bipolar) is needed.
Superimposing a differential input signal vid on the dc
common-mode input voltage VCM such that vI1 = VCM +
vid /2 and vI 2 = VCM − vid /2 causes a virtual signal ground
to appear on the common-source (common-emitter)
connection. In response to vi d , the current in Q1 increases
bygv/2andthecurrentinQ decreasesbygv/2. m id 2 m id
Thus, voltage signals of ±gm RD ∥ ro vid /2 develop at the
two drains (collectors, with RD replaced by RC). If the
output voltage is taken single-endedly, that is, between
√
one of the drains (collectors) and ground, a differential
gainof 1gR∥risrealized.Whentheoutputis 2mDo
taken differentially, that is, between the two drains
(collectors), the differential gain realized is twice as large:
g R ∥r .
mDo C
The analysis of a differential amplifier to determine differential gain, differential input resistance, frequency response of differential gain, and so on is facilitated by employing the differential half-circuit, which is a common-source (common-emitter) transistor biased at I/2.
An input common-mode signal vi c m gives rise to drain (collector) voltage signals that are ideally equal and given
IS IS⇒VOS=VT I
S
A popular circuit in both MOS and bipolar analog ICs is the current-mirror-loaded differential pair. It realizes
cm m3 SS
circuit (ro4 /β3 REE for the bipolar circuit), as well as
by −vicm RD/2RSS [−vicm RC/2REE
for the bipolar pair],
performing the differential-to-single-ended conversion with no loss of gain.
The CMOS two-stage amplifier studied in Section 9.6.1 is intended for use as part of an IC system and thus is required to drive only small capacitive loads. Therefore it does not have an output stage with a low output resistance.
A multistage amplifier typically consists of three or more stages: an input stage having a high input resistance, a reasonably high gain, and, if differential, a high CMRR; one or two intermediate stages that realize the bulk of the gain; and an output stage having a low output resistance. In designing and analyzing a multistage amplifier, the loading effect of each stage on the one that precedes it must be taken into account.
where RSS (REE) is the output resistance of the current
source that supplies the bias current I. When the output is
taken single-endedly, a common-mode gain of magnitude
A = R /2R (R /2R for the bipolar case) results.
cm D SS C EE
Taking the output differentially results, in the perfectly matched case, in zero Acm (infinite CMRR). Mismatches between the two sides of the pair make Acm finite even
when the output is taken differentially: A mismatch
RD causes Acm
g causes A = R /2R (g /g ). Corresponding
= RD /2RSS RD /RD ; a mismatch m cmDSSmm
expressions apply for the bipolar pair.
While the input differential resistance Rid of the MOS pair is infinite, that for the bipolar pair is only 2rπ but can be increased to 2(β + 1)(re + Re ) by including resistances
a high differential gain Ad = gm Ro pair ∥ Ro mirror and a low common-mode gain, A = 1/2g R for the MOS
PROBLEMS
Computer Simulation Problems
Problems identified by the Multisim/PSpice icon are intended to demonstrate the value of using SPICE simulation to verify hand analysis and design, and to investigate important issues such as allowable signal swing and amplifier nonlinear distortion. Instructions to assist in setting up PSpice and Multisim simulations for all the indicated problems can be found in the corresponding files on the website. Note that if a particular parameter value is not specified in the problem statement, you are to make a reasonable assumption.
Section 9.1: The MOS Differential Pair
9.1 For an NMOS differential pair with a common-mode voltage VCM applied, as shown in Fig. 9.2, let VDD = VSS = 1.0 V, kn′ = 0.4 mA/V2, (W/L)1,2 = 10, Vtn = 0.4 V, I = 0.16 mA, RD = 5 k, and neglect channel-length modulation.
(a) Find VOV and VGS for each transistor.
(b) For VCM = 0, find VS, ID1, ID2, VD1, and VD2.
(c) Repeat (b) for VCM = +0.4 V.
(d) Repeat (b) for VCM = −0.1 V.
(e) What is the highest value of VCM for which Q1 and Q2
remain in saturation?
(f) If current source I requires a minimum voltage of 0.2 V
to operate properly, what is the lowest value allowed for VS andhenceforVCM?
9.2 For the PMOS differential amplifier shown in Fig. P9.2 let Vtp = −0.8 V and kp′ W/L = 4 mA/V2. Neglect channel-length modulation.
2.5 V
v Q Q v vv
(a) For vG1 = vG2 =0 V, find |VOV | and VSG for each of Q1 and Q2. Also find VS, VD1, and VD2.
(b) Ifthecurrentsourcerequiresaminimumvoltageof0.4V, find the input common-mode range.
9.3 ForthedifferentialamplifierspecifiedinProblem9.1let vG2 =0andvG1 =vid.Findthevalueofvid thatcorresponds to each of the following situations:
(a) iD1 =iD2 =0.08 mA; (b) iD1 =0.12 mA and iD2 =0.04 mA; (c) iD1 = 0.16 mA and iD2 = 0 (Q2 just cuts off); (d) iD1 =0.04 mA and iD2 =0.12 mA; (e) iD1 =0 mA (Q1 just cuts off) and iD2 =0.16 mA. For each case, find vS, vD1, vD2, and (vD2 –vD1).
9.4 For the differential amplifier specified in Prob- lem9.2,letvG2 =0andvG1 =vid.Findtherangeofvid needed to steer the bias current from one side of the pair to the other. At each end of this range, give the value of the voltage at the common-source terminal and the drain voltages.
9.5 Consider the differential amplifier specified in Prob- lem 9.1 with G2 grounded and vG1 = vid . Let vid be adjusted to the value that causes iD1 = 0.09 mA and iD2 = 0.07 mA. Find the corresponding values of vGS2, vS, vGS1, and hence vid. What is the difference output voltage vD2 −vD1? What is the voltage gain (vD2 − vD1)/vid ? What value of vid results in iD1 =0.07 mA and iD2 =0.09 mA?
D 9.6 Design the circuit in Fig. P9.6 to obtain a dc voltage of +0.1V at each of the drains of Q1 and Q2 when vG1 = vG2 = 0 V. Operate all transistors at VOV = 0.15 V
0.5 mA
v
RD
VDD 0.9 V
Q1 Q2
RD
vG1
vG2
0.9V
0.1 mA
R
0.4 mA
4k 4k Q4 Q3
Figure P9.2
2.5 V VSS 0.9V Figure P9.6
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
and assume that for the process technology in which the circuit is fabricated, Vtn = 0.4 V and μn Cox = 400 μA/V2 . Neglect channel-length modulation. Determine the values of R, RD, and the W/L ratios of Q1, Q2, Q3, and Q4. What is the input common-mode voltage range for your design?
9.7 The table providing the answers to Exercise 9.3 shows
that as the maximum input signal to be applied to the
differential pair is increased, linearity is maintained at the
can be as high as 0.1 V while keeping the nonlinear term under the square root in Eq. (9.23) to a maximum of 0.04. A transconductance gm of 2 mA/V is needed and the amplifier is required to provide a differential output signal of 1 V when the input is at its maximum value. Find the required values of VOV , I, RD, and W/L. Assume that the technology available has μnCox =200 μA/V2 and λ = 0.
D 9.14 Design a MOS differential amplifier to operate from ±1-V power supplies and dissipate no more than 1 mW in the equilibrium state. The differential voltage gain Ad is to be 10 V/V and the output common-mode dc voltage is to be 0.2 V. (Note: This is the dc voltage at the drains.) Assume μn Cox = 400 μA/V2 and neglect the Early effect. Specify I, RD , and W/L.
D 9.15 Design a MOS differential amplifier to operate from ±1-V supplies and dissipate no more than 1 mW in its equilibrium state. Select the value of VOV so that the value of vid that steers the current from one side of the pair to the other is 0.25 V. The differential voltage gain Ad is to be 10 V/V. Assume kn′ = 400 μA/V2 and neglect the Early effect. Specify the required values of I, RD, and W/L.
9.16 An NMOS differential amplifier employing equal drain resistors, RD = 47 k, has a differential gain Ad of 20 V/V.
(a) What is the value of gm for each of the two transistors? (b) If each of the two transistors is operating at an overdrive
voltage V = 0.2 V, what must the value of I be? OV
(c) For v = 0, what is the dc voltage across each R ? id D
(d) If v is 20-mV peak-to-peak sine wave applied in a id
balanced manner but superimposed on V = 0.5 V, what CM
is the peak of the sine-wave signal at each drain?
(e) What is the lowest value that VDD must have to ensure saturation-mode operation for Q1 and Q2 at all times?
Assume V = 0.5 V. t
9.17 A MOS differential amplifier is designed to have a differential gain Ad equal to the voltage gain obtained from a common-source amplifier. Both amplifiers utilize the same values of RD and supply voltages, and all the transistors have the same W/L ratios. What must the bias current I of the differential pair be relative to the bias current ID of the CS amplifier? What is the ratio of the power dissipation of the two circuits?
same level by operating at a higher VOV . If vid max is to be 220 mV, use the data in the table to determine the required VOV and the corresponding values of W/L and gm.
9.8 Use Eq. (9.23) to show that if the term involving v2id is to be kept to a maximum value of k then the maximum possible fractional change in the transistor current is given by
Imax
Problems 675
CHAPTER 9 PROBLEMS
=2 k(1−k) I/2
and the corresponding maximum value of vid is given by √
v=2kV
id max OV
Evaluate both expressions for k = 0.01, 0.1, and 0.2.
9.9 AMOSdifferentialamplifierbiasedwithacurrentsource I = 200 μA is found to switch currents completely to one side of the pair when a difference signal vid = 0.3 V is applied. At what overdrive voltage will each of Q1 and Q2 be operating when vid = 0? If vid for full current switching is to be 0.5 V, what must the bias current I be changed to?
D 9.10 Design the MOS differential amplifier of Fig. 9.5 to operate at VOV =0.25 V and to provide a transconductance gm of 1 mA/V. Specify the W/L ratios and the bias current. The technology available provides Vt =0.5 V and μC =400μA/V2.
n ox
9.11 For the MOS differential pair in Fig. 9.5, specify the valueofvid ≡vG1 −vG2,intermsofVOV,that
(a) causes iD1 to increase by 10% above its equilibrium value of I/2.
(b) makes iD1 /iD2 = 1.0; 2.0; 1.1; 1.01; 20.
9.12 An NMOS differential amplifier is operated at a bias current I of 0.2mA and has a W/L ratio of 32, μnCox=200μA/V2,VA=10V,andRD=10k.FindVOV,gm, ro, and Ad.
D 9.13 It is required to design an NMOS differential amplifier to operate with a differential input voltage that
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676 Chapter 9 Differential and Multistage Amplifiers
Rs = 0? What is the value of Rs (in terms of 1/gm ) that reduces voltage gain equal to the voltage gain of a common-source the gain to half this value?
9.18 A differential amplifier is designed to have a differential
amplifier. Both amplifiers use the same values of RD and
supply voltages and are designed to dissipate equal amounts
of power in their equilibrium or quiescent state. As well, all
the transistors use the same channel length. What must the RD width W of the differential-pair transistors be relative to the
VDD
RD
width of the CS transistor?
D 9.19 Figure P9.19 shows a MOS differential amplifer with
the drain resistors RD implemented using diode-connected PMOS transistors, Q3 and Q4. Let Q1 and Q2 be matched, and Q3 and Q4 be matched.
vod
2 Q1 2 2
vid
Q
vid
CHAPTER 9 PROBLEMS
Rs
VDD
–I
–I
Q3
Q4
22
VSS
*9.21 The resistance Rs in the circuit of Fig. P9.20 can be implemented by using a MOSFET operated in the triode region, as shown in Fig. P9.21. Here Q3 implements Rs , with the value of Rs determined by the voltage VC at the gate of Q3 .
Figure P9.20
vid Q Q vid 12 22
I
Figure P9.19
(a) Find the differential half-circuit and use it to derive an expression for Ad in terms of gm1,2 , gm3,4 , ro1,2 , and ro3,4.
(b) Neglecting the effect of the output resistances ro, find Ad in terms of μn , μp , (W/L)1,2 and (W/L)3,4 .
(c) If μn = 4μp and all four transistors have the same channel length, find (W1,2 /W3,4 ) that results in Ad = 10 V/V.
9.20 Find the differential half-circuit for the differential amplifier shown in Fig.P9.20 and use it to derive an expression for the differential gain Ad ≡ v o d /v i d in terms of gm , RD , and Rs . Neglect the Early effect. What is the gain with
vG1
RD
Q1
VDD
vod
Q3
RD
Q2 vG2
–I V –I 2C2
– VSS
Figure P9.21
(a) With vG1 = vG2 = 0 V, and assuming that Q1 and Q2 are operating in saturation, what dc voltages appear
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CHAPTER 9 PROBLEMS
at the sources of Q1 and Q2? Express these in terms of the overdrive voltage VOV at which each of Q1 and Q2 operates, and Vt .
(b) For the situation in (a), what current flows in Q3? What overdrive voltage VOV 3 is Q3 operating at, in terms of VC , VOV , and Vt ?
(c) Now consider the case vG1 = +vid /2 and vG2 = −vid /2, where vid is a small signal. Convince yourself that Q3 now conducts current and operates in the triode region with a small v DS . What resistance rDS does it have, expressed in terms of the overdrive voltage VOV3 at which it is operating? This is the resistance Rs. Now if all three transistors have the same W/L, express Rs in terms of
VOV , VOV3, and gm1,2.
(d) Find VOV 3 and hence VC that result in (i) Rs = 1/gm1,2 ; (ii)
Rs =0.5/gm1,2.
*9.22 The circuit of Fig. P9.22 shows an effective way of implementing the resistance Rs needed for the circuit in Fig. P9.20. Here Rs is realized as the series equivalent of two MOSFETs Q3 and Q4 that are operated in the triode region, thus, Rs = rDS3 + rDS4 . Assume that Q1 and Q2 are matched and operate in saturation at an overdrive voltage VOV that corresponds to a drain bias current of I/2. Also, assume that Q3 and Q4 are matched.
and Q4? At what overdrive voltages are Q3 and Q4 oper- ating? Find an expression for rDS for each of Q3 and Q4 and hence for Rs in terms of (W/L)1,2 , (W/L)3,4 , and gm1,2 .
(b) Now with vG1 =vid /2 and vG2 =−vid /2, where vid is a small signal, find an expression of the voltage gain Ad ≡vod/vid in terms of gm1,2, RD, (W/L)1,2, and (W/L)3,4.
D *9.23 Figure P9.23 shows a circuit for a differential amplifier with an active load. Here Q1 and Q2 form the differential pair, while the current source transistors Q4 and Q5 form the active loads for Q1 and Q2, respectively. The dc bias circuit that establishes an appropriate dc voltage at the drains of Q1 and Q2 is not shown. It is required to design the circuit to meet the following specifications:
(a) Differential gain A =50 V/V. d
(b)I =I=200μA. REF
(c) The dc voltage at the gates of Q6 and Q3 is +0.8 V.
(d) The dc voltage at the gates of Q7, Q4, and Q5 is −0.8 V.
The technology available is specified as follows: μ C = 2 n ox
2.5μpCox =250 μA/V ;Vtn = Vtp =0.5 V,VAn = VAp =10 V.
Specify the required value of R and the W/L ratios for
all transistors. Also specify I and V at which each D GS
transistor is operating. For dc bias calculations you may neglect channel-length modulation.
Problems 677
VDD
1.5 V
RD
RD
vod
Q1 Q2 v
Q6 IREF
Q3 I
vG1
G2
R
vid2
Q1
Q2 vid2
Q3 22
–VSS
Q4
–I
–I
vod
Q Q4 Q
1.5 V
Figure P9.23
75
Figure P9.22
(a) With vG1 = vG2 = 0 V, what dc voltages appear at the sources of Q1 and Q2? What current flows through Q3
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678 Chapter 9 Differential and Multistage Amplifiers
*9.24 A design error has resulted in a gross mismatch in the circuit of Fig. P9.24. Specifically, Q2 has twice the W/L ratio of Q1. If vid is a small sine-wave signal, find:
(a) ID1 and ID2.
(b) VOV for each of Q1 and Q2.
(c) The differential gain Ad in terms of RD , I, and VOV .
β=100.AssumethattheBJTshavevBE =0.7VatiC =1mA. Find the voltage at the emitters and at the outputs.
9.27 An npn differential amplifier with I = 0.4 mA, VCC = VEE =2.5V,andRC =5kutilizesBJTswithβ=100and vBE =0.7VatiC =1mA.IfvB2 =0,findVE,VC1,andVC2 obtained with vB1 = +0.5 V, and with vB1 = −0.5 V. Assume that the current source requires a minimum of 0.3 V for proper operation.
9.28 An npn differential amplifier with I = 0.4 mA, VCC = VEE =2.5V,andRC =5kutilizesBJTswithβ=100and vBE = 0.7 V at iC = 1 mA. Assuming that the bias current is obtained by a simple current source and that all transistors require a minimum vCE of 0.3 V for operation in the active mode, find the input common-mode range.
9.29 Repeat Exercise 9.7 for an input of –0.3 V.
9.30 An npn differential pair employs transistors for which vBE =690mVatiC =1mA,andβ=50.Thetransistorsleave theactivemodeatvCE ≤0.3V.ThecollectorresistorsRC =82 k, and the power supplies are ±1.2 V. The bias current I = 20 μA and is supplied with a simple current source.
(a) ForvB1 =vB2 =VCM =0V,findVE,VC1,andVC2.
(b) Find the input common-mode range.
(c) If vB2 = 0, find the value of vB1 that increases the current
in Q1 by 10%.
9.31 Consider the BJT differential amplifier when fed with acommon-modevoltageVCM asshowninFig.9.15(a).Asis often the case, the supply voltage VCC may not be pure dc but might include a ripple component vr of small amplitude and a frequency of 120 Hz (see Section 4.5). Thus the supply voltage becomes VCC + vr . Find the ripple component of the collector voltages, v C 1 and v C 2 , as well as of the difference
RD
W L
VDD
vod
RD
2W L
CHAPTER 9 PROBLEMS
Q1
Q2
vid 2
vid 2
Figure P9.24
I
D9.25 ForthecascodedifferentialamplifierofFig.9.13(a), show that if all transistors have the same channel length and
are operated at the same V and assuming that V ′ = V ′ ′ OV An Ap
= Now design the amplifier to obtain a differential gain of
VA , the differential gain Ad is given by
output voltage v
amplifier response to this undesirable power-supply ripple.
Ad =2 VA VOV 2
500 V/V. Use V = 0.2 V. If V′ = 5 V/μm, specify the
D 9.32 Consider the differential amplifier of Fig. 9.14 and let the BJT β be very large:
OV A
required channel length L. If gm is to be as high as possible
(a)
(b)
(c)
Whatisthelargestinputcommon-modesignalthatcanbe applied while the BJTs remain comfortably in the active region with vCB =0?
If the available power supply VCC is 2.0 V, what value of IRC shouldyouchooseinordertoallowacommon-mode input signal of ±1.0 V?
For the value of IRC found in (b), select values for I and RC . Use the largest possible value for I subject to the
but the power dissipation in the amplifier (in equilibrium) is to be limited to 0.5 mW, what bias current I would you use? LetVDD =VSS =0.9V.
Section 9.2: The BJT Differential Pair
9.26 For the differential amplifier of Fig. 9.15(a) let I = 0.4 mA, VCC =VEE =2.5 V, VCM =−1 V, RC =5 k, and
VSS
≡ v − v . Comment on the differential od C2 C1
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CHAPTER 9 PROBLEMS
constraint that the base current of each transistor (when I divides equally) should not exceed 2 μA. Let β = 100.
9.33 To provide insight into the possibility of nonlinear
distortion resulting from large differential input signals
Problems 679 (d) Calculate the effective transconductance Gm as the ratio
of the difference current, (iC 1 − iC 2 ), to vi d in the cases withoutandwiththeRe’s.BywhatfactorisGm reduced? How does this factor relate to the increase in vid? Comment.
applied to the differential amplifier of Fig. 9.14, evaluate the
normalizedchangeinthecurrentiE1,iE1/I=iE1 −(I/2)/I,
9.38 A BJT differential amplifier uses a 400-μA bias current. What is the value of g of each device? If β is 160, what is the differential input resistance?
D 9.39 Design the basic BJT differential amplifier circuit of Fig. 9.18 to provide a differential input resistance of at least 20 k and a differential voltage gain of 100 V/V. The transistor β is specified to be at least 100. Specify I and RC .
9.40 For a differential amplifier to which a total difference signal of 10 mV is applied, what is the equivalent signal to its corresponding CE half-circuit? If the emitter current source I is 200 μA, what is re of the half-circuit? For a load resistance of 10 k in each collector, what is the half-circuit gain? What magnitude of signal output voltage would you expect at each collector? Between the two collectors?
9.41 A BJT differential amplifier is biased from a 0.5-mA constant-current source and includes a 400- resistor in each emitter. The collectors are connected to VCC via 10-k resistors. A differential input signal of 0.1 V is applied between the two bases.
(a) Find the signal current in the emitters (ie) and the signal voltage vbe for each BJT.
(b) What is the total emitter current in each BJT?
(c) What is the signal voltage at each collector? Assume
α = 1.
(d) Whatisthevoltagegainrealizedwhentheoutputistaken
between the two collectors?
D 9.42 Design a BJT differential amplifier to amplify a differential input signal of 0.1 V and provide a differential output signal of 2 V. To ensure adequate linearity, it is required to limit the signal amplitude across each base–emitter junction to a maximum of 5 mV. Another design requirement is that the differential input resistance be at least 100 k. The BJTs available are specified to have β ≥ 100. Give the circuit configuration and specify the values of all its components.
D 9.43 Design a bipolar differential amplifier such as that in Fig. 9.18 to operate from ±2.5 V power supplies and to provide differential gain of 60 V/V. The power dissipation in the quiescent state should not exceed 1 mW.
for differential input signals v of 2, 5, 8, 10, 20, 30,
id m
and 40 mV. Provide a tabulation of the ratio iE 1 /I /v i d , which represents the proportional transconductance gain of the differential pair, versus vid . Comment on the linearity of the differential pair as an amplifier.
D 9.34 Design the circuit of Fig. 9.14 to provide a differen- tial output voltage (i.e., one taken between the two collectors) of 1 V when the differential input signal is 10 mV. A current source of 1 mA and a positive supply of +5 V are available. What is the largest possible input common-mode voltage for which operation is as required? Assume α ≃ 1.
*9.35 For the circuit in Fig. 9.14, assuming α = 1 and
IRC =5 V, use Eqs. (9.48) and (9.49) to find iC1 and iC2, and
hencedeterminevod =vC2 −vC1 forinputdifferentialsignals
vid ≡vB1−vB2 of2mV,5mV,10mV,15mV,20mV,
25 mV, 30 mV, 35 mV, and 40 mV. Plot vod versus vid , and
hence comment on the amplifier linearity. As another way of
visualizing linearity, determine the gain v /v versus v . oid id
Comment on the resulting graph.
9.36 In a differential amplifier using a 1.5-mA emitter bias current source, the two BJTs are not matched. Rather, one has twice the emitter junction area of the other. For a differential input signal of zero volts, what do the collector currents become? What difference input is needed to equalize the collector currents? Assume α = 1.
9.37 This problem explores the linearization of the transfer characteristics of the differential pair achieved by including emitter-degeneration resistances Re in the emitters (see Fig. 9.17). Consider the case I = 200 μA with the transistors exhibitingvBE =690mVatiC =1mAandassumeα≃1.
(a) With no emitter resistances Re, what value of VBE results whenvid =0?
(b) WithnoemitterresistancesRe,usethelarge-signalmodel to find iC1 and iC2 when vid = 20 mV.
(c) Now find the value of Re that will result in the same iC1 and iC2 as in (b) but with vid = 200 mV. Use the large-signal model.
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680 Chapter 9 Differential and Multistage Amplifiers
(a) Specify the values of I and RC . What dc voltage appears at the collectors?
(b) If β = 100, what is the input differential resistance?
(c) For vid = 10 mV, what is the signal voltage at each of the
collectors?
(d) For the situation in (c), what is the maximum allowable
9.47 For each of the emitter-degenerated differential ampli- fiers shown in Fig. P9.47, find the differential half-circuit and derive expressions for the differential gain Ad and differential input resistance Ri d . For each circuit, what dc voltage appears across the bias current source(s) in the quiescent state (i.e., with vid = 0)? Hence, which of the two circuits will allow a
value of the input common-mode voltage, VCM ? Recall larger negative VCM ? that to maintain an npn BJT in saturation, vB should not
exceed v C by more than 0.4 V.
VCC
RC
D *9.44 In this problem we explore the trade-off between input common-mode range and differential gain in the design of the bipolar BJT. Consider the bipolar differential amplifier in Fig. 9.14 with the input voltages
vB1 =VCM +vid/2 vB2 =VCM −vid/2
vid
(a) Bearing in mind that for a BJT to remain in the active 2
mode, vBC should not exceed 0.4 V, show that when vid has a peak vˆid, the maximum input common-mode voltage VCMmax is given by
vˆ vˆ VCMmax =VCC +0.4− id −Ad VT + id
22
(b) For the case VCC = 2.5V and vˆid = 10 mV, use the
relationship above to determine VCMmax for the case Ad =
50 V/V. Also find the peak output signal vˆod and the
required value of IRC . Now if the power dissipation in
the circuit is to be limited to 1 mW in the quiescent
state (i.e., with v i d = 0), find I and RC . (Remember to RC include the power drawn from the negative power supply
−VEE =−2.5V.)
(c) If VCMmax is to be +1 V, and all other conditions remain
thesame,whatmaximumgainAd isachievable?
9.45 For the differential amplifier of Fig. 9.14, let VCC = vid
RC
CHAPTER 9 PROBLEMS
vod
VCM
V
vid CM 2
Re
Re
I VEE
(a)
VCC
RC
vod
+5 V and IRC = 4 V. Find the differential gain Ad . Sketch and
VCM VCM
vid 2 2Re 2
clearly label the waveforms for the total collector voltages v and vC2 and for (vC2 −vC1) for the case:
vB1 =1+0.005sin(ωt) vB2 =1−0.005sin(ωt)
9.46 Consider a bipolar differential amplifier in which the collector resistors RC are replaced with simple current sources implemented using pnp transistors. Sketch the circuit and give its differential half-circuit. If VA = 20 V for all transistors, find the differential voltage gain achieved.
C1
–I –I
22
VEE
(b)
Figure P9.47
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CHAPTER 9 PROBLEMS
9.48 Consider a bipolar differential amplifier that, in addition to the collector resistances RC , has a load resistance RL con- nected between the two collectors. What does the differential gainAd become?
9.49 A bipolar differential amplifier having resistance Re inserted in series with each emitter (as in Fig. P9.47(a)) is biased with a constant current I. When both input terminals are grounded, the dc voltage measured across each Re is found to be 4 VT and that measured across each RC is found to be 60 VT . What differential voltage gain Ad do you expect the amplifier to have?
9.50 A bipolar differential amplifier with emitter- degeneration resistances Re and Re is fed with the arrangement shown in Fig. P9.50. Derive an expression for the overall differential voltage gain Gv ≡ v o d /v sig . If Rsig is of such a value that vid = 0.5vsig, find the gain Gv in terms of RC , re, Re, and α. Now if β is doubled, by what factor does Gv increase?
Problems 681 9.52 Find the voltage gain and the input resistance of the
amplifier shown in Fig. P9.52 assuming β = 100. 5V
25 k
vo
viQ1 Q2
Rin
Figure P9.52
250 250 0.2 mA
Rsig 2
9.53 Find the voltage gain and input resistance of the amplifier in Fig. P9.53 assuming that β = 100.
v
–
sig
2
5V
500
0.1 mA
vid
25 k
vo
0.1 mA
VCM
–
Figure P9.50
v
sig 2
v
Rin
Figure P9.53
i
Rsig 2
9.51 A particular differential amplifier operates from an emitter current source I = 0.4 mA. Each of the collector resistances RC = 20 k and a load resistance RL = 40 k is connected between the two collectors. If the amplifier is fed in the manner shown in Fig. P9.50 with Rsig = 100 k, find the overall voltage gain. Let β = 100.
9.54 Derive an expression for the small-signal voltage gain vo/vi of the circuit shown in Fig. P9.54 in two different ways:
(a) as a differential amplifier
(b) as a cascade of a common-collector stage Q1 and a
common-base stage Q2
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
682 Chapter 9
Differential and Multistage Amplifiers
(e) Usethecommon-modegainfoundin(d)todeterminethe change in VCM that results in Q1 and Q2 entering the triode region.
RD
VDD
Q1
5 V
Q2
RD
vod
CHAPTER 9 PROBLEMS
Figure P9.54
vid
Assume that the BJTs are matched and have a current gain α,
and neglect the Early effect. Verify that both approaches lead
to the same result. VCM
Section 9.3: Common-Mode Rejection
9.55 An NMOS differential pair is biased by a Figure P9.57 current source I = 0.2 mA having an output resistance
1 mA
RSS
1 k
RSS = 100 k. The amplifier has drain resistances RD = 10 k,
using transistors with kn′ W/L = 3 mA/V2 , and ro that is
9.58 It can be shown that if the drain resistors of a MOS differential amplifier have a mismatch RD and if simultaneously the transconductances of Q1 and Q2 have a mismatch gm , the common-mode gain is given by
Rg R Acm≃ D m+ D
2RSS gm RD
Note that this equation indicates that RD can be deliberately varied to compensate for the initial variability in gm and RD, that is, to minimize Acm.
In a MOS differential amplifier for which RD = 5 k and RSS = 25 k, the common-mode gain is measured and found to be 0.002 V/V. Find the percentage change required in one of the two drain resistors so as to reduce Acm to zero (or close to zero).
D 9.59 It is required to design a MOS differential amplifier to have a CMRR of 80 dB. The only source of mismatch in the circuit is a 2% difference between the W/L ratios of the two transistors. Let I = 100 μA and assume that all transistors are operated at VOV = 0.2 V. For the 0.18-μm CMOS fabrication process available, VA′ = 5 V/μm. What is the value of L required for the current-source transistor?
large. If the output is taken differentially and there is a 1%
mismatch between the drain resistances, find A , A , d cm
and CMRR.
9.56 For the differential amplifier shown in Fig. P9.2, let Q1
and Q have k′ (W/L) = 4 mA/V2, and assume that the bias 2p
current source has an output resistance of 30 k. Find V , OV
gm , Ad , Ac m , and the CMRR (in dB) obtained with the output taken differentially. The drain resistances are known to have a mismatch of 2%.
D *9.57 The differential amplifier in Fig. P9.57 utilizes a resistor RSS to establish a 1-mA dc bias current. Note that this amplifier uses a single 5-V supply and thus the dc common-mode voltage VCM cannot be zero. Transistors Q1 andQ2 havekn′W/L=2.5mA/V2,Vt =0.7V,andλ=0.
(a) Find the required value of VCM .
(b) Find the value of RD that results in a differential gain Ad
of 8 V/V.
(c) Determine the dc voltage at the drains.
(d) Determine the single-ended-output common-mode gain
VD1 /VCM . (Hint: You need to take 1/gm into account.)
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
CHAPTER 9 PROBLEMS
D 9.60 A MOS differential amplifier utilizing a simple current source to provide the bias current I is found to have a CMRR of 60 dB. If it is required to raise the CMRR to 100 dB by adding a cascode transistor to the current source, what must the intrinsic gain A0 of the cascode transistor be? If the cascode transistor is operated at VOV = 0.2 V, what must its VA be? If for the specific technology utilized VA′ = 5 V/μm, specify the channel length L of the cascode transistor.
9.61 The differential amplifier circuit of Fig. P9.61 utilizes a resistor connected to the negative power supply to establish the bias current I.
(a) For vB1 = vid /2 and vB2 =−vid /2, where vid is a small
Problems 683 input resistance. For these transistors, β = 100 and
VA=100V.
RC
10 k
Q1
300 kk
10 V
vod RL
20 k
RE
RC
10 k
Q2
200
200
signal with zero average, find the magnitude of the
0.5 mA
Figure P9.62
0.5 mA
differential gain, v /v . o id
(b) Forv =v =v ,wherev hasazeroaverage,find B 1 B 2 i c m i c m
the magnitude of the common-mode gain, v o /v i c m .
(c) Calculate the CMRR.
(d) If vB1 =0.1 sin 2π × 60t + 0.005 sin 2π × 1000t, volts,
andv =0.1sin2π×60t−0.005sin2π×1000t,volts, B2
find v . o
Figure P9.61
9.62 For the differential amplifier shown in Fig. P9.62, identify and sketch the differential half-circuit and the common-mode half-circuit. Find the differential gain, the dif- ferential input resistance, the common-mode gain assuming the resistances RC have 1% tolerance, and the common-mode
9.63 Consider the basic differential circuit in which the transistors have β = 100 and VA = 100 V, with I = 0.2 mA, REE = 500 k, and RC = 25 k. The collector resistances are matched to within 1%. Find:
(a) the differential gain
(b) the differential input resistance
(c) the common-mode gain
(d) the common-mode rejection ratio (e) the common-mode input resistance
9.64 In a bipolar differential-amplifier circuit, the bias cur- rent generator consists of a simple common-emitter transistor operating at 200 μA. For this transistor, and those used in the differential pair, VA = 20 V and β = 50. What common-mode input resistance would result? Assume RC ≪ ro .
9.65 AbipolardifferentialamplifierwithI=0.5mAutilizes transistors for which VA = 50 V and β = 100. The collector resistances RC = 5 k and are matched to within 10%. Find:
(a) the differential gain
(b) thecommon-modegainandtheCMRRifthebiascurrent
I is generated using a simple current mirror
(c) thecommon-modegainandtheCMRRifthebiascurrent I is generated using a Wilson mirror. (Refer to Eq. 8.95
for Ro of the Wilson mirror.)
D 9.66 It is required to design a differential amplifier to
provide the largest possible signal to a pair of 10-k load = Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
684 Chapter 9 Differential and Multistage Amplifiers
resistances. The input differential signal is a sinusoid of 5-mV peak amplitude, which is applied to one input terminal while the other input terminal is grounded. The power supply VCC available is 5 V. To determine the required bias current I, derive an expression for the total voltage at each of the collectors in terms of VCC and I in the presence of the input signal. Then impose the condition that both transistors remain
well out of saturation with a minimum v
0 V. Thus determine the required value of I. For this design, what differential gain is achieved? What is the amplitude of the signal voltage obtained between the two collectors? Assume α ≃1.
D *9.67 Design a BJT differential amplifier that provides two single-ended outputs (at the collectors). The amplifier is to have a differential gain (to each of the two outputs) of at least 100 V/V, a differential input resistance ≥ 10 k, and a common-mode gain (to each of the two outputs) no greater than 0.1 V/V. Use a 2-mA current source for biasing. Give the complete circuit with component values and suitable power supplies that allow for ±2 V swing at each collector. Specify the minimum value that the output resistance of the bias current source must have. If the current source is realized by a simple mirror, what must the minimum value of VA be? The BJTs available have β ≥ 100. What is the value of the input common-mode resistance when the bias source has the lowest acceptable output resistance?
9.68 When the output of a BJT differential amplifier is taken differentially, its CMRR is found to be 34 dB higher than when the output is taken single-endedly. If the only source of common-mode gain when the output is taken differentially is the mismatch in collector resistances, what must this mismatch be (in percent)?
*9.69 In a particular BJT differential amplifier, a production error results in one of the transistors having an emitter– base junction area that is twice that of the other. With the inputs grounded, how will the emitter bias current split between the two transistors? If the output resistance of the current source is 500 k and the resistance in each collector (RC ) is 12 k, find the common-mode gain obtained when the output is taken differentially. Assume α ≃ 1. [Hint: The CM signal currentvicm/REE willsplitbetweenQ1 andQ2 inthesameratio as the bias current I does.]
Section 9.4: DC Offset
D 9.70 An NMOS differential pair is to be used in an amplifier whose drain resistors are 10 k ± 1%. For the
pair, kn′ W/L = 4 mA/V2 . A decision is to be made concerning the bias current I to be used, whether 160 μA or 360 μA. Contrast the differential gain and input offset voltage for the two possibilities.
D 9.71 An NMOS differential amplifier for which the MOSFETs have a transconductance parameter kn and whose drain resistances RD have a mismatch △RD is biased with a current I.
(a) Find expressions for Ad and VOS in terms of kn, RD, △RD /RD , and I. Use these expressions to relate VOS and Ad . (b) Ifkn=4mA/V2,RD=10k,and△RD/RD=0.02,find the maximum gain realized if VOS is to be limited to 1 mV, 2 mV, 3 mV, 4 mV, and 5 mV. For each case, give the value of the required bias current I. Note the trade-off
between gain and offset voltage.
D 9.72 An NMOS amplifier, whose designed operating point is at VOV = 0.3 V, is suspected to have a variability of Vt of ±5 mV, and of W/L and RD (independently) of ±1%. What is the worst-case input offset voltage you would expect to find? What is the major contribution to this total offset? If you used a variation of one of the drain resistors to reduce the output offset to zero and thereby compensate for the uncertainties (including that of the other RD ), what percentage change from nominal would you require?
9.73 An NMOS differential pair operating at a bias current I of 100 μA uses transistors for which kn′ = 200 μA/V2 and W/L = 10. Find the three components of input offset voltage under the conditions that RD/RD = 4%, (W/L)/(W/L) = 4%, and Vt = 5 mV. In the worst case, what might the total offset be? For the usual case of the three effects being independent, what is the offset likely to be?
9.74 A bipolar differential amplifier uses two well-matched transistors, but collector load resistors that are mismatched by 10%. What input offset voltage is required to reduce the differential output voltage to zero?
9.75 A bipolar differential amplifier uses two transistors whose scale currents IS differ by 10%. If the two collector resistors are well matched, find the resulting input offset voltage.
9.76 Modify Eq. (9.114) for the case of a differential amplifier having a resistance RE connected in the emitter of each transistor. Let the bias current source be I.
9.77 A differential amplifier uses two transistors whose β values are β 1 and β 2 . If everything else is matched, show that
CB
of approximately
CHAPTER 9 PROBLEMS
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
the input offset voltage is approximately VT 1/β1 − 1/β2 . EvaluateVOS forβ1=50andβ2=100.
9.78 Two possible differential amplifier designs are consid-
ered, one using BJTs and the other MOSFETs. In both cases,
the collector (drain) resistors are maintained within ±2% of
nominal value. The MOSFETs are operated at V = 200 mV. OV
What input offset voltage results in each case? What does the MOS VOS become if the devices are increased in width by a factor of 4 while the bias current is kept constant?
*9.79 A differential amplifier uses two transistors having VA values of 100 V and 200 V. If everything else is matched, find the resulting input offset voltage. Assume that the two transistorsareintendedtobebiasedataVCE ofabout10V.
*9.80 A differential amplifier is fed in a balanced or push–pull manner, and the source resistance in series with each base is Rs. Show that a mismatch Rs between the values of the two source resistances gives rise to an input offset voltage of approximately (I/2β)Rs / [1+(gmRs)/β].
9.81 One approach to “offset correction” involves the adjustment of the values of RC1 and RC2 so as to reduce the differential output voltage to zero when both input terminals are grounded. This offset-nulling process can be accomplished by utilizing a potentiometer in the collector circuit, as shown in Fig.P9.81. We wish to find the
potentiometer setting, represented by the fraction x of its value connected in series with RC 1 , that is required for nulling the output offset voltage that results from:
(a) RC1 being 4% higher than nominal and RC2 4% lower than nominal
(b) Q1 having an area 5% larger than nominal, while Q2 has area 5% smaller than nominal.
9.82 A differential amplifier for which the total emitter bias current is 400 μA uses transistors for which β is specified to lie between 80 and 200. What is the largest possible input bias current? The smallest possible input bias current? The largest possible input offset current?
**9.83 InaparticularBJTdifferentialamplifier,aproduction error results in one of the transistors having an emitter–base junction area twice that of the other. With both inputs grounded, find the current in each of the two transistors and hence the dc offset voltage at the output, assuming that the collector resistances are equal. Use small-signal analysis to find the input voltage that would restore current balance to the differential pair. Repeat using large-signal analysis and compare results.
D 9.84 A large fraction of mass-produced differential- amplifier modules employing 20-k collector resistors is found to have an input offset voltage ranging from +2 mV to –2 mV. By what amount must one collector resistor be adjusted to reduce the input offset to zero? If an adjustment mechanism is devised that raises one collector resistance while correspondingly lowering the other, what resistance change is needed? If a potentiometer connected as shown in Fig. P9.81 is used, what value of potentiometer resistance (specified to 1 significant digit) is needed? Assume that the offset is entirely due to the finite tolerance of RC .
Section 9.5: The Differential Amplifier with a Current-Mirror Load
9.85 The differential amplifier of Fig. 9.32(a) is measured and found to have a short-circuit transconductance of 2 mA/V. A differential input signal is applied and the output voltage is measured with a load resistance RL connected. It is found thatwhenRL isreducedfrom∞to20k,themagnitudeof the output signal is reduced by half. What do you estimate Ro andAd (withRL disconnected)tobe?
9.86 Acurrent-mirror-loadedNMOSdifferentialamplifieris fabricated in a technology for which |VA′ | = 5 V/μm. All the
Problems 685
CHAPTER 9 PROBLEMS
RC1 5k
Q1
Figure P9.81
VCC
(x) (1 x) 1k
RC2 5k
Q2
1 mA
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
686 Chapter 9 Differential and Multistage Amplifiers
transistors have L = 0.5 μm. If the differential-pair transistors (b) Show that if all transistors are operated at an overdrive
are operated at V = 0.25 V, what open-circuit differential voltageV andhaveequalEarlyvoltagesV,thegainis OV OV A
gain is realized?
9.87 The differential amplifier of Fig. 9.32(a) is biased with I = 200 μA. All transistors have L = 0.5 μm, and Q1 and Q2 have W/L = 50. The circuit is fabricated in a process for which μn Cox = 200 μA/V2 and |VA′ | = 5 V/μm. Find gm1,2 , ro2, ro4, and Ad .
D 9.88 In a current-mirror-loaded differential amplifier of
given by
Evaluate the gain for VOV = 0.20 V and VA = 10 V.
9.91 Figure P9.91 shows the current-mirror-loaded MOS differential amplifier prepared for small-signal analysis. We have “pulled out” ro of each transistor; thus, the current in the drain of each transistor will be gmvgs. To help the reader, we have already indicated approximate values for some of
the form shown in Fig. 9.32(a), all transistors are character-
ized by k′W/L = 4 mA/V2, and V = 5 V. Find the bias Ao
current I for which the gain v /v = 20 V/V. o id
the node voltages. For instance, the output voltage v = 1 g r v , which we have derived in the text. The voltage
+vid/4, which is very far from the virtual ground one
might assume. Also, the voltage at the gate of the mirror
is approximately −vid/4, confirming our contention that the
voltage there is vastly different from the output voltage, hence
the lack of balance in the circuit and the unavailability of a
differential half-circuit. Find the currents labeled i1 to i13 in
terms of (gmvid). Determine their values in the sequence of
their numbering and assume g r ≫ 1. Note that all transistors m o
are assumed to be operating at the same VOV . Write the current values on the circuit diagram and reflect on the results.
A=2V/V 2 d AOV
CHAPTER 9 PROBLEMS
D 9.89 Consider a current-mirror-loaded differential ampli-
fier such as that shown in Fig. 9.32(a) with the bias current
2 mo id
at the common sources has been found to be approximately
source implemented with the modified Wilson mirror of
Fig. P9.89 with I = 200 μA. The transistors have V = 0.5V t
and k′W/L = 5 mA/V2. What is the lowest value of the total power supply (V + V ) that allows each transistor to operate
SS
*9.90 (a) Sketch the circuit of a current-mirror-loaded MOS differential amplifier in which the input transistors are cascoded and a cascode current mirror is used for the load.
with VDS ≥ VGS ?
DD
I
I
Q Q 87
vg3 vid4 r oQ3 Q4o
r
RSS
i13
i11
i12
i2 i3
i6 i4 Q2
i1
1
2 (gmro) vid
(vid 2)
vo
Q5
Q6
(vid 2)
Figure P9.91
i9
i8
Q1
ro
ro
i10
i7
i5
vs vid4
Figure P9.89
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
CHAPTER 9 PROBLEMS
9.92 A current-mirror-loaded NMOS differential amplifier
operates with a bias current I of 200 μA. The NMOS tran-
sistors are operated at V = 0.2 V and the PMOS devices at OV
VOV = 0.3 V. The Early voltages are 20 V for the NMOS and 12 V for the PMOS transistors. Find Gm , Ro , and Ad . For what value of load resistance is the gain reduced by a factor of 2?
9.93 This problem investigates the effect of transis- tor mismatches on the input offset voltage of the current-mirror-loaded MOS differential amplifier of Fig. 9.32(a). For this purpose, ground both input terminals and short-circuit the output node to ground.
(a) If the amplifying transistors Q1 and Q2 exhibit a W/L mismatch of (W/L)A, find the resulting short-circuit output currentandhenceshowthatthecorrespondingVOS isgivenby
VOS1 =VOV/2(W/L)A (W/L)A
where VOV is the overdrive voltage at which Q1 and Q2 are operating.
(b) Repeat for a mismatch (W/L)M in the W/L ratios of the mirror transistor Q3 and Q4 to show that the corresponding VOS isgivenby
VOS2 =VOV/2(W/L)M (W/L)M
where VOV is the overdrive voltage at which Q1 and Q2 are
operating.
of nominal, find the worst-case total offset voltage VOS . 9.94 The differential amplifier in Fig. 9.36(a) is operated
with I = 500 μA, with devices for which VA =10 V and β = 100. What differential input resistance, output resistance, short-circuit transconductance, and open-circuit voltage gain would you expect? What will the voltage gain be if the input resistanceofthesubsequentstageisequaltoRid ofthisstage?
9.95 A bipolar differential amplifier having a simple pnp vd current-mirror load is found to have an input offset voltage of
2 mV. If the offset is attributable entirely to the finite β of the pnptransistors,whatmustβP be?
VCC
5
9.97 For the current-mirror-loaded bipolar differential pair, replacing the simple current-mirror load by the Wilson mirror of Fig. 8.40(a), find the expected systematic input offset voltage. Evaluate VOS for βP , = 50.
9.98 Figure P9.98 shows a differential cascode amplifier with an active load formed by a Wilson current mirror. Utilizing the expressions derived in Chapter 8 for the output resistance of a bipolar cascode and the output resistance of the Wilson mirror, and assuming all transistors to be identical, show that the differential voltage gain Ad is given approximately by
1
Ad = 3βgmro
EvaluateAd forthecaseofβ=100andVA=20V.
Problems 687
Q5
Q6
Q7
(c) For a circuit in which all transistors are operated at
V = 0.2 V and all W/L ratios are accurate to within ±1%
OV o
v
Q3
Q1
VBIAS
I
Q4
Q2
5 V
9.96 For the current-mirror-loaded bipolar differential
pair, replacing the simple current-mirror load by the base-current-compensated mirror of Fig. 8.11, find the
expected systematic input offset voltage. Evaluate VOS for
βP =50. FigureP9.98
VEE
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
688 Chapter 9 Differential and Multistage Amplifiers D 9.99 Consider the bias design of the Wilson-loaded
cascode differential amplifier shown in Fig. P9.98.
(a) What is the largest signal voltage possible at the output without Q7 saturating? Assume that the CB junction conducts when the voltage across it exceeds 0.4 V.
(b) What should the dc bias voltage established at the output (by an arrangement not shown) be in order to allow for positive output signal swing of 1.5 V?
(c) What should the value of VBIAS be in order to allow for a negative output signal swing of 1.5 V?
(d) What is the upper limit on the input common-mode voltagevCM?
(b) With vI =0 V (dc) + vid, find the input signal current ii and hence the input differential resistance Ri d . Compare with the case without the Q7–Q8 connection. By what factor does Rid increase?
9.101 For the folded-cascode differential amplifier of Fig. 9.38, find the value of VBIAS that results in the largest possible positive output swing, while keeping Q3 , Q4 , and the pnp transistors that realize the current sources out of saturation. Assume VCC = VEE = 5 V. If the dc level at the output is 0 V, find the maximum allowable output signal swing. For I = 0.5 mA, βP =50, βN =100, and VA =100 V find Gm, Ro4, Ro5, Ro, and Ad.
CHAPTER 9 PROBLEMS
**9.100 Figure P9.100 shows a modified cascode differen- tial amplifier. Here Q and Q are the cascode transistors.
letV =V =3V,I=0.2mA,k′W/L=6.4mA/V2;V DDSS p A
34
However, the manner in which Q3 is connected with its
for p-channel MOSFETs is 10 V, VA for npn transistors is
base current feeding the current mirror Q7–Q8 results in very interesting input properties. Note that for simplicity the circuit is shown with the base of Q2 grounded. Assume that all transistors have equal β’s.
V
30 V. Find Gm, Ro, and Ad. V
I
QQ
v
QQ
V Figure P9.102
D 9.103 It is required to design the current-mirror-
loaded differential MOS amplifier of Fig. 9.32 to obtain a
9.102 For the BiCMOS differential amplifier in Fig. P9.102
QQ
QQ
Q
v
Q
vQQ I
I
V
differential gain of 50 V/V. The technology available provides
μ C = 4μ C = 400μA/V2, V = 0.5V, and V′ = n ox p ox t A
Figure P9.100
20 V/μm and operates from ±1 V supplies. Use a bias current I = 200 μA and operate all devices at V = 0.2 V.
OV
(a) Find the W/L ratios of the four transistors.
(b) Specify the channel length required of all transistors. (c) If VICM = 0, what is the allowable range of vO?
(a) With vI =0 V dc, find the input bias current IB assuming all transistors have equal value of β. Compare with the case without the Q7–Q8 connection.
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
(d) If I is delivered by a simple NMOS current source operated at the same VOV and having the same channel length as the other four transistors, determine the CMRR obtained.
9.104 Consider the current-mirror-loaded MOS differential amplifier of Fig. 9.32(a) in two cases:
(a) Current source I is implemented with a simple current mirror.
(b) Current source I is implemented with the modified Wilson current mirror shown in Fig. P9.104.
Recalling that for the simple mirror R = r and for SS o QS
the Wilson mirror R ≃ g r r , and assuming that all SS m7 o7 o5
9.105 The MOS differential amplifier of Fig. 9.32(a) is biased with a simple current mirror delivering I = 200 μA. All transistors are operated at VOV = 0.2 V and have VA = 5 V. Find Gm, Ro, Ad, RSS, Gmcm, Rim, Am, Rom, Ro2, Acm, and CMRR.
9.106 A current-mirror-loaded MOS differential amplifier is found to have a differential voltage gain Ad of 30 V/V. Its bias current source has an output resistance RSS = 45 k. The current mirror utilized has a current gain Am of 0.98 A/A and an output resistance Rom of 45 k. If the common-mode output resistances of the amplifier, Ro1 and Ro2 , are very large, find Ac m and CMRR.
9.107 A current-mirror-loaded MOS differential amplifier is found to have a differential voltage gain Ad of 50 V/V and a CMRR of 60 dB. If the output resistance of the bias current source is 20 k and the output resistance of the current-mirror load is 20 k, what is the expected magnitude of the deviation from unity of the current gain of the load mirror?
D *9.108 Design the circuit of Fig. 9.36(a) using a basic current mirror to implement the current source I. It is required that the short-circuit transconductance be 5 mA/V. Use ±5-V power supplies and BJTs that have β = 100 and VA = 100 V. Give the complete circuit with component values and specify the differential input resistance Rid, the output resistance Ro, the open-circuit voltage gain Ad , the input bias current, the input common-mode range, the common-mode gain, and the CMRR.
D *9.109 Repeat the design of the amplifier specified in Problem 9.108 utilizing a Widlar current source (Fig. 8.42) to supply the bias current. Assume that the largest resistance available is 2 k.
9.110 A bipolar differential amplifier such as that shown in Fig.9.36(a)hasI=0.4mA,VA=40V,andβ=150.Find Gm , Ro , Ad , and Ri d . If the bias current source is implemented with a simple npn current mirror, find REE, Acm, and CMRR. If the amplifier is fed differentially with a source having a total of 30 k resistance (i.e., 15 k in series with the base lead of each of Q1 and Q2), find the overall differential voltage gain.
transistors have the same VA and k′W/L, show that for
case (a)
and for case (b)
V 2 A
CMRR = 2
√ V 3
Problems 689
CHAPTER 9 PROBLEMS
VOV CMRR=2 2 A
where VOV is the overdrive voltage that corresponds to a
drain current of I/2. For k′W/L = 4 mA/ V2, I = 160 μA, and
V = 5 V, find CMRR for both cases. A
VOV
I
I
RSS
Q8 Q7
Q5 Q6
Figure P9.104
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
690 Chapter 9 Differential and Multistage Amplifiers
9.111 For the current-mirror-loaded Fig. P9.111, find:
(a) differential input resistance, Rid (b) Ad
(c) CMRR
differential pair
in
Assume β = 100, |VBE | = 0.7 V, |VA | = 60 V, Vt = 0.7 V, and k′(W/L) = 2 mA/V2.
Assume β = 100, |VBE | = 0.7 V, and |VA | = 60 V.
+5 V
+9 V
Q3
Q1
Q4
Q2
CHAPTER 9 PROBLEMS
Q3
Q1
Q4
Q2
vid
vo
+ 15 V
vid
vo
+9 V
6.65 k
Q6
Q7 Q6
R = 144 k Q8
Q5
Q5
–5 V
Figure P9.112
Figure P9.111
Section 9.6: Multistage Amplifiers
9.112 Forthecurrent-mirror-loadeddifferentialamplifierin Fig. P9.112, find:
(a) differential input resistance, R id
(b) Ad
(c) CMRR
μnCox = 180 μA/V2, μpCox = 60 μA/V2, VA = 9 V for all
–5 V
9.113 Consider the circuit in Fig. 9.40 with the
device geometries (in μm) shown in TableP9.113.
Let I = 225 μA, V = 0.75 V for all devices, REF t
devices, VDD = VSS = 1.5 V. Determine the width of Q6 , W,
that will ensure that the op amp will not have a systematic
offset voltage. Then, for all devices evaluate I , V , V , D OV GS
gm , and ro . Provide your results in a table similar to Table 9.1. Also find A1 , A2 , the open-loop voltage gain, the input
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
Table P9.113
Transistor Q1 Q2 Q3 Q4
W/L 30/0.5 30/0.5 10/0.5 10/0.5
common-mode range, and the output voltage range. Neglect the effect of VA on the bias currents.
D 9.114 The two-stage CMOS op amp in Fig. P9.114 is fabricated in a 0.18-μm technology having kn′ = 4kp′ = 400 μA/V2, Vtn = −Vtp = 0.4 V.
(a) With A and B grounded, perform a dc design that will
result in each of Q1 , Q2 , Q3 , and Q4 conducting a drain
Q5 Q6 Q7 Q8 60/0.5 W/0.5 60/0.5 60/0.5
(d) With vA = vid /2 and vB = −vid /2, find the voltage gain vo/vid . Assume an Early voltage of 6 V.
D *9.115 In a particular design of the CMOS op amp of Fig. 9.40 the designer wishes to investigate the effects of increasing the W/L ratio of both Q1 and Q2 by a factor of 4. Assuming that all other parameters are kept unchanged, refer to Example9.6 to help you answer the following questions:
Problems 691
CHAPTER 9 PROBLEMS
current of 100 μA and each of Q and Q a current of
67
200 μA. Design so that all transistors operate at 0.2-V overdrive voltages. Specify the W/L ratio required for each MOSFET. Present your results in tabular form. What is the dc voltage at the output (ideally)?
(b) Findtheinputcommon-moderange.
(c) Find the allowable range of the output voltage.
(a) Find the resulting change in VOV and in gm of Q1 and Q2.
(b) What change results in the voltage gain of the input stage? In the overall voltage gain?
(c) Whatistheeffectontheinputoffsetvoltages?(Youmight wish to refer to Section 9.4).
VDD 0.9 V
Q3 IREF 200 A
A
Q4
Q6
Q1 Q2 B vo
Q Q5 Q 87
VSS 0.9 V
Figure P9.114
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
692 Chapter 9 Differential and Multistage Amplifiers
9.116 Consider the amplifier of Fig. 9.40, whose parameters are specified in Example 9.6. If a manufacturing error results in the W/L ratio of Q7 being 48/0.8, find the current that Q7 will now conduct. Thus find the systematic offset voltage that will appear at the output. (Use the results of Example 9.6.) Assuming that the open-loop gain will remain approximately unchanged from the value found in Example 9.6, find the corresponding value of input offset voltage, VOS .
9.117 Consider the input stage of the CMOS op amp in Fig. 9.40 with both inputs grounded. Assume that the two sides of the input stage are perfectly matched except that the threshold voltages of Q3 and Q4 have a mismatch Vt. Show that a current gm3Vt appears at the output of the first stage. What is the corresponding input offset voltage?
(a) With A and B at a dc voltage of VDD/2, perform a dc design that will result in each of Q1, Q2, Q3, and Q4 conducting a drain current of 200 μA and each of Q6 and Q7 conducting a current of 400 μA. Design so that all transistors operate at 0.15-V overdrive voltages. Specify the W/L ratio required for each MOSFET. Present all results in a table.
(b) Find the input common-mode range.
(c) Find the allowable range of the output voltage.
(d) With vA = vid /2 and vB = −vid /2, find the voltage gain
vo /vi d . Assume an Early voltage of 1.8 V.
*9.119 Figure P9.119 shows a bipolar op-amp circuit
that resembles the CMOS op amp of Fig.9.40. Here,
the input differential pair Q1–Q2 is loaded in a cur-
rent mirror formed by Q3 and Q4. The second stage
is formed by the current-source-loaded common-emitter
transistor Q5. Unlike the CMOS circuit, here there is
CHAPTER 9 PROBLEMS
9.118 The two-stage op amp in Figure P9.114 is fabricated
in a 65-nm technology having k′ = 5.4 × k′ = 540 μA/V2
and Vt n = −Vtp = 0.35 V. The amplifier is operated with ter 11. All transistors have β = 100, VBE = 0.7 V, and
VDD =+1.2 V and VSS =0 V.
0.4 mA
ro=∞.
an output stage formed by the emitter follower Q6. The
function of capacitor C will be explained later, in Chap- np C
5V
0.5 mA
Q1 Q2 CC Q6
vo
Q5
1 mA RL
Q3 Q4
Figure P9.119
5V
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
CHAPTER 9 PROBLEMS
(a) For inputs grounded and output held at 0 V (by negative feedback, not shown) find the emitter currents of all transistors.
(b) Calculate the gain of the amplifier with RL = 1 k.
9.120 A BJT differential amplifier, biased to have re = 50 and utilizing two 50- emitter resistors and 5-k loads, drives a second differential stage biased to have re = 25 . All BJTs have β = 100. What is the voltage gain of the first stage? Also find the input resistance of the first stage, and the current gain from the input of the first stage to the collectors of the second stage.
9.121 In the multistage amplifier of Fig. 9.41, emitter resistors are to be introduced—100 in the emitter lead of each of the first-stage transistors and 25 for each of the second-stage transistors. What is the effect on input resistance, the voltage gain of the first stage, and the overall voltage gain? Use the bias values found in Example 9.7.
D 9.122 Consider the circuit of Fig. 9.41 and its output resistance. Which resistor has the most effect on the output resistance? What should this resistor be changed to if the output resistance is to be reduced by a factor of 2? What will the amplifier gain become after this change? What other change can you make to restore the amplifier gain to approximately its prior value?
D 9.123 (a) If, in the multistage amplifier of Fig. 9.41, the resistor R5 is replaced by a constant-current source ≃ 1 mA, such that the bias situation is essentially unaffected, what does the overall voltage gain of the amplifier become? Assume that the output resistance of the current source is very high. Use the results of Example 9.8.
(b) With the modification suggested in (a), what is the effect of the change on output resistance? What is the overall gain of the amplifier when loaded by 100 to ground? The original amplifier (before modification) has an output resistance of 152 and a voltage gain of 8513 V/V. What is its gain when loaded by 100 ? Comment. Use β = 100.
*9.124 FigureP9.124showsathree-stageamplifierinwhich the stages are directly coupled. The amplifier, however, utilizes bypass capacitors, and, as such, its frequency response falls off at low frequencies. For our purposes here, we shall assume that the capacitors are large enough to act as perfect short circuits at all signal frequencies of interest.
5V
3.3 k
Problems 693
8.2 k
68 k
Q2
vi Q1 Q3
33 k
Figure P9.124
5.6 k
vo 2.4 k
4.7 k
5V
(a) Find the dc bias current in each of the three transistors. Also find the dc voltage at the output. Assume V =
BE
0.7 V, β = 100, and neglect the Early effect.
(b) Find the input resistance and the output resistance.
(c) Use the current-gain method to evaluate the voltage gain
vo/vi.
9.125 For the current mirror in Fig. P9.125, replace the
transistors with their hybrid-π models and show that:
Ri = 1 ∥ro1 gm1
1
Ais ≃Ais 1− ideal
gm1ro1
A =g/g
is m2m1
ideal
Ro =ro2
where Ais denotes the short-circuit current gain.
ii
Ri iosc
Ro
Q1 Q2
Figure P9.125
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
694 Chapter 9 Differential and Multistage Amplifiers
**9.126 The MOS differential amplifier shown in Fig.P9.126 utilizes three current mirrors for signal transmission: Q4−Q6 has a transmission factor of 2 [i.e., (W/L)6/(W/L)4 = 2], Q3−Q5 has a transmission factor of 1,
andQ−Q hasatransmissionfactorof2.Alltransistorsare
VOV , show that the CMRR is given by 2
CMRR=4 VA/VOV
(e) Find the input CM range and the output linear range in
7 8
sized to operate at the same overdrive voltage, V OV
. All
terms of V , V , and V . DDt OV
transistors have the same Early voltage VA. VDD
D ***9.127 For the circuit shown in Fig. P9.127, which uses a folded cascode involving transistor Q , all transistors have
Q5 Q3 Q4 Q6
3
VBE = 0.7 V for the currents involved, VA = 200 V, and
CHAPTER 9 PROBLEMS
Q1
Q2
β = 100. The circuit is relatively conventional except for Q5, which operates in a Class B mode (we will study this in Chapter 12) to provide an increased negative output swing for low-resistance loads.
vo
I
VDD
QF
1
F
1
E
5V
G
QG
Q7
Figure P9.126
Q8
2
QE
Q3
C
(a) Provide in tabular form the values of ID , gm , and ro of each of the eight transistors in terms of I, VOV , and VA .
R
v Q1 Q2
v B QB
Q4
Q5
D vO Q
IREF A
(b) Show that the differential voltage gain Ad is given by Ad=2gm1 ro6∥ro8 =VA/VOV
(c) Show that the CM gain is given by
A ≃ r o 6 ∥ r o 8 1
cm RSS gm7ro7
where RSS is the output resistance of the bias current
source I. [Hint: Replace each of Q1 and Q2 together with their source resistance 2RSS with a controlled current-source v i c m /2RSS and an output resistance. For each current mirror, the current transfer ratio is given by
Ai ≃Ai (ideal) 1− 1 gm ro
where gm and ro are the parameters of the input transistor
of the mirror. (see Problem 9.125 above.)]
(d) If the current source I is implemented using a simple mirror and the MOS transistor is operated at the same
Q
QC AD
1 2 1 10
5 V
Figure P9.127
(b) Provide in tabular form the bias currents in all transistors together with gm and ro for the signal transistors (Q1 , Q2 , Q3, Q4, and Q5) and ro for QC, QD, and QG.
(c) Now, using β=100, find the voltage gain vo/(v+ −v−), and in the process, verify the polarity of the input terminals.
(a) Perform a bias calculation assuming VBE = 0.7 V, high β, VA =∞, v+ =v− =0 V, and vO is stabilized by feedback to about 0 V. Find R so that the reference current IREF is 100 μA. What are the voltages at all the labeled nodes?
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
(d) Findtheinputandoutputresistances.
(e) Find the input common-mode range for linear operation.
(f) For no load, what is the range of available output voltages,
(g) Forwhatloadresistanceconnectedtogroundistheoutput negative voltage limited to −1 V before Q7 begins to conduct?
(h) For a load resistance one-tenth of that found in (g), what is the output signal swing?
assuming V = 0.3 V? CE sat
(g) Now consider the situation with a load resistance connected from the output to ground. At the positive and negative limits of the output signal swing, find the smallest load resistance that can be driven if one or the other of Q1 or Q2 is allowed to cut off.
1W 2W 4W QF Q3 Q4
5V
Q5 2W
Problems 695
CHAPTER 9 PROBLEMS
D ***9.128 In the CMOS op amp shown in Fig. P9.128, all
2FG
MOSdeviceshave V =1V,μ C =2 μ C =40μA/V , Q H t nox pox E
VA = 50 V, and L = 5 μm. Device widths are indicated on 1W the diagram as multiples of W, where W = 5 μm. E
v Q1 Q2 1W
B
Q6 10W
(a) Design R to provide a 10-μA reference current.
(b) Assuming vO =0 V, as established by external feedback, R v
1W
20W
QC
vO
QD
C
Q7
5W
D
perform a bias analysis, finding all the labeled node
voltages, and VGS and ID for all transistors.
(c) ProvideintableformI ,V ,g ,andr foralldevices.
IREF A
D GS m o Q
(d) Calculate the voltage gain vo/ v+ −v− , the input A QB
1W
resistance, and the output resistance. 1W 2W (e) What is the input common-mode range?
5V
(f) What is the output signal range for no load?
Figure P9.128
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
CHAPTER 10
Frequency Response
Introduction 697
10.1 Low-Frequency Response of Discrete-Circuit Common-Source and Common-Emitter Amplifiers 699
10.2 Internal Capacitive Effects and the High-Frequency Model of the MOSFET andtheBJT 711
10.3 High-Frequency Response of the CS andCEAmplifiers 722
10.4 Useful Tools for the Analysis of the High-Frequency Response of Amplifiers 739
10.5 High-Frequency Response of the Common-Gate and Cascode Amplifiers 748
10.6 High-Frequency Response of the SourceandEmitterFollowers 760
10.7 High-Frequency Response of DifferentialAmplifiers 768
10.8 Other Wideband Amplifier Configurations 778
Summary 788 Problems 789
IN THIS CHAPTER YOU WILL LEARN
1. How coupling and bypass capacitors cause the gain of discrete-circuit amplifiers to fall offatlowfrequencies,andhowtoobtainanestimateofthefrequencyfL atwhichthe gain decreases by 3 dB below its value at midband.
2. The internal capacitive effects present in the MOSFET and the BJT and how to model these effects by adding capacitances to the hybrid-π or T model of each of the two transistor types.
3. The high-frequency limitation on the gain of the CS and CE amplifiers, and how the gainfalloffandtheupper3-dBfrequencyfH aremostlydeterminedbythesmall capacitance between the drain and gate (collector and base).
4. Powerful methods for the analysis of the high-frequency response of amplifier circuits of varying complexity.
5. How the cascode amplifier studied in Chapter 8 can be designed to obtain wider bandwidth than is possible with the CS and CE amplifiers.
6. The high-frequency performance of the source and emitter followers.
7. The high-frequency performance of differential amplifiers.
8. Circuit configurations for obtaining wideband amplification.
Introduction
Our study of transistor amplifiers in Chapters 5 through 9 has assumed that their gain is constant independent of the frequency of the input signal. This would imply that their bandwidth is infinite, which of course is not true! To illustrate, we show in Fig. 10.1 a sketch of the magnitude of the gain versus the frequency of the input signal of a discrete-circuit BJT or MOS amplifier. Observe that there is indeed a wide frequency range over which the gain remains almost constant. This is the useful frequency range of operation for the particular amplifier. Thus far, we have been assuming that our amplifiers are operating in this band, called the middle-frequency band or midband. The amplifier is designed so that its midband coincides with the frequency spectrum of the signals it is required to amplify. If this were not the case, the amplifier would distort the frequency spectrum of the input signal, with different components of the input signal being amplified by different amounts.
697
698 Chapter 10
Frequency Response
Vo
V (dB)
sig
Low-frequency band
• Gain falls off due to the effects of coupling and
bypass capacitors
fL
Figure10.1 Sketchofthemagnitudeofthegainofadiscrete-circuitBJTorMOSamplifierversusfrequency. The graph delineates the three frequency bands relevant to frequency-response determination.
Figure 10.1 indicates that at lower frequencies, the magnitude of the amplifier gain falls off. This occurs because the coupling and bypass capacitors no longer have low impedances. Recall that we assumed that their impedances were small enough to act as short circuits. Although this can be true at midband frequencies, as the frequency of the input signal is lowered, the reactance 1/jωC of each of these capacitors becomes significant and, as will be shown in Section 10.1, this results in a decrease in the overall voltage gain of the amplifier. In the analysis of the low-frequency response of discrete-circuit amplifiers in Section 10.1 we will be particularly interested in the determination of the frequency fL , which defines the lower end of the midband. It is usually defined as the frequency at which the gain drops by 3 dB below its value in midband. Integrated-circuit amplifiers do not utilize coupling and bypass capacitors, and thus their midband extends down to zero frequency (dc), as shown in Fig. 10.2.
Figures 10.1 and 10.2 indicate that the gain of the amplifier falls off at the high-frequency end. This is due to internal capacitive effects in the BJT and in the MOSFET. We shall study these effects in Section 10.2 and model them with capacitances that we will add to the hybrid-π or T model of the BJT and the MOSFET. The resulting high-frequency device models will be utilized in Section 10.3 in the analysis of the high-frequency response of the CS and CE amplifiers, both discrete and integrated. We will be specifically interested in the determination of the frequency fH , which defines the upper end of the midband. It is defined as the frequency at which the gain drops by 3 dB below its midband value. Thus, the amplifier bandwidth is defined by fL and fH (0 and fH for IC amplifiers):
BW = fH − fL (discrete-circuit amplifiers) BW=fH (integrated-circuitamplifiers)
A figure of merit for the amplifier is its gain–bandwidth product, defined as GB=|AM|BW
It will be seen that in amplifier design, it is usually possible to trade off gain for bandwidth.
Midband
• All capacitances can be neglected
3 dB
High-frequency band
• Gain falls off
due to the internal
capacitive effects of the BJT or the MOSFET
f (Hz) (log scale)
20 log A
M (dB)
fH
10.1 Low-Frequency Response of Discrete-Circuit Common-Source and Common-Emitter Amplifiers 699 Vo (dB)
Vsig
20 log AM
0
3 dB
fH f
Figure 10.2 Frequency response of a direct-coupled (dc) amplifier. Observe that the gain does not fall off atlowfrequencies,andthemidbandgainAM extendsdowntozerofrequency.
The remainder of this chapter will be concerned with the frequency-response analysis of a variety of amplifier configurations of varying degrees of complexity. Of particular interest to us are ways to extend the amplifier bandwidth (i.e., increase fH ) either by adding specific circuit components, such as source and emitter-degeneration resistances, or by changing the circuit configuration altogether.
Before embarking on the study of this chapter, the reader is urged to review Section 1.6, which introduces the subject of amplifier frequency response and the extremely important topic of single-time-constant (STC) circuits. More details on STC circuits can be found in Appendix E. As well, Appendix F provides a review of important tools from circuit and system theory: poles, zeros, and Bode plots.
Finally, a note on notation: Since we will be dealing with quantities that are functions of frequency, or, equivalently, the Laplace variable s, we will be using capital letters with lowercase subscripts for our symbols. This practice conforms with the symbol notation introduced in Chapter 1.
10.1 Low-Frequency Response of Discrete-Circuit Common-Source and Common-Emitter Amplifiers
In this section, we consider the effect of the coupling and bypass capacitors on the gain of discrete-circuit common-source (CS) and common-emitter (CE) amplifiers. As mentioned earlier, their effect manifests itself only at low frequencies (i.e., below the midband). We consider first the CS amplifier, since the infinite input resistance at the gate of the MOSFET makes the analysis of this circuit simpler than that of its CE counterpart.
10.1.1 The CS Amplifier
Figure 10.3(a) shows a discrete-circuit common-source amplifier utilizing the classical biasing arrangement (Section 7.5.1). Two coupling capacitors, CC1 and CC2, and a bypass capacitor CS are employed. At midband frequencies, these large capacitances have negligibly small
700 Chapter 10
Frequency Response
Rsig
RG1 CC 1
VDD
RD
RS
CC2
RL
CS
Vo
Vsig
RG2
(a)
Id
CC2
Io RD RL Vo
Rsig
C
C1
RG 1
Vg
0
RS
Id = Is 1/gm
Is
Vsig
RG 2
CS
RG = RG1RG2 (b)
ZS = RS CS
Figure 10.3 (a) Capacitatively coupled common-source amplifier. (b) The amplifier equivalent circuit at low frequencies. Note that the T model is used for the MOSFET and ro is neglected.
impedances and can be assumed to be perfect short circuits for the purpose of calculating the midband gain, as was done in Section 7.5.1. However, at low frequencies, the reactance 1/jωC of each of the three capacitances increases and the amplifier gain decreases, as we shall now show.
To determine the amplifier gain Vo/Vsig at low frequencies, we utilize the amplifier equivalent circuit shown in Fig. 10.3(b). This circuit is obtained by short-circuiting VDD and replacing the MOSFET with its T model, which is the most convenient model to use when an impedance, such as ZS, is present in the source lead. The transistor ro has been omitted because including it would complicate the analysis considerably and, moreover, as mentioned in Chapter 7, ro has a negligible effect on the performance of discrete-circuit amplifiers, as can be verified using circuit simulation.
} }
10.1 Low-Frequency Response of Discrete-Circuit Common-Source and Common-Emitter Amplifiers 701 The gain Vo /Vsig of the amplifier can be obtained from the equivalent circuit in Fig. 10.3(b)
by starting at the source and working our way to the load, as
Vo =Vg ×Id ×Vo Vsig Vsig Vg Id
where Vg is the voltage between gate and ground, and Id is the drain current. To find the fraction of Vsig that appears at the transistor gate, Vg, we note that the input resistance at the gate is infinite and thus the amplifier input resistance is RG = RG1 ∥ RG2 . Using the voltage-divider rule gives
V =V RG g sig 1
RG+sC +Rsig C1
which can be rearranged in the form
Vg = RG s Vsig RG+Rsig s+ 1
CC1(RG +Rsig)
(10.1)
Thus, we see that the effect of CC1 is to cause the expression for the signal transmission from the signal source to the amplifier input to acquire a frequency-dependent factor. From Section 1.6 we recognize this factor as the transfer function of a single-time-constant circuit of the high-pass type, with a pole frequency ωP1,
ωP1 = 1/CC1(Rsig + RG) (10.2)
In addition to the pole, CC1 introduces a zero at s = 0 (dc). This is hardly surprising, since CC1 is included in the amplifier circuit because it blocks dc. Figure 10.4 shows a sketch of the magnitude of the frequency-dependent factor in the transfer function of Eq. (10.1) versus frequency ω.
Continuing with the analysis, we next determine the drain current Id , which is equal to the source current Is. The latter can be found by dividing Vg by the total impedance in the source
Magnitude (dB)
0 –3
+20 dBdecade
vP1
Figure 10.4 Sketch of the magnitude of the high-pass function
frequency ω.
v (log scale) s , that is, ω
versus
s+ωP1 ω2 +ω2 P1
702 Chapter 10
Frequency Response
lead, (1/gm + ZS ),
where Thus,
Thus, the bypass capacitor introduces a pole with frequency ωP2,
ωP2 = gm + 1/RS CS
and a transmission zero on the negative real axis of the s plane at sZ=− 1
I=I=Vg =gVYS
d s 1 mggm+YS
YS = 1 = 1 +sCS
g +ZS m
ZS
Id =g V m
RS
s+1 CSRS
(10.3)
(10.4)
(10.5)
(10.6)
gm +1/RS g s+CS
and thus has a frequency
CS RS
ωZ= 1 CS RS
Observe that since gm is usually large, ωP2 ≫ ωZ . That is, ωP2 will be closer to the midband, and thusitplaysamoresignificantroleindeterminingωL thandoesωZ.Figure10.5showsasketch of the magnitude of the frequency-dependent factor of the transfer function in Eq. (10.3).
To complete the analysis, we find Vo by first using the current-divider rule to determine thefractionofId thatflowsthroughRL,
Magnitude (dB)
0 –3
I =−I RD od1
RD+sC +RL C2
+20 dBdecade
vZ vP2
Figure 10.5
Sketch of the magnitude of the function s + ωZ versus frequency ω. s+ωP2
3 dB
v (log scale)
10.1 Low-Frequency Response of Discrete-Circuit Common-Source and Common-Emitter Amplifiers 703 Magnitude
(dB)
0 –3
+20 dBdecade
vP3
Figure 10.6 Sketch of the magnitude of the high-pass function
and then multiplying Io by RL . The result is
Vo =− RDRL s
s
s+ωP3
v (log scale) versus frequency ω.
Id RD+RL s+
from which we see that CC2 introduces a pole with frequency,
ωP3 = 1 CC2(RD +RL)
1 CC2(RD +RL)
(10.7)
(10.8)
and a zero at s = 0 (dc). A sketch of the magnitude of the frequency-dependent factor of the transfer function in Eq. (10.7) is shown in Fig. 10.6.
The overall low-frequency gain function of the amplifier can be found by combining Eqs. (10.1), (10.3), and (10.7),
V R
o=− G gm(RD∥RL)
s s+ω s Z
s+ωP3
Vsig RG +Rsig V
s+ωP1 s+ωP2
s s+ω s
Z VMs+ωs+ωs+ω
o =A
sig P1 P2 P3
(10.9)
(10.10)
where AM , the midband gain, is given by
AM =− RG gm(RD∥RL)
RG +Rsig
which is the value we would have obtained, had we assumed that CC1, CS, and CC2 were acting as perfect short circuits. In this regard, note from Eq. (10.9) that at midband frequencies—that is,atfrequenciess=jωwithωmuchhigherthanωP1,ωP2,ωZ,andωP3—Vo/Vsig approaches AM , as should be expected.
704 Chapter 10 Vo (dB)
Frequency Response
Vsig
3 dB
20 dBdecade
40 dBdecade
60 dBdecade
40 dBdecade
20 log AM
0
fZ fP1 fP3 fP2
Figure 10.7 Sketch of the low-frequency magnitude response of a CS amplifier for which the three pole
frequencies are sufficiently separated for their effects to appear distinct.
Determining the 3-dB Frequency fL The magnitude of the amplifier gain at a frequency
ω can be obtained by substituting s = jω in Eq. (10.9) and evaluating the magnitude of the
resulting complex function. In this way, the low-frequency response of the amplifier can be
L
A simpler approach for determining fL is possible if the poles and zeros are sufficiently separated from one another. In this case, we can employ the Bode plot rules (see Appendix F) to obtain a Bode plot for the gain magnitude. Such a plot is shown in Fig. 10.7. This graph is simply a combination of the graphs in Figs. 10.4, 10.5, and 10.6. Observe that since the poles and zeros are sufficiently separated, their effects appear distinct. As we move downward in frequency from the midband, we find that at each pole frequency, the slope of the asymptote to the gain function increases by 20 dB/decade, and at the zero frequency (fZ ) it decreases by 20 dB/decade. Note that for the purpose of this sketch, we assumed fP2 to be the highest of the three poles and zero frequencies, and that the zero has the lowest frequency.
Aquickwayforestimatingthe3-dBfrequencyfL ispossibleifthehighest-frequencypole (here, assumed to be fP2) is separated from the nearest pole or zero (here, fP1) by at least a factor of 4 (two octaves). In such a case, fL is approximately equal to the highest of the pole frequencies,
fL ≃fP2 (10.11)
We refer to this situation as one in which a dominant pole exists, with the frequency of the dominant pole being fP2. Of course, if a dominant pole exists, fL can be estimated without the need for the Bode plot.
fL
plottedversusfrequency,andthelower3-dBfrequencyf canbedeterminedasthefrequency
√ atwhich|Vo/Vsig |dropsto|AM|/ 2.
f (Hz) (log scale)
10.1 Low-Frequency Response of Discrete-Circuit Common-Source and Common-Emitter Amplifiers 705
Rsig
CC1
t = C (R + R ) 1 C1 G sig
(a)
RG
RS
1gm
t = C (R 1 ) S S S gm
(b)
CS
RD
C C2
t = C (R + R ) 2 C2 D L
(c)
RL
Figure 10.8 Circuits for determining the time constant of each of the three capacitors, and hence the pole associated with each one. Note that this determination is possible because in the circuit of Fig. 10.3, the capacitors do not interact.
Ifadominantpoledoesnotexist,thefollowingapproximateexpressionforfL canbeused1
f ≃ f2 +f2 +f2 −2f2 (10.12) L P1 P2 P3 Z
Determining the Pole and Zero Frequencies by Inspection Since the capacitors in the CS amplifier circuit do not interact, a simple procedure exists for determining the frequencies of the pole and zero introduced by each capacitor.
Consider first the zeros. By its definition, a transmission zero is the value of s at which the input does not reach the output, resulting in Vo = 0. Examination of the circuit in Fig. 10.3(b) indicates that CC1 becomes an infinite impedance at s = 0 and thus introduces a transmission zero at s = 0 (i.e., blocks dc).
An identical statement applies to CC2. However, the bypass capacitor CS has a different effect: Its transmission zero is at the value of s that causes ZS to become infinite, and hence Is , Id , and Vo become zero, which is sZ given by Eq. (10.5).
To determine the poles, we set Vsig = 0.2 This results in the three separate circuits shown in Fig. 10.8. Each of the three circuits can be used to determine the resistance “seen” by the particular capacitor, and hence the time constant associated with this capacitor. The corresponding pole frequency ωP is the inverse of the time constant.
Selecting Values for the Coupling and Bypass Capacitors We now address the
design issue of selecting appropriate values for CC1, CS, and CC2. The design objective is to
place the lower 3-dB frequency f at a specified value while minimizing the capacitor values. L
Since the resistance seen by CS, 1 ∥RS , is usually the smallest of the three resistances, gm
the total capacitance is minimized by selecting CS to provide the highest frequency pole; that is, making its pole frequency fP2 = fL . We then decide on the location of the other two pole frequencies, say, 5 to 10 times lower than the frequency of the dominant pole, fP2. However,
1 The derivation of this expression is simple and is given in Chapter 9 of the fourth edition of this book. 2The poles of a circuit are its natural modes, and thus are independent of the value of the input signal.
706 Chapter 10 Frequency Response
the values selected for fP1 and fP3 should not be too low, for that would require larger values for
CC1 and CC2 than may be necessary. The design procedure will be illustrated by an example. Example 10.1
We wish to select appropriate values for the coupling capacitors CC1 and CC2 and the bypass capacitor CS for a CS amplifier for which RG =4.7 M, RD =RL =15 k, Rsig =100 k, RS =10 k, and gm = 1 mA/V. It is required to have fL at 100 Hz and that the nearest break frequency be at least a decade lower.
Solution
WeselectCS sothat
Thus,
For fP1 = fP3 = 10 Hz, we obtain which yields
and
which results in Finally,wecalculatethefrequencyofthezerofZ as
gm + 1
RS =fL
fP2=
1.1 × 10−3
2π CS
CS = 2π×100 =1.75μF
10= 1
2πC (0.1+4.7)×106
C1
CC1 =3.3nF 10= 1
2πC (15+15)×103 C2
CC2 = 0.53 μF fZ=1= 1
2πCSRS 2π ×1.75×10−6 ×10×103 = 9.1 Hz
EXERCISE
10.1 A CS amplifier has CC1 =CS =CC2 =1μF, RG =10 M, Rsig =100k, gm =2mA/V, RD =RL = RS =10k. Find AM, fP1, fP2, fP3, fZ, and fL.
Ans. –9.9 V/V; 0.016 Hz; 334.2 Hz; 8 Hz; 15.91 Hz; 334.2 Hz
10.1 Low-Frequency Response of Discrete-Circuit Common-Source and Common-Emitter Amplifiers 707 10.1.2 The Method of Short-Circuit Time Constants
In some circuits, such as that of the common-emitter amplifier discussed shortly, the capacitors interact, making it difficult to determine the pole frequencies. Fortunately, however, there is a simple method for obtaining an estimate for fL without the need to determine the frequencies of the poles. Although the method is predicated on the assumption that one of the poles is dominant, the resulting estimate for fL is usually very good even if this assumption is not strictly valid. The method is as follows3:
1. Set the input signal Vsig = 0.
2. Consider the capacitors one at a time. That is, while considering capacitor Ci, set all
the other capacitors to infinite values (i.e., replace them with short circuits—hence
the name of the method).
3. For each capacitor Ci, find the total resistance Ri seen by Ci. This can be determined
eitherbyinspectionorbyreplacingCi withavoltagesourceVx andfindingthecurrent
Ix drawn from Vx; Ri ≡ Vx/Ix.
4. Calculate the 3-dB frequency fL using
fL ≃n 1 (10.13) i=1 CiRi
where n is the total number of capacitors.
Besides its simplicity, this method has a very important side benefit: Equation (10.13) indicates the relative contribution of each capacitor to the value of fL . Specifically, the lower the value of the time constant associated with a particular capacitor, the greater the contribution of this capacitor to fL. As will be seen shortly, this observation has important design implications. Application of the method of short-circuit time constants will be illustrated in the next section, where it is utilized to determine fL of the CE amplifier.
10.1.3 The CE Amplifier
Figure10.9(a) shows a discrete-circuit common-emitter amplifier utilizing the classical biasing arrangement (Section 7.5.2), together with coupling capacitors CC 1 and CC 2 , and bypass capacitor CE. We wish to obtain an estimate of the frequency fL at which the gain of this amplifier drops by 3 dB below its value at midband. As well, we need to determine how to select appropriate values for CC1, CE, and CC2 to ensure that fL is placed at a desired location while minimizing the total capacitance value required.
To analyze the low-frequency gain of the CE amplifier, we utilize the equivalent circuit showninFig.10.9(b).Thisequivalentcircuitisobtainedbyshort-circuitingVCC andreplacing the BJT with its T model, while neglecting ro. The decision to neglect ro is based on the insignificant effect of the transistor’s output resistance on the gain of discrete-circuit amplifiers, and the considerable complication its inclusion causes to the analysis. From the circuit in Fig. 10.9(b), we observe that the finite input current in the base of the BJT causes CC1 and CC2 to interact. That is, unlike the case of the CS amplifier, here each of the two poles caused by CC1 and CC2 will depend on both capacitor values in a complicated fashion that hinders design insight. Therefore, we shall not attempt to determine the pole frequencies
3A proof can be found in Gray and Searle, 1969. (See bibliography in Appendix I.)
708 Chapter 10
Frequency Response
Rsig
RB1 CC 1
RB2
VCC
RC
RE
CC2
CE
Vo
CC2
RL
Vsig
(a)
Vo
aIe RC re
Ie
CE
Figure 10.9 (a) A discrete-circuit common-emitter amplifier. (b) Equivalent circuit of the amplifier in (a).
and, instead, we will use the method of short-circuit time constants to obtain an estimate of fL directly.
Applying the Method of Short-Circuit Time Constants Setting Vsig = 0 in the circuit of Fig. 10.9(b) and considering each capacitor, one at a time, while short-circuiting the other two results in the three circuits shown in Fig. 10.10. These circuits can be used to determine the resistance seen by each capacitor and hence its effective time constant. For CC1 we use the circuit in Fig. 10.10(a) and note that rπ is the input resistance at the base when CE is short-circuited. Capacitor CC 1 sees a resistance RC 1 , which can be found by inspection as
RC1 =(RB∥rπ)+Rsig (10.14)
Rsig
CC 1
(1–a)Ie
RL
Vsig
RB1 RB2
RB
(b)
RE
}
10.1 Low-Frequency Response of Discrete-Circuit Common-Source and Common-Emitter Amplifiers 709 (RB Rsig)/(b+1)
CC1
re
Rsig RBrp RE CE
tE = CE RE re + RB Rsig b+1
(b)
RL
Figure 10.10 Circuits for determining the short-circuit time constants for the amplifier in Fig. 10.9.
and the time constant associated with CC1 becomes
τC1 = CC1RC1 (10.15)
For CE, we use the circuit in Fig.10.10(b). Here, we see that with CC1 shorted [refer to Fig.10.9(b)], the resistance in the base becomes (RB∥Rsig), which can be reflected to the
t1 = CC1[(RB rp) + Rsig] (a)
RC
CC2
emitter side as (RB ∥ Rsig )/(β + 1). The total resistance RCE inspection from the circuit in Fig. 10.10(b) as
and the time constant becomes
seen by CE
can be found by
(10.16)
(10.17)
t2 = CC2(RC + RL) (c)
R∥R RCE=RE∥ re+ B sig
β+1 τCE =CERCE
Finally, the resistance seen by CC2 can be determined by inspection of the circuit in Fig. 10.10(c) as
RC2 =RC +RL (10.18) and the corresponding time constant τC2 as
τC2 = CC2RC2 (10.19)
710 Chapter 10
Frequency Response
With the three time constants in hand, the 3-dB frequency fL can be found from ωL 11 1 1
fL=2π=2π C R +CR +C R (10.20) C1 C1 E E C2 C2
When numerical values are substituted in this expression, it quickly becomes obvious which of the three capacitors is contributing the most to fL . Obviously, it is the capacitor that has the smallesttimeconstants.IntheCEamplifier,thisisusuallyCE becausetheassociatedresistance RCE is typically small. Knowing which of the capacitors has the potential of dominating the determination of fL has significant design implications, as shown next.
Selecting Values for CC1, CE, and CC2 We now address the design issue of selecting appropriate values for CC1, CE, and CC2. The design objective is to place the lower 3-dB frequencyfL ataspecifiedlocationwhileminimizingthecapacitorvalues.Since,asmentioned above,CE usuallyseesthelowestofthethreeresistances,thetotalcapacitanceisminimized byselectingCE sothatitscontributiontofL isdominant.Thatis,byreferencetoEq.(10.20)we may select CS so that 1/(CE RE ) is, say, 80% of ωL = 2π fL , leaving each of the other capacitors to contribute 10% to the value of ωL . Example 10.2 should help illustrate this process.
Example 10.2
We wish to select appropriate values for CC1, CC2, and CE for the common-emitter amplifier, which has RB =100k,RC =8k,RL =5k,Rsig =5k,RE =5k,β=100,gm =40mA/V,andrπ =2.5k. It is required to have fL = 100 Hz.
Solution
We first determine the resistances seen by the three capacitors CC1, CE, and CC2 as follows: RC1 =(RB∥rπ)+Rsig
= (100 ∥ 2.5) + 5 = 7.44 k
R∥R RCE=RE∥re+ B sig
β+1
100∥5
=5∥ 0.025+
RC2 =RC +RL =8+5=13k
101 Now,selectingCE sothatitcontributes80%ofthevalueofωL gives
Next, if CC1 is to contribute 10% of fL,
1 = 0.8 × 2π × 100 CE ×71
CE =28μF
1 = 0.1 × 2π × 100
C ×7.44×103 C1
CC1 =2.1μF
=0.071k
10.2 Internal Capacitive Effects and the High-Frequency Model of the MOSFET and the BJT 711
Similarly, if CC2 is to contribute 10% of fL, its value should be selected as follows: 1 = 0.1 × 2π × 100
C ×13×103 C2
CC2 =1.2μF Inpractice,wewouldselecttheneareststandardvaluesforthethreecapacitorswhileensuringthatfL ≤100
Hz.Finally,thefrequencyofthezerointroducedbyCE canbefound,
fZ = 1 = 1 =1.1Hz
2πCERE 2π ×28×10−6 ×5×103 whichisveryfarfromfL andthushasaninsignificanteffect.
EXERCISE
10.2 A common-emitter amplifier has CC1 = CE = CC2 = 1 μF, RB = 100 k, Rsig = 5 k, gm = 40 mA/V, rπ = 2.5k, RE = 5k, RC = 8k, and RL = 5k. Find the value of the time constant associated with each capacitor, and hence estimate the value of fL . Also compute the frequency of the transmission zero introducedbyCE andcommentonitseffectonfL.
Ans. τC1 = 7.44 ms; τCE = 0.071 ms; τC2 = 13 ms; fL = 2.28 kHz; fZ = 31.8 Hz, which is much smaller thanfL andthushasanegligibleeffectonfL
10.2 Internal Capacitive Effects and the High-Frequency Model of the MOSFET and the BJT
While coupling and bypass capacitors cause the gain of transistor amplifiers to fall off at the low-frequency end, the gain falloff at high frequencies is caused by the capacitive effects internal to the transistors. In this section we shall briefly consider these effects and, more importantly, show how the device small-signal model can be augmented to take these effects into account.
10.2.1 The MOSFET
From our study of the physical operation of the MOSFET in Section 5.1, we know that the device has internal capacitances. In fact, we used one of these, the gate-to-channel capacitance, in our derivation of the MOSFET i−v characteristics. We did, however, implicitly assume that the steady-state charges on these capacitances are acquired instantaneously. In other words,
712 Chapter 10
Frequency Response
SGD
B
Figure10.11 Acrosssectionofthen-channelMOSFEToperatinginthesaturationregion.Thefourinternal capacitances, Cg s , Cg d , Cs b , and Cd b , are indicated. Note that the bias voltages are not shown. Also not shown, to keep the diagram simple, is the depletion region.
we did not account for the finite time required to charge and discharge the various internal capacitances. As a result, the device models we derived, such as the small-signal model, do not include any capacitances. The use of these models would predict constant amplifier gains independent of frequency. We know, however, that this (unfortunately) does not happen; in fact, the gain of every MOSFET amplifier falls off at some high frequency. Similarly, the MOSFET digital logic inverter (Chapter 14) exhibits a finite nonzero propagation delay. To be able to predict these results, the MOSFET model must be augmented by including internal capacitances. This is the subject of this section.
To visualize the physical origin of the various internal capacitances, refer to Fig. 10.11, which shows the cross section of an n-channel MOSFET operating in the saturation region, as signified by the tapered n channel that is pinched off at the drain end. As indicated, there are four internal capacitances: Two of these, Cgs and Cgd , result from the gate-capacitance effect; the other two, Csb and Cdb, are the depletion capacitances of the pn junctions formed by the source region and the substrate, and the drain region and the substrate, respectively.
The gate-capacitive effect was discussed in Section 5.1. Briefly, the polysilicon gate forms
a parallel-plate capacitor with the channel region, with the oxide layer serving as the capacitor
dielectric. The gate (or oxide) capacitance per unit gate area is denoted Cox . When the channel
is tapered and pinched off, the gate capacitance is given by 2 WLCox. In addition to this 3
capacitance, there are two other small capacitances resulting from the overlap of the gate with the source region (or source diffusion) and the drain region (or drain diffusion). Each of these overlapshasalengthLov andthustheresultingoverlapcapacitancesCov aregivenby
Cov =WLovCox (10.21) Typically, Lov = 0.05 to 0.1 L. We can now express the gate-to-source capacitance Cgs as
Cgs = 2 WL Cox + Cov (10.22) 3
For the gate-to-drain capacitance, we note that the channel pinch-off at the drain end causes Cgd toconsistentirelyoftheoverlapcomponentCov,
Cgd =Cov (10.23)
n
Csb
Lov
Cgs
p-type substrate (body)
Cgd n
Lov
Cdb
10.2 Internal Capacitive Effects and the High-Frequency Model of the MOSFET and the BJT 713
The depletion-layer capacitances of the two reverse-biased pn junctions formed between each of the source and the drain diffusions and the p-type substrate (body) can be determined using the formula developed in Section 3.6 (Eq. 3.47). Thus, for the source diffusion, we have the source-body capacitance, Csb,
Csb = Csb0 (10.24) 1 + VSB
V0
where Csb0 is the value of Csb at zero body-source bias, VSB is the magnitude of the reverse-bias voltage, and V0 is the junction built-in voltage (0.6 V to 0.8 V). Similarly, for the drain diffusion, we have the drain-body capacitance Cdb,
Cdb = Cdb0 (10.25) 1 + VDB
V0
where Cdb0 is the capacitance value at zero reverse-bias voltage and VDB is the magnitude
of this reverse-bias voltage. Note that we have assumed that for both junctions, the grading
coefficient m = 1 . 2
It should be noted also that each of these junction capacitances includes a component arising from the bottom side of the diffusion and a component arising from the sidewalls of the diffusion. In this regard, observe that each diffusion has three sidewalls that are in contact with the substrate and thus contribute to the junction capacitance (the fourth wall is in contact with the channel).
The formulas for the junction capacitances in Eqs. (10.24) and (10.25) assume small-signal operation. Typical values for the various capacitances exhibited by an n-channel MOSFET in a 0.5-μm CMOS process are given in the following exercise.
EXERCISE
10.3 For an n-channel MOSFET with tox =10 nm, L = 1.0μm, W = 10μm, Lov =0.05μm, Csb0 = Cdb0 = 10 fF, V0 = 0.6 V, VSB = 1 V,and VDS = 2 V, calculate the following capacitances when the transistor is operating in saturation: Cox, Cov, Cgs, Cgd, Csb, and Cdb.
Ans. 3.45 fF/μm2 ; 1.72 fF; 24.7 fF; 1.72 fF; 6.1 fF; 4.1 fF
The High-Frequency MOSFET Model Figure 10.12(a) shows the small-signal model of the MOSFET, including the four capacitances Cgs, Cgd, Csb, and Cdb. This model can be used to predict the high-frequency response of MOSFET amplifiers. It is, however, quite complex for manual analysis, and its use is limited to computer simulation using, for example, SPICE. Fortunately, when the source is connected to the body, the model simplifies considerably, as shown in Fig. 10.12(b). In this model, Cgd , although small, plays a significant role in determining the high-frequency response of amplifiers and thus must be kept in the
714 Chapter 10 Frequency Response
Cgd
Vgs
gm Vgs
gmb Vbs
Cgs
ro
Cdb
Vbs
Csb
GD
SB
(a)
GD
S
G GD
S
Cgd
Vgs
Cgs
gm Vgs
ro
Cdb
(b)
D
Vgs
Cgd
Cgs
gmVgs
ro
1
gm
Vgs
Cgd
Cgs gm Vgs ro
S
(c)
(d)
Figure10.12 (a)High-frequency,equivalent-circuitmodelfortheMOSFET.(b)Theequivalentcircuitfor the case in which the source is connected to the substrate (body). (c) The equivalent-circuit model of (b) with Cd b neglected (to simplify analysis). (d) The simplified high-frequency T model.
model. Capacitance Cdb, on the other hand, can usually be neglected, resulting in significant simplification of manual analysis. The resulting circuit is shown in Fig. 10.12(c). Finally, we show in Fig. 10.12(d) the high-frequency T model in its simplified form.
10.2 Internal Capacitive Effects and the High-Frequency Model of the MOSFET and the BJT 715
The MOSFET Unity-Gain Frequency (fT) A figure of merit for the high-frequency operation of the MOSFET as an amplifier is the unity-gain frequency, fT , also known as the transition frequency, which gives rise to the subscript T. This is defined as the frequency at which the short-circuit current gain of the common-source configuration becomes unity. Figure 10.13 shows the MOSFET hybrid-π model with the source as the common terminal between the input and output ports. To determine the short-circuit current gain, the input is fed with a current-source signal Ii and the output terminals are short-circuited. It can be seen that the current in the short circuit is given by
Io =gmVgs −sCgdVgs
Recalling that Cgd is small, at the frequencies of interest we can neglect the second term in
this equation,
From Fig. 10.13, we can express Vgs in terms of the input current Ii as
Io = gm (10.28) Ii s Cgs +Cgd
Io ≃gmVgs (10.26)
Vgs = Ii
s Cgs +Cgd
(10.27) Equations (10.26) and (10.27) can be combined to obtain the short-circuit current gain,
For physical frequencies s = jω, it can be seen that the magnitude of the current gain is
I g o= m
Ii ω(Cgs +Cgd)
and it becomes unity at the frequency
ωT =gm/ Cgs +Cgd
Thus the unity-gain frequency fT = ωT /2π is
fT= gm (10.29)
2π Cgs +Cgd
SincefT isproportionaltogm,whichdeterminesthemidbandgain,andinverselyproportional to the MOSFET internal capacitances, which limit the amplifier bandwidth, the higher the value of fT , the more effective the MOSFET becomes as an amplifier. Substituting for gm using Eq. (7.41), we can express fT in terms of the bias current ID (see Problem 10.15). Alternatively, we can substitute for gm from Eq. (7.40) to express fT in terms of the overdrive voltage VOV (see Problem 10.16). Both expressions yield additional insight into the high-frequency operation of the MOSFET. The reader is also referred to Appendix G for a further discussion of fT .
Io
Vgs
Ii
Cgs gmVgs
ro
Figure 10.13 Determining the short-circuit current gain Io/Ii.
Cgd sCgd Vgs
716 Chapter 10 Frequency Response
Typically,fT rangesfromabout100MHzfortheoldertechnologies(e.g.,a5-μmCMOS
process) to many GHz for newer high-speed technologies (e.g., a 0.13-μm CMOS process).
EXERCISE
10.4 Calculate fT for the n-channel MOSFET whose capacitances were found in Exercise 10.3. Assume operation at 100 μA and that k′n = 160 μA/V2.
Ans. 3.4 GHz
Summary We conclude this section by presenting a summary in Table 10.1. Table 10.1 The MOSFET High-Frequency Model
Model
Cgd
GD
Vgs Cgs
gmVgs
Vbs Csb
SB
gmbVbs
ro
Cdb
Model Parameters
W W 2I g=μC V=2μC I=D
C C=sb0
m n ox L OV
n ox L D
VOV
sb V 1+ SB
χ=0.1to0.2
Cgs = 2WLCox +WLovCox 3
Cgd =WLovCox
V0 C = C d b 0
gmb =χgm, r = V / I
db V 1+ DB
oAD
V0
fT = gm 2π(Cgs +Cgd)
10.2 Internal Capacitive Effects and the High-Frequency Model of the MOSFET and the BJT 717
10.2.2 The BJT
In our study of the physical operation of the BJT in Section 6.1, we assumed transistor action to be instantaneous, and as a result the transistor models we developed do not include any elements (i.e., capacitors or inductors) that would cause time or frequency dependence. Actual transistors, however, exhibit charge-storage phenomena that limit the speed and frequency of their operation. We have already encountered such effects in our study of the pn junction in Chapter 3 and have learned that they can be modeled using capacitances. In the following we study the charge-storage effects that take place in the BJT and take them into account by adding capacitances to the hybrid-π and the T models. The resulting augmented BJT model will be able to predict the observed dependence of amplifier gain on frequency, and the time delays that transistor switches and logic gates exhibit.
The Base-Charging or Diffusion Capacitance Cde When the transistor is operating in the active mode, minority-carrier charge is stored in the base region. For an npn transistor, the stored electron charge in the base, Qn, can be expressed in terms of the collector current iC as
Qn =τFiC (10.30)
where τF is a device constant with the dimension of time. It is known as the forward base-transit time and represents the average time a charge carrier (electron) spends in crossing thebase.Typically,τF isintherangeof10psto100ps.
Equation(10.30)appliesforlargesignalsand,sinceiC isexponentiallyrelatedtovBE,Qn will similarly depend on vBE. For small signals, we can define the small-signal diffusion capacitance Cde,
resulting in
Cde ≡ dQn dvBE
=τ diC F dvBE
C =τ g =τ IC de Fm FVT
(10.31)
(10.32)
where IC is the dc collector bias current at which the transistor is operating. Thus, whenever vBE changes by vbe, the collector current changes by gmvbe and the charge stored in the base changesbyCdevbe =(τFgm)vbe.Thisincrementalchargehastobesuppliedbythebasecurrent.
The Base–Emitter Junction Capacitance Cje A change in vBE changes not only the charge stored in the base region but also the charge stored in the base–emitter depletion layer. This distinct charge-storage effect is represented by the EBJ depletion-layer capacitance, Cje. From the development in Chapter 3, we know that for a forward-biased junction, which the EBJ is, the depletion-layer capacitance is given approximately by
Cje ≃ 2Cje0 (10.33) where Cje0 is the value of Cje at zero EBJ voltage.
718 Chapter 10
Frequency Response
The Collector–Base Junction Capacitance Cμ In active-mode operation, the CBJ is reverse biased, and its junction or depletion capacitance, usually denoted Cμ, can be found from
Cμ = Cμ0 m (10.34) 1 + VCB
V0c
where Cμ0 is the value of Cμ at zero voltage; VCB is the magnitude of the CBJ reverse-bias voltage, V0c is the CBJ built-in voltage (typically, 0.75 V), and m is its grading coefficient (typically, 0.2–0.5).
The High-Frequency Models Figure 10.14 shows the hybrid-π and T models of the BJT, including capacitive effects. Specifically, there are two capacitances: the emitter–base capacitance Cπ = Cde + Cje and the collector–base capacitance Cμ. Typically, Cπ is in the range of a few picofarads to a few tens of picofarads, and Cμ is in the range of a fraction of a picofarad to a few picofarads.4 Note that we have also added a resistor rx to model
B
C
(a)
gmVp
ro
Cp re
Cm
rx
Vp
E
(b)
Figure 10.14 The high-frequency models of the BJT: (a) hybrid-π model and (b) T model.
4These values apply for discrete devices and devices fabricated with a relatively old IC process technology (the so-called high-voltage process, see Appendix K). For modern IC fabrication processes, Cπ and Cμ are in the range of tens of femtofarads (fF).
10.2 Internal Capacitive Effects and the High-Frequency Model of the MOSFET and the BJT 719
the resistance of the silicon material of the base region between the base terminal B and a fictitious internal, or intrinsic, base terminal B′ that is right under the emitter region (refer to Fig. 6.6). Typically, rx is a few tens of ohms, and its value depends on the current level in a rather complicated manner. Since (usually) rx ≪ rπ , its effect is negligible at low frequencies. Its presence is felt, however, at high frequencies, as will become apparent later.
The values of the model parameters can be determined at a given bias point using the formulas presented in this section and in Chapter 6. They can also be found from the terminal measurements specified on the BJT data sheets. For computer simulation, SPICE uses the parameters of the given IC technology to evaluate the BJT model parameters (see Appendix B).
The BJT Unity-Gain Frequency The transistor data sheets do not usually specify the value of Cπ . Rather, the behavior of β (or hfe ) versus frequency is normally given. In order to determineCπ andCμ,weshallderiveanexpressionforhfe,theCEshort-circuitcurrentgain, as a function of frequency in terms of the hybrid-π components. For this purpose consider the circuit shown in Fig. 10.15, in which the collector is shorted to the emitter. A node equation at C provides the short-circuit collector current Ic as
Ic = gm −sCμ Vπ (10.35) A relationship between Vπ and Ib can be established by multiplying Ib by the impedance seen
(10.36)
(10.37) Atthefrequenciesforwhichthismodelisvalid,ωCμ ≪gm;thuswecanneglectthesCμ term
between B′ and E:
Thus hfe can be obtained by combining Eqs. (10.35) and (10.36):
V =I r ∥C ∥C = Ib
π b π π μ 1/rπ + sCπ + sCμ
Ic gm −sCμ
hfe ≡I =1/r + sC +C
in the numerator and write
hfe ≃ gmrπ 1+s Cπ +Cμ rπ
bππμ
Figure10.15 Circuitforderivinganexpressionforhfe(s)≡Ic/Ib.
720 Chapter 10
Frequency Response
Thus,
Figure 10.16 Bode plot for h . fe
β0 (10.38) 1+s Cπ +Cμ rπ
hfe =
where β0 is the low-frequency value of β. Thus hfe has a single-pole (or single-time-constant)
response with a 3-dB frequency at ω = ωβ , where
ωβ = 1 (10.39)
Cπ+Cμ rπ
Figure 10.16 shows a Bode plot for h . From the –6-dB/octave slope, it follows that the
frequency at which hfe given by
Thus, and
ωT =β0ωβ
ωT = gm (10.40)
fe
drops to unity, which is called the unity-gain bandwidth ωT , is
fT =
Cπ +Cμ
gm (10.41)
2π(Cπ +Cμ)
This expression is identical to that of fT for the MOSFET (Eq. 10.29) with Cπ replacing Cgs and Cμ replacing Cgd .
The unity-gain bandwidth fT , also known as the transition frequency, which gives rise to the subscript T, is usually specified on the data sheets of a transistor. In some cases fT is given as a function of IC and VCE . To see how fT changes with IC , recall that gm is directly proportionaltoIC,butonlypartofCπ (thediffusioncapacitanceCde)isdirectlyproportionalto IC . It follows that fT decreases at low currents, as shown in Fig. 10.17. However, the decrease infT athighcurrents,alsoshowninFig.10.17,cannotbeexplainedbythisargument;rather, it is due to the same phenomenon that causes β0 to decrease at high currents (Section 6.4.2). In the region where fT is almost constant, Cπ is dominated by the diffusion part and is much greater than Cμ. That is, Cπ +Cμ ≃Cde =τFgm and
fT≃ 1 (10.42) 2π τF
10.2 Internal Capacitive Effects and the High-Frequency Model of the MOSFET and the BJT 721
Figure 10.17 Variation of fT with IC .
Typically, fT is in the range of 100 MHz to tens of gigahertz. The value of fT can be used in Eq. (10.41) to determine Cπ + Cμ . The capacitance Cμ is usually determined separately by measuring the capacitance between base and collector at the desired reverse-bias voltage VCB.
An important observation to make from the high-frequency model of Fig. 10.14(a) is that at frequencies above 5 to 10 fβ , one may ignore the resistance rπ . It can be seen then that rx becomes the only resistive part of the input impedance at high frequencies. Thus rx plays an important role in determining the frequency response of transistor circuits at high frequencies. It follows that an accurate determination of rx can be made only from a high-frequency measurement.
Before leaving this section, we should mention that the high-frequency models of Fig. 10.14 characterize transistor operation fairly accurately up to a frequency of about 0.2 fT . At higher frequencies one has to add other parasitic elements to the model.
EXERCISES
10.5 Find Cde, Cje, Cπ, Cμ, and fT for a BJT operating at a dc collector current IC =1mA and a CBJ reverse bias of 2V. The device has τF =20 ps, Cje0 =20fF, Cμ0 =20fF, V0e =0.9V, V0c =0.5V, andmCBJ =0.33.
Ans. 0.8 pF; 40 fF; 0.84 pF; 12 fF; 7.47 GHz
10.6 ForaBJToperatedatIC =1mA,determinefT andCπ ifCμ =2pFand hfe =10at50MHz. Ans. 500 MHz; 10.7 pF
10.7 If Cπ of the BJT in Exercise 10.6 includes a relatively constant depletion-layer capacitance of 2 pF, find fT of the BJT when operated at IC = 0.1 mA.
Ans. 130.7 MHz
722 Chapter 10
Frequency Response
Summary For convenient reference, Table 10.2 provides a summary of the relationships used to determine the values of the parameters of the BJT high-frequency model.
Table 10.2 The BJT High-Frequency Model
g =I /V r =V /I r =β /g r =r /(β+1) mCT oAC π0m eπ
Cπ +Cμ = gm Cπ =Cde +Cje Cde =τFgm Cje ≃2Cje0 2π fT
Vm
Cμ =Cjc0 1+ CB m=0.3−0.5
V0c
10.3 High-Frequency Response of the CS and CE Amplifiers
Equipped with equivalent-circuit models that represent the high-frequency operation of the MOSFET and the BJT, we now address the question of the high-frequency performance of the CS and CE amplifiers. Our objective is to identify the mechanism that limits the high-frequency performance of these important amplifier configurations. As well, we need to findasimpleapproachtoestimatethefrequencyfH atwhichthegainfallsby3dBbelowits value at midband frequencies, |AM |.
The analysis presented here applies equally well to discrete-circuit, capacitively coupled amplifiers and to IC amplifiers. The frequency response of the first was shown in Fig. 10.1 and that of the latter in Fig. 10.2. At the frequencies of interest to us here (the high-frequency band), all coupling and bypass capacitors behave as perfect short circuits, and amplifiers of both types have identical high-frequency equivalent circuits.
10.3.1 The Common-Source Amplifier
Figure 10.18(a) shows the high-frequency, equivalent-circuit model of a CS amplifier. It is obtained by replacing the MOSFET in an amplifier circuit such as that in Fig. 10.3(a) by its high-frequency, equivalent-circuit model of Fig. 10.6(c), while as always eliminating dc sources. Observe that the circuit in Fig. 10.18(a) is general; for instance, it includes a resistance RG , which arises only in the case of a discrete-circuit amplifier such as that in Fig. 10.3(a), where RG ≡ RG1 ∥ RG2 . Also, RD can be either a passive resistance or the output resistance of a current-source load, and similarly for RL .
The equivalent circuit of Fig. 10.18(a) can be simplified by utilizing The ́venin theorem at the input side and by combining the three parallel resistances at the output side. The resulting simplified circuit is shown in Fig. 10.18(b). The midband gain AM can be found from this circuit by setting Cgs and Cgd to zero. The result is
AM=Vo =− RG gmRL′ (10.43) Vsig RG +Rsig
The circuit in Fig. 10.18(b) can be analyzed to obtain its transfer function Vo /Vsig in terms of the complex frequency variable s. Because two capacitors, Cgs and Cgd, are present, the resulting transfer function will be of second order. The poles and zeros can then be determined. This, however, will not provide us with simple expressions that reveal the essence of what limits the high-frequency operation of the CS amplifier. We need such insight in order to be able to make intelligent decisions when designing the circuit. Therefore, we shall not derive the transfer function and instead opt for an approximate approach that will reveal considerable information about the high-frequency operation of the CS amplifier.
Rsig
VR RRV
10.3 High-Frequency Response of the CS and CE Amplifiers 723
Cgd
GD
Vgs
Cgs gmVgs ro
S
sig G
D L o
(a)
RL
Cgd
X
Igd
X
Rsig RsigRG
GD
Vo
Igd V=RGVsig VgsC gmVgs RL
(b)
Figure 10.18 Determining the high-frequency response of the CS amplifier: (a) equivalent circuit; (b) the circuit of (a) simplified at the input and the output; (c) the equivalent circuit with Cgd replaced at the input side with the equivalent capacitance Ceq ; (d) the frequency-response plot, which is that of a low-pass, single-time-constant circuit.
sig RG Rsig
gs
RL roRDRL
724
Chapter 10
Frequency Response
X
GD
RGV VgsC CgV R
Igd
X
Rsig
Vo gm RL Vgs
RGRsig sig
gs
eq
Ceq Cgd (1 gmRL) Cin
mgs
L
Vo (dB) Vsig
(c)
3 dB
20 dBdecade
Figure 10.18 continued
20 log AM
(d)
fH
f (Hz) (log scale)
Our approach is to focus on the input side of the circuit and seek to simplify the input circuit to a simple RC low-pass network. To do so we need to replace the bridging capacitor Cgd by an equivalent capacitance Ceq between node G and ground. Toward that end, consider first the output node. It can be seen that the load current is (gmVgs –Igd), where (gmVgs) is the output current of the transistor and Igd is the current supplied through the very small capacitance Cgd . At frequencies in the vicinity of fH , which defines the edge of the midband, it is reasonable to assume that Igd is still much smaller than (gmVgs), with the result that Vo can be given approximately by
where
V ≃−g V R′ = −g R′ V (10.44) o m gs L m L gs
RL′ =ro∥RD∥RL
Since Vo = Vds , Eq. (10.44) indicates that the gain from gate to drain is –gm RL′ , the same value asinthemidband.ThecurrentIgd cannowbefoundas
Igd=sCgd Vgs−Vo
=sC V −−g R′V
which results in
sC V =sC 1+g R′V eqgs gd mLgs
C =C 1+g R′ eq gd mL
gd gs m L gs
=sC 1+g R′V gd mLgs
Now, the left-hand side of the circuit in Fig. 10.18(b), at XX′, knows of the existence of Cgd onlythroughthecurrentIgd.Therefore,wecanreplaceCgd byanequivalentcapacitanceCeq between the gate and ground as long as Ceq draws a current equal to Igd . That is,
ThusCgd givesrisetoamuchlargercapacitanceCeq,whichappearsattheamplifierinput. The multiplication effect that Cgd undergoes comes about because it is connected between circuit nodes G and D, whose voltages are related by a large negative gain (–gm RL′ ). This effect is known as the Miller effect, and (1 + gm RL′ ) is known as the Miller multiplier.
Using Ceq enables us to simplify the equivalent circuit at the input side to that shown in Fig. 10.18(c), which we recognize as a single-time-constant (STC) circuit of the low-pass type (Section 1.6 and Appendix E). Reference to Table 1.2 enables us to express the output voltage Vgs of the STC circuit in the form
10.3 High-Frequency Response of the CS and CE Amplifiers 725
R 1
Vgs = G Vsig (10.46)
(10.45)
RG+Rsig 1+ s ω0
where ω0 is the corner frequency, the break frequency, or the pole frequency of the STC circuit,
with
and
ω =1/C R′
0 in sig
C =C +C =C +C 1+g R′ in gs eq gs gd mL
R′ =R ∥R sig sig G
(10.47) (10.48)
(10.49)
Combining Eqs. (10.44) and (10.46) results in the following expression for the high-frequency gain of the CS amplifier,
o = − G gmRL′ Vsig RG+Rsig
which can be expressed in the form
1+ s ω0
(10.50)
(10.51)
V R 1
Vo = AM
Vsig 1+ s ωH
726 Chapter 10
Frequency Response
wherethemidbandgainAM isgivenbyEq.(10.43)andωH istheupper3-dBfrequency,
ωH =ω0 = 1 C R′
fH = ωH = 2π
We thus see that the high-frequency response will be that of a low-pass STC network with a
determined by the time constant C R′ . Figure 10.18(d) shows a sketch of in sig
3-dB frequency f
the magnitude of the high-frequency gain.
H
(10.52)
1 (10.53)
and
in sig
2πC R′ in sig
Before leaving this section we wish to make a number of observations:
1. The upper 3-dB frequency is determined by the interaction of R′ = R ∥R and
′ sig sig G
Example 10.3
Cin =Cgs +Cgd 1+gmRL . Since the bias resistance RG is usually very large, it can
be neglected, resulting in R′ ≃ R , the resistance of the signal source. It follows that sig sig
a large value of Rsig will cause fH to be lowered.
2. The total input capacitance Cin is usually dominated by Ceq, which in turn is made
large by the multiplication effect that Cgd undergoes. Thus, although Cgd is usually a very small capacitance, its effect on the amplifier frequency response can be very significant as a result of its multiplication by the factor (1 + gm RL′ ), which is approximately equal to the midband gain of the amplifier. This is the Miller effect, which causes the CS amplifier to have a large total input capacitance Cin and hence a low fH.
3. To extend the high-frequency response of a MOSFET amplifier, we have to find configurations in which the Miller effect is absent or at least reduced. We shall return to this subject at great length in Section 10.5 and beyond.
4. The above analysis, resulting in an STC or a single-pole response, is approximate. Specifically, it is based on neglecting Igd relative to gmVgs, an assumption that applies well at frequencies not too much higher than fH . An exact analysis of the circuit in Fig. 10.18(a) reveals that the circuit has a second pole with a frequency much greater thanfH,andtransmissionzerosats=∞ands=gm/Cgd;thelatter’sfrequencyisalso much greater than fH . Thus both the second pole and the zero will have negligible effect on our estimate of fH . Thus, the method that uses the Miller effect is more than sufficient for a quick estimate of fH . As well, the approximate approach helps to reveal the primary limitation on the high-frequency response: the Miller effect.
5. The CS amplifier is said to have a dominant high-frequency pole with frequency fP ≃fH.
FindthemidbandgainAM andtheupper3-dBfrequencyfH ofaCSamplifierfedwithasignalsourcehaving an internal resistance Rsig = 100 k. The amplifier has RG = 4.7 M, RD = RL = 15 k , gm = 1 mA/V, ro = 150 k, Cgs = 1 pF, and Cgd = 0.4 pF. Also, find the frequency of the transmission zero.
Solution
where
Thus,
AM=−RG gmRL′ RG +Rsig
RL′ =ro∥RD∥RL =150∥15∥15=7.14k gmRL′ =1×7.14=7.14V/V
AM =− 4.7 ×7.14=−7V/V 4.7 + 0.1
The equivalent capacitance, Ceq , is found as
Ceq =1+gmRL′Cgd
=(1+7.14)×0.4=3.26pF The total input capacitance Cin can be now obtained as
Cin =Cgs +Ceq =1+3.26=4.26pF Theupper3-dBfrequencyfH isfoundfrom
fH= 1 2π Cin Rsig ∥ RG
=1
2π ×4.26×10−12(0.1∥4.7)×106
= 382 kHz Finally, the transmission zero has a frequency
gd which is more than 1000 times higher than fH .
10.3 High-Frequency Response of the CS and CE Amplifiers 727
gm 1 × 10−3
fZ =2πC =2π×0.4×10−12 =398MHz
EXERCISES
10.8 For the CS amplifier specified in Example 10.3, find the values of AM and fH that result when the signal-source resistance is reduced to 10 k.
Ans. –7.12 V/V; 3.7 MHz
10.9 If it is possible to replace the MOSFET used in the amplifier in Example 10.3 with another having the same Cgs but a smaller Cgd , what is the maximum value that its Cgd can be in order to obtain an fH of at least 1 MHz?
Ans. 0.08 pF
728 Chapter 10
Frequency Response
10.3.2 The Common-Emitter Amplifier
Figure 10.19(a) shows the high-frequency equivalent circuit of a CE amplifier. It is obtained by replacing the BJT in a circuit such as that in Fig.10.9(a) with its high-frequency, equivalent-circuit model of Fig. 10.14(a), and, as usual, eliminating all dc sources. Observe that the circuit in Fig. 10.19(a) is general and applies to both discrete- and integrated-circuit amplifiers. Thus, it includes RB, which is usually present in discrete circuits. Also RC can be either a passive resistance or the output resistance of a current-source load, and similarly for RL.
The equivalent circuit of Fig. 10.19(a) can be simplified by utilizing The ́venin theorem at
the input side and by combining the three parallel resistances at the output side. Specifically,
the reader should be able to show that applying The ́venin theorem twice simplifies the resistive
network at the input side to a signal generator V ′ and a resistance R′ , with the values indicated sig sig
in the figure.
The equivalent circuit in Fig. 10.19(b) can be used to obtain the midband gain AM by
setting Cπ and Cμ to zero. The result is
Vo RB rπ ′
where
AM=V =−R+R r+r+R ∥RgmRL sig BsigπxsigB
RL′ =ro∥RC∥RL
(10.54)
(10.55)
Next we observe that the circuit in Fig. 10.19(b) is identical to that of the CS amplifier in Fig. 10.18(b). Thus the analysis can follow the same process we used for the CS case. The analysis is illustrated in Fig. 10.19(c) and (d). The final result is that the CE amplifier gain at high frequencies is given approximately by
Vo = AM Vsig 1+ s
ωH
whereAM isgivenbyEq.(10.54)andthe3-dBfrequencyfH isgivenby
(10.56)
(10.57)
(10.58) (10.59)
fH=ωH= 1 2π 2πC R′
C =C +C 1+g R′ in π μ mL
R′ =r∥r+R∥R sig π x B sig
where
and
in sig
Observe that C
is simply the sum of C and the Miller in
R ′ . The seen by C can be easily found from the circuit in Fig. 10.19(a) as follows:
1 + g
in π μmL
capacitance C
Reduce V to zero, “grab hold” of the terminals B′ and E and look back (to the left). You will
resistance R′ sig
sig
see rπ in parallel with rx , which is in series with RB ∥ Rsig . This way of finding the resistance “seen by a capacitance” is very useful and spares one from tedious work!
Finally, comments very similar to those made on the high-frequency response of the CS amplifier can be made here as well.
10.3 High-Frequency Response of the CS and CE Amplifiers 729 R r Cm
sigBx B C
Vsig
Vp Cp
RB rp
ro RC RL Vo
gmVp
E
(a)
C
RL
X
R sig
B I Cm Im m
X
Vsig
RL Vo
Vp Cp
gmVp
RB
sig sig RBRsig rprx(RsigRB)
V V
Rsig rp [rx (RB Rsig)]
rp
Rr R R
L o
C L
Rsig
(b)
X
B Im
C
X
Cp
V sig
RL Vo
Cin
Cin Cp Ceq Vo gmRLVp
Cp Cm(1 gmRL) (c)
Vp Ceq
gmVp
Figure 10.19 Determining the high-frequency response of the CE amplifier: (a) equivalent circuit; (b) the circuit of (a) simplified at both the input side and the output side; (c) equivalent circuit with Cμ replaced at the input side with the equivalent capacitance Ceq ; (d) sketch of the frequency-response plot, which is that of a low-pass STC circuit.
730 Chapter 10
Frequency Response
Vo (dB) Vsig
Figure 10.19 continued
Example 10.4
0
3 dB
20 log AM
(d)
6 dBoctave 20 dBdecade
fH 1
2p Cin Rsig
fH f (Hz, log scale)
It is required to find the midband gain and the upper 3-dB frequency of the common-emitter amplifier of Fig.10.9(a) for the following case: IE = 1mA, RB =RB1∥RB2 = 100k, RC =8k, Rsig =5k, RL =5k, β0 =100, VA =100V, Cμ =1 pF, fT =800MHz, and rx =50. Also, determine the frequency of the transmission zero.
Solution
The transistor is biased at IC ≃ 1 mA. Thus the values of its hybrid-π model parameters are gm = IC = 1mA =40mA/V
The midband voltage gain is
VT 25mV
rπ=β0 = 100 =2.5k
gm 40 mA/V ro=VA =100V=100k
IC 1mA
gm 40 × 10−3
Cπ +Cμ = ω = 2π×800×106 =8pF T
Cμ = 1 pF Cπ =7pF
rx =50
RB rπ ′
AM=−R+R r+r+R∥RgmRL B sigπ x B sig
where
Thus, and
and
To determine fH we first find Cin,
10.3 High-Frequency Response of the CS and CE Amplifiers 731
RL′ =ro∥RC∥RL
= (100∥8∥5)k = 3 k
gmRL′ =40×3=120V/V
AM =− 100 × 2.5 ×120
and the effective source resistance R′ , sig
Thus,
R′ =r∥r+R∥R sig π x B sig
=2.5∥[0.05+(100∥5)] = 1.65 k
f= 1 = 1
H 2πC R′ 2π ×128×10−12 ×1.65×103
100+5 2.5+0.05+(100∥5) = −39 V/V
20logA =32dB M
Cin =Cπ +Cμ(1+gmRL′) =7+1(1+120)=128pF
=754kHz
Finally, as in the case of the CS amplifier, it can be shown that the CE amplifier has a transmission zero
with frequency
which is much higher than fH .
EXERCISE
gm 40 × 10−3
fZ =2πC =2π×1×10−12 =6.37GHz
μ
in sig
10.10 For the amplifier in Example 10.4, find the value of RL that reduces the midband gain to half the value found. What value of fH results? Note the trade-off between gain and bandwidth.
Ans. 1.9 k; 1.42 MHz
732 Chapter 10
Frequency Response
10.3.3 Miller’s Theorem
In our analysis of the high-frequency response of the common-source and common-emitter amplifiers, we employed a technique for replacing the bridging capacitance (Cgs or Cμ) by an equivalent input capacitance. This very useful and effective technique is based on a general theorem known as Miller’s theorem, which we now present.
Consider the situation in Fig. 10.20(a). As part of a larger circuit that is not shown, we have isolated two circuit nodes, labeled 1 and 2, between which an impedance Z is connected. Nodes 1 and 2 are also connected to other parts of the circuit, as signified by the broken lines emanating from the two nodes. Furthermore, it is assumed that somehow it has been determined that the voltage at node 2 is related to that at node 1 by
V2 = KV1 (10.60)
In typical situations, K is a gain factor that can be positive or negative and has a magnitude usually larger than unity. This, however, is not an assumption for Miller’s theorem.
Miller’s theorem states that impedance Z can be replaced by two impedances: Z1 connected between node 1 and ground and Z2 connected between node 2 and ground, where
and
Z1 =Z/(1−K) 1
Z2 = Z 1 − K
(10.61a)
(10.61b)
to obtain the equivalent circuit shown in Fig. 10.20(b).
The proof of Miller’s theorem is achieved by deriving Eqs. (10.61) as follows: In the
original circuit of Fig. 10.20(a), the only way that node 1 “feels the existence” of impedance Z is through the current I that Z draws away from node 1. Therefore, to keep this current unchanged in the equivalent circuit, we must choose the value of Z1 so that it draws an equal current,
I1=V1 =I=V1−KV1 Z1 Z
1 I Z I 2 1 I1I I2I 2
V1 V2 KV1 V1 Z1 Z2 V2 KV1
121K Z Z(1K), Z Z 1
(a) (b) Figure 10.20 The Miller equivalent circuit.
10.3 High-Frequency Response of the CS and CE Amplifiers 733 which yields the value of Z1 in Eq. (10.61a). Similarly, to keep the current into node 2
unchanged, we must choose the value of Z2 so that
I2=0−V2 =0−KV1 =I=V1−KV1
Z2 Z2 Z which yields the expression5 for Z2 in Eq. (10.61b).
Example 10.5
Figure 10.21(a) shows an ideal voltage amplifier having a gain of −100 V/V with an impedance Z connected between its output and input terminals. Find the Miller equivalent circuit when Z is (a) a 1-M resistance and (b) a 1-pF capacitance. In each case, use the equivalent circuit to determine Vo/Vsig.
Solution
(a) For Z = 1 M, employing Miller’s theorem results in the equivalent circuit in Fig. 10.21(b), where Z1= Z =1000k=9.9k
The voltage gain can be found as follows:
Vo =Vo Vi =−100× Z1
1−K 1+100
Z2= Z =1M=0.99M
us to replace Z by Z1 and Z2, where
Z1 = Z = 1/sC = 1/s(101C)
1−11+1 K 100
Vsig Vi Vsig Z1 +Rsig
= −100 × 9.9 = −49.7 V/V
9.9+10
(b) ForZasa1-pFcapacitance—thatis,Z=1/sC=1/s×1×10−12 —applyingMiller’stheoremallows
1−K 1+100 Z2=Z=11= 1
1− 1 1.01sC s(1.01C) K
5Although not highlighted, the Miller equivalent circuit derived above is valid only as long as the rest of the circuit remains unchanged; otherwise the ratio of V2 to V1 might change. It follows that the Miller equivalent circuit cannot be used directly to determine the output resistance of an amplifier. This is because in determining output resistances it is implicitly assumed that the source signal is reduced to zero and that a test-signal source (voltage or current) is applied to the output terminals—obviously a major change in the circuit, rendering the Miller equivalent circuit no longer valid.
734
Chapter 10 Frequency Response
Example 10.5 continued
Rsig 10 k 1
100
Vi Vo
(a)
12
Z
2
Vsig
Vsig
Vsig Z1 V Z2 V i 100V o
(c)
Figure 10.21 Circuits for Example 10.5.
It follows that Z1 is a capacitance 101C = 101 pF and that Z2 is a capacitance 1.01C = 1.01 pF. The
resulting equivalent circuit is shown in Fig. 10.21(c), from which the voltage gain can be found as follows:
Rsig
Rsig
Z1
Vi (b)
Z2 Vo
100Vi
1
i
Vo
Vo Vi = V V
= −100 1+sC1Rsig
1/sC1 =−1001/sC +R
1 sig
V
sig
i sig
= −100 1+s×101×1×10−12 ×10×103
= −100 1+s×1.01×10−6
10.3 High-Frequency Response of the CS and CE Amplifiers 735
This is the transfer function of a first-order low-pass network with a dc gain of –100 and a 3-dB frequency
f3dB of
f = 1 =157.6kHz 3dB 2π × 1.01 × 10−6
From Example 10.5, we observe that the Miller replacement of a feedback or bridging
resistance results, for a negative K, in a smaller resistance [by a factor (1 − K )] at the input. If
the feedback element is a capacitance, its value is multiplied by (1 − K ) to obtain the equivalent
capacitance at the input side. The multiplication of a feedback capacitance by (1−K) is
referred to as Miller multiplication or Miller effect. We have encountered the Miller effect
in the analysis of the CS and CE amplifiers. Note, however, that we neglected the Miller 1
capacitance at the output because it is small; for the CS case, C2 = Cgd 1 + gm RL′ ≃ Cgd .
JOHN MILTON MILLER—CAPACITANCE MULTIPLICATION:
In 1920 in the Scientific Papers of the National Bureau of Standards, John Miller first published data and analysis on the input capacitance of a vacuum-tube triode amplifier and the phenomenon ultimately known as the Miller effect. Attempts to eliminate or reduce this effect in amplifiers and oscillators led to several developments: First, in 1926, came vacuum-tube pentodes with internal grounded shielding elements; much later, in 1939, the cascode configuration was introduced, initially using vacuum-tube triodes and then with BJTs and MOSFETs.
10.3.4 Frequency Response of the CS Amplifier When Rsig Is Low
There are applications in which the CS amplifier is fed with a low-resistance signal source. In such a case, the high-frequency gain will no longer be limited by the interaction of the source resistance and the input capacitance. Rather, the high-frequency limitation occurs at the amplifier output as we shall now show.
Figure 10.22(a) shows the high-frequency equivalent circuit of the common-source amplifier in the limiting case when Rsig is zero. Observe that we have included a capacitance CL across the load RL . We have done this in the anticipation that a capacitance at the output node, even if it is very small, will play an important role in this case. Also, there always is some capacitance between the output node and ground. This can include Cd b of the MOSFET [see the MOSFET high-frequency model of Fig. 10.12(b)], the input capacitance of another amplifier stage our amplifier feeds, other stray capacitances, and so on. Finally, we note that we did not include CL in the previous analysis because its role is not significant when Rsig is large.
Returning to the circuit in Fig. 10.22(a), we can now derive its transfer function Vo /Vsig . First, note that
Vgs = Vsig (10.62) Second, the current Igd that flows through Cgd can be expressed as
Igd =sCgd (Vgs −Vo) (10.63)
736 Chapter 10
Frequency Response
Vsig RG
Cgd
GD
Vgs
Cgd
CL Vo
Cgs
gmVgs
ro RL
Vgs 0
Cgs 0 RL
(b)
RL (a)
CL
20 dBdecade ft AM f3dB
fZ
2pCgd
Gain (dB) 20 log AM
0
fH
f (log scale)
11 gm
2p (CL Cgd)RL 2p(CL Cgd)
(c)
g m
Figure10.22 (a)High-frequencyequivalentcircuitofaCSamplifierfedwithasignalsourcehavingavery low (effectively zero) resistance. (b) The circuit with Vsig reduced to zero. (c) Bode plot for the gain of the circuit in (a).
Next, we can write a node equation at the output node as
Igd =gmVgs+Vo +sCLVo RL′
(10.64)
where
Combining Eqs. (10.63) and (10.64) to eliminate Igd , substituting Vgs = Vsig from Eq. (10.62),
RL′ =RL∥ro
and manipulating the resulting equation to obtain the transfer function Vo/Vsig results in
Vo =−gmRL′ 1−s(Cgd/gm) (10.65) Vsig 1+s(CL +Cgd)RL′
10.3 High-Frequency Response of the CS and CE Amplifiers 737 Thus, while the dc gain from gate to drain remains equal to gmRL′ , and the frequency of the
transmission zero remains unchanged at
fZ = gm (10.66) 2πCgd
the high-frequency response is now determined by a pole formed by (CL + Cg d ) together with RL′.Thusthe3-dBfrequencyfH isnowgivenby
fH = 1 (10.67) 2 π ( C L + C g d ) R L′
To see how this pole is formed, refer to Fig. 10.22(b), which shows the equivalent circuit with Vsig reduced to zero. Observe that the circuit reduces to a capacitance (CL + Cgd ) in parallel with a resistance RL′ .
We note that the transmission zero frequency, given by Eq. (10.66), is much higher
than fH ,
fZ =(gmRL′) 1+CL (10.68) fH Cgd
Thus,fZ doesnotplayasignificantroleinthevicinityoffH.Infact,thegaindecreasesfromits low-frequency value of (gmRL′ ) at a uniform rate of –6 dB/octave (–20 dB/decade), reaching unity (0 dB) at a frequency ft , which is equal to the gain–bandwidth product,
ft =|AM|fH
= g m R L′ 1
2π(CL +Cgd)RL′
gm (10.69)
Consider an IC CS amplifier fed with a source having Rsig = 0 and having an effective load resistance RL′ composed of ro of the amplifier transistor in parallel with an equal resistance ro of the current-source load. Let gm = 1.25mA/V, ro = 20k, Cgs = 20fF, Cgd = 5fF, and CL = 25fF. Find AM, fH, ft, and fZ . If the amplifying transistor is to be operated at twice the original overdrive voltage while W and L remain unchanged, by what factor must the bias current be changed? What are the new values of AM , fH , ft , and fZ ?
Solution
Thelow-frequencygainAM isgivenby
AM =−gmRL′ =−gm(ro∥ro)
Thus,
Example 10.6
ft =
Figure 10.22(c) shows a sketch of the high-frequency gain of the CS amplifier.
2π(CL +Cgd)
738
Chapter 10 Frequency Response
Example 10.6 continued Thus,
AM =−1gmro =−1 ×1.25×20 22
= −12.5 V/V The3-dBfrequencyfH canbefoundusingEq.(10.67),
f=1
H 2π(CL +Cgd)RL′
=1 2π(25+5)×10−15 ×10×103
= 530.5 MHz
and the unity-gain frequency, which is equal to the gain–bandwidth product, can be determined as
ft =|AM| fH =12.5×530.5=6.63GHz The frequency of the zero is obtained using Eq. (10.66) as
fZ = 1 gm 2π Cgd
gm = ID =2.5mA/V VOV/2
RL′ =1×10=2.5k 4
ThusthenewvalueofAM becomes
AM =−gmRL′ =−2.5×2.5=−6.25V/V
1 1.25×10−3 = 2π 5×10−15
≃40GHz
Now, to double VOV , ID must be quadrupled. The new values of gm and RL′ can be found as follows:
That of fH becomes
f=1
H 2π(CL +Cgd)RL′
=1 2π(25+5)×10−15 ×2.5×103
= 2.12 GHz
and the unity-gain frequency (i.e., the gain–bandwidth product) becomes
ft =6.25×2.12=13.3GHz
We note that doubling VOV results in reducing the dc gain by a factor of 2 and increasing the bandwidth by a factor of 4. Thus, the gain–bandwidth product is doubled—a good bargain!
Finally,thefrequencyofthetransmissionzerofZ willbedoubled,becoming80GHz.
10.4 Useful Tools for the Analysis of the High-Frequency Response of Amplifiers 739
EXERCISE
10.11 FortheCSamplifierconsideredinExample10.6operatingattheoriginalvaluesofVOV andID,find thevaluetowhichCL shouldbeincreasedtoplaceft at2GHz.
Ans. 94.5 fF
We conclude this section by noting that a CE amplifier fed with Rsig = 0 can be analyzed in exactly the same way used for the CS case. The most general case when Rsig is not zero and CL is present will be dealt with in the next section.
10.4 Useful Tools for the Analysis of the High-Frequency Response of Amplifiers
In Section 10.3 we presented an approximate method, utilizing the Miller effect, to analyze the high-frequency response of the CS and CE amplifiers; the method provides a reasonably accurateestimateoffH and,equallyimportant,considerableinsightintothemechanismthat limits high-frequency operation. Unfortunately, however, this method cannot deal with the case when a load capacitance CL is present. As well, the method is not easily extendable to more complex amplifier circuits. For this reason, we will digress briefly into how to equip ourselves with a number of tools that will prove useful in the analysis of more complex circuits such as the cascode amplifier. We will begin by stepping back and more generally considering the amplifier high-frequency transfer function.
10.4.1 The High-Frequency Gain Function
The amplifier gain, taking into account the internal transistor capacitances, can be expressed as a function of the complex-frequency variable s in the general form
A(s) = AM FH (s) (10.70)
whereAM isthemidbandgain,whichforICamplifiersisalsoequaltothelow-frequencyor dc gain (refer to Fig. 10.2). The value of AM can be determined by analyzing the amplifier equivalent circuit while neglecting the effect of the transistor internal capacitances—that is, by assuming that they act as perfect open circuits. By taking these capacitances into account, we see that the gain acquires the factor FH (s), which can be expressed in terms of its poles and zeros, which are usually real, as follows:
FH(s)= (1+s/ωZ1)(1+s/ωZ2)···(1+s/ωZn) (10.71) (1+s/ωP1)(1+s/ωP2)···(1+s/ωPn)
740 Chapter 10
Frequency Response
where ωP1, ωP2,. . . , ωPn are positive numbers representing the frequencies of the n real poles6 and ωZ1, ωZ2,. . . , ωZn are positive, negative, or infinite numbers representing the frequencies of the n real transmission zeros. Since the frequencies of the zeros and poles are by definition greater than the midband frequencies, we see from Eq. (10.71) that as s approaches midband frequencies, FH (s) approaches unity and the gain approaches AM .
10.4.2 Determining the 3-dB Frequency fH
The amplifier designer usually is particularly interested in the part of the high-frequency band that is close to the midband. This is because the designer needs to estimate—and, if need be, modify—the value of the upper 3-dB frequency fH (or ωH ; fH = ωH /2π ). Toward that end, it should be mentioned that in many cases the zeros are either at infinity or such high frequencies as to be of little significance to the determination of ωH . If in addition one of the poles, say ωP1, is of much lower frequency than any of the other poles, then this pole will have the greatest effect on the value of the amplifier ωH . In other words, this pole will dominate the high-frequency response of the amplifier, and the amplifier is said to have a dominant-pole response. In such cases, the function FH (s) can be approximated by
FH (s) ≃ 1 (10.72) 1 + s/ωP1
which is the transfer function of a first-order (or STC) low-pass network (Appendix E). It followsthatifadominantpoleexists,thenthedeterminationofωH isgreatlysimplified;
ωH ≃ωP1 (10.73)
This is the situation we encountered in the cases of the common-source and common-emitter amplifiers analyzed in Section 10.3. As a rule of thumb, a dominant pole exists if the lowest-frequency pole is at least two octaves (a factor of 4) away from the nearest pole or zero.
Ifadominantpoledoesnotexist,the3-dBfrequencyωH canbedeterminedfromaplotof |FH(jω)|.Alternatively,anapproximateformulaforωH canbederivedasfollows.Consider, for simplicity, the case of a circuit having two poles and two zeros in the high-frequency band; that is,
FH (s) = (1 + s/ωZ1)(1 + s/ωZ2) (10.74) (1+s/ωP1)(1+s/ωP2)
Substituting s = jω and taking the squared magnitude gives
1 + ω2/ω2 1 + ω2/ω2 |FH (jω)|2 = Z1 Z2
1 + ω2/ω2P1 1 + ω2/ω2P2
6In certain cases, some of the poles can be complex. One notable such case is the source and emitter followers, which can have a pair of complex-conjugate poles (Section 10.6).
10.4 Useful Tools for the Analysis of the High-Frequency Response of Amplifiers 741 Bydefinition,atω=ωH,|FH|2 = 1;thus,
1 2
2
1+ω2 /ω2 1+ω2 /ω2
= H Z1 H Z2 1 + ω 2H / ω 2P 1 1 + ω 2H / ω 2P 2
1 1 1+ω2H ω2 + ω2
= Z1 Z2 1+ω2 1 + 1
+ω4H/ω2Z1ω2Z2 +ω4/ω2 ω2
(10.75)
Hω2ω2 HP1P2 P1 P2
Since ωH is usually smaller than the frequencies of all the poles and zeros, we may neglect thetermscontainingω4H andsolveforωH toobtain
ωH ≃1 1 + 1 − 2 − 2 (10.76) ω2P1 ω2P2 ω2Z 1 ω2Z 2
This relationship can be extended to any number of poles and zeros as
1 1 1 1
ωH ≃1 ω2 +ω2 +··· −2 ω2 +ω2 +··· (10.77)
P1 P2 Z1 Z2
Note that if one of the poles, say P1, is dominant, then ωP1 ≪ ωP2, ωP3,. . . , ωZ1, ωZ2,. . . , and
Eq. (10.77) reduces to Eq. (10.73).
Example 10.7
The high-frequency response of an amplifier is characterized by the transfer function 1 − s/105
FH(s)= 1+s/1041+s/4×104 Determine the 3-dB frequency approximately and exactly.
Solution
Noting that the lowest-frequency pole at 104 rad/s is two octaves lower than the second pole and a decade lower than the zero, we find that a dominant-pole situation almost exists and ωH ≃ 104 rad/s. A better estimateofωH canbeobtainedusingEq.(10.77),asfollows:
ω=11+1−2 H 108 16 × 108 1010
= 9800 rad/s
TheexactvalueofωH canbedeterminedfromthegiventransferfunctionas9537rad/s.Finally,weshow in Fig. 10.23 a Bode plot and an exact plot for the given transfer function. Note that this is a plot of the high-frequency response of the amplifier normalized relative to its midband gain. That is, if the midband gain is, say, 100 dB, then the entire plot should be shifted upward by 100 dB.
742 Chapter 10 Frequency Response
Example 10.7 continued
Figure 10.23 Normalized high-frequency response of the amplifier in Example 10.7.
EXERCISES
10.12 A direct-coupled amplifier has a dc gain of 1000 V/V and an upper 3-dB frequency of 100 kHz. Find the transfer function and the gain–bandwidth product in hertz.
Ans. 1000 ;108 Hz 1+s
2π ×105
10.13 Thehigh-frequencyresponseofanamplifierischaracterizedbytwozerosats=∞andtwopoles
at ωP1 and ωP2. For ωP2 = kωP1, find the value of k that results in the exact value of ωH being 0.9 ωP1. RepeatforωH =0.99ωP1.
Ans. 2.78; 9.88
10.14 FortheamplifierdescribedinExercise10.13,findtheexactandapproximatevalues(usingEq.10.77) ofωH (asafunctionofωP1)forthecasesk=1,2,and4.
Ans. 0.64, 0.71; 0.84, 0.89; 0.95, 0.97
10.4 Useful Tools for the Analysis of the High-Frequency Response of Amplifiers 743 10.4.3 The Method of Open-Circuit Time Constants
If the poles and zeros of the amplifier transfer function can be determined easily, then we can determinefH usingthetechniquesabove.Inmanycases,however,itisnotasimplematterto determine the poles and zeros by quick hand analysis. In such cases an approximate value for fH canbeobtainedusingthemethodofopen-circuittimeconstants,whichwedescribenext. This method is the dual of the method of short-circuit time constants we used in Section 10.1 for the estimation of fL .
Consider the function FH (s) (Eq. 10.71), which determines the high-frequency response of the amplifier. The numerator and denominator factors can be multiplied out and FH(s) expressed in the alternative form
1+a1s+a2s2 + ··· +ansn
FH (s) = 1 + b1 s + b2 s2 + · · · + bn sn (10.78)
where the coefficients a and b are related to the frequencies of the zeros and poles, respectively. Specifically, the coefficient b1 is given by
b1= 1 + 1 +···+ 1 (10.79) ωP1 ωP2 ωPn
Itcanbeshown[seeGrayandSearle(1969)7]thatthevalueofb1 canbeobtainedbysettingthe input signal to zero and considering the various capacitances in the high-frequency equivalent circuit one at a time while reducing all other capacitors to zero (or, equivalently, replacing them with open circuits). That is, to obtain the contribution of capacitance Ci, we reduce all other capacitances to zero, reduce the input signal source to zero, and determine the resistance Ri seenbyCi.ThiscanbedoneeitherbyinspectionorbyreplacingCi withavoltagesourceVx, findingthecurrentIx drawnfromVx,andcalculatingRi ≡Vx/Ix.Thetimeconstantτi associated with Ci is then found as τi = CiRi. This process is then repeated for all other capacitors in the circuit. The value of b1 is computed by summing the individual time constants, called open-circuit time constants,
n
b1 =
CiRi (10.80)
i=1
where we have assumed that there are n capacitors in the high-frequency equivalent circuit.
This method for determining b1 is exact; the approximation comes about in using the value of b1 to determine ωH . Specifically, if the zeros are not dominant and if one of the poles, say P1 , is dominant, then from Eq. (10.79),
b1 ≃ 1 ωP1
But, also, the upper 3-dB frequency will be approximately equal to ωP1, leading to ωH ≃ 1 =1
(10.81)
(10.82)
b1
Here it should be pointed out that in complex circuits we usually do not know whether
a dominant pole exists. Nevertheless, using Eq. (10.82) to determine ωH normally yields 7The bibliography is in Appendix I.
i
CiRi
744 Chapter 10
Frequency Response
remarkably good results8 even if a dominant pole does not exist. Finally, we note that we will sometimes refer to the sum of time constants in Eq. (10.81) by τH ; that is, τH = b1 , and is known as the effective high-frequency time constant.
10.4.4 Application of the Method of Open-Circuit Time Constants to the CS Amplifier
Figure 10.24 shows a generalized high-frequency equivalent circuit for the common-source
amplifier. Here, V′ and R′ are the The ́venin equivalent of the signal generator together sig sig
with whatever bias circuit may be present at the amplifier input [e.g., RG in the circuit of Fig. 10.3(a)]. Resistance RL′ represents the total resistance between the output (drain) node and ground and includes RD, ro, and RL (if one is present). Similarly, CL represents the total capacitance between the drain node and ground and includes the MOSFET’s drain-to-body capacitance (Cdb), the capacitance introduced by a current-source load, the input capacitance of a succeeding amplifier stage (if one is present), and in some cases, as we will see in later chapters, a deliberately introduced capacitance. In IC MOS amplifiers, CL can be substantial.
The equivalent circuit in Fig. 10.24 can also be used to represent the CE amplifier. Thus, we will not need to repeat the analysis; rather, we can adapt the CS results to the CE case by simply renaming the components (i.e., replacing Cgs by Cπ and Cgd by Cμ).
Wewishtodeterminethe3-dBfrequencyfH oftheCSamplifierinFig.10.24usingthe method of open-circuit time constants. Toward that end, we set Vsig = 0 and consider each of the three capacitances at a time, setting the other two to zero. Figure 10.25(a) shows the resulting circuit for determining the resistance Rgs seen by Cgs, thus
R =R′ (10.83) gs sig
For Cgd, we obtain the circuit in Fig.10.25(b). This circuit is somewhat complex, and we cannot determine Rgd by inspection. Rather, we apply a test current source Ix and determine thevoltageVx thatresultsacrossIx.Weseethat
A loop equation gives
Vsig
Rsig
G
D
V =−IR′ gs xsig
Vd =Vx +Vgs Cgd
gmVgs
(10.84)
Vgs
Cgs
RL CL Vo
Figure 10.24 Generalized high-frequency equivalent circuit for the CS amplifier.
8 The method of open-circuit time constants yields good results only when all the poles are real, as is the case in most of this chapter.
10.4
Useful Tools for the Analysis of the High-Frequency Response of Amplifiers 745 Ix
Rsig
(a)
Rsig
G
Rgs
Rsig
Vx G
D
R Vgs gV L
m gs
Rgd Vx Ix
(b)
GD
Vgs 0
(c)
RL
0
RC
Figure 10.25 Application of the open-circuit time-constants method to the CS equivalent circuit of Fig. 10.24.
A node equation at D gives
Thus,
Ix =gmVgs+Vd RL′
Ix =gmVgs+Vx+Vgs RL′
Substituting for Vgs from Eq. (10.84) and manipulating the resulting equation gives R ≡Vx=R′ (1+gR′)+R′
(10.85)
gd I sig mL L x
Finally, for CL we obtain the circuit shown in Fig. 10.25(c), from which RCL =RL′
(10.86) Next, we use the resistance values in Eqs. (10.83), (10.85), and (10.86) to obtain the effective
high-frequency time constant τH ,
τH =b1 =CgsRgs +CgdRgd +CLRCL (10.87)
=CR′ +C[R′(1+gR′)+R′]+CR′ gssig gdsig mL L LL
746 Chapter 10
Frequency Response
andthe3-dBfrequencyfH is
An important observation is available from Eq. (10.87), which can be rewritten as
τ =[C +C (1+g R′ )]R′ +(C +C )R′ (10.88) H gs gd m L sig gd L L
We note that the first term is simply C R′ , where C is dominated by the Miller capacitance in sig in
Cgd(1 + gmRL′ ). The method of open-circuit time constants, however, also provides the
second term, which results from the interaction of (Cgd + CL) with RL′ . Thus, while the
first term in Eq. (10.88) arises at the input node, the second term occurs at the output
node. The second term can be dominant in cases where R′ is small, as we have seen in sig
fH= 1 2π τH
Section 10.3.4.
Example 10.8
An integrated-circuit CS amplifier has g = 1.25 mA/V, C m
= 20 fF, C = 5 fF, C = 25 fF, R′ = 10k, gs gd L sig
andRL′ =10k.DeterminefH andthefrequencyofthetransmissionzerofZ causedbyCgd. Solution
ToobtainfH wefirstuseEqs.(10.83),(10.85),and(10.86)todeterminetheresistancesseenbythethree capacitors Cgs, Cgd, and CL, respectively,
R =R′ =10k gs sig
R =R′ (1+gR′)+R′ gd sig mL L
=10(1+1.25×10)+10=145k RCL =RL′ =10k
We then determine the three time constants:
τgs =CgsRgs =20×10−15 ×10×103 =200ps τgd =CgdRgd =5×10−15 ×145×103 =725ps τCL =CLRCL =25×10−15 ×10×103 =250ps
Theeffectivehigh-frequencytimeconstantτH cannowbeobtainedbysummingthethreetimeconstants, τH =τgs +τgd +τCL
andthe3-dBfrequencyfH is
=200+725+250=1175ps
fH = 1 = 1 =135.5MHz 2π τH 2π × 1175 × 10−12
The frequency of the transmission zero can be determined by reference to the circuit in Fig. 10.24. Since ats=sZ,Vo willbezero,anodeequationattheoutputnodeats=sZ becomes
sZCgd(Vgs −0)=gmVgs
Thus
and
sZ = gm Cgd
1.25 × 10−3
= 2π×5×10−15 =39.8GHz
10.4
Useful Tools for the Analysis of the High-Frequency Response of Amplifiers 747
gm fZ = 2πC
gd
which is much higher than fH ; hence it plays almost no role in the estimate of fH .
EXERCISES
10.15 FortheCSamplifierinExample10.8,findtheestimateoffH obtainedusingtheMillereffectmethod of Section 10.3.1. By what percentage does this estimate differ from that obtained in Example 10.8 using the method of open-circuit time constants? Which of the two estimates is more realistic, and why?
Ans. 181.9 MHz; greater by 34%; the value obtained by the method of open-circuit time constants
is more realistic because it includes the effect of CL .
10.16 For the CS amplifier in Example 10.8, using the value of fH determined by the method of open-circuit
time constants, find the gain–bandwidth product. Recall that gm = 1.25 mA/V and RL′ = 10 k.
Ans. GBW = 1.69 GHz
10.17 As a way to trade gain for bandwidth, the designer of the CS amplifier in Example 10.8 connects a
load resistor at the output that results in halving the value of R′ . Find the new values of A , f , LMH
and the gain–bandwidth product.
Ans. 6.25 V/V; 223.4 MHz; 1.4 GHz
10.18 As another way to trade dc gain for bandwidth, the designer of the CS amplifier in Example 10.8
decides to operate the amplifying transistor at double the value of V by increasing the bias ′ OV
current fourfold. Find the new values of gm , RL , AM , fH , and the gain–bandwidth product. Assume that RL′ is the parallel equivalent of ro of the amplifying transistor and that of the current-source load.
Ans. 2.5 mA /V; 2.5 k; 6.25 V/V; 250 MHz; 1.56 GHz
We conclude this section by emphasizing that the method of open-circuit time constants reveals to the circuit designer the relative contribution of the various capacitances to the determination of the amplifier bandwidth fH . For instance, for the amplifier in Example 10.8, we see that while Cgd contributes the most (725 ps of 1175 pF, or 62%) because of the Miller effect, the contribution of each of Cgs (17%) and CL (12%) is not insignificant. Such information can be useful in the amplifier-design process.
748 Chapter 10
Frequency Response
10.4.5 Application of the Method of Open-Circuit Time Constants to the CE Amplifier
The formulas developed for the CS case can be easily adapted to the case of the CE amplifier whose equivalent circuit is shown in Fig. 10.19(b). For the general case of a capacitance CL that appears across the output terminals,
Thus, and
Note that expressions for R′ sig
R =R′ π sig
R=R′ (1+gR′)+R′ μ sig mL L
R C L = R L′
τ=CR′ +C[R′(1+gR′)+R′]+CR′
fH= 1 2π τH
are given in Fig. 10.19.
(10.89) (10.90) (10.91)
(10.92)
(10.93)
H πsig μsig mL L LL
and R′ L
EXERCISE
10.19 Consider a bipolar active-loaded CE amplifier having the load current source implemented with
a pnp transistor. Let the circuit be operating at a 1-mA bias current. The transistors are specified
as follows: β(npn)=200, V =130V, V =50V, C =16pF, C =0.3pF, C =5pF, and An Ap π μ L
rx = 200 . The amplifier is fed with a signal source having a resistance of 36 k. Determine: (a) AM;(b)Cin andfH usingtheMillereffect;(c)fH usingopen-circuittimeconstants;(d)fZ;and(e)the gain–bandwidth product.
Ans. (a) −175 V/V; (b) 450 pF, 80.6 kHz; (c) 73.5 kHz; (d) 21.2 GHz; (e) 12.9 MHz
10.5 High-Frequency Response of the Common-Gate and Cascode Amplifiers
Although common-source and common-emitter amplifiers provide substantial gain at midband frequencies, their gain falls off in the high-frequency band at a relatively low frequency. This is primarily due to the large input capacitance Cin , whose value is significantly increased by the Miller component. The latter is large because of the Miller multiplication effect, which the bridging capacitance Cgd (or Cμ) experiences. It follows that the key to obtaining wideband operation, that is, high fH , is to use circuit configurations that do not suffer from the Miller effect. One such configuration is the common-gate circuit.
10.5.1 High-Frequency Response of the CG Amplifier
Figure 10.26(a) shows the CG amplifier with the MOSFET internal capacitances Cgs and Cgd pulled out of the model and indicated. For generality, a capacitance CL is included at the
gm and the other at the output side with a frequency fP2,
10.5 High-Frequency Response of the Common-Gate and Cascode Amplifiers 749
output node to represent the combination of the output capacitance of a current-source load and the input capacitance of a succeeding amplifier stage. Capacitance CL also includes the MOSFET capacitance Cdb. Note the CL appears in effect in parallel with Cgd; therefore, in the following analysis we will lump the two capacitances together.
It is important to note at the outset that each of the three capacitances in the circuit of Fig. 10.26(a) has a grounded node. Therefore none of the capacitances undergoes the Miller multiplication effect observed in the CS stage. It follows that the CG circuit can be designed to have a much wider bandwidth than that of the CS circuit, especially when the resistance of the signal generator is large. To analyze the high-frequency response of the CG amplifier of Fig. 10.26(a), we replace the MOSFET with its T model. The resulting circuit, with Cgd lumped with CL , is shown in Fig. 10.26(b).
We shall consider first the case of a discrete-circuit CG amplifier in which ro can be neglected. Eliminating ro results in the circuit in Fig. 10.26(c). We immediately observe that there are two poles: one at the input side with a frequency fP1,
(10.94)
(10.95)
fP1 = 1 2πCgs Rsig∥ 1
fP2 = 1 2π(Cgd +CL)RL
The relative locations of the two poles will depend on the specific situation. However, fP2 is usually lower than fP1; thus fP2 can be dominant. The important point to note is that both fP1 and fP2 are usually much higher than the frequency of the dominant input pole in the CS stage. An approximate value for fH can be obtained by applying the method of open-circuit time constants to the circuit of Fig. 10.26(c), resulting in
1
1
τgs = Cgs Rsig ∥ g
= 1/2πfP2 τgd =(CL +Cgd)RL =1/2πfP1
(10.96)
(10.97) (10.98)
(10.99)
and Thus,
and
constants to the equivalent circuit in Fig. 10.26(b), we obtain the circuit in Fig. 10.26(d) for determining Rgs. From this circuit we find that
Rgs = Rsig ∥Rin (10.100) where Rin is the input resistance of the CG amplifier with a load resistance RL . An expression
for Rin was derived in Chapter 8 and given in Eq. (8.53),
Rin = ro +RL ≃ ro +RL (10.101) 1+gmro gmro
τH =Cgs
fH=2πτ=1 f+f
m
+(CL +Cgd)RL 1 1 1
Rsig∥g
m
H P1P2
In IC amplifiers, ro has to be taken into account. Applying the method of open-circuit time
750 Chapter 10
Frequency Response
TheresistanceRgd seenby(CL+Cgd)canbeobtainedfromthecircuitinFig.10.26(e),
Rgd = RL ∥Ro D
(10.102)
Vo
Cgd
Cgs Rsig
Vsig
RL
CL
G
S
(a)
D
Vo
gmVgs
RL
(CL + Cgd)
G
V1 gs gm
ro
Rsig
S
Cgs
Vsig
Vsig
(b)
RsigS D
1 Cgs V RL gm gs gmVgs
(c)
Vo
(CLCgd)
Figure 10.26 (a) The common-gate amplifier with the transistor internal capacitances shown. A load capacitanceCL isalsoincluded.(b)EquivalentcircuitoftheCGamplifierwiththeMOSFETreplacedwithits T model. (c) Equivalent circuit for the case in which ro is neglected. (d) Circuit for determining the resistance Rgs seen by Cgs. (e) Circuit for determining the resistance Rgd seen by (CL +Cgd).
10.5 High-Frequency Response of the Common-Gate and Cascode Amplifiers 751
Figure 10.26 continued
where Ro is the output resistance of a CG amplifier with a resistance Rsig connected between source and ground. From Chapter 8, Eq. (8.56), we have
Finally, and
Ro =ro +Rsig +gmroRsig τH = τgs + τgd
fH = 1 2π τH
(10.103)
(10.104)
(10.105)
752 Chapter 10 Frequency Response
Example 10.9
Consider a common-gate amplifier with gm = 1.25 mA/V, ro = 20 k, Cgs = 20 fF, Cgd = 5 fF, CL = 25 fF, Rsig = 10 k, and RL = 20 k. Assume that CL includes Cd b . Determine the input resistance, the midband gain, and the upper 3-dB frequency fH .
Solution
Figure 10.27 shows the CG amplifier circuit at midband frequencies. We note that
Thus, the overall voltage gain is given by
vo =iRL
vsig =i Rsig +Rin
Gv=vo= RL
vsig i
Rsig +Rin
vo RL
Rsig
i
Ro
vsig
Rin
Figure 10.27 The CG amplifier circuit at midband.
The value of Rin is found from Eq. (10.101) as
Rin = ro +RL
1+gmro
= 20 + 20 1+(1.25×20)
= 1.54 k
Thus,Gv cannowbedeterminedas
where Ro is given by Eq. (10.103),
Thus,
Ro=ro+Rsig+gmro Rsig
= 20 + 10 + 25 × 10 = 280 k
Rgd =20∥280=18.7k
10.5 High-Frequency Response of the Common-Gate and Cascode Amplifiers 753
Gv = 20 =1.73V/V 10 + 1.54
ObservethatasexpectedGv isverylow.ThisisduetothefactthattheCGamplifierdrawsalargeinput current, equal, in fact, to the load current i.
Toobtainanestimateofthe3-dBfrequencyfH,wefirstdetermineRgs andRgd usingEqs.(10.100)and (10.102),
Rgs = Rsig ∥Rin = 10∥1.54 = 1.33 k Rgd =RL∥Ro
Now we can compute the sum of the open-circuit time constants, τH ,
τH=CgsRgs+Cgd+CL Rgd
τH =20×10−15 ×1.33×103 +(5+25)×10−15 ×18.7×103
=26.6×10−12 +561×10−12
= 587.6 ps andtheupper3-dBfrequencyfH canbeobtainedas
f = 1 = 1 =270.9MHz H 2πτH 2π × 587.6 × 10−12
Observe that fH is indeed much higher than (about twice) the corresponding value for the CS amplifier found in Example 10.8. Another important observation can be made by examining the two components of τH : The contribution of the input circuit is 26.6 ps, while that of the output circuit is 561 ps; thus the limitation on the high-frequency response is posed by the output circuit.
EXERCISE
10.20 InordertoraisethemidbandgainoftheCGamplifierinExample10.9,thecircuitdesignerdecides to use a cascode current source for the load device, thus raising RL by a factor of gm ro = 25; that is, RL becomes 500 k. Find Rin , the midband gain, and fH . Comment on the results.
Ans. 20 k; 16.7 V/V; 28.8 MHz. While the midband gain has been increased substantially (by a factor of 9.7), the bandwidth fH has been substantially lowered (by a factor of about 9.4). Thus, the high-frequency advantage of the CG amplifier is completely lost!
754 Chapter 10
Frequency Response
We conclude this section by noting that a properly designed CG circuit can have a wide bandwidth. However, the input resistance will be low and the overall midband gain can be very low. It follows that the CG circuit alone will not do the job! However, combining the CG with the CS amplifier in the cascode configuration can result in a circuit having the high input resistance and gain of the CS amplifier together with the wide bandwidth of the CG amplifier, as we shall now see.
10.5.2 High-Frequency Response of the MOS Cascode Amplifier
In Section 8.5 we studied the cascode amplifier and analyzed its performance at midband frequencies. There we learned that by combining the CS and CG configurations, the cascode amplifier exhibits a very high input resistance and a voltage gain that can be as high as A20, where A0 = gm ro is the intrinsic gain of the MOSFET. For our purposes here, we shall see that the versatility of the cascode circuit allows us to trade off some of this high midband gain in return for a wider bandwidth.
Figure 10.28 shows the cascode amplifier with all transistor internal capacitances indicated.AlsoincludedisacapacitanceCL attheoutputnodetorepresentthecombinationof Cd b2 , the output capacitance of a current-source load, and the input capacitance of a succeeding amplifier stage (if any). Note that Cd b1 and Cgs2 appear in parallel, and we shall combine them in the following analysis. Similarly, CL and Cgd2 appear in parallel and will be combined.
Theeasiestand,infact,quiteinsightfulapproachtodeterminingthe3-dBfrequencyfH is to employ the open-circuit time-constants method:
1. 2.
Capacitance Cgs1 sees a resistance Rsig.
Capacitance Cgd1 is the gate-to-drain capacitance of the CS amplifier Q1; thus it sees a resistance Rgd1, which can be obtained by adapting the formula in Eq. (10.85),
Rgd1 = (1 + gm1Rd1)Rsig + Rd1 (10.106) where Rd 1 , the total resistance at D1 , is given by the parallel equivalent of the resistance
lookingintothedrainofQ1 (ro1)andtheresistancelookingintothesourceofQ2 (Rin2),
D2
Vo
Cgd 2
Cgs2
Rsig G1
Vi Cgs1
Q2 RL CL
D1
Q1 Cdb1
Cgd1
Vsig
Figure 10.28 The cascode circuit with the various transistor capacitances indicated.
thus
10.5 High-Frequency Response of the Common-Gate and Cascode Amplifiers 755
Rd1 = ro1 ∥Rin2 = ro1 ∥ ro2 + RL (10.107) gm2 ro2
3. Capacitance (Cdb1 +Cgs2) sees a resistance Rd1.
4. Capacitance (CL +Cgd2) sees a resistance (RL ∥Ro) where Ro, the output resistance of
the cascode amplifier, is given by
Ro =ro2 +ro1 +(gm2ro2)ro1
Withtheresistancesdetermined,theeffectivetimeconstantτH canbecomputedas
τH = Cgs1Rsig + Cgd1 (1 + gm1Rd1)Rsig + Rd1
+ Cdb1 +Cgs2 Rd1 + CL +Cgd2 (RL ∥Ro) andthe3-dBfrequencyfH as
fH≃ 1 2πτH
(10.108)
Design Insight and Trade-Offs To gain insight regarding what limits the high-frequency gain of the MOS cascode amplifier, we rewrite Eq. (10.108) in the form
τH = Rsig Cgs1 + Cgd1(1 + gm1Rd1) + Rd1 Cgd1 + Cdb1 + Cgs2
+(RL∥Ro) CL +Cgd2 (10.109)
Here we note that the first term arises at the input node, the second term at the middle node, namely (D1, S2), and the third term at the output node. The first term is simply due to the interaction of the signal-source resistance Rsig and the input capacitance of Q1, which, as expected, includes the Miller capacitance Cgd1(1 + gm1Rd1).
In the case of a large Rsig, the first term can dominate, especially if the Miller multiplier (1+gm1Rd1) is large. This in turn happens when the load resistance RL is large (on the order of A0ro), causing Rin2 and hence Rd1 to be large and requiring the first stage, Q1, to provide a large proportion of the gain (see Section 8.5.3). It follows that when Rsig is large, to extend the bandwidth we have to lower RL to the order of ro. This in turn lowers Rin2 and hence Rd1 and renders the Miller effect in Q1 insignificant. Note, however, that the dc gain of the cascode will then be A0. Thus, while the dc gain will be the same as (or a little higher than) that achieved in a CS amplifier, the bandwidth will be greater.
In the case when Rsig is small, the Miller effect in Q1 will not be of concern. A large value ofRL (ontheorderofA0ro)canthenbeusedtorealizethelargedcgainpossiblewithacascode amplifier—that is, a dc gain on the order of A20 . Equation (10.109) indicates that in this case the third term will usually be dominant. To pursue this point a little further, consider the case Rsig = 0, and assume that the middle term is much smaller than the third term. It follows that
and the 3-dB frequency becomes
τH ≃ CL +Cgd2 (RL∥Ro) (10.110)
fH = 1 (10.111) 2π(CL + Cgd2)(RL ∥Ro)
756 Chapter 10
Frequency Response
which is of the same form as the formula for the CS amplifier with Rsig = 0 (Eq. 10.67). Here, however, (RL ∥Ro) is larger that RL′ by a factor of about A0. Thus the fH of the cascode will be lower than that of the CS amplifier by the same factor A0. Figure 10.29 shows a sketch of the frequency response of the cascode and of the corresponding common-source amplifier. We observe that in this case, cascoding increases the dc gain by a factor A0 while keeping the unity-gain frequency unchanged at
ft ≃ 1 gm
2π CL +Cgd2
(10.112)
Vo
Common Source
Vo
ro
Vi RLCL R L R L r o
g m R L
1
2p(CL Cgd)RL
gm 2p(CL Cgd)
Cascode
Circuit
DC Gain f3dB
ft
Vi
A0 ro
A0RL CL
A0gmRL 1
2p(CL Cgd)A0RL gm
2p(CL Cgd)
Gain (dB) A 0 g m R L
A0 g m R L
0
Cascode
A0
CS
f3dBCS
f3dBcascode
ft f
(log scale)
Figure 10.29 Effect of cascoding on gain and bandwidth in the case Rsig = 0. Cascoding can increase the dc gain by the factor A0 while keeping the unity-gain frequency constant. Note that to achieve the high gain, the load resistance must be increased by the factor A0.
10.5 High-Frequency Response of the Common-Gate and Cascode Amplifiers 757
Example 10.10
This example illustrates the advantages of cascoding by comparing the performance of a cascode amplifier with that of a common-source amplifier in two cases:
(a) The resistance of the signal source is significant, Rsig = 10 k. (b) Rsig is negligibly small.
Assume all MOSFETs have gm = 1.25mA/V, ro = 20k, Cgs = 20fF, Cgd =5fF, Cdb = 5 fF, and CL (excluding Cd b ) = 10 fF. For case (a), let RL = ro = 20 k for both amplifiers. For case (b), let RL = ro = 20 k for the CS amplifier and RL = Ro for the cascode amplifier. For all cases, determine Av , fH, and ft.
Solution
(a) For the CS amplifier:
To obtain τ H
where
Thus,
For the cascode amplifier:
A0 =gmro =1.25×20=25V/V
Av =−gm RL∥ro =−gm ro∥ro = −1A0 = −12.5 V/V
2
we use Eq. (10.87) and note that R = R′ and that here C sig sig
does not include C τ =C R +C (1+g R′)R +R′+C +C R′
RL′ =ro∥RL =ro∥ro =10k
τH =20×10+5[(1+12.5)10+10]+(10+5)10
=200+725+150=1075ps
, thus
db
H gssig gd mLsig L L dbL
f= 1 =148MHz H 2π × 1075 × 10−12
Ro =2ro + gmro ro =(2×20)+(25×20)=540k
Av =−gm Ro∥RL
= −1.25(540 ∥ 20) = −24.1 V/V
Rin2 =ro+RL =ro+ro = 2 = 2 =1.6k gmro gmro gm 1.25
Rd1 = ro ∥Rin2 = 20∥1.6 = 1.48 k
L
f =A f =12.5×148=1.85GHz tvH
758
Chapter 10 Frequency Response
Example 10.10 continued Using Eq. (10.109),
τH =Rsig Cgs1 +Cgd1 1+gm1Rd1
+Rd1 Cgd1 +Cdb1 +Cgs2
+ RL∥Ro CL+Cdb2+Cgd2
= 10[20 + 5(1 + 1.25 × 1.48)] +1.48(5+5+20) +(20∥540)(10+5+5)
= 342.5 + 44.4 + 385.7 = 772.6 ps
f= 1 =206MHz H 2π × 772.6 × 10−12
ft =24.1×206=4.96GHz
Thus cascoding has increased both the dc gain and the 3-dB frequency, with the combined effect being an increaseofft byafactorof2.7.
(b) For the CS amplifier:
Av =−12.5V/V
τ =C +C +C R′
H gd L db L
= (5 + 10 + 5)10 = 200 ps
f= 1 =796MHz
For the cascode amplifier:
RL =Ro =540k
Av =−gm Ro∥RL
= −1.25(540 ∥ 540) = −337.5 V/V
Rin2 = ro +RL = 20+540 =22.4k gm ro 1.25 × 20
Rd1 = ro1 ∥Rin2 = 20∥22.4 = 10.6 k
H 2π ×200×10−12
ft =12.5×796=9.95GHz
10.5 High-Frequency Response of the Common-Gate and Cascode Amplifiers 759
τH =Rd1 Cgd1 +Cdb1 +Cgs2 + RL∥Ro CL +Cgd2 +Cdb2 =10.6(5+5+20)+(540∥540)(10+5+5) =318+5400=5718ps
f= 1 =27.8MHz H 2π × 5718 × 10−12
ft =337.5×27.8=9.39GHz
Thus cascoding increases the dc gain from 12.5 V/V to 337.5 V/V. This increase has been obtained at the costofadecreaseinfH byapproximatelythesamefactor,resultingintheunity-gainfrequency(which,in this case, is equal to the gain–bandwidth product) remaining nearly constant.
EXERCISE
10.21 In this exercise we wish to contrast the gain and bandwidth of a CS amplifier and a cascode amplifier.AssumethatbotharefedwithalargesourceresistanceRsig thateffectivelydeterminesthe high-frequencyresponse.Thus,neglectcomponentsofτH thatdonotincludeRsig.Alsoassumethat all transistors are operated at the same conditions and thus corresponding small-signal parameters are equal. Also, both amplifiers have equal RL = ro , and gm ro = 40.
(a) Find the ratio of the low-frequency gain of the cascode amplifier to that of the CS amplifier. (b) For the case of Cgd = 0.25Cgs, find the ratio of fH of the cascode to that of the CS amplifier. (c) Use (a) and (b) to find the ratio of ft of the cascode to that of the CS.
Ans. 2; 3.6; 7.2
Conclusion The MOS cascode amplifier is a versatile circuit that, depending on the application at hand, can be designed to provide either higher dc gain, larger bandwidth, or a combination of both, than the CS amplifier.
10.5.3 High-Frequency Response of the Bipolar Cascode Amplifier
The analysis method studied in the previous section can be directly applied to the BJT cascode amplifier. Figure 10.30 presents the circuits and the formulas for determining the high-frequency response of the bipolar cascode. Note that some of these formulas rely on the study of the bipolar cascode in Section 8.5.6.
760 Chapter 10
Frequency Response
C2
Vo Rsig r 1 (rx1 Rsig) R1 Rsig
C2
Q R C C R r r ro2 RL
2 L Lcs2 c1o1e2ro2RL(21)
C 2
R 1 Rsig(1 gm1Rc1) Rc1 Ro 2ro2
(Ccs1 C 2)Rc1 Ccs2 C 2)(RL Ro)
r
M r rx Rsig m o L
C1
H C 1R 1
C 1R 1 (CL
Rsig
C1 f1
H 2H
Q1 Ccs1 A
g(r R)
Vsig V1 C1
Figure10.30 DeterminingthefrequencyresponseoftheBJTcascodeamplifier.Notethatinadditiontothe BJT capacitances Cπ and Cμ, the capacitance between the collector and the substrate Ccs for each transistor are included.
EXERCISE
10.22 The objective of this exercise is to evaluate the effect of cascoding on the performance of the CE
amplifier of Exercise 10.19. The specifications are as follows: I = 1 mA, β = 200, ro = 130 k,
Cπ =16pF,Cμ =0.3 pF,rx =200,Ccs1 =Ccs2 =0,CL =5 pF,Rsig =36k,RL =50k.Find
Rin, A0, Ro1, Rin2, Ro, AM, fH, and ft. Compare AM, fH, and ft with the corresponding values obtained
in Exercise 10.19 for the CE amplifier. What should C be reduced to in order to have f = 1 MHz? L H
Ans. 5.2 k; 5200 V/V; 130 k; 35 ; 26 M; −242 V/V; 470 kHz; 113.8 MHz. AM has increased from 175 V/V to 248 V/V; fH has increased from 73.5 kHz to 470 kHz; ft has increased from 12.9 MHzto113.8MHz.CL mustbereducedto1.6pF.
10.6 High-Frequency Response of the Source and Emitter Followers
In this section, we study the high-frequency response of two important circuit building blocks: the source follower and the emitter follower. Both have a midband voltage gain that is less than but close to unity. Their advantage lies in their high input resistance and low output resistance. Thus, they find application as the output stage of a multistage amplifier and as a voltage buffer. As will be seen shortly, these voltage followers have another important advantage, namely, a wide bandwidth.
Analysis of the high-frequency response of the source and emitter followers is somewhat involved. This is because the follower has two high-frequency poles that can be close to each
1. A loop equation at the input yields
Vsig =IiRsig +Vg
where Vg can be expressed as
Thus,
2. A node equation at G provides
Vg =Vgs +Vo
Vsig = IiRsig +Vgs +Vo
(10.114)
(10.115)
Ii =sCgdVg +sCgsVgs =sCgd(Vgs +Vo)+sCgsVgs
which can be substituted into Eq. (10.114) to obtain
Vsig =[1+s(Cgs +Cgd)Rsig]Vgs +[1+sCgdRsig]Vo
10.6 High-Frequency Response of the Source and Emitter Followers 761
other on the negative real axis of the s plane. Furthermore, in many cases, the poles can become complex. As a result, the method of open-circuit time constants cannot be used to determinefH ofthefollowersexceptinspecialcircumstances.Ourapproach,therefore,will be to analyze the follower circuit to determine its gain Vo/Vsig as a function of frequency and then use it to determine fH . Although the analysis is somewhat lengthy, the results can be applied easily. In the following we shall do the analysis of the source follower in detail. Then, because of similarity, the results for the emitter follower will be given without proof.
10.6.1 The Source-Follower Case
Figure 10.31(a) shows a source follower without the biasing arrangement. The follower is driven by a signal source (Vsig, Rsig) and is loaded with a resistance RL and, for generality, a capacitance CL . Replacing the MOSFET with its hybrid-π equivalent-circuit model results in the equivalent circuit shown in Fig. 10.31(b). Here, we have included the body-effect generator gmbVbs because it plays an important role in determining the source-follower gain. Also, we are assuming that whatever capacitances exist between the MOSFET source and ground, such as Csb of Fig. 10.12(a), have been lumped into CL.
Notingthatthedrainterminalisgrounded,weseethatCgd infactappearsacrosstheinput terminals of the source follower. Also, ro is in parallel with RL and can be combined with it. Finally, we observe that since the body terminal B is connected to ground, the voltage Vbs appears across the controlled source gmbVbs. Thus we can utilize the source-absorption theorem (see Appendix D) to replace the controlled source with a resistance 1/gmb . Since the latter appears between source and ground, it is in parallel with RL and can be combined with it.
Utilizing the above observations, we obtain the simplified equivalent circuit shown in Fig. 10.31(c) where
RL′ =RL∥ro∥ 1 (10.113) gmb
Obtaining the Transfer Function Vo(s)/Vsig(s) Analysis of the equivalent circuit in Fig. 10.31(c) to determine the transfer function Vo(s)/Vsig(s) proceeds as follows.
762 Chapter 10
Frequency Response
Rsig
Vsig
Rsig
VDD
RL
Vo
Cgd
CL
(a)
Vgs
GD
V sig
Cgs
gmVgs
gmbVbs ro
S
CL Vbs Vo B
(b)
RL
Ii
V Cgd sig
sCgs Vgs
Rsig
G
Vg Vgs
Cgs gmVgs
S
RL CL Vo
R = R r 1 L Logmb
(c)
Figure 10.31 (a) A directly coupled source follower without the bias detail; (b) high-frequency equivalent circuit of the source follower; (c) a simplified version of the equivalent circuit.
3. A node equation at S gives
(gm +sCgs)Vgs = RL′ +sCL Vo
1 which can be used to express Vgs in terms of Vo as
10.6 High-Frequency Response of the Source and Emitter Followers 763
1 1 + sCL RL′
Vgs = gmRL′ 1+s(Cgs/gm)Vo (10.116)
Substituting this expression of Vgs into Eq. (10.115) results in an equation containing only Vo and Vsig; this equation can be manipulated to obtain the source-follower transfer function in the form s
V1+ω o (s)=A Z
AM =
(10.117)
(10.118)
(10.119) (10.120) (10.121)
where
R L′ g m R L′
V M 1+b s2 +b s2 sig 12
1 =g R′ +1 RL′+ mL
gm
ωZ =gm/Cgs
CC+C b1=Cgd+gs Rsig+gs LRL′
gmRL′ +1 gmRL′ +1 b2 = (Cgs +Cgd)CL +CgsCgd RsigRL′
g m R L′ + 1
Analysis of the Source-Follower Transfer Function We now make a number of observations on the transfer function in Eq. (10.117), which describes the gain of the source follower at high frequencies:
1. Since the source follower in Fig. 10.31(a) is directly coupled, the gain at dc is equal to AM . This correlates with Eq. (10.117) as
AM =Vo/Vsig|s=0
2. Although the equivalent circuit of Fig. 10.31(c) has three capacitors, the transfer function is of second order. This is because the three capacitors form a continuous loop.
3. The two transmission zeros can be found from Eq. (10.117) as the values of s for which Vo /Vsig = 0. From Eq. (10.117), we see that Vo /Vsig approaches 0 as s approaches ∞. Thus one transmission zero is at s = ∞. Physically, this zero is a result of Cgd , which appears across the input terminals, becoming a short circuit at infinite frequency and thus making Vo = 0. From the numerator of Eq. (10.117) we see that the other transmissionzeroisats=−ωZ whereωZ isgivenbyEq.(10.119).WenotethatωZ isslightlyhigherthantheunity-gainfrequencyωT oftheMOSFET[Eq.(10.29)],
ωT = gm (10.122) Cgs +Cgd
764 Chapter 10
Frequency Response
Thus the finite transmission zero is at such a high frequency that its effect on the
frequency response of the follower is negligibly small.
4. The two poles of the source follower can be found as the roots of the denominator
polynomial(1+b1s+b2s2).Ifthepolesarereal,theirfrequencies,sayωP1 andωP2, can be found from
s s
1+b1s+b2s2 = 1+ ω 1+ ω (10.123)
P1 P2
Now if ωP2 ≫ ωP1 (at least four times larger), a dominant pole exists with frequency
ωP1 and the 3-dB frequency fH is given by
fH ≃ fP1 ≃ 1 (10.124)
2π b1
Here we remind the reader that b1 is also τH , the effective high-frequency time constant evaluated in the method of open-circuit time constants.
5. If the poles are real but none is dominant, the 3-dB frequency can be determined √
analytically from the transfer function as the frequency at which | Vo /Vsig |= AM / 2. An approximate value can be obtained using the formula in Eq. (10.77),
fH ≃1 1 + 1 − 2 (10.125) f2f2f2
6. If the poles are complex, they are best described in terms of their frequency ω0 and Q-factor, where
2 1ss2
1+b1s+b2s =1+Qω +ω2 (10.126)
00
and for complex poles, Q > 0.5. Figure 10.32(a) provides a geometrical interpretation of ω0 and Q. From the study of second-order network responses in Chapter 17, it will be seen that the response of the source follower shows no peaking for Q ≤ 0.707. The boundary case corresponding to Q = 0.707 (poles at 45◦ angles) results in what is known as a maximally flat response for which f3dB = f0. Figure 10.32(b) shows a number of possible responses obtained for various values of Q. In terms of the component values of the source follower,
P1 P2 Z
1
ω0 = b =
(10.127)
(10.128)
2
g m R L′ + 1
RsigRL′ [(Cgs +Cgd)CL +CgsCgd]
b
Q=
b1
2 =
g R′ +1[(C +C )C +C C ]R R′ m L gs gd L gs gd sig L
[Cgs +Cgd(gmRL′ +1)]Rsig +(Cgs +CL)RL′
(a)
Q 0.5
Q 0.3
Q1 Q
0.707 (maximally flat response)
12 dB/octave
v (log scale)
10.6 High-Frequency Response of the Source and Emitter Followers 765
0
(b)
Figure 10.32 (a) A pair of complex-conjugate poles with the definition of ωo and Q indicated. (b) Magnitude response of a source (or emitter) follower for different values of the parameter Q. Note that the response is normalized relative to AM .
Example 10.11
Asourcefolloweroperatedatgm =2mA/Vandro =20kisfedwithasignalsourceforwhichRsig =10k and is loaded in a resistance RL = 20k. The MOSFET has Cgs = 20 fF, Cgd = 5 fF, and gmb = χgm where χ = 0.2, and the total capacitance at the output CL = 15 fF. Determine AM , fT , fZ , Q, fP1, fP2, and f3dB.
Solution
RL′ =RL∥ro∥ 1 gmb
= 20∥20∥ 1 = 20∥20∥2.5 = 2k 0.2×2
Normalized gain (dB)
766
Chapter 10 Frequency Response
Example 10.11 continued
RL′ 2 AM= 1 =
1 =0.8V/V RL′+g 2+2
m fT= gm
2π(Cgs +Cgd)
= 2×10−3 2π(20+5)×10−15
= 12.7 GHz
gm 2 × 10−3
fZ = 2πC = 2π×20×10−15 =15.9GHz gs
To evaluate Q we substitute the given component values into Eq. (10.128), Q=0.42
Thus the poles are real. Their frequencies can be obtained by finding the roots of the polynomial (1 + b1s + b2s2), where
and Thus,
b1 =τH =104ps
b2 =1.9×10−21
fP1 = 1.98 GHz
fP2 = 6.73 GHz
Since fP2 /fP1 = 3.4 < 4, no dominant pole exists. An approximate value for fH can be obtained as
f =1 1 + 1 − 2 =1.93GHz H f2f2f2
P1 P2 Z
The exact value of fH can be found from the transfer function as 1.86 GHz, which is not much different
from the approximate value.
EXERCISES
10.23 Recalling that τH = b1, use the expression for b1 in Eq. (10.120) to find expressions for the three resistances Rgs, Rgd, and RCL for the source follower.
Rsig +RL′ RL′ Ans. Rgs =g R′ +1;Rgd =Rsig;RCL =g R′ +1
mL mL
10.24 In Example 10.11, even though we found that a dominant pole does not exist, use the method of open-circuit time constants to obtain an estimate for fH . (Hint: Recall that τH = b1 .)
Ans. fH = 1.53 GHz; about 18% lower than the exact value of 1.86 GHz; still not a bad estimate!
10.6 High-Frequency Response of the Source and Emitter Followers 767 10.6.2 The Emitter-Follower Case
Figure 10.33 provides the results for the case of the emitter follower. The analysis here is a little more complicated because of the finite β of the BJT.
VCC
I
Rsig
B
rx B
Vr
C
C
Rsig
C
gmV
ro
Vsig
Vsig Vo
CL
E
RL
RL CL Vo
(a)
B
(b)
1 + (s/ωZ ) Vsig(s) =AM 1+b1s+b2s2
Vo(s)
Rsig
RL′ AM=R′+re+R′ /(β+1)
L sig
V CVrC fZ=1/2πCπre
sig
gV′ R′
m
b1 =
RRr RL CL rerπ
rπ L
Cπ+Cμ 1+RL R′ + Cπ+CL 1+ sig R′
re sig
′ R′ 1+RL+ sig
sig sig
RL RL ro
x
Vo
(Cπ +Cμ)CL +CπCμ R′ R′
L sig
b2=
′ R′ 1+RL+ sig
re rπ (d)
(c)
Figure 10.33 (a) Emitter follower. (b) High-frequency equivalent circuit. (c) Simplified equivalent circuit. (d) Transfer function.
EXERCISE
10.25 ForanemitterfollowerbiasedatIC =1mAandhavingRsig =RL =1k,ro =100k,β=100, Cμ =2pF, CL =0, rx =0, and fT =400MHz, find the low-frequency gain AM, fZ, fP1, fP2, and an estimate for fH .
Ans. 0.97 V/V; 458 MHz; 67.2 MHz; 562 MHz; 67.2 MHz
768 Chapter 10
Frequency Response
10.7 High-Frequency Response of Differential Amplifiers
In this section we study the high-frequency response of the differential amplifier. We will consider the variation with frequency of both the differential gain and the common-mode gain and hence of the CMRR. We will rely heavily on the study of frequency response of single-ended amplifiers presented in the sections above. Also, we will consider MOS circuits only; the bipolar case is a straightforward extension, as we saw above on a number of occasions.
10.7.1 Analysis of the Resistively Loaded MOS Amplifier
We begin with the basic, resistively loaded MOS differential pair shown in Fig. 10.34(a). Note that we have explicitly shown transistor QS that supplies the bias current I. Although we are showing a dc bias voltage VBIAS at its gate, usually QS is part of a current mirror. This detail, however, is of no consequence to our present needs. Most importantly, we are interested in the total impedance between node S and ground, ZSS , because this impedance plays a significant role in determining the common-mode gain and the CMRR of the differential amplifier.ResistanceRSS issimplytheoutputresistanceofcurrentsourceQS.CapacitanceCSS is the total capacitance between node S and ground and includes Cdb and Cgd of QS, as well as Csb1 and Csb2. This capacitance can be significant, especially if wide transistors are used for QS, Q1, and Q2.
The differential half-circuit shown in Fig. 10.34(b) can be used to determine the frequency dependence of the differential gain Vo/Vid. Indeed the gain function Ad(s) of the differential
VDD
RD RD
V RD o
Q1 Q2 S
I
ZSS RSS CSS
Vocm
RD
Q1
Vicm
QS VBIAS
VSS (a)
Vo2
CSS
Vid2
2R
SS 2
(c)
Figure 10.34 (a) A resistively loaded MOS differential pair; the transistor supplying the bias current is explicitly shown. It is assumed that the total impedance between node S and ground, ZSS , consists of a resistance RSS inparallelwithacapacitanceCSS.(b)Differentialhalf-circuit.(c)Common-modehalf-circuit.
(b)
10.7 High-Frequency Response of Differential Amplifiers 769
amplifier will be identical to the transfer function of this common-source amplifier.9 We studied the frequency response of the common-source amplifier at great length in Sections 10.3 and 10.4 and will not repeat this material here.
EXERCISE
10.26 AMOSFETdifferentialamplifiersuchasthatinFig.10.34(a)isbiasedwithacurrentI=0.8mA. ThetransistorsQ1 andQ2 haveW/L=100,kn′ =0.2mA/V2,VA =20V,Cgs =50fF,Cgd =10fF, and Cd b = 10 fF. The drain resistors are 5 k each. Also, there is a 100-fF capacitive load between each drain and ground.
(a) Find VOV and gm for each transistor.
(b) FindthedifferentialgainAd.
(c) If the input signal source has a small resistance Rsig and thus the frequency response is determined
primarily by the output pole, estimate the 3-dB frequency fH . [Hint: Refer to Section 10.3.4 and
specifically to Eq. (10.67).]
(d) If,inadifferentsituation,theamplifierisfedsymmetricallywithasignalsourceof20kresistance
(i.e., 10 k in series with each gate terminal), use the open-circuit time-constants method to estimate
fH . [Hint: Refer to Section 10.4.4 and specifically to Eq. (10.87).] Ans. (a) 0.2 V, 4 mA/V; (b) 18.2 V/V; (c) 292 MHz; (d) 53.7 MHz
The common-mode half-circuit is shown in Fig. 10.34(c). Although this circuit has other capacitances,namely,Cgs,Cgd,andCdb ofthetransistorinadditiontootherstraycapacitances, we have chosen to show only CSS/2. This is because (CSS/2) together with (2RSS) form a real-axis zero in the common-mode gain function at a frequency much lower than those of the other poles and zeros of the circuit. This zero then dominates the frequency dependence of Acm and CMRR.
If the output of the differential amplifier is taken single-endedly, then the common-mode gain of interest is Vocm /Vicm . More typically, the output is taken differentially. Nevertheless, as wehaveseeninSection9.3,Vocm/Vicm stillplaysamajorroleindeterminingthecommon-mode gain. To be specific, consider what happens when the output is taken differentially and there is a mismatch RD between the two drain resistances. The resulting common-mode gain was found in Section 9.3 to be (Eq. 9.80)
R R
Acm =− D D (10.129)
2RSS RD
which is simply the product of Vocm /Vicm and the per-unit mismatch (RD /RD ). Similar expressions can be found for the effects of other circuit mismatches. The important point to note is that the factor RD/2RSS is always present in these expressions. Thus, the frequency dependence of Acm can be obtained by simply replacing RSS by ZSS in this factor. Doing so for
9Here we are not showing the resistance of the signal source Rsig, which, of course, must be included in the frequency-response analysis, as we have done in the case of the CS amplifier. See Exercise 10.26.
770 Chapter 10
Frequency Response
the expression in Eq. (10.129) gives
R R Acm(s)=− D D
2ZSS RD
1 R
=−RDY 2D R SS
D
1 R1 =− R D
+sC 2D R R SS
frequency ωZ ,
or in hertz,
ωZ = 1 CSS RSS
fZ = ωZ = 1
2π 2π CSS RSS
(10.131)
(10.132)
D SS R R
=− D D (1+sCSSRSS) 2RSS RD
(10.130) from which we see that Acm acquires a zero on the negative real axis of the s plane with
As mentioned above, usually fZ is much lower than the frequencies of the other poles and zeros. As a result, the common-mode gain increases at the rate of +6 dB/octave (20dB/decade) starting at a relatively low frequency, as indicated in Fig.10.35(a). Of course, Acm drops off at high frequencies because of the other poles of the common-mode half-circuit.Itis,however,fZ thatissignificant,foritisthefrequencyatwhichtheCMRRof the differential amplifier begins to decrease, as indicated in Fig. 10.35(c). Note that if both Ad and Acm are expressed and plotted in dB, then CMRR in dB is simply the difference between Ad andAcm.
Although in the foregoing we considered only the common-mode gain resulting from an RD mismatch, the results apply to the common-mode gain resulting from any other mismatch. For instance, it applies equally well to the case of a gm mismatch, modifying Eq. (9.87) by replacingRSS byZSS,andsoon.
Before leaving this section, it is interesting to point out an important trade-off found in the design of the current-source transistor QS: In order to operate this current source with a small VDS (to conserve the already low VDD), we desire to operate the transistor at a low overdrive voltage VOV . For a given value of the current I, however, this means using a large W/L ratio (i.e., a wide transistor). This in turn increases CSS and hence lowers fZ with the result that the CMRR deteriorates (i.e., decreases) at a relatively low frequency. Thus there is a trade-off between the need to reduce the dc voltage across QS and the need to keep the CMRR reasonably high at higher frequencies.
To appreciate the need for high CMRR at higher frequencies, consider the situation illustrated in Fig. 10.36: We show two stages of a differential amplifier whose power-supply voltage VDD is corrupted with high-frequency noise. Since the quiescent voltage at each of the drains of Q1 and Q2 is [VDD −(I/2)RD] we see that vD1 and vD2 will have the same high-frequency noise as VDD. This high-frequency noise then constitutes a common-mode input signal to the second differential stage, formed by Q3 and Q4. If the second differential stage is perfectly matched, its differential output voltage Vo should be free of high-frequency
Acm (dB)
10.7 High-Frequency Response of Differential Amplifiers 771
2CSS RSS
(a)
f (log scale)
Ad (dB)
CMRR (dB)
1
(b)
f (log scale)
(c)
Figure 10.35 Variation of (a) common-mode gain, (b) differential gain, and (c) common-mode rejection ratio with frequency.
noise. However, in practice there is no such thing as perfect matching, and the second stage will have a finite common-mode gain. Furthermore, because of the zero formed by RSS and CSS of the second stage, the common-mode gain will increase with frequency, causing some of the noise to make its way to Vo. With careful design, this undesirable component of Vo can be kept small.
f (log scale)
772 Chapter 10
Frequency Response
VDD
VDD 2IRD
VDD
RD RD VDD 2IRD RD RD
I RSSCSS I
Q3
Q4
Figure 10.36 The second stage in a differential amplifier, which is relied on to suppress high-frequency noise injected by the power supply of the first stage, and therefore must maintain a high CMRR at higher frequencies.
EXERCISE
10.27 The differential amplifier specified in Exercise 10.26 has RSS = 75 k and CSS = 0.4 pF. Find the 3-dB frequency of the CMRR.
Ans. 5.3 MHz
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Radio-frequency identification (RFID) tags are increasingly important elements in our daily lives. These tiny devices embody a wide range of electronic techniques: linear, digital, radio, power, and signaling, all at very low power levels. They are activated (and powered) by an external interrogation signal that can be located a few feet away. Once activated, they respond with the requested data, most often simply an identifying number. Applications are incredibly diverse, ranging from automobile key fobs to tags that permit the recovery of lost pets.
10.7.2 Analysis of the Current-Mirror-Loaded MOS Amplifier
We next consider the frequency response of the current-mirror-loaded MOS differential-pair circuit studied in Section 9.5. The circuit is shown in Fig. 10.37(a) with two capacitances indicated: Cm, which is the total capacitance at the input node of the current mirror, and CL, which is the total capacitance at the output node. Capacitance Cm is mainly formed by Cgs3
V o
Q1 Q2
10.7
High-Frequency Response of Differential Amplifiers 773
1QQ gm33 4
Vg3
I g Vid d1 m2
Q1
Q2
Id4
I g Vid
Vid2
0V 0 fP2fZ f
Cm
Vid2
d2 m2 L
Io
|Gm| C gm
12 g m
(a) (b) Figure 10.37 (a) Frequency–response analysis of the active-loaded MOS differential amplifier. (b) The
overall transconductance Gm as a function of frequency. and Cgs4 but also includes Cgd1, Cdb1, and Cdb3,
Cm =Cgd1 +Cdb1 +Cdb3 +Cgs3 +Cgs4 (10.133) Capacitance CL includes Cgd2, Cdb2, Cdb4, and Cgd4 as well as an actual load capacitance and/or
the input capacitance of a subsequent stage (Cx ),
CL =Cgd2 +Cdb2 +Cgd4 +Cdb4 +Cx (10.134)
These two capacitances primarily determine the dependence of the differential gain of this amplifier on frequency.
The overall voltage gain of the differential amplifier will be determined by multiplying its short-circuit transconductance Gm by the total impedance at the output mode. As indicated inFig.10.37(a)theinputdifferentialsignalVid isappliedinabalancedfashionandtheoutput node is short-circuited to ground in order to determine the transconductance Gm ; Gm ≡ Io /Vid . Obviously, because of the output short circuit, CL will have no effect on Gm. Transistor Q1 will conduct a drain current signal of gm Vid /2, which, neglecting ro1 , flows through the parallel combination of the diode-connected transistor Q3 and Cm. Neglecting the resistances roi and ro3, which are much larger than the resistance (1/gm3) of Q3 we have
Vg3 =− gmVid/2 gm3 +sCm
1+sCm gm3
(10.135)
(10.136)
In response to Vg3, transistor Q4 conducts a drain current Id4, Id4 =−gm4Vg3 =gm4gmVid/2
Since gm3 = gm4, this equation reduces to
gm3 +sCm Id4 = gmVid/2
774 Chapter 10
Frequency Response
Now, at the output node the total output current that flows through the short circuit is Io =Id4 +Id2
We can now obtain Gm as
= gmVid/2 +gmVid/2 1+sCm
gm3
1+s Cm G ≡ Io =g 2gm3
(10.137)
(10.138)
m V m Cm
id 1+s gm3
Thus, as expected, the low-frequency value of Gm is equal to gm of Q1 and Q2. At high frequencies, Gm acquires a pole and a zero, the frequencies of which are
fP2 = gm3 2π Cm
Cgs2 +Cgs4 =2Cgs,wealsohave
fP2 = gm3 ≃ gm3 ≃fT/2
and
(10.139)
and
fZ = 2gm3 2π Cm
(10.140) That is, the zero frequency is twice that of the pole. Since Cm is approximately equal to
2πCm 2π(2Cgs)
(10.141)
(10.142)
fZ ≃fT
where fT is the unity-gain frequency of the MOSFET Q3. Thus, the mirror pole and zero occur at very high frequencies. Nevertheless, their effect can be significant.
Figure 10.37(b) shows a sketch of the magnitude of Gm versus frequency. It is interesting and useful to observe that the path of the signal current produced by Q1 has a transfer function different from that of the signal current produced by Q2 . It is the first signal that encounters Cm and experiences the mirror pole. This observation leads to an interesting view of the effect of Cm on the overall transconductance Gm of the differential amplifier. As we learned in Section 9.5, at low frequencies Id1 is replicated by the mirror Q3−Q4 in the drain of Q4 as Id4, which adds to Id2 to provide a factor-of-2 increase in Gm (thus making Gm equal to gm, which is double the value available without the current mirror). Now, at high frequencies Cm acts as a short circuit causing Vg3 to be zero, and hence Id4 will be zero, that is, destroying the action of the current mirror and reducing Gm to gm /2, as borne out by the sketch in Fig. 10.37(b).
10.7 High-FrequencyResponseofDifferentialAmplifiers 775 Having determined the short-circuit output current Io, we now multiply it by the total
impedance between the output node and ground to determine the output voltage Vo, V=I1
o
o 1+sCL Ro
=GV Ro
m id1+sCLRo
Ro =ro2∥ro4 ⎛C⎞
where
Thus,
(10.143)
(10.144)
1+sm Vo =(gR)⎜ 2gm3⎟ 1
V m o ⎝1+sCm ⎠ 1+sCR id Lo
gm3
Thus, in addition to the pole and zero of Gm, the gain of the differential amplifier will have a
pole with frequency fP1,
fP1 = 1 (10.145) 2πCLRo
This, of course, is entirely expected, and in fact this output pole is often dominant, especially when a large load capacitance is present.
Example 10.12
Consider an active-loaded MOS differential amplifier of the type shown in Fig. 10.37(a). Assume
that for all transistors, W/L = 7.2 μm/0.36 μm, Cgs = 20 fF, Cgd = 5 fF, and Cdb = 5 fF. Also, let
μ C =387μA/V2,μ C =86μA/V2,V′ =5V/μm,and|V′ |=6V/μm.ThebiascurrentI=0.2mA, n ox p ox An Ap
and the bias current source has an output resistance RSS = 25 k and an output capacitance CSS = 0.2 pF. In addition to the capacitances introduced by the transistors at the output node, there is a capacitance Cx of 25 fF. It is required to determine the low-frequency values of Ad , Acm , and CMRR. It is also required to findthepolesandzeroofAd andthedominantpoleofCMRR.
Solution
SinceI=0.2mA,eachofthefourtransistorsisoperatingatabiascurrentof100μA.Thus,forQ1 andQ2, 100=1×387× 7.2 ×V2
which leads to
2 0.36 OV VOV =0.16V
776
Chapter 10 Frequency Response
Example 10.12 continued Thus,
For Q3 and Q4 we have Thus,
and
gm =gm1 =gm2 = 2×0.1 =1.25mA/V 0.16
ro1 =ro2 = 5×0.36 =18k 0.1
100=1×86× 7.2V2
2 0.36 OV3,4
V = 0.34 V OV 3,4
gm3 =gm4 = 2×0.1 =0.6mA/V 0.34
ro3 =ro4 = 6×0.36 =21.6k 0.1
The low-frequency value of the differential gain can be determined from
Ad =gm ro2∥ro4
= 1.25(18 ∥ 21.6) = 12.3 V/V
The low-frequency value of the common-mode gain can be determined from Eq. (9.157) as Acm=− 1
2gm3 RSS
=− 1 =−0.033V/V
2×0.6×25
The low-frequency value of the CMRR can now be determined as
A CMRR= d=
To determine the poles and zero of Ad we first compute the values of the two pertinent capacitances Cm and CL . Using Eq. (10.133),
Cm =Cgd1 +Cdb1 +Cdb3 +Cgs3 +Cgs4 =5+5+5+20+20=55 fF
12.3 0.033
=369
or,
Acm 20log369=51.3dB
CapacitanceCL isfoundusingEq.(10.134)as
CL =Cgd2 +Cdb2 +Cgd4 +Cdb4 +Cx
=5+5+5+5+25=45 fF Now,thepolesandzeroofAd canbefoundfromEqs.(10.145),(10.139),and(10.140)as
fP1= 1 2πCLRo
1 =2π×Cr ∥r
L o2 o4 =1
10.7 High-Frequency Response of Differential Amplifiers 777
2π × 45 × 10−15 (18 ∥ 21.6)103 = 360 MHz
gm3 0.6 × 10−3
fP2 = 2πC = 2π×55×10−15 =1.74GHz
m
fZ =2fP2 =3.5GHz
Thus the dominant pole is that produced by CL at the output node. As expected, the pole and zero of the mirror are at much higher frequencies.
The dominant pole of the CMRR is at the location of the common-mode-gain zero introduced by CSS and RSS , that is,
fZ= 1
2π CSS RSS
=1
2π ×0.2×10−12 ×25×103
= 31.8 MHz
Thus, the CMRR begins to decrease at 31.8 MHz, which is much lower than fP1.
EXERCISE
10.28 Abipolarcurrent-mirror-loadeddifferentialamplifierisbiasedwithacurrentsourceI=1mA.The transistors are specified to have V = 100 V. The total capacitance at the output node is 2 pF. Find
A
the dc value, and the frequency of the dominant high-frequency pole, of the differential voltage gain.
Ans. 2000 V/V; 0.8 MHz
778 Chapter 10
Frequency Response
10.8 Other Wideband Amplifier Configurations
Thus far, we have studied one wideband amplifier configuration: the cascode amplifier (Section 10.5). Cascoding can, of course, be applied to differential amplifiers to obtain wideband differential amplification. In this section we discuss a number of other circuit configurations that are capable of achieving wide bandwidths.
10.8.1 Obtaining Wideband Amplification by Source and Emitter Degeneration
As we discussed in Chapter 7, adding a resistance in the source (emitter) lead of a CS (CE) amplifier can result in a number of performance improvements at the expense of a reduction in voltage gain. Extension of the amplifier bandwidth, which is the topic of interest to us in this section, is among those improvements.
Figure 10.38(a) shows a common-source amplifier with a source-degeneration resistance Rs . As indicated in Fig. 10.38(b), the output of the amplifier can be modeled at low frequencies by a controlled current-source GmVi and an output resistance Ro, where, for the usual case of gm ro ≫ 1, the transconductance Gm can be shown to be given by
Gm ≃ gm (10.146) 1+gmRs
and the output resistance is given by Eq. (8.61), that is,
Ro ≃ro(1+gmRs) (10.147)
Thus, source degeneration reduces the transconductance and increases the output resistance by the same factor, (1 + gm Rs ). The low-frequency voltage gain can be obtained as
where
AM = Vo =−Gm(Ro∥RL)=−GmRL′ (10.148) Vsig
RL′ =RL∥Ro (10.149)
Let’s now consider the high-frequency response of the source-degenerated amplifier. Figure 10.38(c) shows the amplifier, indicating the capacitances Cgs and Cgd. A capacitance CL that includes the MOSFET capacitance Cdb is also shown at the output. The method of open-circuit time constants can be employed to obtain an estimate of the 3-dB frequency fH . Toward that end, we show in Fig. 10.38(d) the circuit for determining Rgd , which is the resistance seen by Cgd . Straightforward analysis yields
Rgd =Rsig(1+GmRL′)+RL′ (10.150)
Note that the expression for Rgd in Eq. (10.150) is similar to that for the CS amplifier in Eq. (10.85) with gm replaced with Gm , and RL′ = ro ∥ RL of the CS replaced with RL′ = Ro ∥ RL for the source-degenerated case.
10.8
Other Wideband Amplifier Configurations 779
Rsig
Vi
RL
Vo
Vsig
Rsig
Rs
(a)
Vo
Cgd
RL CL
GmVi
Cgs
Vsig
Ix D
Ro
RL Vo
Rs
D
(b)
(c)
Vx Rgd
R RL RoRL
G
Rsig
gd
G GmVi Rsig Vi
Rs
RL RL Rsig(1 GmRL)
Rgd Vx Ix
(d)
Figure10.38 (a)TheCSamplifiercircuit,withasourceresistanceRs.(b)Equivalent-circuitrepresentation of the amplifier output. (c) The circuit prepared for frequency-response analysis. (d) Determining the resistance Rgd seen by the capacitance Cgd .
780 Chapter 10
Frequency Response
The formula for RCL can be seen to be simply
RCL =RL∥Ro =RL′ (10.151)
The formula for Rgs is the most difficult to derive, and the derivation should be performed with the hybrid-π model explicitly utilized. Straightforward, though somewhat tedious, circuit analysis yields (for gm ro ≫ 1),
Rgs ≃
Rsig +Rs +RsigRs/(ro +RL) r
1+gR o
m s ro+RL
(10.152)
(10.153)
Next we compute τH , and use it to determine fH ,
τH =CgsRgs +CgdRgd +CLRCL fH= 1
2π τH
It is interesting and instructive to consider the case when Rsig is relatively large: The frequency response will be dominated by the Miller multiplication of Cgd. Another way for sayingthisisthatCgdRgd willbethelargestofthethreeopen-circuittimeconstantsthatmake upτH inEq.(10.153),enablingustoapproximateτH as
andcorrespondinglytoobtainfH as
τH ≃CgdRgd (10.154)
fH ≃ 1 (10.155) 2πCgdRgd
Now, as Rs is increased, the gain magnitude, |AM|=GmRL′, will decrease, causing Rgd to decrease (Eq. 10.150), which in turn causes fH to increase (Eq. 10.155). To highlight the trade-off between gain and bandwidth that Rs affords the designer, let us simplify the expression for Rgd in Eq. (10.150) by assuming that GmRL′ ≫ 1 and GmRsig ≫ 1, thus
Rgd ≃GmRL′Rsig =|AM|Rsig which can be substituted in Eq. (10.155) to obtain
fH = 1 (10.156) 2πCgdRsig|AM|
which very clearly shows the gain–bandwidth trade-off. The gain–bandwidth product remains constant at
Gain–bandwidthproduct=|AM|fH = 1 (10.157) 2πCgdRsig
In practice, however, the other capacitances will play a role in determining fH, and the gain–bandwidth product will decrease somewhat as Rs is increased.
10.8 Other Wideband Amplifier Configurations 781
EXERCISE
10.29 ConsideraCSamplifierhavinggm =2mA/V,ro =20k,RL =20k,Rsig =20k,Cgs =20 fF, Cgd = 5 fF, and CL = 5 fF. (a) Find the voltage gain AM and the 3-dB frequency fH (using the method of open-circuit time constants) and hence the gain–bandwidth product. (b) Repeat (a) for the case in which a resistance Rs is connected in series with the source terminal with a value selected so that gm Rs =2.
Ans. (a) –20 V/V, 61.2 MHz, 1.22 GHz; (b) –10 V/V, 109 MHz, 1.1 GHz
10.8.2 The CD–CS, CC–CE, and CD–CE Configurations
In Section 8.7.1 we discussed the performance improvements obtained by preceding the CS and CE amplifiers by a buffer implemented by a CD or a CC amplifier, as in the circuits shown in Fig. 10.39. A major advantage of each of these circuits is wider bandwidth than that obtained in the CS or CE stage alone. To see how this comes about, consider as an example the CD–CS amplifier in Fig 10.39(a) and note that the CS transistor Q2 will still exhibit a Miller effect that results in a large input capacitance, Cin2, between its gate and ground. However, the resistance that this capacitance interacts with will be much lower than Rsig; the buffering action of the source follower causes a relatively low resistance, approximately equal to 1/gm1, to appear between the source of Q1 and ground across Cin2.
VDD
Q2 Q2 Q2 I1 I1 I1
(a) (b) (c) Figure10.39 (a)CD–CSamplifier.(b)CC–CEamplifier.(c)CD–CEamplifier.
Example 10.13
VCC
VDD
I2
Q Q1 Q
I2
I2
11
Consider a CC–CE amplifier such as that in Fig. 10.39(b) with the following specifications: I1 = I2 = 1 mA and identical transistors with β = 100, fT = 400 MHz, and Cμ = 2 pF. Let the amplifier be fed with a source Vsig having a resistance Rsig = 4 k, and assume a load resistance of 4 k. Find the voltage gain AM ,
782
Chapter 10 Frequency Response
Example 10.13 continued
and estimate the 3-dB frequency, fH . Compare the results with those obtained with a CE amplifier operating
underthesameconditions.Forsimplicity,neglectro andrx.
Solution
At an emitter bias current of 1 mA, Q1 and Q2 have gm =40mA/V
re =25
rπ = β = 100 = 2.5 k
gm 40 Cπ+Cμ=gm = gm
ωT 2πfT 40 × 10−3
= 2π×400×106 =15.9pF Cμ =2 pF
Cπ =13.9 pF
ThevoltagegainAM canbedeterminedfromthecircuitshowninFig.10.40(a)asfollows:
Rin2 =rπ2 =2.5k
Rin=β1+1 re1+Rin2
= 101(0.025 + 2.5) = 255 k
Vb1 Vsig
Vb2 Vb1
= Rin = 255 =0.98V/V Rin +Rsig 255+4
= Rin2 = 2.5 =0.99V/V Rin2 +re1 2.5+0.025
=−gm2RL =−40×4=−160V/V
AM = Vo =−160×0.99×0.98=−155V/V
Vo Vb2
Thus,
Vsig
TodeterminefH weusethemethodofopen-circuittimeconstants.Figure10.40(b)showsthecircuit
with Vsig set to zero and the four capacitances indicated. Capacitance Cμ1 sees a resistance Rμ1,
Rμ1 =Rsig∥Rin
= 4∥255 = 3.94 k
10.8 Other Wideband Amplifier Configurations 783
Rsig
re1Vb2 RL
Vb1
Q1 Vo
Vsig
Rsig
Cm1
Q2
Rin
(a)
Q1
(b)
B1
Ix
V x
Rout1 Rin2
Cp1
Cm2 Cp2
V p 1
E1, B2
Rin2
(c)
R L
Q2
r p 1
g m V p 1 = g m V x
Rsig
Ix
Figure10.40 CircuitsforExample10.14:(a)theCC–CEcircuitpreparedforlow-frequency,small-signalanalysis; (b) the circuit at high frequencies, with Vsig set to zero to enable determination of the open-circuit time constants; (c) equivalent circuit for the determination of Rπ1; (d) a CE amplifier for comparison.
784
Chapter 10 Frequency Response
Example 10.13 continued
Cm
Vsig Cp (d)
Figure 10.40 continued
Vo
RL
Rsig
TofindtheresistanceRπ1 seenbycapacitanceCπ1 werefertotheequivalentcircuitinFig.10.40(c). Analysis of this circuit results in
Rπ1≡Vx = Rsig+Rin2
Ix
1+Rsig +Rin2 rπ1 re1
= 4000+2500 =63.4 1+ 4000+2500
2500 25
Capacitance Cπ2 sees a resistance Rπ2,
Rπ2 =Rin2∥Rout1
R =rπ2∥ re1+ sig
β1 +1
=2500∥ 25+4000 =63 101
Capacitance Cμ2 sees a resistance Rμ2. To determine Rμ2 we refer to the analysis of the frequency response of the CE amplifier in Section 10.4.4 to obtain
Rμ2 = 1+gm2RL Rin2∥Rout1 +RL
=(1+40×4) 2500∥ 25+ 4000 101
= 14,143 ≃ ̈ 14.1 k
+4000
Thus,
Rπ =rπ ∥Rsig =2.5∥4=1.54k
Rμ = 1+gmRL Rsig∥rπ +RL =(1+40×4)(4∥2.5)+4 = 251.7 k
τH =CπRπ +CμRμ =13.9×1.54+2×251.7 = 21.4 + 503.4 = 524.8 ns
WenowcandetermineτH from
τH =Cμ1Rμ1 +Cπ1Rπ1 +Cμ2Rμ2 +Cπ2Rπ2
=2×3.94+13.9×0.0634+2×14.1+13.9×0.063 =7.88+0.88+28.2+0.88=37.8ns
We observe that Cπ1 and Cπ2 play minor roles in determining the high-frequency response. As expected, C through the Miller effect plays the most significant role. Capacitor C , which interacts directly with
μ2 μ1
Rsig ∥ Rin , also plays an important role. The 3-dB frequency fH can be found as follows:
f= 1 = 1 =4.2MHz H 2πτH 2π × 37.8 × 10−9
Forcomparison,weevaluateAM andfH ofaCEamplifieroperatingunderthesameconditions.Refer toFig.10.40(d).ThevoltagegainAM isgivenby
ObservethedominantroleplayedbyCμ.The3-dBfrequencyfH is
f= 1 = 1 =303kHz
in sig
= rπ −gR r+RmL
10.8 Other Wideband Amplifier Configurations 785
A=Rin −gR MR+RmL
π sig
= 2.5 (−40×4)
2.5+4
= −61.5 V/V
H 2πτH 2π × 524.8 × 10−9
Thus, including the buffering transistor Q increases the gain, A , from 61.5 V/V to 155 V/V—a factor
product is increased from 18.63 MHz to 651 MHz—a factor of 35!
1M
of 2.5—and increases the bandwidth from 303 kHz to 4.2 MHz—a factor of 13.9! The gain–bandwidth
786 Chapter 10
Frequency Response
10.8.3 The CC–CB and CD–CG Configurations
In Section 8.7.3 we showed that preceding a CB or CG transistor with a buffer implemented with a CC or a CD transistor solves the low-input-resistance problem of the CB and CG amplifiers. Examples of the resulting compound-transistor amplifiers are shown in Fig. 10.41. Since in each of these circuits, neither of the two transistors suffers from the Miller effect, the resulting amplifiers have even wider bandwidths than those achieved in the com- pound amplifier stages of the last section. To illustrate, consider as an example the circuit in Fig. 10.41(a).10 The low-frequency analysis of this circuit in Section 8.7.3 provides for the input resistance,
Rin =(β1 +1)(re1 +re2) whichforre1 =re2 =re andβ1 =β2 =β becomes
Rin = 2rπ
If a load resistance RL is connected at the output, the voltage gain Vo/Vi will be
Vo = α2RL = 1gmRL Vi re1 +re2 2
(10.158)
(10.159)
(10.160)
Now, if the amplifier is fed with a voltage signal Vsig from a source with a resistance Rsig, the overall voltage gain will be
V 1 R
o = in (gmRL) (10.161)
The high-frequency analysis is illustrated in Fig. 10.42(a). Here we have drawn the hybrid-π equivalent circuit for each of Q1 and Q2. Recalling that the two transistors are operating at equal bias currents, their corresponding model components will be equal (i.e., rπ1 = rπ2, Cπ1 = Cπ2, etc.). With this in mind the reader should be able to see that Vπ1 = −Vπ2 and the horizontal line through the node labeled E in Fig. 10.42(a) can be deleted. Thus the circuit reduces to that in Fig. 10.42(b). This is a very attractive outcome because the circuit shows clearly the two poles that determine the high-frequency response: The pole at the input, with a frequency fP1, is
(10.162)
(10.163)
Vsig 2 Rin+Rsig
f = 1
P1 C
2π π +Cμ Rsig∥2rπ 2
and the pole at the output, with a frequency fP2, is fP2 = 1
2πCμRL
This result is also intuitively obvious: The input impedance at B1 of the circuit in Fig. 10.42(a) consists of the series connection of rπ1 and rπ2 in parallel with the series connection of Cπ1 and Cπ2. Then there is Cμ1 in parallel. At the output, we simply have RL in parallel with Cμ.
10 The results derived for the circuit in Fig. 10.41(a) apply directly to the circuit of Fig. 10.41(b) and with appropriate change of variables to the MOS circuit of Fig. 10.41(c).
VCC
C1 V B1 Q
C1 C2 Vo
B1 B2 B2
10.8
Other Wideband Amplifier Configurations 787
VCC
VDD
I
i1
I
Vi
Q1 Q2 Q2
E Vo VBIAS Vi Q Q
C2
Vo
Rin
I
2I
2I
VEE (a)
VSS (c)
VEE
Figure 10.41 (a) A CC–CB amplifier. (b) Another version of the CC–CB circuit with Q2 implemented using
a pnp transistor. (c) The MOSFET version of the circuit in (a).
(b)
Rsig
B1
C1
E
C2 RL Vo
C2
RL
Figure10.42 (a)EquivalentcircuitfortheamplifierinFig.10.41(a).(b)Simplifiedequivalentcircuit.Note that the equivalent circuits in (a) and (b) also apply to the circuit shown in Fig. 10.41(b). In addition, they canbeeasilyadaptedfortheMOSFETcircuitinFig.10.41(c),with2rπ eliminated,Cπ replacedwithCgs,Cμ replaced with Cgd, and Vπ replaced with Vgs.
Vsig
B2
Rsig
B1
(a)
(b)
12
E
Vsig
Vo
788 Chapter 10
Frequency Response
Whether one of the two poles is dominant will depend on the relative values of Rsig and RL. If the two poles are close to each other, then the 3-dB frequency fH can be determined either by exact analysis—that is, finding the frequency at which the gain is down by 3 dB—or by using the approximate formula in Eq. (10.77),
fH ≃1 1 + 1 (10.164) f2 f2
10.30 FortheCC–CBamplifierofFig.10.41(a),letI=0.5mA,β=100,Cπ =6pF,Cμ =2pF,Rsig = 10k,andRL =10k.Findthelow-frequencyoverallvoltagegainAM,thefrequenciesofthepoles, andthe3-dBfrequencyfH.FindfH bothexactlyandusingtheapproximateformulainEq.(10.164). Ans. 50 V/V; 6.4 MHz and 8 MHz; fH by exact evaluation = 4.6 MHz; fH using Eq. (10.164) = 5 MHz.
P1 P2
EXERCISE
Summary
The coupling and bypass capacitors utilized in discrete-circuit amplifiers cause the amplifier gain to fall off at low frequencies. In the CS amplifier, the capacitors do not interact, and the frequencies of the low-frequency poles can be estimated by considering each of these capacitors separately and determining the resistance seen by the capacitor. The highest-frequency pole is the one that determines the lower 3-dB frequency fL. In the CE amplifier, the capacitors interact, and thus the poles cannot be easily determined. Rather the method of short-circuit time constants can be used to obtain an estimate of the 3-dB frequency, fL .
Both the MOSFET and the BJT have internal capacitive
effects that can be modeled by augmenting the device
hybrid-π model with capacitances. Usually at least two
capacitances are needed: Cgs and Cgd (Cπ and Cμ for the
BJT). A figure of merit for the high-frequency operation of
the transistor is the frequency fT at which the short-circuit
is possible to trade off gain for increased bandwidth, with GB remaining nearly constant. For amplifiers with a dominant pole with frequency fH , the gain falls off at a uniform 6-dB/octave (20-dB/decade) rate, reaching 0 dB atft=GB.
The high-frequency response of the CS and CE ampli- fiers is severely limited by the Miller effect: The
current gain of the CS (CE) transistor reduces to unity. For
sig
the MOSFET, fT = gm/2π Cgs +Cgd , and for the BJT,
fT =gm/2π Cπ +Cμ .
The internal capacitances of the MOSFET and the BJT cause the amplifier gain to fall off at high frequencies. An estimate of the amplifier bandwidth is provided by the frequency fH at which the gain drops 3 dB below its value at midband, AM . A figure of merit for the amplifier is the gain–bandwidth product GB = AM fH . Usually, it
small capacitance Cgd Cμ is multiplied by a factor
approximately equal to the gain from gate to drain
(base to collector) gmRL′ and thus gives rise to a large
capacitance at the amplifier input. The increased Cin
interacts with the effective signal-source resistance R′ sig
and causes the amplifier gain to have a 3-dB frequency f =1/2πR′ C .
H sig in
The method of open-circuit time constants provides a simple and powerful way to obtain a reasonably good estimate of the upper 3-dB frequency fH . The capacitors that limit the high-frequency response are considered one at time with V = 0 and all the other capacitances set to zero (open circuited). The resistance seen by each capacitance is determined, and the overall time constant τH isobtainedbysummingtheindividualtimeconstants. ThenfH isfoundas1/2πτH.
The CG and CB amplifiers do not suffer from the Miller effect. Thus the cascode amplifier, which consists of a cascade of CS and CG stages (CE and CB stages), can be designed to obtain wider bandwidth than that achieved
in the CS (CE) amplifier alone. The key, however, is to design the cascode so that the gain obtained in the CS (CE) stage is minimized.
The source and emitter followers can have complex poles. Thus, their frequency response is evaluated using the complete transfer function. Followers of both types exhibit wide bandwidths.
The high-frequency response of the differential amplifier can be obtained by considering the differential and common-mode half-circuits. The CMRR falls off at
Problems 789 a relatively low frequency determined by the output
impedance of the bias current source.
The high-frequency response of the current-mirror-loaded differential amplifier is complicated by the fact that there are two signal paths between input and output: a direct path and one through the current mirror.
Combining two transistors in a way that eliminates or minimizes the Miller effect can result in a much wider bandwidth. Some such configurations are presented in Section 10.8.
PROBLEMS
10.4 The amplifier in Fig. 10.3(a) is biased to operate at gm = 5 mA/V, and has the following component values: Rsig =100k,RG1 =47M,RG2 =10M,CC1 =0.01μF, RS =2k, CS =10μF, RD =4.7k, RL =10k, and CC2 =1μF. Find AM, fP1, fP2, fZ, fP3, and fL.
D 10.5 The amplifier in Fig. P10.5 is biased to operate at gm = 2 mA/V. Neglect ro .
Computer Simulation Problems
Problems identified by the Multisim/PSpice icon are intended to demonstrate the value of using SPICE simulation to verify hand analysis and design, and to investigate impor- tant issues such as gain–bandwidth trade-off. Instructions to assist in setting up PSpice and Multisim simulations for all the indicated problems can be found in the corresponding files on the website. Note that if a particular parameter value is not specified in the problem statement, you are to make a reasonable assumption.
Section 10.1: Low-Frequency Response of Discrete-Circuit Common-Source and Common-Emitter Amplifiers
D 10.1 For the amplifier in Fig. 10.3(a), if RG1 = 2 M, RG2 = 1 M, and Rsig = 200 k, find the value of the coupling
VDD
Vo
RD CS
capacitor C
the associated pole at 10 Hz or lower.
VR iS
C1
(specified to one significant digit) that places
4.5 k
VSS Figure P10.5
(a) Determine the value of RD that results in a midband gain of −20 V/V.
(b) Determine the value of CS that results in a pole frequency of 100 Hz.
(c) What is the frequency of the transmission zero introduced by CS ?
D 10.2 For the amplifier in Fig. 10.3(a), if RD = 10 k, RL = 10 k, and ro is very large, find the value of CC2 (specified to one significant digit) that places the associated pole at 10 Hz or lower.
D 10.3 The amplifier in Fig. 10.3(a) is biased to operate at gm = 5 mA/V, and RS = 1.8 k. Find the value of CS (specified to one significant digit) that places its associated pole at 100 Hz or lower. What are the actual frequencies of the pole and zero realized?
(d) Give an approximate value for the 3-dB frequency fL . = Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
790 Chapter 10 Frequency Response
(e) Sketch a Bode plot for the gain of this amplifier. What does the plot tell you about the gain at dc? Does this make sense? Why or why not?
D 10.6 Figure P10.6 shows a CS amplifier biased by a constant-current source I. Let Rsig = 0.5 M, RG = 2 M, gm =3mA/V,RD =20k,andRL =10k.FindAM.Also,
VDD
RD
design the coupling and bypass capacitors to locate the three low-frequency poles at 100 Hz, 10 Hz, and 1 Hz. Use a minimum total capacitance, with the capacitors specified only toasinglesignificantdigit.WhatvalueoffL results?
D 10.7 Figure P10.7 shows a current-biased CE amplifier operating at 100 μA from ±3-V power supplies. It employs
CHAPTER 10 PROBLEMS
CC2
RL
Vo
Rsig
Vsig
CC 1
RG
CS I
Figure P10.6
–VSS
VCC
RC
CC2
RL
Vo
Rsig
Vsig
CC 1
RB
CE I
Figure P10.7
–VEE
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
RC = 20 k, RB = 200 k, and operates between a 20-k source and a 10-k load. The transistor β = 100. Select CE first, for a minimum value specified to one significant digit and providing up to 80% of fL where fL is to be 100 Hz. Then choose CC1 and CC2, each specified to one significant digit, and each contributing about 10% of fL . What fL results? What total capacitance is needed?
10.8 Consider the common-emitter amplifier of Fig. 10.9(a) under the following conditions: Rsig = 5 k, RB1 = 33 k, RB2 =22k, RE =3.9k, RC =4.7k, RL =5.6k, VCC =5V. The dc emitter current can be shown to be IE ≃ 0.3 mA, at which β = 120. Find the input resistance Rin andthemidbandgainAM.IfCC1=CC2=1μFand CE = 20 μF, find the three short-circuit time constants and an estimate for fL .
D 10.9 For the amplifier described in Problem 10.8, design the coupling and bypass capacitors for a lower 3-dB frequency of 50 Hz. Design so that the contribution of each of CC1 and CC2 to determining fL is only 10%.
10.10 Consider the circuit of Fig. 10.9(a). For Rsig = 5 k, RB ≡ RB1∥RB2 = 10k, rπ =1k, β0 =100, and RE = 1.5 k, what is the ratio CE /CC1 that makes their contributions to the determination of fL equal?
D *10.11 For the common-emitter amplifier of Fig. P10.11, neglect ro and assume the current source to be ideal.
(a) Derive an expression for the midband gain.
(b) Convince yourself that the two poles caused by CE and CC do not interact. Find expressions for their frequencies,
ωPE and ωPC .
(c) Give an expression for the amplifier voltage gain
Vo(s)/Vsig(s)intermsofAM,ωPE,andωPC.
(d) ForRsig =RC =RL =10k,β=100,andI=1mA,find
the value of the midband gain.
(e) Select values for CE and CC to place the two pole
frequencies a decade apart and to obtain a lower 3-dB frequency of 100 Hz while minimizing the total capacitance.
(f) Sketch a Bode plot for the gain magnitude, and estimate the frequency at which the gain becomes unity.
*10.12 The BJT common-emitter amplifier of Fig. P10.12 includes an emitter-degeneration resistance Re.
VCC
RC
CE I
Problems 791
CHAPTER 10 PROBLEMS
Vo
Rsig
VCC
RC
I
CC CE
Vo
RL
Vsig Re
Figure P10.12
Vsig
Figure P10.11
(a) Assuming α≃1, neglecting ro, and assuming the cur- rent source to be ideal, derive an expression for the small-signal voltage gain A(s) ≡ Vo/Vsig that applies in the midband and the low-frequency band. Hence find the midband gain AM and the lower 3-dB frequency fL .
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
792 Chapter 10 Frequency Response
(b) Show that including Re reduces the magnitude of AM by a certain factor. What is this factor?
(c) Show that including Re reduces fL by the same factor as in
(b)andthusonecanuseRe totradeoffgainforbandwidth.
(d) For I = 0.25mA, R =10k, and C =10μF, find C E
AM and fL with Re = 0. Now find the value of Re that lowers fL by a factor of 10. What will the gain become? Sketch on the same diagram a Bode plot for the gain magnitude for both cases.
Section 10.2: Internal Capacitive Effects and the High-Frequency Model of the MOSFET and the BJT
10.13 Refer to the MOSFET high-frequency model in Fig.10.12(a). Evaluate the model parameters for an NMOS transistor operating at ID = 200 μA, VS B = 1 V, and VDS =1.5V. The MOSFET has W = 20μm, L = 1μm, tox =8 nm, μn =450 cm2/V·s, γ =0.5V1/2, 2φf =0.65V, λ = 0.05 V−1, V0 = 0.7 V, Csb0 = Cdb0 = 20 fF, and Lov = 0.05 μm. [Recall that gmb = χgm, where χ = γ/22φ +V ,andthate =3.45×10−11 F/m.]
fSB ox
10.14 Find fT for a MOSFET operating at ID = 200 μA and VOV =0.3V.TheMOSFEThasCgs =25fFandCgd =5fF.
Thus note that to obtain a high fT from a given device, it must be operated at a high current. Also note that faster operation is obtained from smaller devices.
10.16 Starting from the expression for the MOSFET unity-gain frequency,
fT= gm 2π(Cgs +Cgd)
3μnVOV fT ≃ 4πL2
Observe that for a given channel length, fT can be increased by operating the MOSFET at a higher overdrive voltage. EvaluatefT fordeviceswithL=0.5μmoperatedatoverdrive voltages of 0.2 V and 0.4 V. Use μ = 450 cm2 /V·s.
n
10.17 It is required to calculate the intrinsic gain A0 and the unity-gain frequency fT of an n-channel transistor fabricated in a 0.13-μm CMOS process for which Lov = 0.1 L, μn = 400 cm2/V·s, and VA′ = 5 V/μm. The device is operated at VOV = 0.2 V. Find A0 and fT for devices with L = Lmin, 2Lmin , 3Lmin , 4Lmin , and 5Lmin . Present your results in a table. (Hint: For fT, use the approximate expression fT≃3μnVOV.)
4πL2
10.18 A particular BJT operating at IC = 0.5 mA has Cμ =
1pF,Cπ =8pF,andβ=100.WhatarefT and fβ forthis situation?
10.19 For the transistor described in Problem 10.18, Cπ includes a relatively constant depletion-layer capacitance
and that the overlap component of Cgs is negligibly small, show that for
and making the approximation that Cg s an n-channel device
≫ Cg d
CHAPTER 10 PROBLEMS
10.15 Starting from the expression of fT gm
for a MOSFET,
the
fT = 2π(Cgs +Cgd) and making the approximation that Cg s
≫ Cg d
and that overlap component of Cgs is negligibly small, show that
Transistor
(a) (b) (c) (d) (e) (f) (g)
fT ≃ 1.5 IE(mA) re()
2
25
10 0.1
gm(mA/V)
rπ (k)
2.5
β0 100
100 100 100
fT (MHz) 500
500
500
150
500
800
Cμ (pF) Cπ (pF) fβ (MHz) 2
210.74 10.7
2
2
2 1980
μnID πL 2CoxWL
1 10
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
of2pF.IfthedeviceisoperatedatIC =0.25mA,whatdoes its fT become?
10.20 An npn transistor is operated at IC = 1 mA and Rsig
VCB =2V. It has β0 =100, VA =50V, τF =30 ps,
C =20fF, C =30 fF, V =0.75V, m =0.5, and
je0 μ0 0c CBJ V
C
sig Vo
C
Problems 793
CHAPTER 10 PROBLEMS
Vi A
rx = 100 . Sketch the complete hybrid-π model, and specify the values of all its components. Also, find fT .
10.21 Measurement of h of an npn transistor at 50 MHz fe
showsthat hfe =10atIC =0.2mAand12atIC =1.0mA. Furthermore, Cμ was measured and found to be 0.1 pF. Find fT at each of the two collector currents used. What must τF and Cje be?
10.22 A particular small-geometry BJT has fT of 10 GHz andCμ =0.1pFwhenoperatedatIC =1.0mA.WhatisCπ inthissituation?Also,findgm.Forβ=120,findrπ andfβ.
10.23 For a BJT whose unity-gain bandwidth is 2 GHz and β 0 = 200, at what frequency does the magnitude of hfe become 40? What is fβ ?
*10.24 For a sufficiently high frequency, measurement of the complex input impedance of a BJT having (ac) grounded emitter and collector yields a real part approximating rx . For what frequency, defined in terms of ωβ , is such an estimate of rx good to within 10% under the condition that rx ≤ rπ /10?
*10.25 Complete the table entries on the previous page for transistors (a) through (g), under the conditions indicated. Neglect rx .
Section 10.3: High-Frequency Response of the CS and CE Amplifiers
10.26 In a particular common-source amplifier for which the midband voltage gain between gate and drain (i.e., −gmRL′ ) is −39 V/V, the NMOS transistor has Cgs = 1.0 pF and Cgd = 0.1 pF. What input capacitance would you expect? For what range of signal-source resistances can you expect the 3-dB frequency to exceed 1 MHz? Neglect the effect of RG .
D 10.27 In the circuit of Fig. P10.27, the voltage amplifier is ideal (i.e., it has an infinite input resistance and a zero output resistance).
(a) UsetheMillerapproachtofindanexpressionfortheinput capacitance Cin in terms of A and C.
(b) Use the expression for Cin to obtain the transfer function Vo (s)/Vsig (s).
in
Figure P10.27
(c) If Rsig = 1 k, and the gain Vo/Vsig is to have a dc value of 40 dB and a 3-dB frequency of 100 kHz, find the values required for A and C.
(d) Sketch a Bode plot for the gain and use it to deter- mine the frequency at which its magnitude reduces to unity.
10.28 An ideal voltage amplifier having a voltage gain of –1000 V/V has a 0.2-pF capacitance connected between its output and input terminals. What is the input capacitance of the amplifier? If the amplifier is fed from a voltage source Vsig having a resistance Rsig = 1 k, find the transfer function Vo/Vsig as a function of the complex-frequency variable s and hence the 3-dB frequency fH and the unity-gain frequency ft .
D 10.29 A design is required for a CS amplifier for which theMOSFETisoperatedatgm =5mA/VandhasCgs =5pF and Cgd = 1 pF. The amplifier is fed with a signal source having Rsig = 1 k, and RG is very large. What is the largest value of RL′ for which the upper 3-dB frequency is at least 6 MHz? What is the corresponding value of midband gain and gain–bandwidth product? If the specification on the upper 3-dB frequency can be relaxed by a factor of 3, that is, to 2 MHz, what can AM and GB become?
10.30 Reconsider Example 10.3 for the situation in which the transistor is replaced by one whose width W is half that of the original transistor while the bias current remains unchanged. Find modified values for all the device parameters along with AM , fH , and the gain–bandwidth product, GB. Contrast this with the original design by calculating the ratios of new value to old for W, VOV, gm, Cgs, Cgd, Cin, AM, fH, and GB.
D *10.31 In a CS amplifier, such as that in Fig. 10.3(a), the resistance of the source Rsig = 100 k, amplifier
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
794 Chapter 10 Frequency Response
input resistance (which is due to the biasing network) Rin =100k, Cgs =1pF, Cgd =0.2pF, gm =3mA/V, ro =50k, RD =8k, and RL =10k. Determine the
10.35 A common-emitter amplifier is measured at midband and found to have a gain of −50 V/V between base and collector. If Cπ = 10 pF, Cμ = 1 pF, and the effective source
expected 3-dB cutoff frequency f and the midband gain.
H sig in
In evaluating ways to double fH, a designer considers the alternatives of changing either RL or Rin. To raise fH as described, what separate change in each would be required? What midband voltage gain results in each case?
10.32 A discrete MOSFET common-source amplifier has RG =2 M, gm =5mA/V, ro =100k, RD =20k, Cgs = 3 pF, and Cgd = 0.5 pF. The amplifier is fed from a voltage source with an internal resistance of 500 k and is connected to a 20-k load. Find:
(a) the overall midband gain AM
(b) the upper 3-dB frequency fH
(c) the frequency of the transmission zero, fZ .
10.33 For the discrete-circuit CS amplifier in Fig. 10.3(a)
let Rsig =100k, RG1 =47M, RG2 =10M, RS =2k,
RD =4.7k, RL =10k, gm =3mA/V, ro =100k,
C =1pF,andC =0.2pF.FindA andf .
gsgdMH sig L
10.34 Consider the integrated-circuit CS amplifier in Fig. P10.34 for the case IBIAS = 100 μA, Q2 and Q3 are matched, and Rsig = 200 k. For Q1: μnCox = 90 μA/V2, VA =12.8V,W/L=100μm/1.6μm,Cgs =0.2 pF,and Cgd = 0.015 pF. For Q2: |VA| = 19.2 V. Neglecting the effect of the capacitance inevitably present at the output node, find the low-frequency gain, the 3-dB frequency fH , and the frequency of the zero fZ .
fH .
resistance R′ = 5 k [refer to Fig. 10.19(b)], find C and the 3-dB frequency fH .
10.36 For a CE amplifier represented by the equivalent circuit in Fig. 10.19(a), let Rsig = 10 k, RB = 100 k, rx = 100,Cπ =10 pF,Cμ =1pF,gm =40mA/V,ro =100k, RC =10k,RL =10k,andβ=100.Findthemidbandgain andthe3-dBfrequencyfH.
10.37 A designer wishes to investigate the effect of changing
the bias current IE on the midband gain and high-frequency
response of the CE amplifier considered in Example 10.4.
Let I be doubled to 2 mA, and assume that β and f remain E0T
unchanged at 100 and 800 MHz, respectively. To keep the
node voltages nearly unchanged, the designer reduces RB and
RC by a factor of 2, to 50 k and 4 k, respectively. Assume
rx = 50 , and recall that VA = 100 V and that Cμ remains
constant at 1 pF. As before, the amplifier is fed with a source
CHAPTER 10 PROBLEMS
havingR =5kandfeedsaloadR =5k.Findthenew
values of AM , fH , and the gain–bandwidth product, AM Comment on the results. Note that the price paid for whatever improvement in performance is achieved is an increase in power. By what factor does the power dissipation increase?
*10.38 The purpose of this problem is to investigate the high-frequency response of the CE amplifier when it is fed with a relatively large source resistance Rsig. Refer to the amplifier in Fig. 10.9(a) and to its high-frequency, equivalent-circuit model and the analysis shown in Fig. 10.19. LetRB ≫Rsig,rx ≪Rsig,Rsig ≫rπ,gmRL′ ≫1,andgmRL′Cμ ≫ Cπ . Under these conditions, show that:
(a) the midband gain AM ≃ −βRL′ /Rsig
(b) the upper 3-dB frequency fH ≃ 1/2πCμβRL′
(c) thegain–bandwidthproduct|AM|fH ≃1/2πCμRsig
Evaluate this approximate value of the gain–bandwidth product for the case Rsig =25k and Cμ =1pF. Now, if the transistor is biased at IC = 1 mA and has β = 100, find the midband gain and fH for the two cases RL′ = 25 k and RL′ = 2.5 k. On the same coordinates, sketch Bode plots for the gain magnitude versus frequency for the two cases. What fH is obtained when the gain is unity? What value of RL′ corresponds?
10.39 For a version of the CE amplifier circuit in Fig. 10.9(a), Rsig = 10 k, RB1 = 68 k, RB2 = 27 k,
Q3 Q2
IBIAS
Rsig Vsig
Figure P10.34
Vo
Q1
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
Problems 795
CHAPTER 10 PROBLEMS
RE =2.2k, RC =4.7k, and RL =10k. The collector current is 0.8mA, β =200, fT =1 GHz, and Cμ =0.8pF. Neglecting the effect of rx and ro, find the midband voltage gain and the upper 3-dB frequency fH .
10.40 Consider an ideal voltage amplifier with a gain of 0.9 V/V, and a resistance R = 100 k connected in the feed- back path—that is, between the output and input terminals. Use Miller’s theorem to find the input resistance of this circuit.
10.41 The amplifiers listed below are characterized by the descriptor (A, C), where A is the voltage gain from input to output and C is an internal capacitor connected between input and output. For each, find the equivalent capacitances at the input and at the output as provided by the use of Miller’s theorem:
(a) –1000 V/V, 1 pF (b) –10 V/V, 10 pF (c) –1 V/V, 10 pF (d) +1 V/V, 10 pF (e) +10 V/V, 10 pF
Note that the input capacitance found in case (e) can be used to cancel the effect of other capacitance connected from input to ground. In (e), what capacitance can be canceled?
Rsig
IL
2 Vo
R
Vsig ZL Figure P10.42
Rin
10 k
Vo
Rin
Vo /Vsig
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
resistancebecomesinfiniteandthecurrentIL intotheload impedance ZL becomes Vsig/R. The circuit then functions as an ideal voltage-controlled current source with an output current IL .
(c) IfZL isacapacitorC,findthetransferfunctionVo/Vsig and show it is that of an ideal noninverting integrator.
10.43 Use Miller’s theorem to investigate the performance of the inverting op-amp circuit shown in Fig. P10.43. Assume the op amp to be ideal except for having a finite differential gain, A. Without using any knowledge of op-amp circuit analysis, find Rin, Vi, Vo, and Vo/Vsig, for each of the following values of A: 10 V/V, 100 V/V, 1000 V/V, and 10,000 V/V. Assume Vsig = 1 V. Present your results in the table below.
*10.42 Figure P10.42 shows an ideal voltage amplifier with
a gain of +2 V/V (usually implemented with an op amp 1 k connected in the noninverting configuration) and a resistance
R connected between output and input.
Vi
Vsig
Show that by selecting Rsig = R, the equivalent parallel Figure P10.43
(a) Using Miller’s theorem, show that the input resistance Rin =−R.
(b) Use Norton’s theorem to replace Vsig, Rsig, and Rin with a signal current source and an equivalent parallel resistance.
A Rin Vi Vo
10 V/V 100 V/V 1000 V/V 10,000 V/V
796 Chapter 10 Frequency Response
*10.44 The amplifier shown in Fig. P10.44 has Rsig =RL =1k, RC =1k, RB =47k, β =100, Cμ =0.8pF, and fT =600MHz. Assume the coupling capacitors to be very large.
(a) Find the dc collector current of the transistor.
(b) Find gm and rπ .
(c) Neglecting ro, find the midband voltage gain from base
to collector (neglect the effect of RB).
(d) Use the gain obtained in (c) to find the component of Rin
10.46 A CS amplifier modeled with the equivalent circuit of Fig. 10.22(a) is specified to have Cgs = 2 pF, Cgd = 0.1 pF, gm =4mA/V,CL =2pF,andRL′ =20k.FindAM,f3dB,fZ, andft.
D 10.47 A common-source amplifier fed with a low-resistance signal source and operating with gm = 2 mA/V has a unity-gain frequency of 2 GHz. What additional capacitance must be connected to the drain node to reduce ft to 1 GHz?
*10.48 It is required to analyze the high-frequency response
of the CMOS amplifier shown in Fig.P10.34 for the
case Rsig = 0. The dc bias current is 100 μA. For Q1 ,
μnCox = 90 μA/V2, VA = 12.8 V, W/L = 100 μm/1.6 μm,
C =0.2pF, C =0.015pF, and C =20fF. For Q , gs gd db 2
Cgd = 0.015 pF, Cdb = 36 fF, and VA = 19.2 V. For simplic- ity, assume that the signal voltage at the gate of Q2 is zero. Find the low-frequency gain, the frequency of the pole, and the frequency of the zero. (Hint: The total capacitance at the outputmode=Cdb1 +Cdb2 +Cgd2).
10.49 Consider an active-loaded common-emitter amplifier. Let the amplifier be fed with an ideal voltage source Vi, and neglect the effect of rx . Assume that the load current source has averyhighresistanceandthatthereisacapacitanceCL present between the output node and ground. This capacitance repre- sents the sum of the input capacitance of the subsequent stage and the inevitable parasitic capacitance between collector and ground. Show that the voltage gain is given by
1−s Cμ/gm
1+sCL+Cμ ro
that arises as a result of RB. Hence find Rin.
(e) Find the overall gain at midband.
(f) Find Cin .
(g) Findf. H
R
Vsig Figure P10.44
1.5 V
CHAPTER 10 PROBLEMS
RC
sig
CC1
RB
CC2
Vo
Rin
RL
*10.45 Figure P10.45 shows a diode-connected transis-
tor with the bias circuit omitted. Utilizing the BJT
high-frequency, hybrid-π model with r = 0 and r = ∞, xo
deriveanexpressionforZi(s)asafunctionofre andCπ.Find the frequency at which the impedance has a phase angle of 45° for the case in which the BJT has fT = 400 MHz and the bias current is relatively high. What is the frequency when the bias current is reduced so that Cπ ≃ Cμ ? Assume α = 1.
FigureP10.45
Vo
V =−gmro i
If the transistor is biased at IC = 200 μA and VA = 100 V, Cμ =0.2pF, and CL =1 pF, find the dc gain, the 3-dB frequency, the frequency of the zero, and the frequency at which the gain reduces to unity. Sketch a Bode plot for the gain magnitude.
10.50 A particular BJT operating at 2 mA is specified to havefT =2GHz,Cμ =1pF,rx =100,and β=120. The device is used in a CE amplifier operating from a very-low-resistance voltage source.
(a) If the midband gain obtained is −10 V/V, what is the value of fH ?
(b) If the midband gain is reduced to −1 V/V (by changing RL′),whatfH isobtained?
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
Section 10.4: Useful Tools for the Analysis of the High-Frequency Response of Amplifiers
10.51 A direct-coupled amplifier has a low-frequency gain of 40 dB, poles at 2 MHz and 20 MHz, a zero on the negative real axis at 200 MHz, and another zero at infinite frequency. Express the amplifier gain function in the form of Eqs. (10.70) and (10.71), and sketch a Bode plot for the gain magnitude. Whatdoyouestimatethe3-dBfrequencyfH tobe?
10.52 Anamplifierwithadcgainof60dBhasasingle-pole, high-frequency response with a 3-dB frequency of 100 kHz.
(a) Give an expression for the gain function A(s).
(b) SketchBodediagramsforthegainmagnitudeandphase.
(c) What is the gain–bandwidth product?
(d) What is the unity-gain frequency?
(e) If a change in the amplifier circuit causes its transfer
function to acquire another pole at 1MHz, sketch the resulting gain magnitude and specify the unity-gain frequency. Note that this is an example of an amplifier with a unity-gain bandwidth that is different from its gain–bandwidth product.
10.53 Consider an amplifier whose FH (s) is given by
1
10.55 A direct-coupled amplifier has a dominant pole at 1000 rad/s and three coincident poles at a much higher fre- quency. These nondominant poles cause the phase lag of the amplifier at high frequencies to exceed the 90° angle due to the dominant pole. It is required to limit the excess phase at ω = 107 rad/s to 30° (i.e., to limit the total phase angle to –120°). Find the corresponding frequency of the nondominant poles.
FH(s)= s 1+ω 1+ω
estimate for fH . Also, find the frequency of the transmission zero, fZ .
10.57 For a particular amplifier modeled by the circuit of Fig. 10.18(a), gm = 5 mA/V, Rsig = 150 k, RG = 0.65 M, RL′ =10k, Cgs =2pF, and Cgd =0.5pF. There is also a load capacitance of 30 pF. Find the corresponding midband voltage gain, the open-circuit time constants, and an estimate of the 3-dB frequency.
10.58 Consider the high-frequency response of an amplifier consisting of two identical stages in cascade, each with an input resistance of 10 k and an output resistance of 2 k. The two-stage amplifier is driven from a 10-k source and drives a 1-k load. Associated with each stage is a parasitic input capacitance (to ground) of 10 pF and a parasitic output capacitance (to ground) of 2 pF. Parasitic capacitances of 10 pF and 7 pF also are associated with the signal-source and load connections, respectively. For this arrangement, find the three poles and estimate the 3-dB frequency fH .
10.59 A CS amplifier that can be represented by the
equivalent circuit of Fig. 10.24 has Cgs = 2 pF, Cgd = 0.1 pF,
C =2 pF, g =4mA/V, and R′ =R′ =20k. Find the Lm sigL
midband gain AM , the input capacitance Cin using the Miller approximation, and hence an estimate of the 3-dB frequency fH.Also,obtainanotherestimateoffH usingopen-circuittime constants. Which of the two estimates is more appropriate and why?
s P1 P2
10.56 An IC CS amplifier has gm = 2 mA/V, Cgs = 30 fF, C =5fF, C =30fF, R′ =10k, and R′ =20k.
gd L sig L
Use the method of open-circuit time constants to obtain an
Problems 797
CHAPTER 10 PROBLEMS
with ωP1 < ωP2 . Find the ratio ωP2 /ωP1 for which the value of the 3-dB frequency ωH calculated using the dominant-pole approximation differs from that calculated using the root-sum-of-squares formula (Eq. 10.77) by:
(a) 10% (b) 1%
10.54 The high-frequency response of a direct-coupled amplifier having a dc gain of –1000 V/V incorporates zeros at ∞ and 104 rad/s (one at each frequency) and poles at 103 rad/s and 105 rad/s (one at each frequency). Write an expression for theamplifiertransferfunction.FindωH using
(a) the dominant-pole approximation
(b) the root-sum-of-squares approximation (Eq. 10.77).
If a way is found to lower the frequency of the finite zero to 103 rad/s, what does the transfer function become? What is the 3-dB frequency of the resulting amplifier?
D10.60 ForaCSamplifierwithgm =5mA/V,Cgs =5pF, C =1pF, C =5pF, R′ =10k, and R′ =10k, find
gd L sig L
τH and fH . What is the percentage of τH that is caused by the
interaction of R′ with the input capacitance? To what value
sig
be lowered in order to double f ?
H
D 10.61
of the additional capacitance to be connected at the output node in order to lower fH to 100 MHz.
must R′ sig
For the CS amplifier in Example 10.8, find the value
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
798 Chapter 10 Frequency Response
10.62 Consider the CE amplifier whose equivalent circuit is
shown in Fig. 10.19(a) but with a capacitance CL connected
across the output terminals. Let R′ = 5 k, R = ∞, r = 0, sig B x
gm =20mA/V,β=100,Cπ =10 pF,Cμ =1 pF,RL′ =5k, and CL =10 pF. Find AM and fH.
expressions in Eqs. (10.94) and (10.95).
(b) Evaluate fP1 and fP2 and hence obtain an estimate for
fH forthecaseCπ =10pF,Cμ =1pF,CL =1pF, IC =1mA,Rsig =1k,andRL =10k.Also,find fT of the transistor.
10.68 ConsideraCGamplifierloadedinaresistanceRL =ro
and fed with a signal source having a resistance Rsig = ro/2.
Also let C = C . Use the method of open-circuit time L gs
constantstoshowthatforg r ≫1,theupper3-dBfrequency mo
is related to the MOSFET fT by the approximate expression
fH =fT/ gmro
10.69 For the CG amplifier in Example 10.9, how much additional capacitance should be connected between the outputnodeandgroundtoreducefH to200MHz?
10.70 An IC CG amplifier is fed from a signal source with Rsig =ro/2,wherero istheMOSFEToutputresistance.Ithasa current-source load with an output resistance equal to ro . The MOSFET is operated at ID = 100 μA and has gm = 1.5 mA/V, VA =10 V, Cgs =0.2pF, Cgd =0.015pF, and Cdb =20fF. As well, the current-source load provides an additional 30 fF capacitance at the output node. Find fH .
10.71 Find the dc gain and the 3-dB frequency of a MOS cascode amplifier operated at gm = 2 mA/V and ro = 20 k. TheMOSFETshaveCgs =20fF,Cgd =5fF,andCdb =5fF. The amplifier is fed from a signal source with Rsig = 100 k and is connected to a load resistance of 1 M. There is also aloadcapacitanceCL of20fF.
*10.72 (a) Consider a CS amplifier having Cgd = 0.2 pF, Rsig =RL =20k, gm =4mA/V, Cgs =2 pF, CL (including Cdb) = 1pF, Cdb = 0.2 pF, and ro = 20k. Find the low-frequency gain AM , and estimate fH using open-circuit time constants. Hence determine the gain–bandwidth product. (b) If a CG stage utilizing an identical MOSFET is cascaded with the CS transistor in (a) to create a cascode amplifier, determine the new values of AM , fH , and gain–bandwidth product. Assume RL remains unchanged.
10.63 A common-emitter amplifier has C = 10 pF, C = πμμLL
0.3pF,CL =3pF,gm =40mA/V,β=100,rx =100, R′ = 5k, and R = 1k. Find the midband gain A
LsigM and an estimate of the 3-dB frequency fH using the Miller
approximation. Also, obtain another estimate of fH using the method of open-circuit time constants. Which of the two estimates would you consider to be more realistic, and why?
10.64 Consider a CS amplifier loaded in a current source with an output resistance equal to ro of the amplifying transistor. The amplifier is fed from a signal source with Rsig = ro/2. The transistor is biased to operate at gm = 2 mA/V and ro = 20 k; Cgs = Cgd = 0.1 pF. Use the Miller approximation to determine an estimate of fH . Repeat for the following two cases: (i) the bias current I in the entire system is reduced by a factor of 4, and (ii) the bias current I in the entire system is increased by a factor of 4. Remember that both Rsig and RL will change as ro changes.
10.65 Use the method of open-circuit time constants to find fH for a CS amplifier for which gm = 1.5 mA/V, Cgs = Cgd = 0.2pF, ro = 20k, RL = 12k, and Rsig = 100k for the following cases: (a) CL = 0, (b) CL = 10 pF, and (c) CL = 50 pF. Compare with the value of fH obtained using the Miller approximation.
Section 10.5: High-Frequency Response of the Common-Gate and Cascode Amplifiers
10.66 A CG amplifier is specified to have Cgs = 4 pF, Cgd = 0.2pF, CL =2 pF, gm =5mA/V, Rsig =1k, and RL = 10 k. Neglecting the effects of ro, find the low-frequency gain Vo /Vsig , the frequencies of the poles fP1 and fP2 , and hence an estimate of the 3-dB frequency fH .
*10.67 Sketchthehigh-frequencyequivalentcircuitofaCB amplifier fed from a signal generator characterized by Vsig and Rsig and feeding a load resistance RL in parallel with a capacitance CL .
(a) Show that for rx =0 and ro =∞, the circuit can be separated into two parts: an input part that produces a
pole at
fP1 = 1 2πCπ Rsig ∥re
and an output part that forms a pole at 1
fP2 = 2π(C + C )R
Note that these are the bipolar counterparts of the MOS
CHAPTER 10 PROBLEMS
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
D 10.73 It is required to design a cascode amplifier to provide a dc gain of 74 dB when driven with a low-resistance generator and utilizing NMOS transistors for which VA = 10V,μnCox =200μA/V2,W/L=50,Cgd =0.1pF,and CL = 1 pF. Assuming that RL = Ro, determine the overdrive voltage and the drain current at which the MOSFETs should be operated. Find the unity-gain frequency and the 3-dB frequency.IfthecascodetransistorisremovedandRL remains unchanged, what will the dc gain become?
10.74 (a) Show that introducing a cascode transistor to an IC CS amplifier whose bandwidth is limited by the interaction of Rsig and the input capacitance, and whose load resistance is equal to ro, increases the dc gain by approximately a factor of2andfH bythefactorN,
C +1(gr)C N=gs 2mo gd
Cgs +3Cgd
Assume that the bandwidth of the cascode amplifier is
primarily determined by the input circuit.
(b) If Cgd = 0.1 Cgs and the dc gain of the CS amplifier is 50, what is the value of N?
(c) If VA = 10 V, μnCox = 400 μA/V2, and W/L=10, find VOV and ID at which the transistors must be operating.
10.75 (a) For an integrated-circuit MOS cascode amplifier fed with a source having a very small resistance and loaded in a resistance equal to its Ro , use the expression for the unity-gain bandwidth in Fig. 10.29 to show that
2μ C (W/L) ft= nox
(b)ForμnCox =400μA/V2,W/L=20,CL =20fF,Cgd = 5 fF, and VA = 10 V, provide in table form ft (GHz), VOV (V), gm (mA/V), ro (k), Ro (M), AM (V/V), and fH (MHz) for ID = 100 μA, 200 μA, and 500 μA.
10.76 Consider a bipolar cascode amplifier biased at a current of 1 mA. The transistors used have β = 100, ro = 100k,Cπ =10pF,Cμ =2 pF,Ccs =0,andrx =50.The amplifier is fed with a signal source having Rsig = 5 k. The load resistance RL = 2 k. Find the low-frequency gain AM , and estimate the value of the 3-dB frequency fH .
*10.77 In this problem we consider the frequency response of the bipolar cascode amplifier in the case that ro can be neglected.
(a) Refer to the circuit in Fig. 10.30, and note that the total resistance between the collector of Q1 and ground will be equal to re2 , which is usually very small. It follows that the pole introduced at this node will typically be at a very high frequency and thus will have negligible effect on fH . It also follows that at the frequencies of interest the gain from the base to the collector of Q1 will be −gm1 re2 ≃ − 1. Use this to find the capacitance at the input of Q1 and hence show that the pole introduced at the input node will have a frequency
fP1≃′1 2πRsig Cπ1 +2Cμ1
Then show that the pole introduced at the output node will have a frequency
fP2≃1 2πRL CL +Ccs2 +Cμ2
(b) Evaluate fP1 and fP2, and use the sum-of-the-squares formula to estimate fH for the amplifier with I = 1 mA, Cπ =10 pF,Cμ =2 pF,Ccs =CL =0,β=100,RL =2 k, and rx = 0 in the following two cases:
(i) Rsig=1k (ii) Rsig = 10 k
10.78 A BJT cascode amplifier uses transistors for which β=100,VA =100V,fT =1GHz,andCμ =0.1pF.Itoperates at a bias current of 0.1 mA between a source with Rsig = rπ and aloadRL =βro.LetCL =Ccs =0,andrx =0.Findtheoverall voltage gain at dc. By evaluating the various components of τH show that the pole introduced at the output mode is dominant. FinditsfrequencyandhenceanestimateoffH andft.
Section 10.6: High-Frequency Response of the Source and Emitter Followers
10.79 A source follower has gm = 5 mA/V, gmb = 0, ro = 20k, Rsig =20k, RL =2k, Cgs =2pF, Cgd = 0.1 pF, and CL = 1 pF. Find AM, Ro, fZ, the frequencies of the two poles, and an estimate of fH .
10.80 Using the expression for the source follower fH in Eq. (10.124) show that for situations in which CL = 0, Rsig
Problems 799
CHAPTER 10 PROBLEMS
2π(CL +Cgd)
ID
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
800 Chapter 10 Frequency Response is large and RL is small,
(c) If the input signal source has a small resistance Rsig and thus the frequency response is determined primarily by the output pole, estimate the 3-dB frequency fH .
(d) If, in a different situation, the amplifier is fed symmetri- cally with a signal source of 40 k resistance (i.e., 20 k in series with each gate terminal), use the open-circuit time-constants method to estimate fH .
10.86 A MOS differential amplifier is biased with a current sourcehavinganoutputresistanceRSS =100kandanoutput capacitanceCSS =1pF.Ifthedifferentialgainisfoundtohave a dominant pole at 20 MHz, what is the 3-dB frequency of the CMRR?
10.87 The differential gain of a MOS amplifier is 100 V/V with a dominant pole at 10 MHz. The common-mode gain is 0.1 V/V at low frequencies and has a transmission zero at 1 MHz. Sketch a Bode plot for the CMRR.
10.88 In a particular MOS differential amplifier design, the
bias current I = 100 μA is provided by a single transistor
operating at VOV = 0.4 V with VA = 40 V and output
capacitance C of 100 fF. What is the frequency of the SS
common-mode gain zero fZ at which Acm begins to rise above its low-frequency value? To meet a requirement for reduced power supply, consideration is given to reducing VOV to 0.2 V while keeping I unchanged. Assuming the current-source capacitance to be directly proportional to the device width, what is the impact on fZ of this proposed change?
fH≃1 2πR C + Cgs
sig gd 1+gmRL′
Find fH for the case Rsig =100k, RL =2k, ro =20k,
gm =5mA/V,Cgd =10pF,andCgs =2pF.
10.81 Refer to Fig. 10.31(c). In situations in which Rsig is large, the high-frequency response of the source follower is determinedbythelow-passcircuitformedbyRsig andtheinput capacitance. An estimate of Cin can be obtained by using the MillerapproximationtoreplaceCgs withaninputcapacitance Ceq = Cgs(1 − K) where K is the gain from gate to source. Using the low-frequency value of K = gm RL′ /(1 + gm RL′ ) find Ceq andhenceCin andanestimateoffH.
10.82 A source follower has a maximally flat gain response with a dc gain of 0.8 and a 3-dB frequency of 1 MHz. Give its transfer function.
10.83 A discrete-circuit source follower driven with Rsig = 100khasCgs =10pF,Cgd =1pF,CL =10pF,gmb =0, and ro very large. The transfer function of the source follower is measured as RL is varied. At what value of RL will the transferfunctionbemaximallyflat?AtthisvalueofRL thedc gain is found to be 0.9 V/V. What is the 3-dB frequency? What is the value of gm at which the source follower is operating?
10.84 For an emitter follower biased at IC = 1 mA, having Rsig = RL = 1 k, and using a transistor specified to have fT =2GHz,Cμ =0.1 pF,CL =0,rx =100,β=100,and VA = 20 V, evaluate the low-frequency gain AM , the frequency of the transmission zero, the pole frequencies, and an estimate of the 3-dB frequency fH .
Section 10.7: High-Frequency Response of Differential Amplifiers
10.85 A MOSFET differential amplifier such as that shown in Fig. 10.34(a) is biased with a current source I = 400 μA. The transistors have W/L = 16, kn′ = 400 μA/V2,VA = 20 V, Cgs =40fF,Cgd =5fF,andCdb =5fF.Thedrainresistors are 10 k each. Also, there is a 100-fF capacitive load between each drain and ground.
(a) Find VOV and gm for each transistor. (b) Find the differential gain Ad .
10.89 Repeat Exercise 10.26 for the situation in which the bias current is reduced to 80 μA and R is raised to 20 k.
CHAPTER 10 PROBLEMS
D
For (d), let Rsig be raised from 20 k to 100 k. (Note: This
is a low-voltage, low-power design.)
10.90 A BJT differential amplifier operating with a 0.5-mA current source uses transistors for which β = 100, fT = 500 MHz, Cμ = 0.5 pF, and rx = 100 . Each of the collector resistances is 10 k, and ro is very large. The amplifier is fed in a symmetrical fashion with a source resistance of 10 k in series with each of the two input terminals.
(a) Sketch the differential half-circuit and its high-frequency equivalent circuit.
(b) Determine the low-frequency value of the overall differ- ential gain.
(c) Use the Miller approximation to determine the input capacitance and hence estimate the 3-dB frequency fH and the gain–bandwidth product.
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
CHAPTER 10 PROBLEMS
10.91 A differential amplifier is biased by a current source having an output resistance of 1 M and an output capacitance of 1 pF. The differential gain exhibits a dominant pole at 2 MHz. What are the poles of the CMRR?
10.92 A current-mirror-loaded MOS differential amplifier is biased with a current source I = 0.2 mA. The two NMOS transistors of the differential pair are operating at VOV = 0.2 V,
Problems 801 Section 10.8: Other Wideband Amplifier
Configurations
10.95 Consider the case of a discrete-circuit CS amplifier in which a source-degeneration resistance is utilized to control the bandwidth. Assume that ro is very large and CL is negligibly small. Adapt the formulas given in the text for this case and thus give the expressions for AM and fH . Let
andthePMOSdevicesofthemirrorareoperatingat|V |=
OV sig m L gs
0.2 V. The Early voltage VAn = VAp = 10 V. The total capacitance at the input node of the mirror is 0.1 pF and that at the output node of the amplifier is 0.2 pF. Find the dc value and the frequencies of the poles and zero of the differential voltage gain.
10.93 Consider the current-mirror-loaded CMOS differen-
R =100k, g =5mA/V, R =5k, C =10pF, and Cgd = 2 pF. Find |AM |, fH , and the gain–bandwidth product for these three cases: Rs = 0, 100 , and 200 .
10.96 A CS amplifier is specified to have gm = 5 mA/V, ro =40 k, Cgs =2pF, ggd =0.1pF, CL =1pF, Rsig =20k,andRL =40k.
(a) Find the low-frequency gain AM, and use open-circuit time constants to estimate the 3-dB frequency fH . Hence determine the gain–bandwidth product.
(b) If a 400- resistance is connected in the source lead, find the new values of A , f , and the gain–bandwidth
MH
product.
D 10.97 (a) Use the approximate expression in Eq. (10.156) to determine the gain–bandwidth product of a CS amplifier with a source-degeneration resistance. Assume Cgd = 0.2 pF and Rsig = 100 k.
(b) If a low-frequency gain of 20 V/V is required, what fH corresponds?
(c)For gm =5mA/V,A0 =100V/V,and RL =20k,find the required value of Rs.
10.98 For the CS amplifier with a source-degeneration resistance Rs, show for Rsig ≫ Rs, ro ≫ Rs, and RL = ro that
tial amplifier of Fig. 10.37(a) for the case of all transistors
operated at the same V and having the same V . Also let OV A
the total capacitance at the output node CL be four times
the total capacitance at the input node of the current mirror
Cm . Give expressions for Ad , fP1 , fP2 , and fZ . Hence show that
fP2/fP1 =4Ad and ft =gm/2πCL. For VA =20 V, VOV =0.2 V,
I =0.2mA, CL =100fF, and Cm =25fF, find the dc value
ofA,andthevalueoff ,f,f ,andf andsketchaBode d P1 t P2 Z
plot for Ad .
*10.94 For the current mirror in Fig. P10.94, derive an expression for the current transfer function Io(s)/Ii(s) taking into account the BJT internal capacitances and neglecting rx and ro. Assume the BJTs to be identical. Observe that a signal ground appears at the collector of Q2. If the mirror is biased at 1 mA and the BJTs at this operating point are characterized by fT = 500 MHz, Cμ = 2 pF, and β0 = 100, find the frequencies of the pole and zero of the transfer function.
AM = −A0 2+k
and
CRA gs sig +CgdRsig 1+ 0
Figure P10.94
M fH, and ft versus k ≡ gmRs for a CS amplifier with a
source-degeneration resistance Rs. The table should have entries for k = 0,1,2,..., 15. The amplifier is specified to have gm = 5mA/V, ro =40k, RL =40k, Rsig = 20k, Cgs =2 pF, Cgd =0.1 pF, and CL =1 pF. Use the formulas
where k ≡ gm Rs
τH ≃
1+(k/2) +C+Cr 1+k
2+k
D *10.99 It is required to generate a table of A ,
L gd o 2+k
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
802 Chapter 10 Frequency Response
for AM and τH given in the statement for Problem 10.98. If
f = 2 MHz is required, find the value needed for R and the H s
corresponding value of AM .
*10.100 In this problem we investigate the bandwidth extension obtained by placing a source follower between the signal source and the input of the CS amplifier.
(a) First consider the CS amplifier of Fig. P10.100(a). Show that
AM=−gmro
τH =CgsRsig +Cgd Rsig 1+gmro +ro +CLro
where CL is the total capacitance between the output node and ground. Calculate the value of AM , fH , and the gain–bandwidth product for the case gm = 1 mA/V,
ro =20k, Rsig =20 k, Cgs =20fF, Cgd =5fF, and CL =10fF.
(b) For the CD−CS amplifier in Fig. P10.100(b), show that
1 +Cgd2 g ∥ro1 1+gm2ro2 +ro2
m1
r o1 gm2ro2
AM =−
τ =C R +C Rsig+ro1 +C
1/gm1 +ro1
H gd1 sig gs1 1 + g r gs2 g o1
1 ∥r m1 o1 m1
+CLro2
the values of AM , fH , and the gain–bandwidth
Calculate
product for the same parameter values used in (a). Compare with the results of (a).
CHAPTER 10 PROBLEMS
*10.101 The transistors in the circuit of Fig. P10.101 have β0 =100, VA =100V, and Cμ =0.2 pF. At a bias current of 100 μA, fT = 200 MHz. (Note that the bias details are not shown.)
I
Vo
I
Vo
Rsig
(a)
Rsig
Q1
(b)
Q2
Vsig
Vsig
I
Figure P10.100
Rsig Vsig
Figure P10.101
100 A
100 A
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
CHAPTER 10 PROBLEMS
(a) Find Rin and the midband gain.
(b) Find an estimate of the upper 3-dB frequency fH . Which
capacitor dominates? Which one is the second most significant?
(Hint: Use the formulas in Example 10.13.)
10.102 Consider the circuit of Fig. P10.102 for the case: I = 200μA and VOV =0.2V, Rsig =100k, RD =50k, Cgs =4 pF, and Cgd =0.5pF. Find the dc gain, the high-frequency poles, and an estimate of fH .
(b)
Figure P10.105(b) shows an amplifier stage suitable for the realization of low gain and wide bandwidth. Transistors Q1 and Q2 have the same channel length L but different widths W1 and W2. They are biased at the same VGS and have the same fT . Use the MOSFET equivalent circuit of Fig. P10.105(a) to model this amplifier stage, assuming that its output is connected to the input of an identical stage. Show that the voltage gain Vo/Vi is given by
VDD
Vo = − G0
Vi 1+s
ωT / G0 + 1 G0=gm1 =W1
gm2 W2
Problems 803
where
RD
Vo
Rsig
Vsig
Figure P10.102
Q1
Q2
I
(a)
10.103 For the amplifier in Fig. 10.41(a), let I = 1 mA, β=120,fT =500MHz,andCμ =0.5pF,andneglectrx and ro . Assume that a load resistance of 10 k is connected to the output terminal. If the amplifier is fed with a signal Vsig having a source resistance Rsig = 12 k, find AM and fH .
10.104 Consider the CD–CG amplifier of Fig. 10.41(c) for the case gm =5mA/V, Cgs =2pF, Cgd =0.1pF, CL (at the output node) = 1 pF, and Rsig = RL = 20 k. Neglecting ro , find AM and fH . (Hint: Evaluate fH directly from the transfer function.)
D **10.105 This problem investigates the use of MOSFETs in the design of wideband amplifiers (Steininger, 1990). Such amplifiers can be realized by cascading low-gain stages.
(a) Show that for the case Cgd ≪ Cgs and the gain of the common-source amplifier is low so that the Miller effect is negligible, the MOSFET can be modeled by the approximate equivalent circuit shown in Fig. P10.105(a), where ωT is the unity-gain frequency of the MOSFET.
(b)
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
Figure P10.105
(c) For L = 0.5μm, W2 =25μm, fT =12 GHz, and μn Co x = 200 μA/V2 , design the circuit to obtain a gain of 3 V/V per stage. Bias the MOSFETs at VOV = 0.3 V. Specify the required values of W1 and I. What is the 3-dB frequency achieved?
804 Chapter 10 Frequency Response
*10.106 Figure P10.106 shows an amplifier formed by **10.107 Consider the BiCMOS amplifier shown in
cascading two CS stages. Note that the input bias voltage Fig. P10.107. The BJT has V = 0.7 V, β = 200, BE
is not shown. Each of Q and Q is operated at an overdrive C = 0.8 pF, and f = 600 MHz. The NMOS transistor has 12μT
voltage of 0.2 V, and VA = 10 V. The transistor capacitances
areasfollows:Cgs =20fF,Cgd =5fF,andCdb =5fF.The signal-source resistance Rsig = 10 k.
(a) Find the dc voltage gain.
(b) Use the method of open-circuit time constants to
Vt =1V,kn′W/L=2mA/V2,andCgs =Cgd =1pF.
(a) Considerthedcbiascircuit.NeglectthebasecurrentofQ2 in determining the current in Q1 . Find the dc bias currents in Q1 and Q2, and show that they are approximately 100 μA and 1 mA, respectively.
(b) Evaluate the small-signal parameters of Q1 and Q2 at their bias points.
(c) Consider the circuit at midband frequencies. First, determine the small-signal voltage gain Vo /Vi . (Note that RG can be neglected in this process.) Then use Miller’s theorem on RG to determine the amplifier input resistance Rin. Finally, determine the overall voltage gain Vo /Vsig. Assume ro of both transistors to be very large.
(d) Consider the circuit at low frequencies. Determine the frequency of the poles due to C1 and C2, and hence estimate the lower 3-dB frequency, fL .
(e) Consider the circuit at higher frequencies. Use Miller’s theorem to replace RG with a resistance at the input. (The one at the output will be too large to matter.) Use open-circuit time constants to estimate fH .
***10.108 In each of the six circuits in Fig. P10.108, let β=100,Cμ =2pF,and fT =400MHz,andneglectrx and ro . Calculate the midband gain AM and the 3-dB frequency fH .
determine an estimate for the 3-dB frequency fH . VDD
CHAPTER 10 PROBLEMS
0.1 mA
Q2
Rsig
Vo 0.1 mA
Q1
Vsig
Figure P10.106
5V
3k
RG
6.8 k
10 M
Q1
C2
Vo
100 k
C1
Vi
1F
Q2
1 k
0.1 F
Vsig
Rin Figure P10.107
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
Problems 805
CHAPTER 10 PROBLEMS
Vo
Vo
Vo
Vsig
Vsig
Vsig
(a)
Vsig
(b)
(c)
Vo
Vsig
Vo
(d)
(e)
Vo
Figure P10.108
Vsig
(f)
CHAPTER 11
Feedback
Introduction 807
11.1 The General Feedback Structure 808
11.2 Some Properties of Negative Feedback 815
11.3 The Feedback Voltage Amplifier 820
11.4 Systematic Analysis of Feedback
VoltageAmplifiers 828
11.5 Other Feedback-Amplifier Types 840
11.6
11.7 11.8
11.9 11.10
Summary of the Feedback-Analysis Method 871
The Stability Problem 871
Effect of Feedback on the Amplifier Poles 875
StabilityStudyUsingBodePlots 885 FrequencyCompensation 889 Summary 895
Problems 896
IN THIS CHAPTER YOU WILL LEARN
1. The general structure of the negative-feedback amplifier and the basic principle that underlies its operation.
2. The advantages of negative feedback, how these come about, and at what cost.
3. The appropriate feedback topology to employ with amplifiers of each of the four
types: voltage, current, transconductance, and transresistance.
4. An intuitive and insightful approach for the analysis of practical feedback-amplifier circuits.
5. Why and how negative-feedback amplifiers can become unstable (i.e., oscillate) and how to design the circuit to ensure stable performance.
Introduction
Most physical systems incorporate some form of feedback. It is interesting to note, though, that the theory of negative feedback has been developed by electronics engineers. In his search for methods for the design of amplifiers with stable gain for use in transatlantic telephone repeaters, Harold Black, an electronics engineer with the Western Electric Company, invented the feedback amplifier in 1928. Since then, the technique has been so widely used that it is almost impossible to think of electronic circuits without some form of feedback, either implicit or explicit. Furthermore, the concept of feedback and its associated theory are currently used in areas other than engineering, such as in the modeling of biological systems.
Feedback can be either negative or positive. In amplifier design, negative feedback is applied to effect one or more of the following goals:
1. Desensitize the gain: that is, make the value of the gain less sensitive to variations in the values of circuit components, such as might be caused by changes in temperature.
2. Reduce nonlinear distortion: that is, make the output proportional to the input (in
other words, make the gain constant, independent of signal level).
3. Reduce the effect of noise: that is, minimize the contribution to the output of unwanted electric signals generated, either by the circuit components themselves
or by extraneous interference.
4. Control the input and output resistances: that is, raise or lower the input and output
resistances by the selection of an appropriate feedback topology.
5. Extend the bandwidth of the amplifier.
807
808 Chapter 11
Feedback
All of the desirable properties above are obtained at the expense of a reduction in gain. It will be shown that the gain-reduction factor, called the amount of feedback, is the factor by which the circuit is desensitized, by which the input resistance of a voltage amplifier is increased, by which the bandwidth is extended, and so on. In short, the basic idea of negative feedback is to trade off gain for other desirable properties. This chapter is devoted to the study of negative-feedback amplifiers: their analysis, design, and characteristics.
Under certain conditions, the negative feedback in an amplifier can become positive and of such a magnitude as to cause oscillation. In fact, in Chapter 18 we will study the use of positive feedback in the design of oscillators and bistable circuits. Here, in this chapter, however, we are interested in the design of stable amplifiers. We shall therefore study the stability problem of negative-feedback amplifiers and their potential for oscillation.
It should not be implied, however, that positive feedback always leads to instability. In fact, positive feedback is quite useful in a number of nonregenerative applications, such as the design of active filters, which are studied in Chapter 17.
Before we begin our study of negative feedback, we wish to remind the reader that we have already encountered negative feedback in a number of applications. Almost all op-amp circuits (Chapter 2) employ negative feedback. Another popular application of negative feedback is the use of the emitter resistance RE to stabilize the bias point of bipolar transistors and to increase the input resistance, bandwidth, and linearity of a BJT amplifier. In addition, the source follower and the emitter follower both employ a large amount of negative feedback. The question then arises about the need for a formal study of negative feedback. As will be appreciated by the end of this chapter, the formal study of feedback provides an invaluable tool for the analysis and design of electronic circuits. Also, the insight gained by thinking in terms of feedback can be extremely profitable.
11.1 The General Feedback Structure 11.1.1 Signal-Flow Diagram
Figure 11.1 shows the basic structure of a feedback amplifier. Rather than showing voltages and currents, Fig. 11.1 is a signal-flow diagram, where each of the quantities x can represent either a voltage or a current signal. The basic amplifier is unilateral and has a gain A, known as the open-loop gain; thus its output xo is related to the input xi by
xo = Axi (11.1)
Σ
Figure 11.1 General structure of the feedback amplifier. This is a signal-flow diagram, and the quantities x represent either voltage or current signals.
A
β
11.1 The General Feedback Structure 809 The feedback network measures or samples the output signal xo and provides a feedback
signal xf that is related to xo by the feedback factor β,
xf =βxo (11.2)
It is assumed that connecting the feedback network to the amplifier output does not change the gain A or the value of xo; that is, the feedback network does not load the amplifier output. Also, the feedback network is unilateral.
The feedback signal xf is subtracted from the source signal xs, which is the input to the completefeedbackamplifier,1 toproducethesignalxi,whichistheinputtothebasicamplifier,
xi = xs − xf (11.3)
Here we note that it is this subtraction that makes the feedback negative. In essence, negative feedback reduces the signal that appears at the input of the basic amplifier. Here, too, we assume that connecting the output of the feedback network to the amplifier input, through the subtractor or differencing circuit, does not change the gain A; that is, the feedback network does not load the amplifier input.
11.1.2 The Closed-Loop Gain
The gain of the feedback amplifier, known as the closed-loop gain or the gain-with-feedback
and denoted Af , is defined as
Combining Eqs. (11.1) through (11.3) provides the following expression for Af :
Af = A (11.4) 1+Aβ
The quantity Aβ is called the loop gain, a name that follows from Fig. 11.1. For the feedback to be negative, the loop gain Aβ must be positive; that is, the feedback signal xf should have the same sign as xs, thus resulting in a smaller difference signal xi. Equation (11.4) indicates that for positive Aβ the gain with feedback Af will be smaller than the open-loop gain A by a factor equal to 1 + Aβ, which is called the amount of feedback.
If, as is the case in many circuits, the loop gain Aβ is large, Aβ ≫ 1, then from Eq. (11.4) it follows that
Af ≃1 (11.5) β
which is a very interesting result: When the loop gain is large, the gain of the feedback amplifier is almost entirely determined by the feedback network. Since the feedback network usually consists of passive components, which usually can be chosen to be as accurate as one wishes, the advantage of negative feedback in obtaining accurate, predictable, and stable gain
1In earlier chapters, we used the subscript “sig” for quantities associated with the signal source (e.g., vsig and Rsig). We did that to avoid confusion with the subscript “s,” which is usually used with FETs to denote quantities associated with the source terminal of the transistor. At this point, however, it is expected that readers have become sufficiently familiar with the subject that the possibility of confusion is minimal. Therefore, we will revert to using the simpler subscript s for signal-source quantities.
Af ≡ xo xs
810 Chapter 11
Feedback
should be apparent. In other words, the overall gain will have very little dependence on the gain of the basic amplifier, A, a desirable property because the gain A is usually a function of many manufacturing and application parameters, some of which might have wide tolerances. We have seen a dramatic illustration of all of these effects in op-amp circuits in Chapter 2, where the closed-loop gain is almost entirely determined by the feedback elements. Generally, we will consider (1/β) to be the ideal value of Af .
Equations (11.1) through (11.3) can be combined to obtain the following expression for the feedback signal x f :
xf = Aβ xs (11.6) 1+Aβ
Thus for Aβ ≫ 1 we see that xf ≃ xs , which implies that the signal xi at the input of the basic amplifier is reduced to almost zero. Thus if a large amount of negative feedback is employed, thefeedbacksignalxf becomesanalmostidenticalreplicaoftheinputsignalxs.Thedifference between xs and xf , which is xi , is sometimes referred to as the error signal.2 Accordingly, the input differencing circuit is often also called a comparison circuit. (It is also known as a mixer.) An expression for xi can be easily determined as
xi = 1 xs (11.7) 1+Aβ
from which we can verify that for Aβ ≫ 1, xi becomes very small. An outcome of this property is the tracking of the two input terminals of an op amp. Observe that negative feedback reduces the signal that appears at the input terminals of the basic amplifier by the amount of feedback (1 + Aβ). As will be seen later, it is this reduction of input signal that results in the increased linearity of the feedback amplifier.3
11.1.3 The Loop Gain
From the discussion above we see that the loop gain Aβ is a very important—in fact, the most important—characteristic parameter of a feedback amplifier:
1. The sign of Aβ determines the polarity of the feedback; the loop gain Aβ must be positive for the feedback to be negative.
2. The magnitude of Aβ determines how close the closed-loop gain Af is to the ideal value of 1/β.
3. The magnitude of Aβ determines the amount of feedback (1 + Aβ ) and hence, as we shall see in the next section, the magnitude of the various improvements in amplifier performance resulting from the negative feedback.
4. As we shall see in later sections, the inevitable variation of Aβ with frequency can cause Aβ to become negative, which in turn can cause the feedback amplifier to become unstable. It follows that the design of a stable feedback amplifier may involve modifying the frequency behaviors of its loop gain Aβ appropriately (Section 11.10).
2This terminology is more common in feedback control systems than in feedback amplifiers.
3We have in fact already seen examples of this: adding a resistance Re in the emitter of a CE amplifier (or a resistance Rs in the source of a CS amplifier) increases the linearity of these amplifiers because for the same input signal as before, vbe and vgs are now smaller (by the amount of feedback).
0
xr xt
A
11.1 The General Feedback Structure 811
β
The significance of the loop gain requires us to consider its determination. Reference to Fig. 11.1 indicates that the value of the loop gain Aβ can be determined as follows:
1. Setxs=0.
2. Break the feedback loop at a convenient location, ensuring that the values of A and
β do not change. Since we assumed that the feedback network does not load the amplifier output, we can break the loop at the amplifier output (see Fig. 11.2) without causing A to change.
3. Apply a test signal xt to the input of the loop (where the break has been made) and determinethereturnedsignalxr attheloopoutput(i.e.,attheothersideofthebreak). From Fig. 11.2 we see that
xr =−Aβxt and the loop gain Aβ is obtained as
Aβ = − xr (11.8) xt
We observe that since Aβ is positive, the returned signal xr will be out of phase with the test signal xt, verifying that the feedback is indeed negative. In fact, this approach is used qualitatively to ascertain the polarity of the feedback. We will have a lot more to say about the loop gain in subsequent sections.
Example 11.1
The noninverting op-amp configuration shown in Fig. 11.3(a) provides a direct implementation of the feedback loop of Fig. 11.1.
(a) Assume that the op amp has infinite input resistance and zero output resistance. Find an expression for the feedback factor β.
(b) Find the condition the open-loop gain A must satisfy so that the closed-loop gain Af is almost entirely determined by the feedback network. Also, give the value of Af in this case.
Figure 11.2 Determining the loop gain by breaking the feedback loop at the output of the basic amplifier, applying a test signal xt , and measuring the returned signal xr : Aβ ≡ −xr /xt .
812
Chapter 11 Feedback
Example 11.1 continued
Vo
Vi
AVi
Vs
Vs A Vo
R2
R2
(b)
R1
Vf R1
(a)
Figure11.3 (a)Anoninvertingop-ampcircuitforExample11.1.(b)Thecircuitin(a)withtheopampreplaced with its equivalent circuit.
(c) If the open-loop gain A = 104 V/V, find R2 /R1 to obtain a closed-loop gain Af of 10 V/V. (d) What is the amount of feedback in decibels?
(e) IfVs =1V,findVo,Vf,andVi.
(f) If A decreases by 20%, what is the corresponding decrease in Af ? Solution
(a) TobeabletoseemoreclearlythedirectcorrespondencebetweenthecircuitinFig.11.3(a)andtheblock diagram in Fig. 11.1, we replace the op amp with its equivalent-circuit model, as shown in Fig. 11.3(b). Since the op amp is assumed to have infinite input resistance and zero output resistance, its model is simply an ideal voltage-controlled voltage source of gain A. From Fig. 11.3(b) we observe that the feedback network, consisting of the voltage divider (R1 , R2 ), is connected directly to the output and feeds asignalVf totheinvertinginputterminaloftheopamp.Itisimportantatthispointtonotethatthezero output resistance of the op amp causes the output voltage to be AVi irrespective of the values of R1 and R2 . That is what we meant by the statement that in the block diagram of Fig. 11.1, the feedback network is assumed to not load the basic amplifier. Now we can easily determine the feedback factor β from
β≡Vf = R1
Vo R1 +R2
Let’s next examine how Vf is subtracted from Vs at the input side. The subtraction is effectively performed by the differential action of the op amp; by its very nature, a differential-input amplifier takes the difference between the signals at its two input terminals. Observe also that because the input resistance of the op amp is assumed to be infinite, no current flows into the negative input terminal of the op amp and that the feedback network does not load the amplifier at the input side.
(b) The closed-loop gain Af is given by
Af= A 1+Aβ
To make Af nearly independent of A, we must ensure that the loop gain Aβ is much larger than unity Aβ ≫ 1
in which case
Thus,
or equivalently,
and
Af ≃1/β A/Af ≫1 A≫Af
Af ≃1=1+R2 β R1
11.1 The General Feedback Structure 813
(c)ForA=104 V/VandAf =10V/V,weseethatA≫Af,thuswecanselectR1 andR2 toobtain β≃ 1 =0.1
Thus,
which yields
Af
1=1+R2 =Af =10 β R1
R2/R1 =9
A more exact value for the required ratio R2/R1 can be obtained from
which results in
and,
Af= A 1+Aβ
10= 104 1+104β
β = 0.0999
R2 = 9.01 R1
814
Chapter 11 Feedback
Example 11.1 continued
(d) The amount of feedback is
which is 60 dB. (e)ForVs =1V,
A
1 + Aβ =
Af
=
104 10
= 1000
the value of Af becomes
A=0.8×104 V/V
0.8 × 104
Af = 1+0.8×104 ×0.0999 =9.9975V/V
Vo =AfVs =10×1=10V
Vf =βVo =0.0999×10=0.999V
V = Vo = 10 = 0.001 V i A 104
Note that if we had used the approximate value of β = 0.1, we would have obtained Vf = 1 V and Vi = 0 V.
(f) If A decreases by 20%, thus becoming
that is, it decreases by 0.025%, which is less than the percentage change in A by approximately a factor (1 + Aβ).
EXERCISES
11.1 RepeatExample11.1(c)to(f)forA=100V/V.
Ans. (c) 10.11; (d) 20 dB; (e) 10 V, 0.9 V, 0.1 V; (f) 2.44%
11.2 Repeat Example 11.1 (c) to (f) for Af = 103 V/V. For (e) use Vs = 0.01 V. Ans. (c) 1110.1; (d) 20 dB; (e) 10 V, 0.009 V, 0.001 V; (f) 2.44%
11.1.4 Summary
We conclude this section by presenting in Table 11.1 a summary of the important parameters and formulas that characterize the ideal negative-feedback amplifier structure of Fig. 11.1.
Assume that β is constant. Taking differentials of both sides of Eq. (11.4) results in
dA = dA (11.9)
11.2 Some Properties of Negative Feedback 815
Table 11.1 Summary of the Parameters and Formulas for the Ideal Feedback-Amplifier Structure of Fig. 11.1
• Open-loop gain ≡ A
• Feedback factor ≡ β
• Loop gain ≡ Aβ (positive number)
• Amount of feedback ≡ 1 + Aβ
• Closed-loop gain ≡ Af = xo = A
xs 1+Aβ
• Feedback signal ≡ xf = Aβ xs 1+Aβ
• Input signal to basic amplifier ≡ xi = 1 xs 1+Aβ
• Closed-loop gain as a function of the ideal value 1 : Af = 1 1
β β 1+1/Aβ
• For large loop gain, Aβ ≫ 1,
Af ≃ 1 xf ≃xs xi ≃0
β
11.2 Some Properties of Negative Feedback
The properties of negative feedback were mentioned in the introduction. In the following, we shall consider some of these properties in more detail.
11.2.1 Gain Desensitivity
The effect of negative feedback on desensitizing the closed-loop gain was demonstrated in Example 11.1, where we saw that a 20% reduction in the gain of the basic amplifier gave rise to only a 0.025% reduction in the gain of the closed-loop amplifier. This sensitivity-reduction property can be analytically established as follows.
f (1+Aβ)2 Dividing Eq. (11.9) by Eq. (11.4) yields
dAf = 1 dA (11.10) Af (1+Aβ) A
which says that the percentage change in Af (due to variations in some circuit parameter) is smaller than the percentage change in A by a factor equal to the amount of feedback. For this reason, the amount of feedback, 1 + Aβ, is also known as the desensitivity factor.
816 Chapter 11 Feedback
EXERCISE
11.3 An amplifier with a nominal gain A = 1000 V/V exhibits a gain change of 10% as the operating temperature changes from 25°C to 75°C. If it is required to constrain the change to 0.1% by applying negative feedback, what is the largest closed-loop gain possible? If three of these feedback amplifiers are placed in cascade, what overall gain and gain stability are achieved?
Ans. 10 V/V; 1000 V/V, with a maximum variability of 0.3% over the specified temperature range.
11.2.2 Bandwidth Extension
Consider an amplifier whose high-frequency response is characterized by a single pole. Its gain at mid and high frequencies can be expressed as
A(s) = AM (11.11) 1+s/ωH
where AM denotes the midband gain and ωH is the upper 3-dB frequency. Application of negative feedback, with a frequency-independent factor β, around this amplifier results in a closed-loop gain Af (s) given by
Af (s) = A(s)
1 + βA(s)
Substituting for A(s) from Eq. (11.11) results, after a little manipulation, in
Af (s)= AM/(1+AMβ) (11.12)
frequency ωHf given by
ωHf =ωH(1+AMβ) (11.13)
It follows that the upper 3-dB frequency is increased by a factor equal to the amount of feedback.
Similarly, it can be shown that if the open-loop gain is characterized by a dominant low-frequency pole giving rise to a lower 3-dB frequency ωL , then the feedback amplifier will have a lower 3-dB frequency ωLf ,
ωLf = ωL (11.14) 1+AMβ
Note that the amplifier bandwidth is increased by the same factor by which its midband gain is decreased, maintaining the gain–bandwidth product at a constant value. This point is further illustrated by the Bode plot in Fig. 11.4.
Finally, note that the action of negative feedback in extending the amplifier bandwidth should not be surprising: Negative feedback works to minimize the change in gain magnitude, including its change with frequency.
1+s/ωH(1+AMβ)
Thus the feedback amplifier will have a midband gain of AM /(1 + AM β ) and an upper 3-dB
20 log (1
AM b)
20 dB/decade
A
11.2
Some Properties of Negative Feedback 817
Gain 20 log (AM) (dB)
20 dB/decade
20 log (AMf)
log (1 AM b)
Af
log (1 AM b)
fLf
f fL
Lf 1 AMb
fL
fH
fHf
f (log scale)
AM AMf 1 AMb
ff(1Ab) Hf H M
Figure 11.4 Application of negative feedback reduces the midband gain, increases fH , and reduces fL , all by the same factor, (1 + AM β ), which is equal to the amount of feedback.
EXERCISE
11.4 Consider the noninverting op-amp circuit of Example 11.1. Let the open-loop gain A have a low-frequency value of 104 and a uniform –6-dB/octave rolloff at high frequencies with a 3-dB frequency of 100 Hz. Find the low-frequency gain and the upper 3-dB frequency of a closed-loop amplifierwithR1 =1kandR2 =9k.
Ans. 9.99 V/V; 100.1 kHz
11.2.3 Interference Reduction
Negative feedback can be employed to reduce the interference in an amplifier or, more precisely, to increase the ratio of signal to interference. However, as we shall now explain, this interference-reduction process is possible only under certain conditions. Consider the situation illustrated in Fig.11.5. Figure11.5(a) shows an amplifier with gain A1, an input signal Vs, and interference, Vn. It is assumed that for some reason this amplifier suffers from interference and that the interference can be assumed to be introduced at the input of the amplifier. The signal-to-interference ratio for this amplifier is
S/I = Vs/Vn (11.15)
Consider next the circuit in Fig. 11.5(b). Here we assume that it is possible to build another amplifier stage with gain A2 that does not suffer from the interference problem. If this is the
818 Chapter 11
Feedback
(a)
(b)
Figure 11.5 Illustrating the application of negative feedback to improve the signal-to-interference ratio in amplifiers.
case, then we may precede our original amplifier A1 by the clean amplifier A2 and apply negative feedback around the overall cascade of such an amount as to keep the overall gain unchanged. The output voltage of the circuit in Fig. 11.5(b) can be found by superposition:
A1
A2
V =V A1A2 +V A1
o s 1+A1A2β n 1+A1A2β
Thus the signal-to-interference ratio at the output becomes S = Vs A2
I Vn
(11.16)
(11.17)
A1
which is A2 times higher than in the original case.
We emphasize once more that the improvement in signal-to-interference ratio by the
application of feedback is possible only if one can precede the interference-prone stage by a (relatively) interference-free stage. This situation, however, is not uncommon in practice. The best example is found in the output power-amplifier stage of an audio amplifier. Such a stage usually suffers from a problem known as power-supply hum. The problem arises because of the large currents that this stage draws from the power supply and because it is difficult to provide adequate power-supply filtering inexpensively. The power-output stage is required to provide large power gain but little or no voltage gain. We may therefore precede the power-output stage by a small-signal amplifier that provides large voltage gain and then apply a large amount of negative feedback, thus restoring the voltage gain to its original value. Since the small-signal amplifier can be fed from another, less hefty (and hence better regulated) power supply, it will not suffer from the hum problem. The
11.2 Some Properties of Negative Feedback 819 hum at the output will then be reduced by the amount of the voltage gain of this added
preamplifier.
EXERCISE
11.5 Consider a power-output stage with voltage gain A1 = 1, an input signal Vs = 1 V, and a hum Vn of 1 V. Assume that this power stage is preceded by a small-signal stage with gain A2 = 100 V/V and that overall feedback with β = 1 is applied. If Vs and Vn remain unchanged, find the signal and interference voltages at the output and hence the improvement in S/I.
Ans. ≃1 V; ≃0.01 V; 100 (40 dB)
11.2.4 Reduction in Nonlinear Distortion
Curve (a) in Fig. 11.6 shows the transfer characteristic vO versus vI of an amplifier. As indicated, the characteristic is piecewise linear, with the voltage gain changing from 1000 to 100 and then to 0. This nonlinear transfer characteristic will result in this amplifier generating a large amount of nonlinear distortion.
The amplifier transfer characteristic can be considerably linearized (i.e., made less nonlinear) through the application of negative feedback. That this is possible should not be too surprising, since we have already seen that negative feedback reduces the dependence of the overall closed-loop amplifier gain on the open-loop gain of the basic amplifier. Thus large
vI, vS (V)
Figure11.6 Illustratingtheapplicationofnegativefeedbacktoreducethenonlineardistortioninamplifiers. Curve (a) shows the amplifier transfer characteristic (vO versus vI ) without feedback. Curve (b) shows the characteristic (v O versus v S ) with negative feedback (β = 0.01) applied.
820 Chapter 11
Feedback
changes in open-loop gain (1000 to 100 in this case) give rise to much smaller corresponding changes in the closed-loop gain.
To illustrate, let us apply negative feedback with β = 0.01 to the amplifier whose open-loop voltage transfer characteristic is depicted in Fig. 11.6. The resulting transfer characteristic of theclosed-loopamplifier,vO versusvS,isshowninFig.11.6ascurve(b).Heretheslopeof the steepest segment is given by
Af1 = 1000 =90.9 1+1000×0.01
and the slope of the next segment is given by
Af2 = 100 =50
Thus the order-of-magnitude change in slope has been considerably reduced. The price paid, of course, is a reduction in voltage gain. Thus if the overall gain has to be restored, a preamplifier should be added. This preamplifier should not present a severe nonlinear-distortion problem, since it will be dealing with smaller signals.
Finally, it should be noted that negative feedback can do nothing at all about amplifier saturation, since in saturation the gain is very small (almost zero) and hence the amount of feedback is almost unity.
11.3 The Feedback Voltage Amplifier
Based on the quantity to be amplified (voltage or current) and on the desired form of output (voltage or current), amplifiers can be classified into four categories. These categories were discussed in Chapter 1. In this section we study the most common amplifier type: the voltage amplifier. We begin by identifying the appropriate configuration for applying negative feedback to a voltage amplifier. Then, we present a simple method for the analysis of the feedback voltage amplifier. The method makes use of the loop gain Aβ, whose determination was discussed in Section 11.1.3.
11.3.1 The Series–Shunt Feedback Topology
Voltage amplifiers are intended to amplify an input voltage signal and provide an output voltage signal. The voltage amplifier is essentially a voltage-controlled voltage source. The input resistance is required to be high, and the output resistance is required to be low. Since the signal source is essentially a voltage source, it is appropriately represented in terms of a The ́venin equivalent circuit. As the output quantity of interest is the output voltage, the feedback network should sample the output voltage, just as a voltmeter measures a voltage. Also, because of the The ́venin representation of the source, the feedback signal xf should be a voltage that can be mixed with the source voltage in series.
From the discussion above, it follows that the most suitable feedback topology for the voltage amplifier is the voltage-mixing, voltage-sampling one shown in Fig. 11.7. Because of the series connection at the input and the parallel or shunt connection at the output, this feedback topology is also known as series–shunt feedback. As will be shown, this topology not only stabilizes the voltage gain Vo/Vs but also results in a higher input resistance Rin (intuitively, a result of the series connection at the input) and a lower output resistance Rout
1+100×0.01
Basic voltage amplifier
Vs
Rs
Rin
Vf
1
RL Vo
Rout
11.3 The Feedback Voltage Amplifier 821
Feedback network
Figure 11.7 Block diagram of a feedback voltage amplifier. Here the appropriate feedback topology is series–shunt.
(intuitively, a result of the parallel connection at the output), which are desirable properties for a voltage amplifier.
The increased input resistance results because Vf subtracts from Vs, resulting in a smaller signal Vi at the input of the basic amplifier. The lower Vi, in turn, causes the input current to be smaller, with the result that the resistance seen by Vs will be larger. We shall derive a formula for the input resistance of the feedback voltage amplifier in the next section.
The decreased output resistance results because the feedback works to keep Vo as constant as possible. Thus if the current drawn from the amplifier output changes by Io, the change Vo in Vo will be lower than it would have been if feedback were not present. Thus the output resistance Vo /Io will be lower than that of the open-loop amplifier. In the following section we shall derive an expression for the output resistance of the feedback voltage amplifier.
11.3.2 Examples of Series–Shunt Feedback Amplifiers
Three examples of series–shunt feedback amplifiers are shown in Fig. 11.8. The amplifier in Fig. 11.8(a) is the familiar noninverting op-amp configuration. The feedback network, composed of the voltage divider (R1, R2), develops a voltage Vf that is applied to the negative input terminal of the op amp. The subtraction of Vf from Vs is achieved by utilizing the differencing action of the op-amp differential input. For the feedback to be negative, Vf must be of the same polarity as Vs, thus resulting in a smaller signal at the input of the basic amplifier. To ascertain that this is the case, we follow the signal around the loop, as follows: As Vs increases, Vo increases and the voltage divider causes Vf to increase. Thus the change in Vf is of the same polarity as the change in Vs, and the feedback is negative.
The second feedback voltage amplifier, shown in Fig. 11.8(b), utilizes two MOSFET amplifier stages in cascade. The output voltage Vo is sampled by the feedback network composed of the voltage divider (R1, R2), and the feedback signal Vf is fed to the source terminal of Q1. The subtraction is implemented by applying Vs to the gate of Q1 and Vf to its source, with the result that the signal at this amplifier input Vi = Vgs = Vs − Vf . To ascertain that the feedback is negative, let Vs increase. The drain voltage of Q1 will decrease, and since this is applied to the gate of Q2, its drain voltage Vo will increase. The feedback network will
2
822 Chapter 11
Feedback
Vi
Vf
VDD
RD2
RD1
Vf
VDD RD
Vo
Q1
Vi
Vs
Vo
Vs
(a)
(b)
Vs
Q Vo Vi
(c)
Figure 11.8 Examples of a feedback voltage amplifier. All these circuits employ series–shunt feedback. Note that the dc bias circuits are only partially shown.
then cause Vf to increase, which is the same polarity initially assumed for the change in Vs. Thus the feedback is indeed negative.
The third example of series–shunt feedback, shown in Fig. 11.8(c), utilizes a CG transistor Q with a fraction Vf of the output voltage Vo fed back to the gate through a voltage divider (R1, R2). Observe that the subtraction of Vf from Vs is effected by applying Vs to the source, thus the input Vi to the CG amplifier is obtained as Vs − Vf . As usual, however, we must check the polarity of the feedback: If Vs increases, Vd (which is Vo) will increase and Vf will correspondingly increase. Thus Vf and Vs change in the same direction, verifying that the feedback is negative.
Q2
R2 R1
R2
R1
R2
Vf R1
11.3 The Feedback Voltage Amplifier 823
FEEDBACK— HISTORICAL NOTE:
The idea of feedback as an element of self-regulating behavior dates back to the eighteenth century, but the term itself did not appear in the context of a discussion on economics until the 1860s. Still later, in 1909, Karl Ferdinand Braun, a German physicist working at the University of Strasbourg, referred publicly to feedback as an undesired coupling between components of a vacuum-tube electronic system. The occasion was the lecture Braun delivered as a recipient of the Nobel Prize in Physics, shared with Guglielmo Marconi (often solely credited as the inventor of radio).
In 1927, Harold Black, at Bell Labs, invented the negative-feedback amplifier, which he described in detail in a seminal paper, “Stabilized Feedback Amplifiers,” published in 1934. This invention was motivated by the need to provide low-distortion amplifiers that could be concatenated in long-distance transcontinental telephone circuits.
11.3.3 Analysis of the Feedback Voltage Amplifier Utilizing the Loop Gain
The feedback analysis method studied in Section 11.1 cannot be directly applied to a practical feedback voltage amplifier such as those in Fig. 11.8. This is because the analysis method of Section 11.1 is predicated on the assumption that the feedback network does not load the basic amplifier. Unfortunately, this assumption does not hold in most practical amplifier circuits. As shown in the circuits of Fig. 11.8, the feedback network is a simple resistive circuit that obviously loads the basic amplifier. As an example, in the circuit of Fig. 11.8(b), the values of the resistances R2 and R1, which comprise the feedback network, affect the gain of the common-source stage Q2, which is part of the basic amplifier. Also, the value of the feedback-network resistance R1 affects the gain of the Q1 amplifier stage, which is part of the basic amplifier. It follows that we cannot easily disassemble a practical amplifier circuit to determine A and β and thus be able to use the feedback formulas of Sections 11.1 and 11.2.
While it is not easy to determine A and β, their product, the loop gain Aβ, can always be determined using the method presented in Section 11.1.3. Also, we can easily obtain the value of β by identifying and isolating the feedback network (e.g., the resistive divider (R1,R2) in each of the circuits in Fig. 11.8). We can then use the values of Aβ and β to determine A and Af . This loop-gain method is simple, and we shall use it in this section to perform the analysis of the feedback voltage amplifier. The method, however, has limitations that will be mentioned later. A more accurate and systematic approach for the analysis of feedback voltage amplifiers will be presented in the next section.
The loop-gain analysis method comprises four steps:
1. Identify the feedback network and use it to determine the value of β.
2. Determine the ideal value of the closed-loop gain Af as 1/β. This value of Af is approached when Aβ ≫ 1. The ideal or upper-bound value of Af can be used in the initial design of the feedback amplifier. It also serves as a check on the actual value
of Af calculated below.
3. Use the method described in Section 11.1.3 to determine the loop gain Aβ. Recall
that in breaking the loop, care should be taken to not change the conditions in the loop. Thus, if we break a feedback loop at XX′, as shown in Fig. 11.9(a), and apply a test voltage Vt to the terminals thus created to the left of XX′, the terminals to the right of XX′ must be connected to an impedance Zt. The value of Zt is equal
824 Chapter 11
Feedback
X
X' (a)
Zt
Vt
Vr
determine the closed-loop gain Af from
Af= A
Zt
A Vr / Vt
(b)
Figure11.9 Breakingtheconceptualfeedbackloopin(a)todeterminetheloopgainrequiresthetermination of the loop as shown in (b), to ensure that the loop conditions do not change.
to the impedance previously seen looking to the left of XX′. The loop gain is then determined from
Aβ = − Vr Vt
Whenever possible, we should break the loop at a location where Zt is infinite.
4. Use the value of Aβ together with that of β to determine the open-loop gain A. Then,
1+Aβ
We shall illustrate the application of the loop-gain method via two examples.
Example 11.2
For the series–shunt feedback amplifier of Fig. 11.8(b), neglect the MOSFETs’ ro and
(a) give the feedback network (β circuit) and an expression for β. Also give an expression for the ideal or upper-bound value of the closed-loop gain Af .
(b) find the ratio R2 /R1 that results in an ideal closed-loop gain of 10 V/V. If R1 = 1 k, what value must R2 have?
(c) find an expression for the loop gain Aβ.
(d) ifgm1 =gm2 =4mA/VandRD1 =RD2 =10k,determinethevaluesofAβ,A,andAf.
11.3
The Feedback Voltage Amplifier 825
RD1
Id1
RD2
Id2
Q2
Q1 Id1
Vr Vt
R2
(b)
I1
R2
1/gm1
f o R1
VR1 V (a)
Figure 11.10 Determining: (a) the feedback factor β; and (b) the loop gain Aβ for the feedback voltage amplifier of Fig. 11.8(b).
Solution
(a) The feedback network is highlighted in Fig. 11.8(b) and is redrawn in Fig. 11.10(a). It is a simple resistive voltage divider. Thus,
β=Vf = R1 Vo R1 +R2
ForAβ≫1,theclosed-loopgainAf =Vo/Vs isgivenby Af ≃1=1+R2
β R1 This is the ideal or upper-bound value of Af .
(b) For Af to have an ideal value of 10,
Thus,
10 = 1 + R2 R1
R2 =9 R1
ForR1 =1k,R2 =9k.
(c) To determine the loop gain, we set Vs = 0. Examining the feedback loop reveals that it is most
convenient to break the loop at the connection between the drain of Q1 and the gate of Q2. This is
826
Chapter 11 Feedback
Example 11.2 continued
because of the infinite input impedance at the gate of Q2 . The resulting circuit is shown in Fig. 11.10(b),
forwhichtheanalysistodetermineAβ≡−Vr/Vt proceedsasfollows: Id2 =gm2Vt
I 1 = − I d 2
RD2 +R2 +
I=I R1
d1 1 1
R1 + gm1 Vr =Id1RD1
Combining these four equations results in
1 R1gm1
RD2
Vr 1R1 Aβ≡−V =(gm1RD1)(gm2RD2)1+g R 1
(d)
Since
and
t
Aβ = 4 × 10 × 4 × 10 × = 16.67
m1 1 RD2 +R2 + R1gm1
1 × 1 1+4×1 10+9+(1 1)
β= R1 R1 +R2
= 1 =0.1 1+9
4
A= Aβ = 16.67 =166.7V/V β 0.1
A = 166.7 = 166.7 =9.43V/V 1+Aβ 1+16.67 17.67
In the series–shunt feedback amplifier of Fig.11.11(a), the op amp has an input resistance Rid, an open-circuit voltage gain μ, and an output resistance ro. Find expressions for β, the ideal value of Af ≡Vo/Vs,andtheloopgainAβ.
Af =
which, given that the loop gain (16.67) is only moderately high, is reasonably close to the ideal value
of 10 V/V.
Example 11.3
11.3 TheFeedbackVoltageAmplifier 827
Rs
ro
Vo
mV1
(b)
Rs
Rid
V1
Vs
(a)
Rs
(c)
Figure 11.11 Example 11.3. (a) A series–shunt feedback amplifier; (b) the feedback loop obtained by setting Vs = 0 and replacing the op amp with its equivalent-circuit model; (c) breaking the feedback loop to determine the loop gain Aβ =−Vr/Vt.
Solution
The feedback network consists of the voltage divider (R1,R2), thus β= R1
R1 +R2
Af =1=1+R2
To determine the loop gain, we set Vs = 0 and replace the op amp with its equivalent-circuit model. The resulting circuit is shown in Fig. 11.11(b). Next, we break the loop to apply a test voltage Vt while terminating the loop at the break in an impedance equal to that seen prior to breaking the loop. The resulting circuit is shown in Fig. 11.11(c), where the loop has been broken at the input terminals of the op amp and the left-hand-side terminals are connected to a resistance equal to Rid . Analysis of the circuit to determine
and the ideal value of Af is
β R1
828
Chapter 11 Feedback
Example 11.3 continued
Aβ≡−Vr/Vt involvesrepeatedapplicationofthevoltagedividerrule,resultingin
Aβ=μ {RL∥[R2 +R1∥(Rid +Rs)]} × {RL ∥[R2 +R1 ∥(Rid +Rs)]}+ro
[R1∥(Rid +Rs)] × Rid [R1 ∥(Rid +Rs)]+R2 Rid +Rs
EXERCISE
11.6 For the feedback voltage amplifier of Fig. 11.8(c):
(a) Find an expression for β.
(b) Neglecting the MOSFET ro, find an expression for the loop gain Aβ. (Hint: Break the loop at the gate
of Q.)
(c) Find an expression for the open-loop gain A.
(d) Forgm =4mA/V,RD =10k,R1 =20k,andR2 =80k,findthevaluesofβ,Aβ,A,andthe
closed-loop gain Af . What would Af be if Aβ were much greater than unity?
Ans. (a)
R1 ; (b) g RDR1 ; (c) g RD(R1 +R2) ; (d) 0.2, 7.27, 36.36 V/V, 4.4 V/V, 5 V/V. R +R m R +R +R m R +R +R
11.3.4 A Final Remark
The loop-gain analysis method, though simple, is not complete: It does not enable us to find the input and output resistances of the feedback amplifier. This shortcoming is remedied in the next section, where we present a systematic approach to the analysis of feedback voltage amplifiers.
11.4 Systematic Analysis of Feedback Voltage Amplifiers
In this section we provide a systematic procedure for the analysis of feedback voltage amplifiers. The procedure essentially disassembles a given feedback voltage-amplifier circuit so as to obtain the “A circuit,” from which we can determine the open-loop gain A and other parameters of the open-loop amplifier, such as the input and output resistances, and the “β circuit” from which the value of the feedback factor β can be found. We can then use the
12 D12 D12
feedback formulas to determine the characteristic parameters of the feedback amplifier, such as the closed-loop gain Af and the input and output resistances with feedback.
Our approach will be to first consider the ideal case in which the feedback network does not load the basic amplifier. Then, we consider the practical case in which not only does the feedback network load the basic amplifier, but also there is a finite source resistance Rs and a finite load resistance RL .
11.4.1 The Ideal Case
As mentioned before, series–shunt is the appropriate feedback topology for a voltage amplifier.The ideal structure of the series–shunt feedback amplifier is shown in Fig. 11.12(a). It consists of a unilateral open-loop amplifier (the A circuit) and an ideal voltage-sampling, voltage-mixing feedback network (the β circuit). The A circuit has an input resistance Ri , an open-circuit voltage gain A, and an output resistance Ro. It is assumed that the source is ideal with a zero resistance and that there is no load resistance. Furthermore, note that the β circuit
11.4 Systematic Analysis of Feedback Voltage Amplifiers 829
Ro Vi Ri AVi
Rif
Rof
Rof Rif Af Vs
SO
Vs Vo SO
(b)
Figure 11.12 The series–shunt feedback amplifier: (a) ideal structure; (b) equivalent circuit.
(a)
830 Chapter 11
Feedback
does not load the A circuit; that is, connecting the β circuit does not change the value of A (defined as A ≡ Vo /Vi ).
The circuit of Fig.11.12(a) exactly follows the ideal feedback model of Fig.11.1. Therefore the closed-loop voltage gain Af is given by
Af ≡ Vo = A (11.18) Vs 1+Aβ
The equivalent-circuit model of the series–shunt feedback amplifier is shown in Fig. 11.12(b). Observe that Af is the open-circuit voltage gain of the feedback amplifier, Ri f is its input resistance, and Rof is its output resistance. Expressions for Ri f and Rof can be derived as follows.
For Ri f , refer to the input loop of the circuit in Fig. 11.12(a). The series mixing subtracts Vf from Vs and thus reduces Vi by a factor equal to the amount of feedback (Eq. 11.7),
Thus the input current Ii becomes
Vi= Vs 1+Aβ
Ii = Vi = Vs
Ri (1 + Aβ)Ri
Since Ii is the current drawn from Vs , the input resistance Ri f Rif ≡Vs
can be expressed as
(11.19)
(11.20)
and using Eq. (11.19) is found to be
Ii
Rif =(1+Aβ)Ri
Thus, as expected, the series-mixing feedback results in an increase in the amplifier input resistance by a factor equal to the amount of feedback, (1 + Aβ ), a highly desirable property for a voltage amplifier.
To determine the output resistance Rof of the feedback amplifier in Fig. 11.12(a), we set Vs = 0 and apply a test voltage Vx between the output terminals, as shown in Fig. 11.13. If the current drawn from Vx is Ix , the output resistance Rof is
An equation for the output loop yields
Rof ≡ Vx Ix
Ix = Vx − AVi Ro
Vi =−Vf Vi =−βVx
(11.21)
(11.22)
From the input loop we see that
NowVf =βVo=βVx;thus,
S
S
Vi Ri
11.4
Systematic Analysis of Feedback Voltage Amplifiers 831 Ix
Vx
Vf
Figure11.13 DeterminingtheoutputresistanceofthefeedbackamplifierofFig.11.12(a):Rof =Vx/Ix. which when substituted in Eq. (11.22) yields
Ix = Vx(1+Aβ) Ro
Substituting this value of Ix into Eq. (11.21) provides the following expression for Rof ,
Rof = Ro (11.23)
1+Aβ
Thus, as expected, the shunt sampling (or voltage sampling) at the output results in a decrease in the amplifier output resistance by a factor equal to the amount of negative feedback, (1 + Aβ ), another highly desirable property for a voltage amplifier.
Although perhaps not entirely obvious, the reduction of the output resistance is a result only of the method of sampling the output and does not depend on the method of mixing. Thus, the transistance amplifier, which is the other amplifier type in which shunt (or voltage) sampling is employed, will also exhibit a reduced output resistance.
11.4.2 The Practical Case
In a practical series–shunt feedback amplifier, the feedback network will not be an ideal voltage-controlled voltage source. Rather, as in the circuits of Fig. 11.8, the feedback network is usually resistive and hence will load the basic amplifier and thus affect the values of A, Ri, and Ro. In addition, there will be finite source and load resistances, which in turn will affect these three parameters. Thus the problem we have is as follows: Given a series–shunt feedback amplifier represented by the block diagram of Fig. 11.14(a), find the A circuit and the β circuit.
The problem in essence is to represent the general feedback voltage amplifier of Fig. 11.14(a) with the ideal structure of Fig. 11.12(a). The solution is presented, without derivation, in Fig. 11.14(b). We make the following observations.
1. The A circuit is obtained by augmenting the basic amplifier at the input with the source resistance Rs and a resistance R11, and at the output with the load resistance RL and a resistance R22. Resistances R11 and R22 represent the loading effect of the feedback network on the basic amplifier at the input and the output, respectively.
2. Resistance R11 is the resistance looking into port 1 of the feedback network while port 2 is short-circuited. Resistance R22 is the resistance looking into port 2 of the
832 Chapter 11
Feedback
Basic amplifier
Rif Rin
Rout
Rof
(a)
A circuit
Vs
Vo
Vf
Rs Vi R11
Basic amplifier
RL R22
βVo Vo
(b)
b circuit
Feedback network
Feedback network
2
R11
112
(c)
Vf I1 1 2 Vo Vf
R22
Feedback network
Vo I 0
(d)
Figure 11.14 (a) Block diagram of a practical series–shunt feedback amplifier. (b) The circuit in (a) represented by the ideal structure of Fig. 11.12(a). (c) Definition of R11 and R22 . (d) Determination of the feedback factor β. (e) The A circuit, showing the open-loop resistances Ri and Ro.
Vi
Ri
Rs
R11
Ro
5. The values of A and β can be used to determine the closed-loop gain Af , Af≡Vo= A
Vs 1+Aβ
Basic amplifier
11.4
Systematic Analysis of Feedback Voltage Amplifiers 833
R22 RL Vo
Figure 11.14 continued
(e)
feedback network while port 1 is open-circuited. These definitions are illustrated in Fig. 11.14(c). Since the feedback network is connected in shunt with the output, shorting its port 2 destroys the feedback. Similarly, because the feedback network is connected in series with the input, opening its port 1 destroys the feedback. It follows that the loading effect of the feedback network is obtained by looking into its appropriate port while the other port is open-circuited or short-circuited so as to destroy the feedback.4
3. The feedback factor β is the transmission from port 2 to port 1 of the feedback network, with port 1 open-circuited (which destroys the feedback). Reference to Fig. 11.14(c)
shows that
V
β≡ f (11.24)
Vo I1=0
4. The open-loop gain A can be obtained from the A circuit in Fig. 11.14(e) as A = Vo
Vi
6. The open-loop input resistance Ri and output resistance Ro can be determined from the A circuit [see Fig. 11.14(e)]. These values can be used to determine the input and output resistances with feedback,
Rif =Ri(1+Aβ) Rof =Ro/(1+Aβ)
From Fig. 11.14(a) we see that Ri f is the resistance seen by the ideal signal source Vs. The actual input resistance of the feedback amplifier Rin excludes Rs and is found from Ri f ,
Rin =Rif −Rs (11.25)
4A simple rule to remember: If the connection is shunt, short it; if series, sever it.
834 Chapter 11
Feedback
Similarly, Rof is the output resistance of the feedback amplifier including RL. The actual output resistance excludes RL (see Fig. 11.14(a)) and is found from Rof ,
1 1
Rout=1 R −R (11.26)
of L
A final and important note: The representation in Fig.11.14(b) is only approximately equivalent to the original circuit in Fig. 11.14(a). The approximation is a result of neglecting the small forward transmission in the feedback network relative to the much larger forward transmission in the basic amplifier. Also, recall that we continue to assume that the basic amplifier is unilateral—that is, it does not have internal feedback; all the feedback occurs in the feedback network and is represented by the feedback factor β.
Example 11.4
Figure 11.15(a) shows an op amp connected in the noninverting configuration. The op amp has an open-circuit voltage gain μ, a differential input resistance Rid, and an output resistance ro. Recall that inouranalysisofop-ampcircuitsinChapter2,weneglectedtheeffectsofRid (assumedittobeinfinite) and of ro (assumed it to be zero). Here we wish to use the feedback method to analyze the circuit taking both Rid and ro into account. Find expressions for A, β, the closed-loop gain Vo/Vs, the input resistance Rin [seeFig.11.15(a)],andtheoutputresistanceRout.Alsofindnumericalvalues,givenμ=104,Rid =100k, ro =1 k, RL =2 k, R1 =1 k, R2 =1 M, and Rs =10 k. Note that this circuit was analyzed in Example 11.3 using the loop-gain method and, where appropriate, compare results.
Solution
We observe that the feedback network consists of R2 and R1. This network samples the output voltage Vo and provides a voltage signal (across R1) that is mixed in series with the input source Vs.
The A circuit can be easily obtained following the rules of Fig. 11.14, and is shown in Fig. 11.15(b). Observe that the loading effect of the feedback network at the input side is obtained by short-circuiting port 2 of the feedback network (because it is connected in shunt) and looking into port 1, with the result that R11 = R1 ∥ R2 . The loading effect of the feedback network at the output side is found by open-circuiting port 1 (because it is connected in series) and looking into port 2, with the result that R22 = R2 + R1 . For the resulting A circuit in Fig. 11.15(b), we can write by inspection:
Vo RL ∥ R1 + R2 Rid
A ≡ V = μ R ∥ R + R + r R + R + ( R ∥ R )
i L12oids12 For the values given, we find that A ≃ 6000 V/V.
Thus,
Vo R1 +R2
Aβ =6000×10−3 =6
The circuit for determining β is shown in Fig. 11.15(c), from which we obtain β≡Vf= R1 ≃10−3V/V
Rs
ro
Vo I0
R2
11.4 Systematic Analysis of Feedback Voltage Amplifiers 835
Rs
Vs
Rif
Rid V1
ro
Vo
RL
Rof
Rin
V1
Rout
1 R2 2 R1
(a)
Vi
Rid V1
R22 = V1 RL (R2 R1)
VfR1 Vo
(c)
R
R11 = (R1 R2) io
1 + Aβ = 7
Identical results are obtained by substituting the given numerical values into the expression for Aβ derived in Example 11.3.
The voltage gain with feedback can now be obtained as
Af ≡Vo = A =6000=857V/V Vs 1+Aβ 7
R
Figure 11.15 Circuits for Example 11.4. and
(b)
836
Chapter 11 Feedback
Example 11.4 continued
The input resistance Ri f determined by the feedback equations is the resistance seen by the external source
(see Fig. 11.15a), and is given by
Rif =Ri(1+Aβ) where Ri is the input resistance of the A circuit in Fig. 11.15(b):
Ri =Rs +Rid +(R1∥R2) For the values given, Ri ≃ 111 k, resulting in
Rif =111×7=777k
This, however, is not the resistance asked for. What is required is Rin , indicated in Fig. 11.15(a). To obtain
Rin wesubtractRs fromRif:
Rin =Rif −Rs =767k
The resistance Rof given by the feedback equations is the output resistance of the feedback amplifier,
including the load resistance RL , as indicated in Fig. 11.15(a). Rof is given by Rof= Ro
1+Aβ
where Ro is the output resistance of the A circuit. Ro can be obtained by inspection of Fig.11.15(b) with Vi
set to zero, as
For the values given, Ro ≃ 666 , and
Ro =ro∥RL∥ R2 +R1
Rof = 666 =95.2 7
The resistance asked for, Rout, is the output resistance of the feedback amplifier excluding RL. From Fig. 11.15(a) we see that
Thus
Rof = Rout ∥RL
Rout ≃100
11.4 SystematicAnalysisofFeedbackVoltageAmplifiers 837
Example 11.5
As another example of a series–shunt feedback amplifier, consider the circuit shown in Fig. 11.8(b), which we analyzed in Example 11.2 by determining the loop gain Aβ. In this example we wish to first analyze the circuit using our systematic procedure and then compare the results to those obtained in Example 11.2. For convenience, the circuit is repeated in Fig. 11.16(a). It is required to obtain the voltage gain Vo/Vs, input resistance Rin, and output resistance Rout. Find numerical values for the case gm1 = gm2 = 4 mA/V, RD1 =RD2 =10 k, R1 =1 k, and R2 =9 k. For simplicity, neglect ro of each of Q1 and Q2.
RD1
RD2
Vo
V Q2R2 d1
Q1 Ro
R1 I0 R2
Vi
R1 R2 VR1 Vo Ri f
(b) (c)
Figure 11.16 (a) Series–shunt feedback amplifier for Example 11.5; (b) the A circuit; (c) the β circuit.
Vs
R2
Rin
1R1 2
Q1
Rout
RD1
RD2
Vo
(a)
Q2
838
Chapter 11 Feedback
Example 11.5 continued
Solution
We identify the feedback network as the voltage divider (R1 , R2 ). Its loading effect at the input is obtained by short-circuiting its port 2 (because it is connected in shunt with the output). Then, looking into its port 1, we see R1 ∥ R2 . The loading effect at the output is obtained by open-circuiting port 1 of the feedback network (because it is connected in series with the input). Then, looking into port 2, we see R2 in series with R1 . The A circuit will therefore be as shown in Fig. 11.16(b). The gain A is determined as the product of the gain of Q1 and the gain of Q2 as follows:
Vd1 RD1 gm1RD1 A1=V =−1/g +R∥R=−1+g R∥R
i m112 m112
A=Vo =−g R ∥R+R 2 V m2 D2 1 2
d1
Vo A=V=A1A2=
i
For the numerical values given,
A= 4×10×4[10∥(1+9)] =173.9 V/V
1+4(1∥9)
which is reasonably close to the value of 166.7 V/V obtained in Example 11.2.
The value of β is determined from the β circuit in Fig. 11.16(c), β≡Vf = R1
gm1RD1gm2 RD2∥R1+R2 1+g R∥R
m1 1 2
For the numerical values given,
Vo R1 +R2
β= 1 =0.1 1+9
The closed-loop gain Vo/Vs can now be found as Vo =Af = A =
173.9 =9.46V/V Vs 1+Aβ 1+173.9×0.1
which is very close to the value of 9.43 V/V obtained in Example 11.2.
The input resistance is obviously infinite because of the infinite input resistance of the MOSFET. The
outputresistanceRout isobtainedasfollows,
Rout=Rof= Ro 1+Aβ
where Ro is the output resistance of the A circuit. From Fig. 11.16(b),
The amount of feedback is
Thus,
Ro = RD2 ∥ R1 + R2 =10∥10=5k
1+Aβ =1+(173.9×0.1)=18.39
Rout = 5000 = 272 18.39
11.4 Systematic Analysis of Feedback Voltage Amplifiers 839
which is relatively low given that the open-loop amplifier has Ro = 5000 . We finally note that the loop-gain method utilized in Example 11.2 cannot provide the input and output resistances because the A circuit is not determined.
EXERCISES
11.7 If the op amp of Example 11.4 has a uniform –6-dB/octave high-frequency rolloff with f3dB = 1 kHz, find the 3-dB frequency of the closed-loop gain Vo/Vs.
Ans. 7 kHz
11.8 The circuit shown in Fig. E11.18 consists of a differential stage followed by an emitter follower, with series–shunt feedback supplied by the resistors R1 and R2. Assuming that the dc component of Vs is zero, and that β of the BJTs is very high, find the dc operating current of each of the three transistors and show that the dc voltage at the output is approximately zero. Then find the values of A,β,Af ≡Vo/Vs,Rin,andRout.Assumethatthetransistorshaveβ=100.
Ans. 0.5 mA, 0.5 mA, 5 mA; 85.7 V/V; 0.1 V/V; 8.96 V/V; 191 k; 19.1 .
Rin Rout
Figure E11.8
840
Chapter 11 Feedback
11.9 For the series–shunt amplifier in Fig. 11.8(c), which was considered in Exercise 11.6, find A, β, Af , R , and R . Neglect r of Q. Compare results to those obtained in Exercise 11.6.
in outo Ans.A=gR∥R+R ;β=R/R+R;
mD12112
A =A/(1+Aβ);R = 1/g (1+Aβ); f inm
Rout = RD∥ R1 +R2 /(1+Aβ)
Comparison: A and β are identical to the corresponding expressions found in Exercise 11.6. However,
Rin and Rout cannot be determined using the method of Exercise 11.6.
11.5 Other Feedback-Amplifier Types
Having studied in detail the most common feedback-amplifier type, the feedback voltage amplifier, we now consider the three other types of feedback amplifier: the feedback transconductance amplifier, the feedback current amplifier, and the feedback transresistance amplifier. The presentation builds on that of the feedback voltage amplifier, and the results will be given without derivation. The analysis method will be illustrated with a large number of worked-out examples dealing with practical and widely utilized circuits.
11.5.1 Basic Principles
1. Sensing: The feedback network must sample the output signal of interest. Thus if Vo is the output signal of interest, as in the case of voltage and transresistance amplifiers, the feedback network is connected in parallel (or shunt) with the amplifier output node, just as a voltmeter is connected to measure a voltage. On the other hand, if Io is the output signal of interest, as in the case of transconductance and current amplifiers, the feedback network is connected in series with the output loop, just as a current meter is connected to measure a current.
2. Mixing: If the input signal to be amplified is a voltage, as in the case of voltage and transconductance amplifiers, the signal source is represented by its The ́venin equivalent and the feedback voltage signal Vf is connected in series with the input signal source Vs . On the other hand, if the signal to be amplified is a current, as in the case of current and transresistance amplifiers, the Norton form is used to represent the signal source, and the feedback current signal If is connected in parallel (shunt) with the input signal source Is.
3. Feedback topology: From the above, it follows that for each of the four amplifier types there is a uniquely appropriate feedback topology:
Amplifier Type
Appropriate Feedback Topology
Voltage Transconductance Current Transresistance
Series–Shunt Series–Series Shunt–Series Shunt–Shunt
The appropriate feedback topology not only stabilizes the gain of interest (e.g., the transconductance Af ≡ Io/Vs in a transconductance amplifier), but also makes the input and output resistances more ideal (e.g., the shunt–series topology decreases the input resistance and increases the output resistance of a current amplifier).
4. Input and output resistance: The increase or decrease of the input or output resistance depends solely on the type of connection: Series connection always increases the resistance; parallel (shunt) connection always decreases the resistance. Furthermore, the increase or decrease is always by the amount of feedback, (1 + Aβ). Thus, as an example, for the feedback current amplifier, the shunt connection at the input decreases the input resistance; Ri f = Ri /(1 + Aβ ), and the series connection at the output increases the output resistance; Rof = (1 + Aβ)Ro, where Ri and Ro are the input and output resistances of the open-loop amplifier (A circuit).
5. Dimensions of A, β , Aβ , and Af : Depending on the amplifier type, A, β , and Af have the dimensions of V/V, A/A, V/A, or A/V. However, Aβ is always dimensionless. Forafeedbacktransconductanceamplifier,forexample,A≡Io/Vi (A/V),β≡Vf/Io (V/A), Af ≡ Io/Vs (A/V), and Aβ is in V/V or essentially dimensionless.
6. Analysis using the loop gain: For any feedback-amplifier type, the loop gain Aβ can be determined using the method described in Section 11.3.3. The loop gain can then be used together with the feedback factor β to determine the open-loop gain A and hence the closed-loop gain Af . This approach, however, does not enable the determination of the input and output resistances of the feedback amplifier. For these, we need to obtain the A circuit using the systematic analysis approach described below.
Example 11.6
Figure 11.17(a) shows a feedback transconductance amplifier utilizing an op amp together with an NMOS transistor. The feedback network consists of a resistor RF that senses the output current Io (recall that the drain and source currents of the MOSFET are equal) and provides a feedback voltage that is subtracted from Vs by means of the differencing action of the op-amp input. Observe that the feedback topology is series–series, which is uniquely appropriate for transconductance amplifiers.
(a) Find β and hence the closed-loop gain Af ≡ Io /Vs obtained when Aβ ≫ 1.
(b) Replace the op amp with its equivalent-circuit model characterized by an open-circuit voltage gain μ, an input differential resistance Rid , and an output resistance ro1 . Also, replace the MOSFET with its hybrid-π model characterized by a transconductance gm and an output resistance ro2. With the
complete equivalent circuit in hand, set Vs = 0 and break the loop to determine Aβ.
(c) Use Aβ together with β to find A.
(d) Forμ=1000,Rid =100k,gm =2mA/V,ro2 =20k,andRF =1k,findthevaluesofβ,Aβ,
A, and Af . Compare Af to the ideal value obtained when Aβ ≫ 1.
11.5 Other Feedback-Amplifier Types 841
842
Chapter 11 Feedback
Example 11.6 continued
Vs
Io
RF 1 RF 2
(b)
ro1G DIo
mQ
Rid
(a)
Vid
mVid Vgs
gV ro2 m gs
Vs
S
RF
(c)
ro1
Vt mVt
Vr Rid
GD
Vgs gV ro2 m gs
S
RF
Figure 11.17 Example 11.6.
(d)
Solution
(a) The two-port feedback network is shown in Fig. 11.17(b). When port 2 is fed with a current Io the voltage Vf appearing across port 1 is Io RF , thus
When Aβ ≫ 1,
β = RF
Af ≡ Io ≃ 1 = 1 Vs β RF
(b) Figure 11.7(c) shows the equivalent-circuit model of the feedback transconductance amplifier. To determine Aβ, we set Vs = 0 and break the loop at the input terminals of the op amp as shown in Fig.11.17(d).NotethatwehaveappliedaninputvoltageVt andterminatedtheloopatthebreakin theresistanceRid topreventanychangeintheloopconditions.Thiscircuitcanbeeasilyanalyzedto determineAβ≡−Vr/Vt asfollows:
Vgs =μVt −(−Vr)=μVt +Vr −Vr = gmVgs(RF ∥Rid ∥ro2)
Combining these two equations yields
Aβ ≡ −Vr = μ gm(RF ∥Rid ∥ro2)
11.5 Other Feedback-Amplifier Types 843
(c) Substituting β = RF provides
(d) For the given numerical values,
Vt
A = μ RF
1+gm(RF ∥Rid ∥ro2)
gm(RF ∥Rid ∥ro2) 1+gm(RF ∥Rid ∥ro2)
2(1∥100∥20) 1+2(1∥100∥20)
β = 1 k Aβ = 1000 ×
= 653.6
A = 653.6 mA/V
Af ≡ Io = 653.6 = 0.9985 mA/V Vs 1 + 653.6
Since the ideal value of Af is 1 mA/V, the actual Af is only 0.15% lower than ideal.
844 Chapter 11 Feedback
EXERCISES
11.10 For the circuit in Example 11.6, let the op-amp gain decrease by 10%. What is the corresponding percentagechangeinAf ≡Io/Vs?
Ans. −0.02%
D11.11 RedesignthecircuitinExample11.6toobtainanominalclosed-looptransconductanceof2mA/V. What is the required value of RF , and what is the actual transconductance Af realized?
Ans. RF = 500 ; Af = 1.996 mA/V
11.5.2 The Feedback Transconductance Amplifier (Series–Series)
Figure 11.18(a) shows the ideal structure of the feedback transconductance amplifier. The open-loop amplifier (A circuit) is unilateral, has an input resistance Ri, a short-circuit transconductance gain A in A/V, and an output resistance Ro. The short-circuit output current Io = AVi is sensed by the feedback network. Note that since the resistance looking into port 2 of the feedback network is zero, the feedback network does not load the amplifier output. The feedbacknetworkprovidesatport1avoltagesignalVf =βIo,wherethefeedbackfactorβhas the dimensions of V/A. The feedback signal is connected in series with the input signal source Vs, and the feedback network does not load the amplifier input. Finally, note the definitions of the input resistance with feedback, Ri f , and the output resistance with feedback, Rof . The latter is the resistance found by looking into the output loop between any two nodes such as O and O′.
The equivalent circuit of the feedback transconductance amplifier is shown in Fig. 11.18(b). Note that the closed-loop gain Af is the ratio of the short-circuit output current Io and the input voltage Vs, thus it is the short-circuit transconductance of the feedback amplifier. Also, Rof is the resistance seen between any two nodes in the output loop, such as O and O′, while Vs is set to zero. Finally, Fig. 11.18(c) provides the formulas for determining Af , Ri f , and Rof .
With the ideal case in hand, we now consider the general or practical case of a feedback transconductance amplifier, shown in Fig. 11.19(a). To be able to apply feedback analysis to this circuit, we have to find the A circuit and β. These are shown in Fig.11.19(b). The A circuit is obtained by augmenting the basic amplifier with Rs and RL and the two resistances R11 and R22, which represent the loading effect of the feedback network on the basic amplifier at the input and output, respectively. Figure 11.19(b) shows how R11 and R22 are determined. Here, the series connection at both the input and the output means that the other port of the feedback network must be left open-circuited. This is also the case when β is determined.
11.5 Other Feedback-Amplifier Types 845
(b) Equivalent Circuit
S
Vs
Io
O
Rif
Af Vs Rof
SO
(c) Formulas
Af=Io= A Vs 1+Aβ
Rif =(1+Aβ)Ri
Rof =(1+Aβ)Ro
Figure 11.18 The feedback transconductance amplifier (series–series).
Finally Fig. 11.19(c) gives the formulas for determining the actual values of the input and output resistances, Rin and Rout, of the feedback amplifier from Rif and Rof . To see how these formulas come about, note from Fig. 11.19(a) that unlike Ri f , Rin does not include Rs , and unlike Rof , Rout does not include RL .
846 Chapter 11
Feedback
(a) General Structure
R R ifn ouft
Basic amplifier
(c) Gain, Input, and Output Resistance
• Use the formulas in Fig. 11.18 to find Af , Rif , and Rof .
• Rin and Rout can then be found from
Rin =Rif −Rs
Rout =Rof −RL
Figure 11.19 The feedback transconductance amplifier (series–series).
11.5 Other Feedback-Amplifier Types 847
Example 11.7
Figure 11.20(a) shows a feedback transconductance amplifier composed of a differential amplifier A1 with an input differential resistance Rid , an open-circuit voltage gain A1 , and an output resistance Ro1 , connected in cascade with a common source MOSFET Q2 having a transconductance gm2 and an output resistance ro2.Usethefeedback-analysismethodtodeterminetheclosed-looptransconductanceAf ≡Io/Vs,theinput resistance Rin , and the output resistance Rout . The latter is the resistance seen between the terminals of RL , looking back into the output loop.
Rs
S2 A G2 Q2
1
Io
D2 Rof
D2
Vs
Rif
Rin
RL
RF
Ro1 G2 Vgs2
S2 (c)
1 RF 2
(a)
(b)
Ro
D2 D2
ro2
Rs
Vid
Rid RF
Io
RL RF
Vi
A1Vid
gm2Vgs2
Ri
I1 0
Vf RF Io
(d)
Figure 11.20 Circuits for Example 11.7.
848
Chapter 11 Feedback
Example 11.7 continued Solution
First we identify the basic amplifier and the feedback circuit. The basic amplifier consists of the differential amplifier A1 cascaded with the CS PMOS transistor Q2. The output current Io is sensed by the series resistance RF . The latter is the feedback network (Fig. 11.20b). It develops a voltage Vf that is mixed in series with the input loop.
The second step is to ascertain that the feedback is negative. This can be done by assuming an increase in Vs and following the resulting change around the loop. An increase in Vs will cause the voltage at the invertinginputterminalofA1 toincrease.ThisinturncausesadecreaseintheoutputvoltageofA1,which is the voltage at the gate of Q2. Thus, transistor Q2 will have a larger VSG, which will cause Io to increase. This in turn causes an increase in the voltage across RF , which is the same polarity as the change in Vs . Thus, the feedback is indeed negative.
Next,wedetermineanapproximatevalueforAf ≡Io/Vs undertheassumptionthattheloopgainAβ is much greater than unity. This value, found before any analysis is undertaken, will help us determine at the end whether our analysis is correct: If the loop gain is found to be much greater than unity, then the final Af should be close to the value initially determined. From the circuit of Fig. 11.20(d),
and thus for large Aβ,
β = RF
Af ≃ 1 = 1 β RF
Next, we determine the A circuit. Since the feedback network (Fig. 11.20b) is connected in series with boththeinputandoutputloops,weincludearesistanceRF ineachoftheseloops(whichisequivalentto saying we include, at the input, the input resistance of the feedback circuit with port 2 open and, at the output, the input resistance of the feedback circuit with port 1 open). Doing this, including Rs and RL in the A circuit, and replacing A1 and Q2 with their small-signal models, results in the A circuit shown in Fig. 11.20(c). Analysis of this circuit is straightforward:
V =−V Rid
id i Rid +Rs +RF
(11.27)
(11.28) (11.29)
(11.30)
(11.31)
Vgs2 =A1Vid
I =−g V ro2
o m2 gs2 ro2 +RL +RF Combining these three equations results in
I R r
A≡ o = Ag V 1 m2
i
Usually Rid ≫ (Rs + RF ), ro2 ≫ (RL + RF ), resulting in the approximate expression for A:
A ≃ A1gm2
id o2
R +R +R r +R +R
id s F o2 L F
The input resistance Ri can be found by inspection as
Ri =Rs +Rid +RF (11.32)
The output resistance Ro is found by setting Vi = 0, and breaking the output loop at any location, say between D2 and D2′ . Thus,
The loop gain Aβ is thus
Aβ = A g R 1 m2
F
id o2
Rid +Rs +RF ro2 +RL +RF
Ro =ro2 +RL +RF
(11.33)
(11.34)
R r
11.5 OtherFeedback-AmplifierTypes 849
≃ A1 gm2 RF
With numerical values, one can now obtain the value of Aβ and determine whether it is indeed much
greater than unity. We next determine the closed-loop gain
Af= A 1+Aβ
Substituting for A from Eq. (11.31) and for Aβ from Eq. (11.35), we have
Af ≃ A1gm2 (11.36)
(11.35)
For A1gm2RF ≫ 1,
1 + A1gm2RF
Af ≃ 1 RF
which is the value we found at the outset.
The series mixing raises the input resistance with feedback,
Rif =Ri(1+Aβ) andRin canbeobtainedbysubtractingRs fromRif.
To obtain Rof , we note that the series connection at the output raises the output resistance, thus, Rof =Ro(1+Aβ)
andRout,whichistheresistanceseenbyRL,canbeobtainedbysubtractingRL fromRof.
850 Chapter 11 Feedback EXERCISES
D11.12 For the circuit analyzed in Example 11.7, select a value for RF that will result in Af ≃ 5 mA/V. Now, for A1 = 200V/V, gm2 = 2 mA/V, Rid = 100 k, ro2 = 20 k, and assuming that Rs ≪ Rid and RL ≪ ro2 , find the value of Af realized and the input and output resistances of the feedback transconductance amplifier. If for some reason gm2 drops in value by 50%, what is the corresponding percentage change in Af ?
Ans. 200 ; 4.94 mA/V; 8.1 M; 1.64 M; −1.25%
11.13 Determine the loop gain of the feedback amplifier of Fig. 11.20(a) by setting Vs = 0, breaking the feedback loop at G2, applying a voltage Vg2, and determining the voltage Vo1 that appears at the outputofA1;Aβ≡−Vo1/Vg2.AssumeRF ≪(Rid +Rs)andro2 ≫RL +RF.
Ans. Aβ≃A1gm2RF
11.14 Utilizing the full expression for Aβ in Eq. (11.34) but assuming that ro2 ≫ RL + RF and RF ≪ Rid , show that
Rin ≃Rid(1+A1gm2RF)
11.15 Utilizing the full expression for Aβ in Eq. (11.34) but assuming that Rid ≫ Rs + RF and RF ≪ ro2
show that
Example 11.8
Rout ≃ro2(1+A1gm2RF)
Because negative feedback extends the amplifier bandwidth, it is commonly used in the design of broadband amplifiers. One such amplifier is the MC1553. Part of the circuit of the MC1553 is shown in Fig. 11.21(a). The circuit shown (called a feedback triple) is composed of three gain stages with series–series feedback provided by the network composed of RE1, RF, and RE2.
Observe that the feedback network samples the emitter current Io of Q3, and thus Io is the output quantity of the feedback amplifier. However, practically speaking, Io is rather difficult to utilize. Thus it is usual to take as the output Ic, the collector current of Q3. This current is of course almost equal to Io; Ic = αIo. Thus, as a transconductance amplifier with Ic as the output current, the output resistance of interest is that labeled Rout in Fig. 11.21(a). In some applications, Ic is passed through a load resistance, such as RC3, and the voltage Vo is taken as the output. Assume that the bias circuit, which is not shown, establishes IC1 = 0.6 mA, IC2 = 1 mA, and IC3 = 4 mA. Also assume that for all three transistors,5 hfe = 100 and ro = ∞.
5To avoid possible confusion of the BJT current gain β and the feedback factor β, we sometimes use hfe to denote the transistor β.
Ic
RC3 600 Vo
Q3
Y Rout Y Io
11.5 Other Feedback-Amplifier Types 851
RC1 9 k
RC2 5 k
RF 640
(a)
Q1
Q2
Rof
Vs
Rin Rif
RE1 100
RE2
100
RF
VfRE1RE2 Io (b)
RC2
RC3 Q3
Y
RC1
Rout
Q2
Io
Ro RC2
Q1 Y Q3
RF
(c)
RF
Vi
RE1
RE2 RE1
RE2
Rof
Ri
Figure 11.21 Circuits for Example 11.8.
(d)
852
Chapter 11 Feedback
Example 11.8 continued
(a) Anticipating that the loop gain will be large, find an approximate expression and value for the closed-loopgainAf ≡Io/Vs andhenceforIc/Vs.AlsofindVo/Vs.
(b) Use feedback analysis to find A, β, Af , Vo/Vs, Rin, and Rout. For the calculation of Rout, assume that ro ofQ3 is25k.
Solution
(a) When Aβ ≫ 1,
Af ≡ Io ≃ 1 Vs β
where the feedback factor β can be found from the feedback network. The feedback network is highlighted in Fig. 11.21(a), and the determination of the value of β is illustrated in Fig. 11.21(b), from which we find
β≡Vf = Io
RE2 ×RE1 RE2 +RF +RE1
100 × 100 = 11.9 100+640+100
1
β
1R+R 1+E2 F
RE2 RE1 1 =84mA/V
11.9
Io =84mA/V
Vs
=−IcRC3 =−84×0.6=−50.4V/V Vs
Thus,
=
≃ =
= ≃
Af
Ic Vs
Vo Vs
(b) Employing the loading rules given in Fig. 11.19, we obtain the A circuit shown in Fig. 11.21(c). To findA≡Io/Vi wefirstdeterminethegainofthefirststage.Thiscanbewrittenbyinspectionas
Vc1 −α1 RC1∥rπ2
V =r +R ∥R +R
RE2 = 100 , results in
Vc1 = −14.92 V/V Vi
i e1 E1 F E2
Since Q1 is biased at 0.6 mA, re1 = 41.7 . Transistor Q2 is biased as 1 mA; thus rπ 2 = hfe /gm2 = 100/40 = 2.5 k. Substituting these values together with α1 = 0.99, RC1 = 9 k, RE1 = 100 , RF = 640 , and
Next,wedeterminethegainofthesecondstage,whichcanbewrittenbyinspection(notingthatVb2 =Vc1)as Vc2 =−g R ∥h +1r +R ∥R +R
Substitutinggm2 =40mA/V,RC2 =5k,hfe =100,re3 =25/4=6.25,RE2 =100,RF =640,and RE1 = 100 results in
Vc2 = −131.2 V/V Vc1
V m2 C2 fe e3 E2 F E1 c1
11.5 Other Feedback-Amplifier Types 853
Finally, for the third stage we can write by inspection IoIe3 1
V =V =r +R ∥R +R c2 b3 e3 E2 F E1
= 1 = 10.6 mA/V 6.25 + (100 ∥ 740)
Combining the gains of the three stages results in
A≡ Io =−14.92× −131.2×10.6×10−3
Vi
= 20.7 A/V The closed-loop gain Af can now be found from
Af≡Io= A
Vs 1+Aβ
= 20.7 = 83.7 mA/V 1+20.7×11.9
which we note is very close to the ideal value found in (a) above. This is not surprising, since the loop gain Aβ = 20.7 × 11.9 = 246.3 is large (≫ 1).
The voltage gain is found from
Vo = −IcRC3 ≃ −IoRC3 = −Af RC3 Vs Vs Vs
= −83.7 × 10−3 × 600 = −50.2 V/V which is also very close to the approximate value found in (a) above.
854
Chapter 11 Feedback
Example 11.8 continued
The input resistance of the feedback amplifier is given by
Rin =Rif =Ri(1+Aβ)
where Ri is the input resistance of the A circuit. The value of Ri can be found from the circuit in
Fig. 11.21(c) as follows:
Thus,
Ri=hfe+1 re1+RE1∥RF+RE2 = 13.11 k
Rif =13.11(1+20.7×11.9)=3.24M
To determine the output resistance Rout, which is the resistance looking into the collector of Q3, we face a dilemma. The feedback does not sample Ic and thus we cannot employ the feedback formulas directly.6 Nevertheless, we present a somewhat indirect solution to this problem below. Here we note parenthetically that had Q1 been a MOSFET, this problem would not have existed, since Id = Is .
Since the feedback senses the emitter current Io, the output resistance given by the feedback analysis will be the resistance seen in the emitter circuit, say between Y and Y′,
Rof =Ro(1+Aβ)
whereRo canbedeterminedfromtheAcircuitinFig.11.21(c)bybreakingthecircuitbetweenYandY′.
The resistance looking between these two nodes can be found to be
R =R ∥R +R +r + RC2
now be found as
Rof =Ro(1+Aβ)=143.9(1+20.7×11.9)=35.6 k
6This important point was first brought to the authors’ attention by Gordon Roberts (see Roberts and Sedra, 1992).
o E2 F E1 e3 hfe+1
which, for the values given, yields Ro = 143.9 . The output resistance Rof of the feedback amplifier can
We can now use the value of Rof to obtain an approximate value for Rout. To do this, we assume that the effect of the feedback is to place a resistance Rof (35.6 k) in the emitter of Q3, and find the output resistance from the equivalent circuit shown in Fig. 11.21(d). This is the output resistance of a BJT with a resistance Rof in its emitter and a resistance RC2 in its base. The formula we have for this (Eq. 8.66) does not unfortunately account for a resistance in the base. The formula, however, can be modified (see Problem 11.54) to obtain
r R =r + R ∥ r +R 1+g r π3
out o3 of π3 C2 m3 o3rπ3+RC2
=25+[35.6∥(0.625+5)] 1+160×25× 0.625 0.625 + 5
= 2.19 M
ThusRout isincreased(fromro3)butnotby(1+Aβ).
EXERCISES
D11.16 For the feedback triple in Fig. 11.21(a), analyzed in Example 11.8, modify the value of RF to obtain a closed-loop transconductance Io /Vs of approximately 100 mA/V. Assume that the loop gain remains large. What is the new value of RF ? For this value, what is the approximate value of the voltage gain if the output voltage is taken at the collector of Q3?
Ans. 800 ; –60 V/V
11.17 Determine the loop gain of the feedback amplifier of Fig. 11.21(a). Set Vs = 0, break the loop
between the collector of Q1 and the base of Q2, apply a voltage Vt to the base of Q2, and connect a resistance equal to rπ2 between the collector of Q1 and ground. Find Aβ as (−Vr/Vt) where Vr =Vc1.
Ans. Aβ = 248.9 (slightly different from the value found in Example 11.8 because of the approx- imations inherent in the systematic feedback-analysis method).
11.5.3 The Feedback Transresistance Amplifier (Shunt–Shunt)
Figure 11.22(a) shows the ideal feedback transresistance amplifier, which, as expected, utilizes the shunt–shunt topology. The amplifier equivalent circuit is shown in Fig. 11.22(b), with the formulas for determining Af , Ri f , and Rof given in Fig. 11.22(c).
11.5 Other Feedback-Amplifier Types 855
856 Chapter 11
Feedback
(a) Ideal Structure
SO
Ii
Ri AIi
Ro
S
O
(b) Equivalent Circuit
Is
S
S
O
Vo
O
Rof
Rif Af Is
(c) Formulas
Af≡Vo= A
Is 1+Aβ
Rif =Ri/(1+Aβ)
Rof =Ro/(1+Aβ)
Figure 11.22 The feedback transresistance amplifier (shunt–shunt).
Application of the feedback-analysis method to a general transresistance amplifier is shown in Fig. 11.23, which presents all the steps and formulas needed. The method is now illustrated by a detailed example.
(a) General Structure
Rif Rin Rout
Rof
11.5 Other Feedback-Amplifier Types 857
Basic amplifier
(c) Gain, Input, and Output Resistance
• Use the formulas in Fig. 11.21 to find Af , Rif , and Rof .
• Rin and Rout can then be found from
Rin =1 1 − 1
Rif Rs Rout =1 1 − 1
Rof RL
Figure 11.23 The feedback transresistance amplifier (shunt–shunt).
858 Chapter 11 Feedback
Example 11.9
Figure 11.24(a) shows a feedback transresistance amplifier. It is formed by connecting a resistance RF in the negative-feedback path of a voltage amplifier with gain μ, an input resistance Rid, and an output resistance ro. The amplifier μ can be implemented with an op amp, a simple differential amplifier, a single-ended inverting amplifier, or, in the limit, a single-transistor CE or CS amplifier. The latter case will be considered in Exercise 11.18. Of course, the higher the gain μ, the more ideal the characteristics of the feedback transresistance amplifier will be, simply because of the concomitant increase in loop gain.
(a) If the loop gain is large, find an approximate expression for the closed-loop transresistance Vo/Is of the feedback amplifier.
(b) Find the A circuit and expressions for A, Ri, and Ro.
(c) Find expressions for the loop gain, Af , Ri f , Rin , Rof , and Rout .
(d) FindthevaluesofRi,Ro,A,β, Aβ,Af,Rif,Rin,Rof,andRout forthecaseμ=104 V/V,Rid =∞,
ro =100,RF =10k,andRs =RL =1k.
(e) If instead of a current source Is having a source resistance Rs = 1 k, the amplifier is fed from a
voltage source Vs having a source resistance Rs = 1 k, find an expression for and the value of the voltage gain Vo/Vs.
Solution
(a) If the loop gain Aβ is large,
Af ≡ Vo ≃ 1 Is β
where β can be found from the β circuit in Fig. 11.24(b) as shown in Fig. 11.24(c), β≡If =−1
(11.37)
Thus,
Vo RF
Vo ≃−RF Is
Note that in this case the voltage at the input node (the inverting input terminal of μ) will be very close to ground and thus very little, if any, current flows into the input terminal of the amplifier. Nearly all of Is will flow through RF , resulting in Vo ≃ 0 − Is RF = −Is RF . This should be reminiscent of the inverting op-amp configuration studied in Section 2.2.
(b) From the feedback network in Fig. 11.24(b), we see that the loading effect at the amplifier input and output will simply be RF . This is indicated in the A circuit shown in Fig. 11.24(c), where we have replaced the amplifier μ with its equivalent-circuit model. The open-loop transresistance A can be obtained as follows:
Vid =IiRi (11.38)
11.5 Other Feedback-Amplifier Types 859
RF
m
RF
RL 1 2 Vo
Is
Rif
Rs
Rin
Rout
Rof
(a)
(b)
RF
If
Vo
Ii
ro
(c)
Rs RF Rid Vid mVid RF RL Ri
(d)
Figure 11.24 (a) A feedback transresistance amplifier; (b) the β circuit; (c) determining β; (d) the A circuit.
Vo
Ro
860
Chapter 11 Feedback
Example 11.9 continued where
Ri = Rid ∥RF ∥Rs
RF ∥RL
Vo =−μVid r +R ∥R
oFL
(11.39)
(11.40)
(11.41) The open-loop output resistance can be obtained by inspection of the A circuit with Ii set to 0. We see that
Combining Eqs. (11.38) and (11.40) gives
Vo RF ∥RL A≡ I =−μRi r +R ∥R
ioFL
Vid =0,and
Ro = ro ∥RF ∥RL
(c) The loop gain Aβ can be obtained by combining Eqs. (11.37) and (11.41),
Observe that although both A and β are negative, Aβ is positive, a comforting fact confirming that the feedback is negative. Also note that Aβ is dimensionless, as it must always be.
R R∥R iFL
(11.42)
(11.43)
Aβ=μ R r+R∥R FoFL
The closed-loop gain Af can now be found as Af≡Vo= A
Thus
Is 1+Aβ
RF ∥RL −μRi r +R ∥R
Af =
R R ∥R iFL
(11.44)
(11.45)
oFL
1+μR r +R ∥R FoFL
NotethattheconditionofAβ≫1thatresultsinAf ≃−RF correspondsto R R∥R
iFL
μR r+R∥R≫1 FoFL
Theinputresistancewithfeedback,Rif,isobtainedbydividingRi by(1+Aβ)withtheresult Rif= Ri
1+Aβ
1 1 Aβ 1 μ RF∥RL
R =R+R =R+R r+R∥R
Substituting for R from Eq. (11.39) and replacing μR ∥R r +R ∥R by μ′, where μ′ is lower i FLoFL
or
11.5 Other Feedback-Amplifier Types 861
than but usually close to the value of μ, results in
Rif =Rid∥RF∥Rs∥(RF/μ′)
ThetwotermscontainingRF canbecombined,
Rif =Rs∥Rid∥[RF/(μ′ +1)]
(11.46)
(11.47)
Since Rif = Rs ∥Rin, we see that
UsuallyRid islargeandthus
Rin =Rid ∥[RF/(μ′ +1)]
Rin ≃ RF ≃ RF μ′ +1 μ′
ifiiiFoFL
from which we observe that for large amplifier gain μ, the input resistance will be low. The output resistance with feedback Rof can be found by dividing Ro by (1 + Aβ ):
Thus,
Rof= Ro 1+Aβ
1 = 1 + Aβ Rof Ro Ro
1 Ri RF∥RL 1
=R+μR r+R∥RR oFoFLo
862
Chapter 11 Feedback
Example 11.9 continued Substituting for Ro from Eq. (11.42),
1=1+1+1+μRi 1
Rof
RL RF ro RF ro
=1+1+1 1+μRi RL RF ro RF
Rof =RL∥RF∥ ro
1 + μ Ri
RF
Rout = RF ∥ ro
1 + μ Ri
RF
Thus,
Since, moreover,
we obtain for Rout
Rof =RL∥Rout
UsuallyRF ≫ro
1+μ Ri/RF ;thus,
Rout≃ro ≃RF ro 1 + μ Ri Ri μ
RF
from which we see that for large μ, the output resistance will be considerably reduced. (d) For the numerical values given:
Ri =Rid∥RF∥Rs
= ∞∥10∥1 = 0.91 k
Ro =ro∥RF∥Rs
= 0.1∥10∥1 = 90
RF ∥RL A=−μRi r +R ∥R
oFL
which is very close to the ideal value of −RF = −10 k.
=−104 ×0.91× (10∥1) =−8198k 0.1+(10∥1)
β=− 1 =− 1 =−0.1mA/V
Rif = Ri
1 + Aβ
= 910 =1.11 820.8
11.5 Other Feedback-Amplifier Types 863
RF Aβ = 819.8 1 + Aβ = 820.8
Af = A
1 + Aβ
10
=−8198 =−9.99k 820.8
Rin = 1 − 1 1−11−1
Rif Ri 1.11 1000 which is very low, a highly desirable property. We also have
≃1.11
Rof = Ro
1 + Aβ
= 90 =0.11 820.8
Rout = 1 = 1 1−1 1−1
Rof RL 0.11 1000 which as well is very low, another highly desirable property.
≃0.11
(e) If the amplifier is fed with a voltage source Vs having a resistance Rs = 1 k, the output voltage can be found from
Thus,
V = A I = A Vs o fs fRs
Vo = Af = 9.99 k =−9.99 V/V Vs Rs 1 k
864 Chapter 11 Feedback
EXERCISES
11.18 It is required to determine the loop gain of the amplifier of Fig. 11.24(a) directly. Set Is = 0, replace the amplifier μ with its equivalent circuit, and break the loop at the amplifier input, ensuring that a resistanceequaltoRid isconnectedacrossRs.Showthat
Aβ = μRL(Rid ∥Rs)
ro[RL +RF +(Rid ∥Rs)]+RL[RF +(Rid ∥Rs)]
Evaluate Aβ using the numerical values given in Example 11.9.
Ans. Aβ = 819.7
11.19 For the transresistance amplifier in Fig. E11.19, replace the MOSFET with its small-signal
equivalent-circuit model and use feedback analysis to show the following:
I (ideal) RF
Vo
Rout
Q
Is Rs
Rin
Figure E11.19
(a) For large loop gain (which cannot be achieved here), A ≡ V /I ≃ −R .
fosF
−Rs∥RF gm ro∥RF (b) Af = 1+R ∥R g r ∥R /R
(c) Rin = 1+g r ∥R moF
sFmoFF RF
RF
(d) Rout =ro∥1+g R ∥R
msF
(e) Forgm =5mA/V,ro =20k,RF =10k,andRs =1k,findA,β,Aβ,Af Ri,Ro,Rif,Rin,Rof,
and Rout .
Ans. (e) −30.3 k; −0.1 mA/V; 3.03; −7.52 k (compare to the ideal value of −10 k); 909 ; 6.67 k; 226 ; 291 ; 1.66 k; 1.66 k
11.5 Other Feedback-Amplifier Types 865 11.5.4 The Feedback Current Amplifier (Shunt–Series)
Figure 11.25(a) shows the ideal feedback current amplifier, which, as expected, utilizes the shunt–series topology. The amplifier equivalent circuit is shown in Fig. 11.25(b), with the formulas for determining Af , Ri f , and Rof given in Fig. 11.25(c).
Figure 11.26 shows how the feedback-analysis method can be applied to a general feedback current amplifier. All the necessary analysis steps and the formulas are given. The method is now illustrated by a detailed example.
(a) Ideal Structure
S
S
(b) Equivalent Circuit
S
S
(c) Formulas
Is
O
O
Io
Rif Af Is
Af≡Io= A
Is 1+Aβ
Rif =Ri/(1+Aβ)
Rof =(1+Aβ)Ro
Figure 11.25 The feedback current amplifier (shunt–series).
Ii
Ri AIi Ro
Rof
866 Chapter 11
Feedback
(a) General Structure
Is Rs
Rif Rin I
12
Io
YY RL
Rof Rout
Basic amplifier
o
Feedback network
(c) Gain, Input, and Output Resistance
• Use the formulas in Fig. 11.25 to find Af , Rif , and Rof .
• Rin and Rout can then be found from
Rin =1 1 − 1
Rif Rs Rout =Rof −RL
Figure 11.26 The feedback current amplifier (shunt–series).
11.5 Other Feedback-Amplifier Types 867
Example 11.10
Figure 11.27 shows a feedback current amplifier formed by cascading an inverting voltage amplifier μ with a MOSFET Q. The output current Io is the drain current of Q. The feedback network, consisting of resistors R1 and R2, senses an exactly equal current, namely, the source current of Q, and provides a feedbackcurrentsignalthatismixedwithIs attheinputnode.Notethatthebiasarrangementisnotshown.
The amplifier μ can be implemented in a variety of ways, including by means of an op amp, a differential amplifier, or a single-ended inverting amplifier. The simplest approach is to implement μ with a CS
Io
mQ
Io
R2
Rout Rof
R2
Is Rs
Rif Rin
R1 1 R1 2
(a)
(b)
mQ
Io Is1R2
Io Is1R2 R1
Vi 0 IfR Rs
R1
2
1 R12Io
(c)
Figure 11.27 Circuit for Example 11.10.
Ii 0
If Is
R2
Is R2 IsR2
R1
Is
R1
(d)
868
Chapter 11 Feedback
Example 11.10 continued
Ii
Ri
ro1 0 1/gm
Io
Ro
Q
R2 R1
ro2 Io
Rs Rid
Vi
mVi
R2 R1
Ri
(e)
Figure 11.27 continued
MOSFET amplifier. However, in such a case the loop gain will be very limited. Assume that the amplifier
μ has an input resistance Rid , an open-circuit voltage gain μ, and an output resistance ro1 .
(a) If the loop gain is large, find an approximate expression for the closed-loop gain Af ≡ Io /Is .
(b) Find the A circuit and derive expressions for A, Ri, and Ro.
(c) Give expressions for Aβ, Af , Rif , Rin, Rof , and Rout.
(d) Find numerical values for A, β, Aβ, Af , Ri, Rif , Rin, Ro, Rof , and Rout for the following case: μ =
1000V/V, Rs =∞, Rid =∞, ro1 =1 k, R1 =10 k, R2 =90 k; for Q: gm =5mA/V and ro =20k.
Solution
(a)WhentheloopgainAβ≫1,Af ≃1/β.Theβcircuit,showninFig.11.27(b),isusedtodetermineβ as shown in Fig. 11.27(c),
Thus,
β≡If =− R1
Io R1 +R2
Af ≃1=− 1+R2 β R1
(11.48)
(11.49)
To see what happens in this case more clearly, refer to Fig. 11.27(d). Here we have assumed the loop gain
to be large, so that Ii ≃ 0 and thus If ≃ Is. Also note that because Ii ≃ 0, Vi will be close to zero. Thus, we
can easily determine the voltage at the source of Q as −I R ≃ −I R . The current through R will then be f2s2 1
IsR2/R1. The source current of Q will be − Is +IsR2/R1 , which means that the output current Io will be
Io =−Is 1+R2 R1
which confirms the expression for Af obtained above (Eq. 11.49).
(b) To obtain the A circuit we load the input side of the basic amplifier with Rs and R11. The latter in this case is simply R1 + R2 (because port 2 of the feedback network is opened). We also load the output of the basic amplifier with R22 , which in this case is R1 ∥ R2 (because port 1 of the feedback network is shorted). The resulting A circuit is shown in Fig. 11.27(e), where we have replaced the amplifier μ with its equivalent circuit. Analysis of the A circuit is straightforward and proceeds as follows:
Ri = Rs ∥ Rid ∥ R1 + R2 Vi =IiRi
(11.50) (11.51)
(11.52)
(11.53)
(11.54) NotingthatRo istheoutputresistanceofQ,whichhasaresistance(R1∥R2)initssourcelead,wecanwrite
Ro = ro2 +(R1 ∥R2)+ gmro2 (R1 ∥R2) (11.55) (c) The loop gain is obtained by combining Eqs. (11.48) and (11.53),
Aβ = μ Ri (R1 ∥R2 ∥ro2) (11.56) R2 1/gm +(R1 ∥R2 ∥ro2)
The closed-loop gain Af can be obtained by substituting the expressions of A and Aβ (Eqs. 11.54 and 11.56)inAf =A/(1+Aβ).
ro2 Io=−μVi1/g +R∥R∥r r +R∥R
1
Io Ri ro2 A≡I =−μ1/g +R∥R∥r r +R∥R
11.5 OtherFeedback-AmplifierTypes 869
m 1 2 o2 o2 1 2 Combining Eqs. (11.51) and (11.52) results in A:
i m12o2o212 which with some manipulation can be expressed in the form
A = −μ Ri (R1 ∥R2 ∥ro2) (R1 ∥R2) 1/gm +(R1 ∥R2 ∥ro2)
The input resistance Ri f
Since by definition,
is found as
we can easily find Rin.
For the output resistance, we have
(d) For the numerical values given,
Rout =Rof =Ro(1+Aβ)
Ri =∞∥∞∥(10+90)=100k
Rif =Ri/(1+Aβ)
Rif =Rs∥Rin
870
Chapter 11 Feedback
Example 11.10 continued
The open-loop gain A can be determined by using Eq. (11.54),
A = −10, 764 A/A and the feedback factor β can be found by using Eq. (11.48),
Thus,
and
β = − R1 = − 10 = −0.1 A/A R1 +R2 10+90
Aβ = 1076.4
Af =− 10,764 =−9.99A/A 1 + 1076.4
which is very close to the ideal value of
since Rs = ∞,
EXERCISES
Rin =Rif =92.8
Ro=ro2+(R1∥R2)+gmro2 R1∥R2 =929k
Rout =Rof =(1+Aβ)Ro =1077.4×929=1001 M
Af ≃− 1+ R2 =− 1+ 90 =−10A/A R1 10
Rif = Ri = 100k =92.8 1+Aβ 1+1076.4
11.20 FortheamplifierinExample11.10,findthevaluesofAf,Rin,andRout whenthevalueofμis10times lower, that is, when μ = 100.
Ans. −9.91 A/A; 920 ; 101 M
11.21 If in the circuit in Fig. 11.27(a), R2 is short-circuited, find the ideal value of Af . For the case Rs = Rid =
∞, give expressions for Ri, Ro, A, β, Af , Rin, and Rout.
Ans. A =−1A/A;R =R ;R =r ,A=−μg R ;β=−1;A =−μg R / 1+μg R ;R ≃1/μg ;
fi1oo2 m1 f m1 m1in m
Rout≃μgmro2 R1.
11.7 The Stability Problem 871 11.6 Summary of the Feedback-Analysis Method
Table 11.2 provides a summary of the rules and relationships employed in the analysis and design of the four types of feedback amplifier. In addition to the wealth of information in Table 11.2, we offer the following important analysis tips.
1. Always begin the analysis by determining an approximate value for the closed-loop gain Af , assuming that the loop gain Aβ is large and thus
Af ≃1/β
This value should serve as a check on the final value you find for Af . How close the
actual Af is to this ideal value will depend on how large Aβ is compared to unity.
2. The shunt connection at input or output always results in reducing the corresponding resistance (input or output). The series connection at input or output always results
in increasing the corresponding resistance (input or output).
3. In utilizing negative feedback to improve the properties of an amplifier under design,
the starting point in the design is the selection of the feedback topology appropriate for the application at hand. Then the required amount of negative feedback (1 + Aβ ) can be ascertained utilizing the fact that it is this quantity that determines the magnitude of improvement in the various amplifier parameters. Also, the feedback factor β can be determined from the required closed-loop gain Af ,
β ≃ 1/Af
11.7 The Stability Problem
11.7.1 Transfer Function of the Feedback Amplifier
In a feedback amplifier such as that represented by the general structure of Fig. 11.1, the open-loop gain A is generally a function of frequency, and it should therefore be more accurately called the open-loop transfer function, A(s). Also, we have been assuming for the most part that the feedback network is resistive and hence that the feedback factor β is constant, but this need not be always the case. We shall therefore assume that in the general case the feedback transfer function is β(s). It follows that the closed-loop transfer function Af (s) is given by
Af (s) = A(s) (11.57) 1 + A(s)β(s)
To focus attention on the points central to our discussion in this section, we shall assume that the amplifier is direct coupled with constant dc gain A0 and with poles and zeros occurring in the high-frequency band. Also, for the time being let us assume that at low frequencies β(s) reduces to a constant value. Thus at low frequencies the loop gain A(s)β(s) becomes a constant, which should be a positive number; otherwise the feedback would not be negative. The question then is: What happens at higher frequencies?
872 Chapter 11 Feedback
Table 11.2
Summary of Relationships for the Four Feedback-Amplifier Topologies
Feedback Amplifier
Feedback Topology
xi xo xf xs A β Af V V V V Vo Vf Vo
Source Form
At Input
At Output
Ri f
Rof
Refer to Figs.
Voltage
Series–shunt
iofsVVV ios
The ́venin
By short- circuiting
By open- circuiting
a voltage,
and find the open-circuit voltage at port 1
R (1 + Aβ)
11.12 11.14
Current
Shunt–series
I I I I Io If Io i o f s Ii Io Is
Norton
By open- circuiting
By short- circuiting
a current,
and find the short-circuit current at port 1
Ri R (1+Aβ) 1+Aβ o
11.25 11.26
Transconductance
Series–series
V I V V Io Vf Io iofsVIV
The ́venin
By open- circuiting
By open- circuiting
a current,
and find the open-circuit voltage at port 1
R(1+Aβ) R(1+Aβ) io
11.18 11.19
Transresistance
Shunt–shunt
I V I I Vo If Vo i o f s Ii Vo Is
Norton
By short- circuiting
By short- circuiting
a voltage,
and find the short-circuit current at port 1
Ri Ro 1+Aβ 1+Aβ
11.22 11.23
ios
Loading of Feedback Network Is Obtained
To Find β, Apply to Port 2 of Feedback Network
port 2 of feedback network
port 1 of feedback network
port 2 of feedback network
port 1 of feedback network
port 2 of feedback network
port 1 of feedback network
port 2 of feedback network
port 1 of feedback network
Ro
i 1+Aβ
For physical frequencies s = jω, Eq. (11.57) becomes Af ( jω) = A( jω)
(11.58)
1+A(jω)β(jω)
Thus the loop gain A( jω)β( jω) is a complex number that can be represented by its magnitude
and phase,
L(jω) ≡ A(jω)β(jω)
= |A(jω)β(jω)|ejφ(ω) (11.59)
11.7 The Stability Problem 873
It is the manner in which the loop gain varies with frequency that determines the stability or instability of the feedback amplifier. To appreciate this fact, consider the frequency at which the phase angle φ(ω) becomes 180°. At this frequency, ω180, the loop gain A( jω)β( jω) will be a real number with a negative sign. Thus at this frequency the feedback will become positive. If at ω = ω180 the magnitude of the loop gain is less than unity, then from Eq. (11.58) we see that the closed-loop gain Af ( jω) will be greater than the open-loop gain A( jω), since the denominator of Eq. (11.58) will be smaller than unity. Nevertheless, the feedback amplifier will be stable.
On the other hand, if at the frequency ω180 the magnitude of the loop gain is equal to unity, it follows from Eq. (11.58) that Af ( jω) will be infinite. This means that the amplifier will have an output for zero input; this is by definition an oscillator. To visualize how this feedback loop may oscillate, consider the general loop of Fig. 11.1 with the external input xs set to zero. Any disturbance in the circuit, such as the closure of the power-supply switch, will generate a signal xi (t) at the input to the amplifier. Such a noise signal usually contains a wide range of frequencies, and we shall now concentrate on the component with frequency ω = ω180, that is, the signal Xi sin (ω180t). This input signal will result in a feedback signal given by
Xf =A(jω180)β(jω180)Xi =−Xi
SinceXf isfurthermultipliedby–1inthesummerblockattheinput,weseethatthefeedback causes the signal Xi at the amplifier input to be sustained. That is, from this point on, there will be sinusoidal signals at the amplifier input and output of frequency ω180. Thus the amplifier is said to oscillate at the frequency ω180.
The question now is: What happens if at ω180 the magnitude of the loop gain is greater than unity? We shall answer this question, not in general, but for the restricted yet very important class of circuits in which we are interested here. The answer, which is not obvious from Eq. (11.58), is that the circuit will oscillate, and the oscillations will grow in amplitude until some nonlinearity (which is always present in some form) reduces the magnitude of the loop gain to exactly unity, at which point sustained oscillations will be obtained. This mechanism for starting oscillations by using positive feedback with a loop gain greater than unity, and then using a nonlinearity to reduce the loop gain to unity at the desired amplitude, will be exploited in the design of sinusoidal oscillators in Chapter 18. Our objective here is just the opposite: Now that we know how oscillations could occur in a negative-feedback amplifier, we wish to find methods to prevent their occurrence.
11.7.2 The Nyquist Plot
The Nyquist plot is a formalized approach for testing for stability based on the discussion above. It is simply a polar plot of loop gain, with frequency used as a parameter. Figure 11.28
874 Chapter 11
Feedback
Figure 11.28 The Nyquist plot of an unstable amplifier.
shows such a plot. Note that the radial distance is |Aβ| and the angle is the phase angle φ. The solid-line plot is for positive frequencies. Since the loop gain—and for that matter any gain function of a physical network—has a magnitude that is an even function of frequency and a phase that is an odd function of frequency, the Aβ plot for negative frequencies (shown in Fig. 11.28 as a broken line) can be drawn as a mirror image through the Re axis.
The Nyquist plot intersects the negative real axis at the frequency ω180. Thus, if this intersection occurs to the left of the point (–1, 0), we know that the magni- tude of loop gain at this frequency is greater than unity and the amplifier will be unstable. On the other hand, if the intersection occurs to the right of the point (–1, 0) the amplifier will be stable. It follows that if the Nyquist plot encircles the point (–1, 0) then the amplifier will be unstable. It should be mentioned, however, that this statement is a simplified version of the Nyquist criterion; nevertheless, it applies to all the circuits in which we are interested. For the full theory behind the Nyquist method and for details of its application, consult Haykin (1970).
EXERCISE
11.22 Consider a feedback amplifier for which the open-loop transfer function A(s) is given by 10 3
A(s) = 1 + s/104
Let the feedback factor β be a constant independent of frequency. Find the frequency ω180 at which the phase shift is 180°. Then, show that the feedback amplifier will be stable if the feedback
factorβislessthanacriticalvalueβcr andunstableifβ≥βcr,andfindthevalueofβcr.Hence,find the minimum value of the closed-loop gain for which the amplifier is stable.
Ans. ω180 = √3 × 104 rad/s; βcr = 0.008; Af min = 111.1
11.8 Effect of Feedback on the Amplifier Poles 875
HARRY NYQUIST— A DIVERSE ELECTRONICS FUNDAMENTALIST:
Harry Nyquist, a Swedish-born electrical engineer working for Bell Labs and its predecessor, was responsible for developments in communications electronics involving thermal noise, feedback-amplifier stability, telegraphy, facsimile, television, and many other areas.
In The Idea Factory, an excellent book on the history of Bell Labs, Jon Gertner notes that
[S]ome lawyers in the patent office of the Bell Labs decided to study whether there was an organizing principle that could explain why certain individuals were more productive than others. They discerned only one common thread: Workers with the most patents often shared lunch or breakfast with a Bell Labs electrical engineer named Harry Nyquist. It wasn’t the case that Nyquist gave them specific ideas. Rather, as one scientist recalled, “he drew people out, got them thinking.” More than anything, Nyquist asked good questions.
11.8 Effect of Feedback on the Amplifier Poles
The amplifier frequency response and stability are determined directly by its poles. Therefore we shall investigate the effect of feedback on the poles of the amplifier.7
11.8.1 Stability and Pole Location
We shall begin by considering the relationship between stability and pole location. For an amplifier or any other system to be stable, its poles should lie in the left half of the s plane. A pair of complex-conjugate poles on the jω axis gives rise to sustained sinusoidal oscillations. Poles in the right half of the s plane give rise to growing oscillations.
To verify the statement above, consider an amplifier with a pole pair at s = σ0 ± jωn. If this amplifier is subjected to a disturbance, such as that caused by closure of the power-supply switch, its transient response will contain terms of the form
v(t)=eσ0te+jωnt +e−jωnt=2eσ0t cos(ω t) (11.60) n
This is a sinusoidal signal with an envelope eσ0 t . Now if the poles are in the left half of the s plane, then σ0 will be negative and the oscillations will decay exponentially toward zero, as shown in Fig. 11.29(a), indicating that the system is stable. If, on the other hand, the poles are in
7For a brief review of poles and zeros and related concepts, refer to Appendix F.
876 Chapter 11
Feedback
(a)
(b)
(c)
Figure 11.29 Relationship between pole location and transient response.
the right half-plane, then σ0 will be positive, and the oscillations will grow exponentially (until some nonlinearity limits their growth), as shown in Fig. 11.29(b). Finally, if the poles are on the jω axis, then σ0 will be zero and the oscillations will be sustained, as shown in Fig. 11.29(c).
Although the discussion above is in terms of complex-conjugate poles, it can be shown that the existence of any right-half-plane poles results in instability.
11.8.2 Poles of the Feedback Amplifier
From the closed-loop transfer function in Eq. (11.57), we see that the poles of the feedback amplifier are the zeros of 1 + A(s)β(s). That is, the feedback amplifier poles are obtained by solving the equation
1 + A(s)β(s) = 0 (11.61)
which is called the characteristic equation of the feedback loop. It should therefore be apparent that applying feedback to an amplifier changes its poles.
In the following, we shall consider how feedback affects the amplifier poles. For this purpose we shall assume that the open-loop amplifier has real poles and no finite zeros (i.e., all the zeros are at s = ∞). This will simplify the analysis and enable us to focus our attention on the fundamental concepts involved. We shall also assume that the feedback factor β is independent of frequency.
11.8.3 Amplifier with a Single-Pole Response
Consider first the case of an amplifier whose open-loop transfer function is characterized by a single pole:
A(s) = A0 1+s/ωP
The closed-loop transfer function is given by
Af (s) = A0/(1 + A0β)
1+s/ωP(1+A0β)
Thus the feedback moves the pole along the negative real axis to a frequency ωPf , ωPf =ωP(1+A0β)
(11.62)
(11.63)
(11.64) This process is illustrated in Fig. 11.30(a). Figure 11.30(b) shows Bode plots for |A| and A .
f Note that while at low frequencies the difference between the two plots is 20 log(1 + A0β),
the two curves coincide at high frequencies. One can show that this indeed is the case by approximating Eq. (11.63) for frequencies ω ≫ ωP(1 + A0β):
Af(s)≃A0ωP ≃A(s) (11.65) s
Physically speaking, at such high frequencies the loop gain is much smaller than unity and the feedback is ineffective.
Figure 11.30(b) clearly illustrates the fact that applying negative feedback to an amplifier results in extending its bandwidth at the expense of a reduction in gain. Since the pole of the
–20 dB/decade
(a) (b)
Figure 11.30 Effect of feedback on (a) the pole location and (b) the frequency response of an amplifier having a single-pole, open-loop response.
11.8 Effect of Feedback on the Amplifier Poles 877
878 Chapter 11
Feedback
closed-loop amplifier never enters the right half of the s plane, the single-pole amplifier is stable for any value of β. Thus this amplifier is said to be unconditionally stable. This result, however, is hardly surprising, since the phase lag associated with a single-pole response can never be greater than 90°. Thus the loop gain never achieves the 180° phase shift required for the feedback to become positive.
EXERCISE
11.23 An op amp having a single-pole rolloff at 100 Hz and a low-frequency gain of 105 is operated in a feedback loop with β = 0.01. What is the factor by which feedback shifts the pole? To what frequency? If β is changed to a value that results in a nominal closed-loop gain of +1, to what frequency does the pole shift?
Ans. 1001; 100.1 kHz; 10 MHz
11.8.4 Amplifier with a Two-Pole Response
Consider next an amplifier whose open-loop transfer function is characterized by two real-axis poles:
A(s) = A0 (1+s/ωP1)(1+s/ωP2)
In this case, the closed-loop poles are obtained from 1 + A(s)β = 0, which leads to s2 +s(ωP1 +ωP2)+(1+A0β)ωP1ωP2 =0
(11.66)
(11.67)
(11.68)
From Eq. (11.68) we see that as the loop gain A0 β is increased from zero, the poles are brought closer together. Then a value of loop gain is reached at which the poles become coincident. If the loop gain is further increased, the poles become complex conjugate and move along a vertical line. Figure 11.31 shows the locus of the poles for increasing loop gain. This plot is called a root-locus diagram, where “root” refers to the fact that the poles are the roots of the characteristic equation.
From the root-locus diagram of Fig. 11.31 we see that this feedback amplifier also is unconditionally stable. Again, this result should come as no surprise; the maximum phase shift of A(s) in this case is 180° (90° per pole), but this value is reached at ω = ∞. Thus there is no finite frequency at which the phase shift reaches 180°.
Another observation to make on the root-locus diagram of Fig. 11.31 is that the open-loop amplifier might have a dominant pole, but this is not necessarily the case for the closed-loop amplifier. The response of the closed-loop amplifier can, of course, always be plotted once the poles have been found from Eq. (11.68). As is the case with second-order responses generally, the closed-loop response can show a peak (see Chapter 17). To be more specific,
Thus the closed-loop poles are given by
1 1
s=−2(ωP1 +ωP2)±2 (ωP1 +ωP2)2 −4(1+A0β)ωP1ωP2
Figure 11.31 Root-locus diagram for a feedback amplifier whose open-loop transfer function has two real poles.
the characteristic equation of a second-order network can be written in the standard form
s2 +sω0 +ω20 =0 (11.69)
Q
where ω0 is called the pole frequency and Q is called pole Q factor. The poles are complex if Q is greater than 0.5. A geometric interpretation for ω0 and Q of a pair of complex-conjugate poles is given in Fig. 11.32, from which we note that ω0 is the radial distance of the poles from the origin and that Q indicates the distance of the poles from the jω axis. Poles on the jω axis have Q = ∞.
By comparing Eqs. (11.67) and (11.69), we obtain the Q factor for the poles of the feedback amplifier as
Q = (1 + A0β)ωP1ωP2 (11.70) ωP1 +ωP2
From the study of second-order network responses in Chapter 17, it will be seen that the response of the feedback amplifier under consideration shows no peaking for Q ≤ 0.707. The boundary case corresponding to Q = 0.707 (poles at 45° angles) results in the maximally flat response. Figure 11.33 shows a number of possible responses obtained for various values of Q (or, correspondingly, various values of A0β).
Figure 11.32 Definition of ω0 and Q of a pair of complex- conjugate poles.
11.8 Effect of Feedback on the Amplifier Poles 879
880 Chapter 11
Feedback
Q1 Q
0.707 (maximally flat response)
12 dB/octave
0
Q 0.5
Q 0.3
v (log scale)
Figure 11.33 Normalized gain of a two-pole feedback amplifier for various values of Q. Note that Q is
determined by the loop gain according to Eq. (11.70).
EXERCISE
11.24 An amplifier with a low-frequency gain of 100 and poles at 104 rad/s and 106 rad/s is incorporated in a negative-feedback loop with feedback factor β. For what value of β do the poles of the closed-loop amplifier coincide? What is the corresponding Q of the resulting second-order system? For what value of β is a maximally flat response achieved? What is the low-frequency closed-loop gain in the maximally flat case?
Ans. 0.245; 0.5; 0.5; 1.96 V/V
Example 11.11
As an illustration of some of the ideas just discussed, we consider the positive-feedback circuit shown in Fig. 11.34(a). Find the loop transmission L(s) and the characteristic equation. Sketch a root-locus diagram for varying K, and find the value of K that results in a maximally flat response and the value of K that makes the circuit oscillate. Assume that the amplifier has frequency-independent gain, infinite input impedance, and zero output impedance.
Solution
To obtain the loop transmission, we short-circuit the signal source and break the loop at the amplifier input.WethenapplyatestvoltageVt andfindthereturnedvoltageVr,asindicatedinFig.11.34(b).The
Normalized gain (dB)
11.8 Effect of Feedback on the Amplifier Poles 881
Vs R RR
C
CC Vr CR KVo K
Vt
V1
(a)
1.586 0.707
(b)
j
s plane 45
K3 Q
K Q
K0
1 3
K1 Q 0.5
Q
45
0s
K3 Q
K 1.586 Q 0.707
(c)
Figure 11.34 Circuits and plot for Example 11.11.
loop transmission L(s) ≡ A(s)β(s) is given by
L(s)=−Vr =−KT(s) Vt
(11.71)
882
Chapter 11 Feedback
Example 11.11 continued
where T(s) is the transfer function of the two-port RC network shown inside the broken-line box in
Fig. 11.34(b):
Thus,
The characteristic equation is
that is,
T(s)≡Vr = V1
s(1/CR)
s2 +s(3/CR)+(1/CR)2
(11.72)
(11.73)
(11.74)
L(s) =
−s(K /CR)
s2 +s(3/CR)+(1/CR)2
1+L(s)=0
2 312 K s+s+−s=0
CR CR CR
we see that the pole frequency ω0 is given by
and the Q factor is
2 3−K12 s+s+=0
(11.75) By comparing this equation to the standard form of the second-order characteristic equation (Eq. 11.69),
CR CR
ω0 = 1 CR
Q=1 3−K
(11.76)
(11.77)
ThusforK=0,thepoleshaveQ=1 andarethereforelocatedonthenegativerealaxis.AsKisincreased, 3
the poles are brought closer together and eventually coincide (Q = 0.5, K = 1). Further increasing K results in the poles becoming complex and conjugate. The root locus is then a circle because the radial distance ω0 remains constant (Eq. 11.76) independent of the value of K.
The maximally flat response is obtained when Q = 0.707, which results when K = 1.586. In this case the poles are at 45° angles, as indicated in Fig. 11.34(c). The poles cross the jω axis into the right half of the s plane at the value of K that results in Q = ∞, that is, K = 3. Thus for K ≥ 3 this circuit becomes unstable. This might appear to contradict our earlier conclusion that the feedback amplifier with a second-order response is unconditionally stable. Note, however, that the circuit in this example is quite different from the negative-feedback amplifier that we have been studying. Here we have an amplifier with a positive gain K and a feedback network whose transfer function T(s) is frequency dependent. This feedback is in fact positive, and the circuit will oscillate at the frequency for which the phase of T(jω) is zero (which is 1/CR).
Example 11.11 illustrates the use of feedback (positive feedback in this case) to move the poles of an RC network from their negative real-axis locations to complex-conjugate locations. One can accomplish the same task using negative feedback, as the root-locus diagram of
11.8 Effect of Feedback on the Amplifier Poles 883
Figure 11.35 Root-locus diagram for an amplifier with three poles. The arrows indicate the pole movement as A0β is increased.
Fig. 11.31 demonstrates. The process of pole control is the essence of active-filter design, as will be discussed in Chapter 17.
11.8.5 Amplifiers with Three or More Poles
Figure 11.35 shows the root-locus diagram for a feedback amplifier whose open-loop response is characterized by three poles. As indicated, increasing the loop gain from zero moves the highest-frequency pole outward while the two other poles are brought closer together. As A0β is increased further, the two poles become coincident and then become complex and conjugate. A value of A0β exists at which this pair of complex-conjugate poles enters the right half of the s plane, thus causing the amplifier to become unstable.
This result is not entirely unexpected, since an amplifier with three poles has a phase shift that reaches –270° as ω approaches ∞. Thus there exists a finite frequency, ω180, at which the loop gain has 180° phase shift.
From the root-locus diagram of Fig. 11.35, we observe that one can always maintain amplifier stability by keeping the loop gain A0β smaller than the value corresponding to the poles entering the right half-plane. In terms of the Nyquist diagram, the critical value of A0β is that for which the diagram passes through the (–1, 0) point. Reducing A0β below this value causes the Nyquist plot to shrink and thus intersect the negative real axis to the right of the (–1, 0) point, indicating stable amplifier performance. On the other hand, increasing A0β above the critical value causes the Nyquist plot to expand, thus encircling the (–1, 0) point and indicating unstable performance.
For a given open-loop gain A0 the conclusions above can be stated in terms of the feedback factor β. That is, there exists a maximum value for β above which the feedback amplifier becomes unstable. Alternatively, we can state that there exists a minimum value for the closed-loop gain Af 0 below which the amplifier becomes unstable. To obtain lower values of closed-loop gain, one needs therefore to alter the loop transfer function L(s). This is the process known as frequency compensation. We shall study the theory and techniques of frequency compensation in Section 11.10.
884 Chapter 11
Feedback
Before leaving this section, we point out that construction of the root-locus diagram for amplifiers having three or more poles as well as finite zeros is an involved process for which a systematic procedure exists. However, such a procedure will not be presented here, and the interested reader should consult Haykin (1970). Although the root-locus diagram provides the amplifier designer with considerable insight, other, simpler techniques based on Bode plots can be effectively employed, as will be explained in Section 11.9.
EXERCISE
11.25 Consider a feedback amplifier for which the open-loop transfer function A(s) is given by 10 3
A(s) = 1 + s/104
Let the feedback factor β be frequency independent. Find the closed-loop poles as functions of β, and show that the root locus is that of Fig. E11.26. Also find the value of β at which the amplifier becomes unstable. (Note: This is the same amplifier that was considered in Exercise 11.22.)
Ans. See Fig. E11.26; βcritical = 0.008
Figure E11.26
11.9 Stability Study Using Bode Plots 11.9.1 Gain and Phase Margins
From Sections 11.17 and 11.18 we know that whether a feedback amplifier is or is not stable can be determined by examining its loop gain Aβ as a function of frequency. One of the simplest and most effective means for doing this is through the use of a Bode plot for Aβ, such as the one shown in Fig. 11.36. (Note that because the phase approaches –360°, the circuit examined is a fourth-order one.) The feedback amplifier whose loop gain is plotted in Fig. 11.36 will be stable, since at the frequency of 180° phase shift, ω180, the magnitude of the loop gain is less than unity (negative dB). The difference between the value of |Aβ| at ω180 and unity, called the gain margin, is usually expressed in decibels. The gain margin represents the amount by which the loop gain can be increased while stability is maintained. Feedback amplifiers are usually designed to have sufficient gain margin to allow for the inevitable changes in loop gain with temperature, time, and so on.
Another way to investigate the stability and to express its degree is to examine the Bode plot at the frequency for which |Aβ| = 1, which is the point at which the magnitude plot crosses the 0-dB line. If at this frequency the phase angle is less (in magnitude) than 180°, then the amplifier is stable. This is the situation illustrated in Fig. 11.36. The difference between the phase angle at this frequency and 180° is termed the phase margin. On the other hand, if at the frequency of unity loop-gain magnitude, the phase lag is in excess of 180°, the amplifier will be unstable.
Figure 11.36 Bode plot for the loop gain Aβ illustrating the definitions of the gain and phase margins.
11.9 Stability Study Using Bode Plots 885
886 Chapter 11 Feedback
EXERCISE
11.26 Consider an op amp having a single-pole, open-loop response with A0 = 105 and fP = 10 Hz. Let the op amp be ideal otherwise (infinite input impedance, zero output impedance, etc.). If this amplifier is connected in the noninverting configuration with a nominal low-frequency, closed-loop gain of 100, find the frequency at which |Aβ| = 1. Also, find the phase margin.
Ans. 104 Hz; 90°
11.9.2 Effect of Phase Margin on Closed-Loop Response
Feedback amplifiers are normally designed with a phase margin of at least 45°. The amount of phase margin has a profound effect on the shape of the closed-loop gain response. To see this relationship, consider a feedback amplifier with a large low-frequency loop gain, A0β ≫ 1. It follows that the closed-loop gain at low frequencies is approximately 1/β. Denoting the frequency at which the magnitude of loop gain is unity by ω1, we have (refer to Fig. 11.36)
where
At ω1 the closed-loop gain is
A(jω1)β =1×e−jθ
θ = 180° − phase margin
Af (jω1) = A(jω1) 1+A(jω1)β
(11.78)
(11.79)
(11.80)
(11.81)
(11.82)
(11.83)
Substituting from Eq. (11.78) gives
Thus the magnitude of the gain at ω1 is
Af (jω1) = 1/β
(1/β)e−jθ Af(jω1)= 1+e−jθ
|1+e−jθ| For a phase margin of 45°, θ = 135°; and we obtain
Af (jω1) = 1.3 1 β
That is, the gain peaks by a factor of 1.3 above the low-frequency value of 1/β. This peaking increases as the phase margin is reduced, eventually reaching ∞ when the phase margin is zero. Zero phase margin, of course, implies that the amplifier can sustain oscillations [poles on the jω axis; Nyquist plot passing through (–1, 0)].
11.9 Stability Study Using Bode Plots 887
EXERCISE
11.27 Find the closed-loop gain at ω1 relative to the low-frequency gain when the phase margin is 30°, 60°, and 90°.
Ans. 1.93; 1; 0.707
11.9.3 An Alternative Approach for Investigating Stability
Investigating stability by constructing Bode plots for the loop gain Aβ can be a tedious and time-consuming process, especially if we have to investigate the stability of a given amplifier for a variety of feedback networks. An alternative approach, which is much simpler, is to construct a Bode plot for the open-loop gain A( jω) only. Assuming for the time being that β is independent of frequency, we can plot 20 log(1/β) as a horizontal straight line on the same plane used for 20 log|A|. The difference between the two curves will be
20log|A(jω)|−20log 1 =20log|Aβ| (11.84) β
which is the loop gain (in dB). We may therefore study stability by examining the difference between the two plots. If we wish to evaluate stability for a different feedback factor, we simply draw another horizontal straight line at the level 20 log(1/β).
To illustrate, consider an amplifier whose open-loop transfer function is characterized by three poles. For simplicity let the three poles be widely separated—say, at 0.1 MHz, 1 MHz, and 10 MHz, as shown in Fig. 11.37. Note that because the poles are widely separated, the phase is approximately –45° at the first pole frequency, –135° at the second, and –225° at the third. The frequency at which the phase of A( jω) is –180° lies on the –40-dB/decade segment, as indicated in Fig. 11.37.
The open-loop gain of this amplifier can be expressed as 105
obtained as
φ = −tan−1 f /105 + tan−1 f /106 + tan−1 f /107 (11.86)
The magnitude and phase graphs shown in Fig. 11.37 are obtained using the method for constructing Bode plots (Appendix F). These graphs provide approximate values for important amplifier parameters, with more exact values obtainable from Eqs. (11.85) and (11.86). For example, the frequency f180 at which the phase angle is 180° can be found from Fig. 11.37 to be approximately 3.2 × 106 Hz. Using this value as a starting point, a more exact value can be found by trial and error using Eq. (11.86). The result is f180 = 3.34 × 106 Hz. At this frequency, Eq. (11.85) gives a gain magnitude of 58.2 dB, which is reasonably close to the approximate value of 60 dB given by Fig. 11.37.
A = (1 + jf /105)(1 + jf /106)(1 + jf /107) (11.85) from which |A| can be easily determined for any frequency f (in Hz), and the phase can be
888 Chapter 11
Feedback
dB
A
20 dB/decade (a)
25 dB gain margin
100
90 20 log A X1
20 log 1/
85 dB (stable)
20 log 1/
for zero margins
20 log 1/
50 dB (unstable)
10 102 10 102
80
70
60
50
40
30
20
10
0
103 104
0 45
90 135 180
225 270
105
X2
107
107
40 dB/decade (b)
60 dB/decade
108 f (Hz)
108 f (Hz)
72 phase margin
Figure 11.37 Stability analysis using Bode plot of |A|.
Consider next the straight line labeled (a) in Fig. 11.37. This line represents a feedback factorforwhich20log(1/β)=85dB,whichcorrespondstoβ=5.623×10−5 andaclosed-loop gain of 83.6 dB. Since the loop gain is the difference between the |A| curve and the 1/β line, the point of intersection X1 corresponds to the frequency at which |Aβ| = 1. Using the graphs of Fig. 11.37, this frequency can be found to be approximately 5.6 × 105 Hz. A more exact value of 4.936 × 105 can be obtained using the transfer function equations. At this frequency the phase angle is approximately –108°. Thus the closed-loop amplifier, for which 20 log(1/β) = 85 dB, will be stable with a phase margin of 72°. The gain margin can be easily obtained from Fig. 11.37; it is 25 dB.
Next, suppose that we wish to use this amplifier to obtain a closed-loop gain of 50-dB nominal value. Since A0 = 100 dB, we see that A0β ≫ 1 and 20 log(A0β) ≃ 50 dB, resulting in 20 log(1/β) ≃ 50 dB. To see whether this closed-loop amplifier is or is not stable, we draw line (b) in Fig. 11.37 with a height of 50 dB. This line intersects the open-loop gain curve at point X2, where the corresponding phase is greater than 180°. Thus the closed-loop amplifier with 50-dB gain will be unstable.
f180
106
f180
104 105 108
106
In fact, it can easily be seen from Fig. 11.37 that the minimum value of 20 log(1/β) that can be used, with the resulting amplifier being stable, is 60 dB. In other words, the minimum value of stable closed-loop gain obtained with this amplifier is approximately 60 dB. At this value of gain, however, a manufactured version of this amplifier may still oscillate, since no margin is left to allow for possible changes in gain.
Since the 180°-phase point always occurs on the –40-dB/decade segment of the Bode plot for |A|, a rule of thumb to guarantee stability is as follows: The closed-loop amplifier will be stable if the 20 log(1/β) line intersects the 20 log|A| curve at a point on the –20-dB/decade segment. Following this rule ensures that a phase margin of at least 45° is obtained. For the example of Fig. 11.37, the rule implies that the maximum value of β is 10−4 , which corresponds to a closed-loop gain of approximately 80 dB.
The rule of thumb above can be generalized for the case in which β is a function of frequency. The general rule states that at the intersection of 20 log[1/|β(jω)|] and 20 log|A( jω)| the difference of slopes (called the rate of closure) should not exceed 20 dB/ decade.
EXERCISE
11.28 Consider an op amp whose open-loop gain is identical to that of Fig. 11.37. Assume that the op amp is ideal otherwise. Let the op amp be connected as a differentiator. Use the rule of thumb above to show that for stable performance the differentiator time constant should be greater than 159 ms. [Hint: Recall that for a differentiator, the Bode plot for 1/|β(jω)| has a slope of +20 dB/decade and intersects the 0-dB line at 1/τ , where τ is the differentiator time constant.]
11.10 Frequency Compensation
In this section, we shall discuss methods for modifying the open-loop transfer function A(s) of an amplifier having three or more poles so that the closed-loop amplifier is stable for a given desired value of closed-loop gain. This process is referred to as frequency compensation.
11.10.1 Theory
The simplest method of frequency compensation consists of introducing a new pole in the function A(s) at a frequency, fD, sufficiently low that the modified open-loop gain, A′(s), intersects the 20 log(1/|β|) curve with a slope difference of 20dB/decade. As an example, let it be required to compensate the amplifier whose A(s) is shown in Fig. 11.38 such that closed-loop amplifiers with β as high as 10−2 (i.e., closed-loop gains as low as approximately 40 dB) will be stable. First, we draw a horizontal straight line at the 40-dB level to represent 20 log(1/β), as shown in Fig. 11.38. We then locate point Y on this line at the frequency of the first pole, fP1. From Y we draw a line with –20-dB/decade slope and determine the point at which this line intersects the dc gain line, point Y′. This latter point
11.10 Frequency Compensation 889
890 Chapter 11
Feedback
dB
Z
100
80
60
40
20
0 102 103
fD fD
Y
A
A
A 20 dB/decade
20 log 1/ 40 dB
YZ
105 106
40 dB/decade
60 dB/decade
107 108
10
104
f (Hz)
Figure 11.38 Frequency compensation for β = 10− 2 . The response labeled A′ is obtained by introducing an ′′ ′
additional pole at fD . The A response is obtained by moving the original low-frequency pole to fD .
gives the frequency fD of the new pole that has to be introduced in the open-loop transfer function.
fP1 fP2 fP3
The compensated open-loop response A′(s) is indicated in Fig. 11.38. It has four poles:
at fD, fP1, fP2, and fP3. Thus A′ begins to roll off with a slope of –20 dB/decade at fD. At fP1
the slope changes to – 40 dB/decade, at f it changes to – 60 dB/decade, and so on. Since the ′P2
20 log(1/β) line intersects the 20log A curve at point Y on the –20-dB/decade segment, the closed-loop amplifier with this β value (or lower values) will be stable.
A serious disadvantage of this compensation method is that at most frequencies the open-loop gain has been drastically reduced. This means that at most frequencies the amount of feedback available will be small. Since all the advantages of negative feedback are directly proportional to the amount of feedback, the performance of the compensated amplifier will be impaired.
Careful examination of Fig. 11.38 shows that the gain A′(s) is low because of the pole at fP1. If we can somehow eliminate this pole, then—rather than locating point Y, drawing YY′, and so on—we can start from point Z (at the frequency of the second pole) and draw the line ZZ′. This would result in the open-loop curve A′′(s), which shows considerably higher gain than A′(s).
Although it is not possible to eliminate the pole at fP1, it is usually possible to shift that pole from f = fP1 to f = fD′ . This makes the pole dominant and eliminates the need for introducing an additional lower-frequency pole, as will be explained next.
11.10 Frequency Compensation 891
B B
Q1
(b) (c)
Figure11.39 (a)Twocascadedgainstagesofamultistageamplifier.(b)Equivalentcircuitfortheinterface between the two stages in (a). (c) Same circuit as in (b), but with a compensating capacitor CC added. Note that the analysis here applies equally well to MOS amplifiers.
11.10.2 Implementation
We shall now address the question of implementing the frequency-compensation scheme discussed above. The amplifier circuit normally consists of a number of cascaded gain stages, with each stage responsible for one or more of the transfer function poles. Through manual and/or computer analysis of the circuit, one identifies the stage that introduces each of the important poles fP1, fP2, and so on. For the purpose of our discussion, assume that the first pole fP1 is introduced at the interface between the two cascaded differential stages shown in Fig. 11.39(a). In Fig. 11.39(b) we show a simple small-signal model of the circuit at this interface. Current source Ix represents the output-signal current of the Q1−Q2 stage. Resistance Rx and capacitance Cx represent the total resistance and capacitance between the two nodes B and B′. It follows that the pole fP1 is given by
fP1 = 1 (11.87) 2πCxRx
LetusnowconnectthecompensatingcapacitorCC betweennodesBandB′.Thiswillresult in the modified equivalent circuit shown in Fig. 11.39(c), from which we see that the pole introducedwillnolongerbeatfP1;rather,thepolecanbeatanydesiredlowerfrequencyfD′ :
fD′ = 1 (11.88) 2π(Cx +CC)Rx
(a)
B
B
BB
892 Chapter 11
Feedback
We thus conclude that one can select an appropriate value for CC to shift the pole frequency from fP1 to the value fD′ determined by point Z′ in Fig. 11.38.
AtthisjunctureitshouldbepointedoutthataddingthecapacitorCC willusuallyresultin changes in the location of the other poles (those at fP2 and fP3). One might therefore need to calculate the new location of fP2 and perform a few iterations to arrive at the required value for CC .
AdisadvantageofthisimplementationmethodisthattherequiredvalueofCC isusually quite large. Thus if the amplifier to be compensated is an IC op amp, it will be difficult, and probably impossible, to include this compensating capacitor on the IC chip. (As pointed out in Chapter 8 and in Appendix A, the maximum practical size of a monolithic capacitor is about 100 pF.) An elegant solution to this problem is to connect the compensating capacitor in the feedback path of an inverting amplifier stage. Because of the Miller effect (Section 10.3), the compensating capacitance will be multiplied by the stage gain, resulting in a much larger effective capacitance. Furthermore, as explained later, another unexpected benefit accrues.
11.10.3 Miller Compensation and Pole Splitting
Figure 11.40(a) shows one gain stage in a multistage amplifier. For simplicity, the stage is shown as a common-emitter amplifier, but in practice it can be a more elaborate circuit. In the feedback path of this common-emitter stage we have placed a compensating capacitor Cf .
Figure 11.40(b) shows a simplified equivalent circuit of the gain stage of Fig. 11.40(a). Here R1 and C1 represent the total resistance and total capacitance between node B and ground. Similarly, R2 and C2 represent the total resistance and total capacitance between node C and ground. Furthermore, it is assumed that C1 includes the Miller component due to capacitance Cμ, and C2 includes the input capacitance of the succeeding amplifier stage. Finally, Ii represents the output signal current of the preceding stage.
In the absence of the compensating capacitor Cf , we can see from Fig. 11.40(b) that there are two poles—one at the input and one at the output. Let us assume that these two poles are fP1 and fP2 of Fig. 11.38; thus,
fP1 = 1 2πC1R1
fP2 = 1 (11.89) 2πC2R2
(a)
(b)
Figure 11.40 (a) A gain stage in a multistage amplifier with a compensating capacitor connected in the feedback path, and (b) equivalent circuit. Note that although a BJT is shown, the analysis applies equally well to the MOSFET case.
With Cf present, analysis of the circuit yields the transfer function
its effect. The denominator polynomial D(s) can be written in the form
s s 1 1 s2
D(s)= 1+ω′ 1+ω′ =1+s ω′ +ω′ +ω′ ω′ (11.91) P1P2 P1P2P1P2
where ω′ and ω′ are the new frequencies of the two poles. Normally one of the poles will P1 P2
be dominant; ω′ ≪ ω′ . Thus, P1 P2
s s2
D(s)≃1+ ω′ + ω′ ω′ (11.92)
P1 P1P2
Equating the coefficients of s in the denominator of Eq. (11.90) and in Eq. (11.92) results in
ω′= 1
P1 C1R1 +C2R2 +Cf (gmR1R2 +R1 +R2)
which can be approximated by
ω′ ≃ 1 (11.93) P1 gmR2Cf R1
To obtain ω′ we equate the coefficients of s2 in the denominator of Eq. (11.90) and in P2
Eq. (11.92) and use Eq. (11.93):
ω′ ≃ gmCf (11.94) P2 C1C2 +Cf (C1 +C2)
From Eqs. (11.93) and (11.94), we see that as C is increased, ω′ is reduced and ω′ is f P1 P2
increased. This action is referred to as pole splitting. Note that the increase in ω′ is highly P2
beneficial; it allows us to move point Z (see Fig. 11.38) further to the right, thus resulting in higher compensated open-loop gain. Finally, note from Eq. (11.93) that Cf is multiplied by the Miller effect factor gmR2, thus resulting in a much larger effective capacitance, gmR2Cf . In other words, the required value of Cf will be much smaller than that of CC in Fig. 11.39.
Example 11.12
Consider an op amp whose open-loop transfer function is identical to that shown in Fig. 11.37. We wish to compensate this op amp so that the closed-loop amplifier with resistive feedback is stable for any gain (i.e., for β up to unity). Assume that the op-amp circuit includes a stage such as that of Fig. 11.40 with C1 = 100 pF, C2 = 5 pF, and gm = 40 mA/V, that the pole at fP1 is caused by the input circuit of that stage, and that the pole at fP2 is introduced by the output circuit. Find the value of the compensating capacitor
Vo sCf −gm R1R2
I =1+sCR +CR +C(g RR +R +R)+s2CC +C(C +C)RR (11.90)
11.10 Frequency Compensation 893
i 1122fm1212 12f1212
The zero is usually at a much higher frequency than the dominant pole, and we shall neglect
894
Chapter 11 Feedback
Example 11.12 continued
for two cases: either if it is connected between the input node B and ground or in the feedback path of the
transistor.
Solution
First we determine R1 and R2 from
Thus,
Thus,
fP1 =0.1MHz= 1 2πC1R1
105
R1 = 2π
fP2 =1MHz= 105
1 2πC2R2
R2 = π
IfacompensatingcapacitorCC isconnectedacrosstheinputterminalsofthetransistorstage,thenthe
frequency of the first pole changes from fP1 to fD′ :
fD′= 1
2πC1+CC R1
The second pole remains unchanged at 1 MHz. The required value for fD′ is determined by drawing a –20-dB/decade line from the 1-MHz frequency point on the 20 log(1/β) = 20 log 1 = 0 dB line. This line will intersect the 100-dB dc gain line at 10 Hz. Thus,
fD′ =10Hz= 1 2π(C1 +CC)R1
whichresultsinCC ≃1μF,whichisquitelargeandcertainlycannotbeincludedontheICchip.
Next, if a compensating capacitor Cf is connected in the feedback path of the transistor, then both
poles change location to the values given by Eqs. (11.93) and (11.94):
′ 1 ′ gmCf
fP1 ≃2πg RCR fP2 ≃2πCC +CC +C (11.95)
m2f1 12f12 Todeterminewhereweshouldlocatethefirstpole,weneedtoknowthevalueoff′ .Asanapproximation,
P2
letusassumethatCf ≫C2,whichenablesustoobtain
f′ ≃ gm =60.6MHz
assume that the second pole will be at fP3. This requires that the modified first pole be located at
f′ =fP3 =107Hz=100Hz P1 A0 105
P2 2π C1 +C2
Thus it appears that this pole will move to a frequency higher than fP3 (which is 10 MHz). Let us therefore
Thus,
f′ =100Hz= 1
P1 2πgmR2Cf R1
which results in Cf = 78.5 pF. Although this value is indeed much greater than C2 , we can determine the location of the pole f ′ from Eq. (11.95), which yields f ′ = 57.2 MHz, confirming that this pole has indeed
P2 P2 been moved past fP3.
We conclude that using Miller compensation not only results in a much smaller compensating capacitor but, owing to pole splitting, also enables us to place the dominant pole a decade higher in frequency. This results in a wider bandwidth for the compensated op amp.
EXERCISES
11.29 Amultipoleamplifierhavingafirstpoleat1MHzandanopen-loopgainof100dBistobecompensated for closed-loop gains as low as 20 dB by the introduction of a new dominant pole. At what frequency must the new pole be placed?
Ans. 100 Hz
11.30 FortheamplifierdescribedinExercise11.29,ratherthanintroducinganewdominantpole,wecanuse additional capacitance at the circuit node at which the first pole is formed to reduce the frequency of the first pole. If the frequency of the second pole is 10 MHz and if it remains unchanged while additional capacitance is introduced as mentioned, find the frequency to which the first pole must be lowered so that the resulting amplifier is stable for closed-loop gains as low as 20 dB. By what factor must the capacitance at the controlling node be increased?
Summary 895
Ans. 1000 Hz; 1000
Summary
Negative feedback is employed to make the amplifier gain less sensitive to component variations; to control input and output resistances; to extend bandwidth; to reduce nonlinear distortion; and to enhance signal-to-interference ratio.
The advantages above are obtained at the expense of a reduction in gain and at the risk of the amplifier becoming unstable (that is, oscillating). The latter problem is solved by careful design.
The structure of an ideal negative-feedback amplifier is shown in Fig. 11.1. Table 11.1 summarizes the parameters
and relationships governing the operation of the ideal structure.
For each of the four basic types of amplifier, there is an appropriate feedback topology. The four topologies, together with their analysis procedure and their effects on input and output impedances, are summarized in Table 11.2 in Section 11.6.
The key feedback parameters are the loop gain (Aβ), which for negative feedback must be a positive dimen- sionless number, and the amount of feedback (1 + Aβ). The latter directly determines gain reduction, gain
896 Chapter 11 Feedback
desensitivity, bandwidth extension, and changes in Ri
andRo.
The loop gain Aβ can be determined by breaking the feedback loop, as illustrated in Figs. 11.2 and 11.9. The value of Aβ can be used together with the feedback factor β to determine A and hence Af . This method, though simple, is incomplete as it does not enable the determination of the input and output resistances. For these, we utilize the systematic method for feedback analysis (refer to Table 11.2).
The ideal or upper-bound value of the closed-loop gain
Af is 1/β and is approached when Aβ ≫ 1.
Since A and β are in general frequency dependent, the poles of the feedback amplifier are obtained by solving the characteristic equation 1 + A(s)β(s) = 0.
For the feedback amplifier to be stable, its poles must all be in the left half of the s plane.
Stability is guaranteed if at the frequency for which the phase angle of Aβ is 180° (i.e., ω180), |Aβ| is less than
PROBLEMS
Computer Simulation Problems
Problems identified by the Multisim/PSpice icon are intended to demonstrate the value of using SPICE simulation to verify hand analysis and design, and to investigate important issues such as allowable signal swing and amplifier nonlinear distortion. Instructions to assist in setting up PSpice and Multisim simulations for all the indicated problems can be found in the corresponding files on the website. Note that if a particular parameter value is not specified in the problem statement, you are to make a reasonable assumption.
Section 11.1: The General Feedback Structure
11.1 A negative-feedback amplifier has a closed-loop gain
Af = 200 and an open-loop gain A = 104 . What is the feedback factor β? If a manufacturing error results in a reduction of A to 103, what closed-loop gain results? What is the percentage change in Af corresponding to this factor of 10 reduction in A?
unity; the amount by which it is less than unity, expressed in decibels, is the gain margin. Alternatively, the amplifier is stable if, at the frequency at which |Aβ| = 1, the phase angle is less than 180°; the difference is the phase margin.
The stability of a feedback amplifier can be analyzed by constructing a Bode plot for |A| and superimposing on it a plot for 20 log 1/|β |. Stability is guaranteed if the two plots intersect with a difference in slope no greater than 6 dB/octave.
To make a given amplifier stable for a given feedback factor β, the open-loop frequency response is suitably modified by a process known as frequency compensation.
A popular method for frequency compensation involves connecting a feedback capacitor across an inverting stage in the amplifier. This causes the pole formed at the input of the amplifier stage to shift to a lower frequency and thus become dominant, while the pole formed at the output of the amplifier stage is moved to a very high frequency and thus becomes unimportant. This process is known as pole splitting.
11.2 Consider the op-amp circuit shown in Fig. P11.2, where the op amp has infinite input resistance and zero output resistance but finite open-loop gain A.
A
Vs Vo
R2 R1
Figure P11.2
(a) Convince yourself that β = R1 / R1 + R2 .
(b) If R1 = 10 k, find R2 that results in Af = 10 V/V
for the following three cases: (i) A = 1000 V/V; (ii) A = 200 V/V; (iii) A = 15 V/V.
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CHAPTER 11 PROBLEMS
(c) For each of the three cases in (b), find the percentage change in Af that results when A decreases by 20%. Comment on the results.
11.3 The noninverting buffer op-amp configuration shown in Fig. P11.3 provides a direct implementation of the feedback loop of Fig. 11.1. Assuming that the op amp has infinite input resistance and zero output resistance, what is β? If A = 1000, what is the closed-loop voltage gain? What is the amount of feedback(indB)?ForVs =1V,findVo andVi.IfAdecreases by 10%, what is the corresponding percentage decrease in Af ?
D 11.8 An amplifier has an open-loop gain with a nominal value of 1000 but can vary from unit to unit by as much as ±50% of nominal. It is required to apply negative feedback to this amplifier so that the variability of the closed-loop gain of the resulting feedback amplifier is limited to ±1%. What is the largest possible nominal value of closed-loop gain that can be achieved? Now if three of these feedback amplifiers are placed in cascade, what is the nominal value of the gain of the resulting cascade amplifier? What is the expected variability of this gain?
11.9 The op amp in the circuit of Fig. P11.9 has an open-circuit voltage gain μ, a differential input resistance Rid , and a negligibly small output resistance. It is connected in the noninverting configuration with a feedback network consisting of a voltage divider (R1,R2). While β is still determined by the divider ratio [i.e., β = R1 /(R1 + R2 )], the open-loop gain A is no longer simply equal to μ. This is because the feedback network now loads the input of the amplifier (because of the finite Rid ). To determine the value of A, use the method outlined in Section 11.1.3 to determine the loop gain Aβ. Thus show that
Problems 897
Figure P11.3
A
11.4 In a particular circuit represented by the block diagram of Fig. 11.1, a signal of 1 V from the source results in a difference signal of 10 mV being provided to the amplifying element A, and 5 V appearing at the output. For this arrangement, identify the values of A and β that apply.
11.5 (a) Show that in a negative-feedback amplifier with loop gain Aβ ≫ 1, the closed-loop gain Af is lower than its ideal value of 1/β by (100/Aβ)%.
(b) What is the minimum loop gain required so that Af is within (i) 0.1%, (ii) 1%, and (iii) 5% of its ideal value?
Vs
Figure P11.9
A=μ Rid
Rid +(R1∥R2)
m
R2 R1
Vo
11.6 In a particular amplifier design, the β network consists of a linear potentiometer for which β is 0.00 at one end, 1.00 at the other end, and 0.50 in the middle. As the potentiometer is adjusted, find the three values of closed-loop gain that result when the amplifier open-loop gain is (a) 1 V/V, (b) 10 V/V, (c) 100 V/V, (d) 1000 V/V, and (e) 10,000 V/V. Provide your results in a table in which there is a row for each value of A and a column for each value of β.
11.7 A newly constructed feedback amplifier undergoes a performance test with the following results: With the feedback connection removed, a source signal of 2 mV is required to provide a 5-V output; with the feedback connected, a 5-V output requires a 100-mV source signal. For this amplifier, identify values of A, β , Aβ , the closed-loop gain, and the amount of feedback (in dB).
Section 11.2: Some Properties of Negative Feedback
11.10 For the negative-feedback loop of Fig. 11.1, find the loop gain Aβ for which the sensitivity of closed-loop gain to open-loop gain [i.e., (dAf /Af )/(dA/A)] is –40 dB. For what value of Aβ does the sensitivity become 1/5?
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898 Chapter 11 Feedback
D 11.11 A designer is considering two possible designs of a feedback amplifier. The ultimate goal is Af = 10 V/V. One design employs an amplifier for which A = 1000 V/V and the other uses A = 500 V/V. Find β and the desensitivity factor in both cases. If the A = 1000 amplifier units have a gain uncertainty of ±10%, what is the gain uncertainty for the closed-loop amplifiers utilizing this amplifier type? If the same result is to be achieved with the A = 500 amplifier, what is the maximum allowable uncertainty in its gain?
D11.12 Adesignerisrequiredtoachieveaclosed-loopgain of 10 ± 0.1% V/V using a basic amplifier whose gain variation is ± 10%. What nominal value of A and β (assumed constant) are required?
D 11.13 A circuit designer requires a gain of 25 ± 1% V/V using an amplifier whose gain varies by a factor of 10 over temperature and time. What is the lowest gain required? The value of β? (Hint: Since the change in the open-loop gain is very large, do not use differential analysis.)
D 11.14 A power amplifier employs an output stage whose gain varies from 2 to 12 for various reasons. What is the gain of an ideal (nonvarying) amplifier connected to drive it so that an overall gain with feedback of 100 ± 5% V/V can be achieved? What is the value of β to be used? What are the requirements if Af must be held within ±0.5%? For each of these situations, what preamplifier gain and feedback factor β are required if Af is to be 10 V/V (with the two possible tolerances)? (Hint: Since the change in the open-loop gain is very large, do not use differential analysis.)
D 11.15 It is required to design an amplifier with a gain of 100 that is accurate to within ±1%. You have available amplifier stages with a gain of 1000 that is accurate to within ±30%. Provide a design that uses a number of these gain stages in cascade, with each stage employing negative feedback of an appropriate amount. Obviously, your design should use the lowest possible number of stages while meeting specification.
D *11.16 It is required to design an amplifier to have a nominal closed-loop gain of 10 V/V using a battery-operated amplifier whose gain reduces to half its normal full-battery value over the life of the battery. If only 2% drop in closed-loop gain is desired, what nominal open-loop amplifier gain must be used in the design? (Note that since the change in A is large, it is inaccurate to use differentials.) What value
of β should be chosen? If component-value variation in the β network may produce as much as a ±1% variation in β, to what value must A be raised to ensure the required minimum gain?
D 11.17 Design a feedback amplifier that has a closed-loop gain of 100V/V and is relatively insensitive to change in basic-amplifier gain. In particular, it should provide a reduction in Af to 99 V/V for a reduction in A to one-tenth its nominal value. What is the required loop gain? What nominal value of A is required? What value of β should be used? What would the closed-loop gain become if A were increased tenfold? If A were made infinite?
11.18 Consider an amplifier having a midband gain AM and a low-frequency response characterized by a pole at s = −ωL and a zero at s = 0. Let the amplifier be connected in a negative-feedback loop with a feedback factor β. Find an expression for the midband gain and the lower 3-dB frequency of the closed-loop amplifier. By what factor have both changed?
11.19 A capacitively coupled amplifier has a midband gain of 1000 V/V, a single high-frequency pole at 10 kHz, and a single low-frequency pole at 100 Hz. Negative feedback is employed so that the midband gain is reduced to 10. What are the upper and lower 3-dB frequencies of the closed-loop gain?
D11.20 Low-costaudiopoweramplifiersoftenavoiddirect coupling of the loudspeaker to the output stage because any resulting dc bias current in the speaker can use up (and thereby waste) its limited mechanical dynamic range. Unfortunately, the coupling capacitor needed can be large! But feedback helps. For example, for an 8- loudspeaker and fL = 100 Hz, what size capacitor is needed? Now, if feedback is arranged around the amplifier and the speaker so that a closed-loop gain Af =10V/Visobtainedfromanamplifierwhoseopen-loop gain is 1000 V/V, what value of fLf results? If the ultimate product-design specification requires a 50-Hz cutoff, what capacitor can be used?
D *11.21 It is required to design a dc amplifier with a low-frequency gain of 1000 and a 3-dB frequency of 1 MHz. You have available gain stages with a gain of 1000 but with a dominant high-frequency pole at 20 kHz. Provide a design that employs a number of such stages in cascade, each with negative feedback of an appropriate amount. Use identical stages.
CHAPTER 11 PROBLEMS
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CHAPTER 11 PROBLEMS
Hint: The 3-dB frequency of a cascade of N iden- tical gain stages, each with a 3-dB frequency f3dB|stage is given by
√
f| =f| 21/N−1
D11.22 Designasupply-ripple-reducedpoweramplifierfor which the output stage can be modeled by the block diagram of Fig. 11.5, where A1 = 0.9 V/V, and the power-supply ripple VN = ± 1 V. A closed-loop gain of 10 V/V is desired. What is the gain of the low-ripple preamplifier needed to reduce the output ripple to ±100 mV? To ±10 mV? To ±1 mV? For each case, specify the value required for the feedback factor β.
D 11.23 A feedback amplifier is to be designed using a feedback loop connected around a two-stage amplifier. The first stage is a direct-coupled, small-signal amplifier with a high upper 3-dB frequency. The second stage is a power-output stage with a midband gain of 10 V/V and upper and lower 3-dB frequencies of 8 kHz and 80 Hz, respectively. The feedback amplifier should have a midband gain of 100 V/V and an upper 3-dB frequency of 40 kHz. What is the required gain of the small-signal amplifier? What value of β should be used? What does the lower 3-dB frequency of the overall amplifier become?
*11.24 The complementary BJT follower shown in Fig. P11.24(a) has the approximate transfer characteristic shown in Fig. P11.24(b). Observe that for −0.7 V ≤ vI ≤ +0.7 V, the output is zero. This “dead band” leads to crossover distortion (see Section 12.3). Consider this follower to be driven by the output of a differential amplifier of gain 100
vO
1
Problems 899
3dB cascade 3dB stage
1
V
10.700.7 vI 1
(b)
FigureP11.24 continued
whose positive-input terminal is connected to the input signal source vS and whose negative-input terminal is connected to the emitters of the follower. Sketch the transfer characteristic v O versus v S of the resulting feedback amplifier. What are the limits of the dead band, and what are the gains outside the dead band?
D 11.25 A particular amplifier has a nonlinear transfer characteristic that can be approximated as follows:
(a) (b)
(c)
3 Forsmallinputsignals, v ≤10mV,v /v =10 .
I O I
For intermediate input signals, 10 mV ≤ vI ≤ 60 mV,
vO/vI =102.
For large input signals, v I ≥ 60 mV, the output saturates.
If the amplifier is connected in a negative-feedback loop, find the feedback factor β that reduces the factor-of-10 change in
gain (occurring at v I = 10 mV) to only a 10% change. What is the transfer characteristic vO versus vS of the amplifier with feedback?
Section 11.3: The Feedback Voltage Amplifier
D 11.26 For the feedback voltage amplifier of Fig. 11.8(a), let the op amp have an infinite input resistance, a zero output resistance, and a finite open-loop gain of 1000 V/V. If R1 = 10 k, what value should R2 have to obtain an ideal closed-loop gain of 10? Now, calculate the loop gain Aβ and use it to find the actual value of the closed-loop gain Af . If Af is to be exactly 10, what must the value of R2 be?
D 11.27 Consider the series–shunt feedback amplifier in Fig. 11.11(a), which is analyzed in Example 11.3.
(a) If R1 = 10 k, find the value of R2 that results in an ideal closed-loop gain of 10.
vI
vO
V
(a)
Figure P11.24
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900 Chapter 11
Feedback
0.1 mA
Rs Vs
Rin Figure P11.29
Q2
R2 V
Q1 o
R1 1 mA
RL
D 11.30 Consider the series–shunt feedback amplifier of Fig. 11.8(c), which was the subject of Exercise 11.6. Assume that the voltage divider (R1 , R2 ) is implemented with a 1-M potentiometer. Assume that the MOSFET is biased so that gm =4 mA/V and ro is large. Also, RD =10k. Find the value of R1 that results in a closed-loop gain of 5 V/V.
D 11.31 Figure P11.31 shows a series–shunt feedback amplifier known as a “feedback triple.” All three MOSFETs are biased to operate at gm = 4 mA/V. You may neglect their ro’s.
(a) Select a value for RF that results in a closed-loop gain that is ideally 10 V/V.
Rout
CHAPTER 11 PROBLEMS
(b) Use the expression for Aβ derived in Example 11.3 to find the value of the loop gain for the case μ = 1000, Rid =100k,ro =1k,Rs =100k,andRL =10k. Hence determine the value of the closed-loop gain Af .
(c) By what factor must μ be increased to ensure that Af is within 1% of the ideal value of 10?
D 11.28 Consider the series–shunt feedback amplifier of Fig. 11.8(b) that is analyzed in Example 11.2.
(a) If R1 = 1 k, what value should R2 have to obtain a closed-loop gain whose ideal value is 5 V/V?
(b) If gm1 =gm2 =4mA/V, RD1 =RD2 =10k, and the MOSFET’s ro is very large, use the expression for Aβ derived in Example 11.2 to find the value of Aβ and hence determine the closed-loop gain Af .
*11.29 In the series–shunt feedback amplifier shown in Fig. P11.29, the devices operate with VBE = 0.7 V and have β1 = β2 = 100. The input signal Vs has a zero dc component. Resistances Rs =100, R1 =1k, R2 =10k, and RL =1k.
(a) If the loop gain is large, what do you expect the closed-loop gain to be? Give both an expression and its value.
(b) Find the dc emitter current in each of Q1 and Q2. Also, find the dc voltage at the emitter of Q2.
(c) Calculate the value of the loop gain Aβ . (Hint: Set Vs = 0 and break the loop at the base of Q1 . Simplify the circuit by eliminating dc sources.)
(d) Calculate the value of Af .
RD2 10 k
Q2
RF
Io
3
Rout1
Vo
100 100
Rout2
RD1 10 k
Q1
Q
Vs R R S1 S2
Figure P11.31
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CHAPTER 11 PROBLEMS
(b) Determine the loop gain Aβ and hence the value of Af . By what percentage does Af differ from the ideal value you designed for? How can you adjust the circuit to make Af equalto10?
11.32 Figure P11.32 shows a series–shunt feedback ampli- fier without details of the bias circuit.
(a) If RE is selected to be 50 , find the value for RF that results in a closed-loop gain with an ideal value of 25 V/V.
(b) IfQ1 isbiasedat1mA,Q2 at2mA,andQ3 at5mA, and assuming that the transistors have hfe = 100 and largero,andthatRC1 =2kandRC2 =1k,findthe value of the loop gain Aβ and hence of the closed-loop gain Af .
D 11.33 The current-mirror-loaded differential amplifier in Fig. P11.33 has a feedback network consisting of the voltage divider (R1 , R2 ), with R1 + R2 = 1 M. The devices are sized to operate at |VOV | = 0.2 V. For all devices, |VA| = 10 V. The input signal source has a zero dc component.
(a) Find the loop gain Aβ and hence the value of A.
(b) Find the values of R1 and R2 that result in a closed-loop
gain of exactly 5 V/V.
Section 11.4: Systematic Analysis of Feedback Voltage Amplifiers (Series–Shunt)
11.34 A series–shunt feedback amplifier employs a basic amplifier with input and output resistances each of 2 k and gain A = 1000 V/V. The feedback factor β = 0.1 V/V. Find
VCC
RC2
Problems 901
RC1
Q2
Q3
Vs Q1
RE
Figure P11.32
Vo
RF
VDD
Q3
Q4
Rs
Vs
Figure P11.33
Q1
Q2
200 A
Vo
R1
Rout
R2
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
902 Chapter 11 Feedback
the gain Af , the input resistance Ri f , and the output resistance
Rof of the closed-loop amplifier.
11.35 Foraparticularamplifierconnectedinafeedbackloop in which the output voltage is sampled, measurement of the output resistance before and after the loop is connected shows a change by a factor of 200. Is the resistance with feedback higher or lower? What is the value of the loop gain Aβ ? If Rof is 100 , what is Ro without feedback?
11.36 The formulas for Rif and Rof in Eqs. (11.20) and
(11.23), respectively, also apply for the case in which A is a
function of frequency. In this case, the resulting impedances
Zi f and Zof will be functions of frequency. Consider the case
(b) Find the dc emitter current in each of Q1 and Q2. Also find the dc voltage at the emitter of Q2.
(c) Sketch the A circuit without the dc sources. Derive expressions for A, Ri, and Ro, and find their values.
(d) Give an expression for β and find its value.
(e) Find the closed-loop gain Vo/Vs, the input resistance Rin, and the output resistance Rout. By what percentage does the value of Af differ from the approximate value found
in (a)?
D *11.40 Figure P11.40 shows a series–shunt ampli-
fier with a feedback factor β = 1. The amplifier is designed
so that vO = 0 for vS = 0, with small deviations in vO from
CHAPTER 11 PROBLEMS
of a series–shunt amplifier that has an input resistance Ri , an
technology utilized has k′ = 2k′ = 120 μA/V2, V = 0.7 V, npt
output resistance R , and open-loop gain A = A /1 + s/ω , o0H
and VA′ = 24 V/μm.
(a) Show that the feedback is negative.
(b) With the feedback loop opened at the gate of Q2, and
the gate terminals of Q1 and Q2 grounded, find the dc current and the overdrive voltage at which each of Q1 to Q5 is operating. Ignore the Early effect. Also find the dc voltage at the output.
(c) Find gm and ro of each of the five transistors.
(d) FindexpressionsandvaluesofAandRo.Assumethatthe
bias current sources are ideal.
(e) Findthegainwithfeedback,Af,andtheoutputresistance
Rout .
(f) Howwouldyoumodifythecircuittorealizeaclosed-loop
voltage gain of 5 V/V? What is the value of output resistance obtained?
and a feedback factor β that is independent of frequency. Find Zif and Zof and give an equivalent circuit for each, together with the values of all the elements in the equivalent circuits.
11.37 A feedback amplifier utilizing voltage sampling and employing a basic voltage amplifier with a gain of 1000 V/V and an input resistance of 1000 has a closed-loop input resistance of 10 k. What is the closed-loop gain? If the basic amplifier is used to implement a unity-gain voltage buffer, what input resistance do you expect?
11.38 Consider the noninverting op-amp circuit of Example 11.4forthecaseR1 =∞andR2 =0.
(a) Whatisthevalueofβ,andwhatistheidealvalueofthe closed-loop gain?
(b) Adapt the expressions found in Example 11.4 to obtain expressions for A and Aβ for this case.
(c) Forμ=104,Rid =100k,Rs =10k,ro =1k,and R =2k,findA,Aβ,A,R ,andR .
*11.39 This problem deals with the series–shunt feedback
amplifier of Fig. P11.29 and overlaps somewhat with Problem
11.29. Thus, if you have already solved 11.29, you can use
some of the results in the solution of this problem. The devices
operatewithV =0.7Vandhaveβ =β =100.Theinput BE 12
signal V has a zero dc component. Resistances R = 100 , ss
R =1k,R =10k,andR =1k. 12L
(a) If the loop gain is large, what do you expect the closed-loop gain Vo/Vs to be? Give both an expression and its approximate value.
*11.41 Figure P11.41 shows a series–shunt amplifier in which the three MOSFETs are sized to operate at V =
L fin out
utilize single transistors and thus have output resistances equal to ro .
(a) Show that the feedback is negative.
(b) Assuming the loop gain to be large, what do you expect
the closed-loop voltage gain Vo/Vs to be approximately? (c) If Vs has a zero dc component, find the dc voltages at nodes S1, G2, S3, and G3. Verify that each of the current sources has the minimum required dc voltage across it for
proper operation.
(d) Find the A circuit. Calculate the gain of each of the three
stages and the overall voltage gain, A.
0 V dc being minimized by the negative-feedback action. The
OV 0.2V.Let Vt =0.5Vand VA =10V.Thecurrentsources
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2.5 V
Problems 903
CHAPTER 11 PROBLEMS
Q3 (40 1)
Q4
(120 1)
300 A
Q5
(20 1)
Q1Q2 vO
(20 1)
(20 1)
200 A
vS
Figure P11.40
0.8 mA
2.5 V
VDD 1.8 V
Q2
G3
I3 0.1 mA R2
18 k
Rout
I1
0.1 mA
G2
Q1
I2 0.1 mA S1
R1 2k
Q3
S3
Vo
Vs
VDC
0.9 V
Rout
Figure P11.41
[Hint: A CS amplifier with a resistance R in the source sfos
lead has an effective transconductance g
an output resistance ro 1 + gm Rs .] (e) Find β.
/ 1 + g R and mms
approximate (g) Find the output resistance Rout.
value
obtained
(f) Find A = V /V . By what percentage does this
value differ from the
in (b)?
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904
Chapter 11 Feedback
VDD 2.5 V
Q3
Q4
Q5 In Q1 Q2 In
Out
80 k
Out
R1
Q In 100k
2.5 V
(b)
R1 and R2 found in (d) to determine β and Af . Compare the value of Af to that found in (f).
D**11.43 TheCMOSopampinFig.P11.43(a)isfabricated in a 1-μm technology for which Vtn = −Vtp = 0.75 V, μn Cox = 2μp Cox = 100 μA/V2 , and VA′ = 10 V/μm. All transistors in the circuit have L = 1 μm.
(a) It is required to perform a dc bias design of the circuit. For this purpose, let the two input terminals be at zero volts dc and neglect channel-length modulation (i.e., let VA =∞).DesigntoobtainID1 =ID2 =50μA,ID5 =250 μA, and VO = 0, and operate all transistors except for the
CHAPTER 11 PROBLEMS
Q7
6 8R2
Q
Figure P11.43
VSS
D *11.42 This problem deals with the series–shunt feedback
amplifier of Fig. P11.33. Certain aspects of this amplifier
were considered in Problem 11.33. If you have already solved
problem 11.33, you will have the opportunity to compare
results. The current-mirror-loaded differential amplifier has
a feedback network consisting of the voltage divider R1 , R2 , with R + R = 1 M. The devices are sized to operate at
1 2
VOV = 0.2 V. For all devices, VA = 10 V. The input signal
source has a zero dc component.
(a) Show that the feedback is negative.
(b) What do you expect the dc voltage at the gate of Q2 to
be? At the output? (Neglect the Early effect.)
(c) Find the A circuit. Derive an expression for A and find its
(d) Select values for R1 and R2 to obtain a closed-loop voltage gainVo/Vs=5V/V.
(e) Find the value of Rout . (b)
(f) Utilizing the open-circuit, closed-loop gain (5 V/V) and
the value of Rout found in (e), find the value of gain (c) obtained when a resistance RL = 10 k is connected to the (d)
output.
(g) As an alternative approach to (f) above, redo the analysis
Q2 are perfectly matched, and similarly for Q3 and Q4. For each transistor, find ID and W/L.
What is the allowable range of input common-mode voltage?
Find gm for each of Q1, Q2, and Q5.
(a)
of the A circuit including RL. Then utilize the values of
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value. source follower Q5 at VOV = 0.25 V. Assume that Q1 and
For each transistor, calculate ro .
(e) The 100-k potentiometer shown in Fig. 11.43(b)
is connected between the output terminal (Out) and the inverting input terminal (–In) to provide negative
CHAPTER 11 PROBLEMS
Rs A1 A2 A3
Rout
Vo
RL
Problems 905
Vs
Figure P11.45
R2
Rin
R1
feedback whose amount is controlled by the setting of the wiper. A voltage signal Vs is applied between the noninverting input (+In) and ground. A load resistance RL = 100 k is connected between the output terminal and ground. The potentiometer is adjusted to obtain a closed-loop gain Af ≡ Vo /Vs ≃ 10 V/V.
Specify the required setting of the potentiometer by giving the values of R1 and R2. Toward this end, find the A circuit (supply a circuit diagram), the value of A, the β circuit (supply a circuit diagram), and the value of β.
(f) What is the output resistance of the feedback amplifier, excluding RL ?
D *11.44 Figure P11.32 shows a series–shunt feedback amplifier without details of the bias circuit.
(a) Eliminating the dc sources, sketch the A circuit and the circuit for determining β.
(b) Show that if Aβ is large then the closed-loop voltage gain is given approximately by
A ≡ Vo ≃ RF +RE fVR
(c) If RE is selected equal to 50 , find RF that will result in a closed-loop gain of approximately 25 V/V.
(d) If Q1 is biased at 1mA, Q2 at 2mA, and Q3 at 5mA, and assuming that the transistors have hfe = 100, find approximate values for RC 1 and RC 2 to obtain gains from the stages of the A circuit as follows: a voltage gain of Q1 of about –10 and a voltage gain of Q2 of about –50.
(e) For your design, what is the closed-loop voltage gain realized?
(f) Calculate the input and output resistances of the closed-loop amplifier designed.
D *11.45 Figure P11.45 shows a three-stage feedback amplifier:
A1 has an 82-k differential input resistance, a 20-V/V open-circuit differential voltage gain, and a 3.2-k output resistance.
A2 has a 5-k input resistance, a 20-mA/V short-circuit transconductance, and a 20-k output resistance.
A3 has a 20-k input resistance, unity open-circuit voltage gain, and a 1-k output resistance.
The feedback amplifier feeds a 1-k load resistance and is fed by a signal source with a 9-k resistance.
(a) Show that the feedback is negative.
(b) If R1 = 20 k, find the value of R2 that results in a
closed-loop gain Vo/Vs that is ideally 5 V/V.
(c) Supply the small-signal equivalent circuit.
(d) Sketch the A circuit and determine A.
(e) Find β and the amount of feedback.
(f) Findtheclosed-loopgainAf ≡Vo/Vs.
(g) Find the feedback amplifier’s input resistance Rin . (h) Find the feedback amplifier’s output resistance Rout .
(i) If the high-frequency response of the open-loop gain A is dominated by a pole at 100 Hz, what is the upper 3-dB frequency of the closed-loop gain?
(j) If for some reason A1 drops to half its nominal value, what is the percentage change in Af ?
sE
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906 Chapter 11 Feedback
Section 11.5: Other Feedback-Amplifier Types
D 11.46 Refer to the circuit in Fig. 11.17(a), which is analyzedinExample11.6.SelectavalueforRF thatresultsin a closed-loop transconductance Af ≡ Io /Vs ≃ 10 mA/V. Use the formulas derived in Example 11.6 to find the actual value of Af realized. Let μ=1000, Rid =100k, gm =2 mA/V, and ro2 = 20 k.
D 11.47 Figure P11.47 shows a feedback current amplifier. The feedback network consists of the highlighted two-port networkcomprisingRM andRF.Itisfedwiththeoutputcurrent Io and delivers a feedback current If at its port 1 to the input node. The feedback factor β is the current ratio If /Io measured with port 1 short-circuited (because it is connected in shunt with the amplifier input).
(a) Find an expression for β and hence for the ideal value ofAf ≡Io/Is.
(b) Setting Is = 0, break the loop at the gate of Q2 and thus determine the loop gain Aβ. Show that
A=− gm2RD 1+1/[gm1(RM +RF)]
(c) Forgm1 =gm2 =4mA/V,RD =10k,and(RM +RF)=
Assume that the op amp is modeled by an input resistance Rid , an open-circuit voltage gain μ, and an output resistance ro.
If
Ii
If RF
(b)
RF
Is
Vo
CHAPTER 11 PROBLEMS
1 k, find the value of RM current gain of 5 A/A.
VDD
RF
that results in a closed-loop
(a)
Vo
(a) Show that the feedback factor β, determined as shown in Fig. P11.48(b), is given by β = −1/RF . Hence find the ideal value of the closed-loop gain Af ≡ Vo /Is . Find RF that results in Af of approximately 1 k.
(b) By setting Is = 0 and breaking the loop at the input terminals of the op amp, show that the loop gain is given by
Aβ = μ Rid
Rid +RF +ro
(c) Forμ=1000,Rid =100k,ro =1k,andRF having the value found in (a), what is the actual value of Af realized?
Feedback Transconductance Amplifiers (Series–Series)
11.49 A series–series feedback amplifier employs a transconductance amplifier having a short-circuit transcon- ductance Gm of 0.6 A/V, input resistance of 10 k, and output resistance of 100 k. The feedback network has β = 200 ,
Figure P11.48
Q1
Ii
RD
If
VG
Q2 Io
RL
Is 1 RM2 Rin
Figure P11.47
D 11.48 Figure P11.48(a) shows a feedback transresistance amplifier formed by an op amp and a feedback resistance RF .
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CHAPTER 11 PROBLEMS
an input resistance (with port 1 open-circuited) of 200 , and an input resistance (with port 2 open-circuited) of 10 k. The amplifier operates with a signal source having a resistance of 10 k and with a load resistance of 10 k. Find Af , Rin, and Rout .
11.50 Reconsider the circuit in Fig. 11.21(a), analyzed in Example 11.8, this time with the output voltage taken at the emitter of Q3. In this case the feedback can be considered to be of the series–shunt type. Note that RE2 should now be considered part of the basic amplifier and not of the feedback network.
(a) Determine β.
(b) FindanapproximatevalueforAf ≡Ve3/Vs assumingthat
the loop gain remains large (a safe assumption, since the loop in fact does not change).
[Note: If you continue with the feedback analysis, you’ll find that Aβ in fact changes somewhat; this is a result of the different approximations made in the feedback analysis approach.]
(c) IftheloopgainremainsatthevaluecalculatedinExample 11.8(i.e.,246.3),findtheoutputresistanceRout (measured betweentheemitterofQ3 andground).(Neglecttheeffect of r03.)
D *11.51 Figure P11.31 (page 851) shows a feedback triple utilizing MOSFETs. All three MOSFETs are biased and sized to operate at gm = 4 mA/V. You may neglect their ro ’s (except for the calculation of Rout1 as indicated below).
(a) Consideringthefeedbackamplifierasatransconductance amplifier with output current Io, find the value of RF that results in a closed-loop transconductance of approx- imately 100 mA/V.
(b) SketchtheAcircuitandfindthevalueofA≡Io/Vi.
(c) Find 1 + Aβ and Af ≡ Io/Vs. Compare to the value of
Af you designed for. What is the percentage difference? What resistance can you change to make Af exactly 100 mA/V, and in which direction (increase or decrease)? (d) Assuming that ro3 = 20 k, find Ro of the A circuit. For this purpose, recall that the resistance looking into the drain of a MOSFET having a resistance Rs in its source is (ro + Rs + gm ro Rs ). Hence find the output resistance Rout1. Since the current sampled by the feedback network is exactly equal to the output current, you can use the
feedback formula.
(e) If the voltage Vo is taken as the output, in which case
the amplifier becomes series–shunt feedback, what is
Problems 907 the value of the closed-loop voltage gain Vo /Vs ? Assume
that RF has the original value you selected in (a). Note that in this case RS2 should be considered part of the amplifier and not the feedback network. The feedback analysis will reveal that Aβ changes somewhat, which may be puzzling given that the feedback loop did not change. The change is due to the different approximation used.
(f) What is the closed-loop output resistance Rout2 of the voltage amplifier in (e) above?
11.52 Consider the circuit in Fig. P11.52 as a transconduc- tance amplifier with input Vs and output Io. The transistor is specified in terms of its gm and ro.
(a) Sketch the small-signal equivalent circuit using the hybrid-π model of the MOSFET and convince yourself that the feedback circuit is comprised of resistor RF .
(b) Find the A circuit and the β circuit.
(c) Derive expressions for A, β, (1+Aβ), Af , Ro, and Rof .
Io
Rof
RF
Vs
Figure P11.52
D 11.53 The transconductance amplifier in Fig. P11.53 utilizes a differential amplifier with gain μ and a very high input resistance. The differential amplifier drives a transistor Q characterized by its gm and ro. A resistor RF senses the output current Io.
(a) For Aβ ≫ 1, find an approximate expression for the closed-loop transconductance Af ≡ Io /Vs . Hence, select a value for RF that results in Af ≃ 5 mA/V.
(b) Find the A circuit and derive an expression for A. Evaluate A for the case μ = 1000 V/V, gm = 2 mA/V, ro = 20 k, and the value of RF you selected in (a).
(c) Give an expression for Aβ and evaluate its value and that of1+Aβ.
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908 Chapter 11 Feedback
(d) Find the closed-loop gain Af and compare to the value you designed for in (a) above.
(e) Find expressions and values for Ro and Rof . [Hint: The resistance looking into the drain of a MOSFET with a resistanceRs initssourceis(ro+Rs+gmroRs).]
the base, in the gm Vπ generator, and in ro , all in terms of Ix ? Show these currents on a sketch of the equivalent circuit with Resetto∞.
11.55 As we found out in Example 11.8, whenever the feedback network senses the emitter current of the BJT, the feedback output resistance formula cannot predict the output resistance looking into the collector. To understand this issue more clearly, consider the feedback transconductance amplifier shown in Fig. P11.55(a). To determine the output resistance, we set Vs = 0 and apply a test voltage Vx to the collector, as shown in Fig. P11.55(b). Now, let μ be increased tothepointwherethefeedbacksignalacrossRF almostequals the input to the positive terminal of the differential amplifier,
Io
Q
RF
Rof
m
CHAPTER 11 PROBLEMS
Vs
Figure P11.53
Rout
Vs
m
(a)
*11.54 Itisrequiredtoshowthattheoutputresistanceofthe BJT circuit in Fig. P11.54 is given by
r R=r+R∥r+R 1+gr π
RF
ooeπb morπ+Rb
Rb
Ro
To derive this expression, set Vs = 0, replace the BJT with its small-signal, hybrid-π model, apply a test voltage Vx to thecollector,andfindthecurrentIx drawnfromVx andhence Ro asVx/Ix.Notethatthebiasarrangementisnotshown.For the case of Rb = 0, find the maximum possible value for Ro . Note that this theoretical maximum is obtained when Re is so large that the signal current in the emitter is nearly zero. In this case, with Vx applied and Vs = 0, what is the current in
Ix
Vx
RF
Vs Re
Figure P11.54
m
0V
0
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Figure P11.55
(b)
Problems 909
CHAPTER 11 PROBLEMS
now zero. Thus the signal current through RF will be almost zero. By replacing the BJT with its hybrid-π model, show that
Rout =rπ + hfe +1 ro ≃hfero
where hfe is the transistor β. Thus for large amounts of
feedback, Rout is limited to a maximum of hfero independent Vs
of the amount of feedback. This phenomenon does not occur
in the MOSFET version of this circuit, where the output R3
mQ R2
Io
Rout
R1 100
resistance can be theoretically made infinite.
100
11.56 For the feedback transconductance amplifier of
Fig. P11.56 derive expressions for A, β, Aβ, Af , Ro, and Rof .
Evaluate Af and Rof for the case of gm1 = gm2 = 4 mA/V, Figure P11.57 RD =20k,ro2 =20k,RF =100,andRL =1k.For
simplicity, neglect ro1 and take ro2 into account only when
calculating output resistances.
11.58 All the MOS transistors in the feedback
transconductance amplifier (series–series) of Fig. P11.58 are
sized to operate at V = 0.2 V. For all transistors, V = OV t
RD
0.4Vand VA =20V.
(a) If Vs has a zero dc component, find the dc voltage at the output, at the drain of Q1, and at the drain of Q2.
(b) Find an approximate expression and value for Af ≡ Io/Vs forthecaseAβ≫1.
(c) Use feedback analysis to obtain a more precise value for Af .
(d) Find the value of Rout .
(e) If the voltage at the source of Q5 is taken as the output,
find the voltage gain using the value of Io/Vs obtained in (c). Also find the output resistance of this series–shunt voltage amplifier.
11.59 By setting Vs = 0 and breaking the feedback loop, show that the loop gain of the amplifier circuit in Fig. P11.58 is
RF ∥ro5 Aβ=gm1,2 ro2∥ro4 R ∥r +1/g
Fo5 m5 where gm1,2 is the gm of each of Q1 and Q2.
Feedback Transresistance Amplifiers (Shunt–Shunt)
11.60 For the transresistance amplifier analyzed in Exam- ple 11.9, use the formulas derived there to evaluate Af , Rin , and Rout when μ is one-tenth the value used in the example. That is, evaluateforμ = 103 V/V,Rid = ∞,ro = 100,RF = 10k, and Rs = RL = 1 k. Compare to the corresponding values obtained in Example 11.9.
Q2 Io
Vs
Vi
Q1 R L
Vf RF
Figure P11.56
D 11.57 For the feedback transconductance amplifier in Fig.P11.57, derive an approximate expression for the closed-looptransconductanceAf ≡Io/Vs forthecaseofAβ≫ 1. Hence select a value for R2 to obtain Af = 100 mA/V. If Q is biased to obtain gm = 1 mA/V, specify the value of the gain μ of the differential amplifier to obtain an amount of feedback of 60 dB. If Q has ro = 50 k, find the output resistance Rout. [Hint: Recall that for a MOSFET with a resistance Rs in its source, the resistance looking into the drain is (ro +Rs +gmroRs).]
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910 Chapter 11 Feedback
Rout
CHAPTER 11 PROBLEMS
Figure P11.58
11.61 Use the formulas derived in Example 11.9 to solve the problem in Exercise 11.19. Show that the results are identical to those given in the answer to Exercise 11.19.
11.62 By setting Is = 0, replacing the MOSFET with its hybrid-π model, and breaking the feedback loop, determine the loop gain of the feedback amplifier in Fig. E11.19. Hence find the open-loop gain. Evaluate Aβ, β, A, and Af for the numerical values given in Exercise 11.8. Why do the results differ somewhat from those given in the answer to Exercise 11.19?
11.63 The CE BJT amplifier in Fig. P11.63 employs shunt–shunt feedback: Feedback resistor RF senses the output voltage Vo and provides a feedback current to the base node.
(a) If Vs has a zero dc component, find the dc collector current of the BJT. Assume the transistor β = 100.
(b) Find the small-signal equivalent circuit of the amplifier with the signal source represented by its Norton equiva- lent (as we usually do when the feedback connection at the input is shunt).
(c) Find the A circuit and determine the value of A, Ri, and Ro .
(d) Find β and hence Aβ and 1+Aβ.
(e) Find Af , Rif , and Rof and hence Rin and Rout.
(f) What voltage gain Vo /Vs is realized? How does this value
compare to the ideal value obtained if the loop gain is very large and thus the signal voltage at the base becomes almost zero (like what happens in an inverting op-amp circuit). Note that this single-transistor poor-man’s op amp is not that bad!
Rf 56 k
15 V
RC 5.6 k Vo
Rout
Rs 10 k
Vs
Rin
Figure P11.63
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CHAPTER 11 PROBLEMS
D 11.64 The circuit in Fig. P11.64 utilizes a voltage amplifier with gain μ in a shunt–shunt feedback topology with the feedback network composed of resistor RF . In order to be able to use the feedback equations, you should first convert the signal source to its Norton representation. You will then see that all the formulas derived in Example 11.9 apply here as well.
(a) If the loop gain is very large, what approximate closed-loop voltage gain Vo /Vs is realized? If Rs = 2 k, give the value of RF that will result in Vo /Vs ≃ − 10 V/V.
(b) If the amplifier μ has a dc gain of 103 V/V, an input resistance Rid = 100 k, and an output resistance ro = 2 k, find the actual Vo/Vs realized. Also find Rin and Rout (indicated on the circuit diagram). You may use formulas derived in Example 11.9.
(c) If the amplifier μ has an upper 3-dB frequency of 1 kHz
and a uniform −20-dB/decade gain rolloff, what is the
Problems 911 (c) Provide the A circuit and derive an expression for A in
terms of gm1, ro1, gm2, ro2, and RF.
(d) What is β? Give an expression for the loop gain Aβ and
the amount of feedback (1 + Aβ ).
(e) Derive an expression for Af .
(f) Derive expressions for Ri , Rin , Ro , and Rout .
(g) Evaluate A, β, Aβ, Af , Ri, Ro, Rin, and Rout for the
component values given.
VDD I
Q1
Is I
Q2
3-dB frequency of the gain V /V ? os
Vo
Rout
Rs
Rin
RF
m Vo Rout
Rin Figure P11.65
RF
Vs Figure P11.64
11.66 By setting Is = 0 and breaking the feedback loop, find the loop gain of the feedback amplifier in Fig. P11.65. If you have already solved Problem 11.65, compare results. Which result do you think is more accurate, and why? For the numerical values given in Problem 11.65, by how much (in percent) do the two values of loop gain differ?
11.67 AnalyzethecircuitinFig.E11.19fromfirstprinciples (i.e., do not use the feedback approach) and hence show that
1 V Rs ∥RF gm − R ro ∥RF
11.65 The feedback transresistance amplifier in Fig. P11.65 utilizes two identical MOSFETs biased by ideal current sources I = 0.4 mA. The MOSFETs are sized to operate at VOV =0.2VandhaveVt =0.5VandVA =16V.Thefeedback resistance RF = 10 k.
(a) If Is has a zero dc component, find the dc voltage at the input,atthedrainofQ1,andattheoutput.
(b) Findgm andro ofQ1 andQ2.
A≡o=− F
f Is 1+R ∥R g − 1 r ∥R /R
sFm oFF RF
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912 Chapter 11 Feedback
Comparing this expression to the one given in Exercise 11.19,
part (b), you will note that the only difference is that g has m
VCC
Q2
RE –V
RC
D 11.68 For the feedback amplifier in Fig. P11.68, select Is
a value for RF that results in a closed-loop gain Af ≡
Vo/Is ≃ −10 k. Then, analyze the circuit to determine
the actual value of Af realized. As well, determine Rin and R Rout. Transistors Q1 and Q2 are operated so that gm1 =
been replaced by gm − 1/RF . Note that −1/RF represents
the forward transmission in the feedback network, which the
feedback-analysis method neglects. What is the condition then
for the feedback-analysis method to be reasonably accurate
for this circuit? Q1
Vo
Rout
CHAPTER 11 PROBLEMS
gm2 = 4 mA/V and ro1 and ro2 can be neglected. Also, RD1 =RD2 =10k.
Rin Figure P11.69
VDD
F
EE
Q1
VG RF
Vo Q2
Rout
RD1
RD2
(b) Find the A circuit and the value of A, Ri, and Ro. Neglect
ro1 and ro2.
(c) Find the value of β, the loop gain, and the amount of
feedback.
(d) Find Af ≡ Vo /Is , the input resistance Rin , and the output
resistance Rout .
D **11.70 (a) Show that for the circuit in Fig. P11.70(a), if the loop gain is large, the voltage gain Vo/Vs is given approximately by
Vo ≃−Rf Vs Rs
(b) Using three cascaded stages of the type shown in Fig.P11.70(b) to implement the amplifier μ, design a feedback amplifier with a voltage gain of approximately –100 V/V. The amplifier is to operate between a source resistance Rs = 10 k and a load resistance RL = 1 k. Calculate the actual value of Vo /Vs realized, the input resistance (excluding Rs ), and the output resistance (excluding RL ). Assume that the BJTs have hfe of 100. [Note: In practice, the three amplifier stages are not made identical, for stability reasons.]
Is
Rin Figure P11.68
11.69 For the feedback transresistance amplifier in Fig.P11.69, let VCC =−VEE =5 V, RC =RE =RF =10 k. The transistors have VBE = 0.7 V and β = 100.
(a) If Is has a zero dc component, show that Q1 and Q2 are operating at dc collector currents of approximately 0.35mA and 0.58mA, respectively. What is the dc voltage at the output?
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CHAPTER 11 PROBLEMS
Vs
Vo
RL
Rs
Rf
Voltage amplifier
(a)
15 V
7.5 k
isnotshown.ItisrequiredtoderiveexpressionsforAf ≡Vo/Is, Rin,andRout.AssumethatC1 andC2 aresufficientlysmallthat their loading effect on the basic amplifier can be neglected. Alsoneglectro.FindthevaluesofAf,Rin,andRout forthecase inwhichgm1 =5mA/V,RD =10k,C1 =0.9pF,C2 =0.1 pF, and gmf = 2 mA/V.
Problems 913
15 k
4.7 k
VDD
RD
V Q1 BIAS
C
C2
Vo
Rout
1
10 k
Is
Rin Figure P11.72
Qf
Figure P11.70
(b)
D 11.71 Negative feedback is to be used to modify the characteristics of a particular amplifier for various purposes. Identify the feedback topology to be used if:
(a) input resistance is to be lowered and output resistance raised.
(b) both input and output resistances are to be raised. (c) both input and output resistances are to be lowered.
11.72 The feedback amplifier of Fig. P11.72 consists of a common-gate amplifier formed by Q1 and RD , and a feedback circuit formed by the capacitive divider (C1 , C2 ) and the common-source transistor Qf . Note that the bias circuit for Qf
D *11.73 Figure P11.73 shows a shunt–shunt feedback amplifier. The MOSFETs have Vtn = 0.6 V, VA = 20 V, and μnCox = 200 μA/V2. The power supply VDD = 3.3 V, and RL = 2 k. The coupling capacitor CC can be assumed to be very large.
(a) Performadcdesigntomeetthefollowingspecifications: ID1 =100μA, ID2 =1 mA, IR2,R1 =10μA, VOV1 = VOV 2 = 0.2 V. Neglect the Early effect. Specify the values required for I1, R1, R2, (W/L)1, and (W/L)2.
(b) Find an expression for β and hence an expression for the ideal value of Vo/Vs.
(c) Find the value of Rs that results in Vo/Vs being ideally −6 V/V.
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914
Chapter 11 Feedback
VDD I1
Q2 Q1
RCC R2 s
Vo
CHAPTER 11 PROBLEMS
Vs R RL 1
Rin
Rout
Figure P11.73
(d) Find the A circuit and use it to determine the values of A, Ri, and Ro.
(e) Find the value obtained for Vo/Vs.
(f) Find Rin and Rout.
Feedback Current Amplifiers (Shunt–Series)
11.74 For the feedback current amplifier in Fig. P11.47:
(a) Provide the A circuit and derive expressions for Ri and A. Neglect ro of both transistors.
(b) Provide the β circuit and an expression for β.
(c) Find an expression for Aβ.
(d) Forgm1 =gm2 =5mA/V,RD =20k,RM =10k,and
RF =90k,findthevaluesofA,β,Aβ,Af,Ri,andRif.
(e) If ro2 = 20 k and RL = 1 k, find the output resistance
asseenbyRL.
D 11.75 Design the feedback current amplifier of Fig.
11.27(a) to meet the following specifications:
(i) Af ≡Io/Is =−100A/A
(ii) amount of feedback ≃ 40 dB
(iii) Rin ≃1k
Specify the values of R1 , R2 , and μ. Assume that the amplifier
μ has infinite input resistance and that Rs = ∞. For the
MOSFET, gm = 5 mA/V and ro = 20 k. What Rout is obtained?
11.76 Consider the feedback current amplifier in Fig. 11.27(a) (which was analyzed in Example 11.10). Let Rs = Rid = ∞. By setting Is = 0 and breaking the feedback loop at the gate of Q, find an expression for the loop gain Aβ. Evaluate Aβ for the component values given in Example 11.10 and hence determine A and Af . Why do the results differ somewhat from those found in Example 11.10?
11.77 The feedback current amplifier in Fig. P11.77 utilizes two identical NMOS transistors sized so that at ID = 0.2 mA they operate at VOV = 0.2 V. Both devices have Vt = 0.5 V andVA =10V.
(a) If Is has zero dc component, show that both Q1 and Q2 are operating at ID = 0.2 mA. What is the dc voltage at the input?
(b) Find gm and ro for each of Q1 and Q2.
(c) Find the A circuit and the value of Ri, A, and Ro. (d) Find the value of β.
(e) FindAβandAf.
(f) Find Rin and Rout .
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Problems 915
CHAPTER 11 PROBLEMS
I 0.2 mA
Q2
Q1
out
Io
R
Io
Rout
m Q2
Is
VG
Rs
Is
Rin Figure P11.77
R2 14 k
R1 3.5 k
Rin
(a)
*11.78 ThefeedbackcurrentamplifierinFig.P11.78(a)can be thought of as a “super” CG transistor. Note that rather than connecting the gate of Q2 to signal ground, an amplifier is placed between source and gate.
(a) If μ is very large, what is the signal voltage at the input terminal? What is the input resistance? What is the current gain Io/Is?
(b) For finite μ but assuming that the input resistance of the amplifier μ is very large, find the A circuit and derive expressions for A, Ri, and Ro.
(c) What is the value of β?
(d) FindAβandAf.Ifμislarge,whatisthevalueofAf?
(e) Find Rin and Rout assuming the loop gain is large.
(f) The “super” CG transistor can be utilized in the cascode configuration shown in Fig. P11.78(b), where VG is a dc bias voltage. Replacing Q1 by its small-signal model, use the analogy of the resulting circuit to that in Fig. P11.78(a) tofindIo andRout.
*11.79 Figure P11.79 shows an interesting and very useful application of feedback to improve the performance of the current mirror formed by Q1 and Q2. Rather than connecting the drain of Q1 to the gate, as is the case in simple current mirrors, an amplifier of gain +μ is connected between the drain and the gate. Note that the feedback loop does not include transistor Q2. The feedback loop ensures that the value of the gate-to-source voltage of Q1 is such that Io1 equals Is. This regulated Vgs is also applied to Q2. Thus, if W/L of Q2
Vi
Io
Rout
Q2
Q1
Figure P11.78
(b)
Is
Rin Io1
Rout Io2
m Q1 Q2
VBIAS
Figure P11.79
is n times W/L of Q1, Io2 = nIo1 = nIs. This current tracking, however, is not regulated by the feedback loop.
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916 Chapter 11 Feedback
(a) Show that the feedback is negative.
(b) If μ is very large and the input resistance of the amplifier
μ is infinite, what dc voltage appears at the drain of Q1? If Q1 is to operate at an overdrive voltage of 0.2 V, what is the minimum value that VBIAS must have?
(c) Replacing Q1 by its small-signal model, find an expres- sion for the small-signal input resistance Rin assuming finite gain but infinite input resistance for the amplifier μ. Note that here it is much easier to do the analysis directly than to use the feedback-analysis approach. For large μ, what does Rin become?
(d) What is the output resistance Rout ?
*11.80 The circuit in Fig. P11.80 is an implementation of a particular circuit building block known as second-generation current convoyer (CCII). It has three terminals besides ground: x, y, and z. The heart of the circuit is the feedback amplifier consisting of the differential amplifier μ and the complementary source follower (QN, QP). (Note that this feedback circuit is one we have encountered a number of times in this chapter, albeit with only one source-follower transistor.) In the following, assume that the differential amplifier has a very large gain μ and infinite differential input resistance. Also, let the two current mirrors have unity current-transfer ratios.
(a) If a resistance R is connected between y and ground, a voltage signal Vx is connected between x and ground, and z is short-circuited to ground. Find the current Iz through the short circuit. Show how this current is developed and its path for Vx positive and for Vx negative.
(b) If x is connected to ground, a current source Iy is connected to input terminal y, and z is connected to ground, what voltage appears at y and what is the input resistance seen by Iy ? What is the current Iz that flows through the output short circuit? Also, explain the current flow through the circuit for Iy positive and for Iy negative.
(c) What is the output resistance at z?
*11.81 For the amplifier circuit in Fig. P11.81, assum- ing that Vs has a zero dc component, find the dc voltages at all nodes and the dc emitter currents of Q1 and Q2. Let the BJTs have β = 100. Use feedback analysis to find Vo/Vs and Rin. Let VBE = 0.7 V.
CHAPTER 11 PROBLEMS
μA
Vo
15
Q1
Q2
x
QN
QP
m
y
z
Rin Figure P11.81
Q3
Q4
**11.82 Figure P11.82 shows a feedback amplifier utilizing the shunt–series topology. All transistors have β = 100 and VBE = 0.7 V. Neglect ro except in (f).
(a) Perform a dc analysis to find the dc emitter currents in Q1 and Q2 and hence determine their small-signal parameters.
Figure P11.80
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
CHAPTER 11 PROBLEMS
RC1 10 k
15 k
12 V
Q1
870
RC2 8 k Iout
Problems 917
RB1
Rin
100 k
Rs
10 k
Q2
RE2 3.4 k
RL 1 k
Vs
Iin
R
B2
Rout
Rf
10 k
Figure P11.82
(b) Replacing the BJTs with their hybrid-π models, give the equivalent circuit of the feedback amplifier.
(c) Give the A circuit and determine A, Ri, and Ro. Note that Ro is the resistance determined by breaking the emitter loop of Q2 and measuring the resistance between the terminals thus created.
(d) Find the β circuit and determine the value of β.
(e) Find Aβ, 1+ Aβ, Af , Rif , and Rof . Note that Rof represents the resistance that in effect appears in the emitter of Q2
as a result of the feedback.
(f) Determine Rin , Iout /Iin , and Rout . To determine Rout , use
VA2 = 75 V and recall that the maximum possible output resistance looking into the collector of a BJT
11.85 An op amp having a low-frequency gain of 104 and a single-pole rolloff at 103 rad/s is connected in a negative-feedback loop via a feedback network having a transmission k and a two-pole rolloff at 103 rad/s. Find the value of k above which the closed-loop amplifier becomes unstable.
11.86 Considerafeedbackamplifierforwhichtheopen-loop gain A(s) is given by
10, 000
A(s) =
If the feedback factor β is independent of frequency, find the
is approximately β ro , where β is the Problem 11.55).
Section 11.7: The Stability Problem
BJT’s
β (see
1 + s/104 1 + s/105 2
frequency at which the phase shift is 180°, and find the critical
11.83 An op amp designed to have a low-frequency gain of 105 and a high-frequency response dominated by a single pole at 100 rad/s acquires, through a manufacturing error, a pair of additional poles at 20,000 rad/s. At what frequency does the total phase shift reach 180°? At this frequency, for what value of β, assumed to be frequency independent, does the loop gain reach a value of unity? What is the corresponding value of closed-loop gain at low frequencies?
*11.84 For the situation described in Problem 11.83, sketch Nyquist plots for β = 1.0 and 10−3 . (Plot for ω = 0 rad/s, 100 rad/s,103 rad/s,104 rad/s,2×104 rad/s,and∞rad/s.)
value of β at which oscillation will commence. Section 11.8: Effect of Feedback on the
Amplifier Poles
11.87 A dc amplifier having a single-pole response with pole frequency 10 Hz and unity-gain frequency of 1 MHz is operated in a loop whose frequency-independent feed- back factor is 0.1. Find the low-frequency gain, the 3-dB frequency, and the unity-gain frequency of the closed-loop amplifier. By what factor does the pole shift?
11.88 An amplifier has dc open-loop gain of 80 dB and a single pole with 100-Hz frequency. It is utilized to design a feedback amplifier with a 3-dB frequency of 10 kHz. What β is needed? What is the dc closed-loop gain realized? Give an expression for Af (s).
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
918 Chapter 11 Feedback
*11.89 An amplifier having a low-frequency gain of 104 and poles at 104 Hz and 105 Hz is operated in a closed negative-feedback loop with a frequency-independent β.
(a) For what value of β do the closed-loop poles become coincident? At what frequency?
(b) Whatisthelow-frequency,closed-loopgaincorrespond- ing to the situation in (a)? What is the value of the closed-loop gain at the frequency of the coincident poles?
(c) What is the value of Q corresponding to the situation in (a)?
(d) If β is increased by a factor of 10, what are the new pole locations? What is the corresponding pole Q?
D 11.90 A dc amplifier has an open-loop gain of 1000 and two poles, a dominant one at 1 kHz and a high-frequency one whose location can be controlled. It is required to connect this amplifier in a negative-feedback loop that provides a dc closed-loop gain of 10 and a maximally flat response. Find the required value of β and the frequency at which the second pole should be placed. What is the 3-dB frequency of the closed-loop amplifier?
11.91 Reconsider Example 11.11 with the circuit in Fig.11.34, modified to incorporate a so-called tapered network, in which the components immediately adjacent to the amplifier input are raised in impedance to C/10 and 10R. Find expressions for the resulting pole frequency ω0 and Q factor. For what value of K do the poles coincide? For what value of K does the response become maximally flat? For what value of K does the circuit oscillate?
D 11.92 A feedback amplifier having a dc closed-loop gain of 10 and a maximally flat second-order response with a 3-dB frequency of 1 kHz is required. The open-loop amplifier utilizes a cascade of two identical amplifier stages, each having a single-pole frequency response. Find the values required for β, the 3-dB frequency, and the dc gain of each of the two amplifier stages. Give an expression for Af (s).
11.93 Three identical inverting amplifier stages, each char- acterized by a low-frequency gain K and a single-pole response with f3dB = 100 kHz, are connected in a feedback loop with β = 1. What is the minimum value of K at which the circuit oscillates? What would the frequency of oscillation be?
Section 11.9: Stability Study Using Bode Plots
11.94 Reconsider Exercise 11.26 for the case of the op amp wired as a unity-gain buffer. At what frequency is |Aβ| = 1? What is the corresponding phase margin?
11.95 Reconsider Exercise 11.26 for the case of a manufac- turing error introducing a second pole at 103 Hz. What is now the frequency for which |Aβ| = 1? What is the corresponding phase margin? For what values of β is the phase margin 45° or more?
11.96 For what phase margin does the gain peaking have a value of 5%? Of 10%? Of 0.1 dB? Of 1 dB? Of 3 dB? [Hint: Use the result in Eq. (11.82).]
11.97 An amplifier has a dc gain of 104 and poles at 105 Hz, 3.16 × 105 Hz, and 106 Hz. Find the value of β, and the corresponding closed-loop gain, for which a phase margin of 45° is obtained.
11.98 A two-pole amplifier for which A0 = 103 and having poles at 1MHz and 10MHz is to be connected as a differentiator. On the basis of the rate-of-closure rule, what is the smallest differentiator time constant for which operation is stable? What are the corresponding gain and phase margins?
11.99 For the amplifier described by Fig. 11.37 and with frequency-independent feedback, what is the minimum closed-loop voltage gain that can be obtained for phase margins of 90° and 45°?
Section 11.10: Frequency Compensation
D 11.100 A multipole amplifier having a first pole at 1 MHz and a dc open-loop gain of 80 dB is to be compensated for closed-loop gains as low as unity by the introduction of a new dominant pole. At what frequency must the new pole be placed?
D 11.101 For the amplifier described in Problem 11.100, rather than introducing a new dominant pole we can use additional capacitance at the circuit node at which the pole is formed to reduce the frequency of the first pole. If the frequency of the second pole is 20 MHz and if it remains unchanged while additional capacitance is introduced as
CHAPTER 11 PROBLEMS
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
mentioned, find the frequency to which the first pole must be lowered so that the resulting amplifier is stable for closed-loop gains as low as unity. By what factor is the capacitance at the controlling node increased?
11.102 For the amplifier whose A(s) is depicted in Fig. 11.38, to what value must the first pole frequency be lowered to obtain stable performance for (a) β = 0.001 and (b) β = 0.1?
11.103 Contemplate the effects of pole splitting by consid- ering Eqs. (11.89), (11.93), and (11.94) under the conditions thatR1 ≃R2=R,C2 ≃C1/10=C,Cf ≫C,andgm =100/R,
with C1 =150 pF, C2 =5 pF, and gm =40mA/V, and that fP1 is caused by the input circuit and fP2 by the output circuit of this amplifier. Find the required value of the compensating Miller capacitance and the new frequency of the output pole.
**11.106 The op amp in the circuit of Fig. P11.106 has an open-loop gain of 105 and a single-pole rolloff with ω 3dB = 10 rad/s.
Problems 919
CHAPTER 11 PROBLEMS
by calculating ω , ω P1
, and ω′ , ω′ . Comment on the results. P2 P1 P2
(a) (b)
(c)
Sketch a Bode plot for the loop gain.
Find the frequency at which |Aβ| = 1, and find the corresponding phase margin.
Find the closed-loop transfer function, including its zero and poles. Sketch a pole-zero plot. Sketch the magnitude of the transfer function versus frequency, and label the important parameters on your sketch.
D11.104 Anopampwithopen-loopvoltagegainof105 and poles at 106 Hz, 107 Hz, and 108 Hz is to be compensated by the addition of a fourth dominant pole to operate stably with unity feedback (β = 1). What is the frequency of the required dominant pole? The compensation network is to consist of an RC low-pass network placed in the negative-feedback path of the op amp. The dc bias conditions are such that a 1-M resistor can be tolerated in series with each of the negative and positive input terminals. What capacitor is required between the negative input and ground to implement the required fourth pole?
D *11.105 An op amp with an open-loop voltage gain of 80dB and poles at 105 Hz, 106 Hz, and 2×106 Hz is to be compensated to be stable for unity β. Assume that the op amp incorporates an amplifier equivalent to that in Fig. 11.40,
Figure P11.106
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
CHAPTER 12
Output Stages and Power Amplifiers
Introduction 921
12.1 Classification of Output Stages
12.2 Class A Output Stage 923
12.3 Class B Output Stage 929
12.4 Class AB Output Stage 935
12.5 Biasing the Class AB Circuit 940
12.6 Variations on the Class AB Configuration 945
12.7 12.8 12.9 12.10
CMOS Class AB Output Stages 950 ICPowerAmplifiers 961 ClassDPowerAmplifiers 967 PowerTransistors 971
Summary 982 Problems 983
922
IN THIS CHAPTER YOU WILL LEARN
1. The classification of amplifier output stages on the basis of the fraction of the cycle of an input sine wave during which the transistor conducts.
2. Analysis and design of a variety of output-stage types ranging from the simple but power-inefficient emitter follower (class A) to the popular push–pull class AB circuit in both bipolar and CMOS technologies, and the power-efficient class D amplifier.
3. Useful and interesting circuit techniques employed in the design of power amplifiers.
4. The special structures and characteristics of bipolar and MOS power transistors.
5. Thermal considerations in the design and fabrication of high-output-power circuits.
Introduction
An important function of the output stage is to provide the amplifier with a low output resistance so that it can deliver the output signal to the load without loss of gain. Since the output stage is the final stage of the amplifier, it usually deals with relatively large signals. Thus the small-signal approximations and models either are not applicable or must be used with care. Nevertheless, linearity remains a very important requirement. In fact, a measure of goodness of the output stage is the amount of total harmonic distortion (THD) it introduces. This is the rms value of the harmonic components of the output signal, excluding the fundamental, expressed as a percentage of the rms value of the fundamental. A high-fidelity audio power amplifier features a THD in the order of a fraction of a percent.
The most challenging requirement in the design of an output stage is for it to deliver the required amount of power to the load in an efficient manner. This implies that the power dissipated in the output-stage transistors must be as low as possible. This requirement stems mainly from the fact that the power dissipated in a transistor raises its internal junction temperature (the temperature of the silicon die), and there is a maximum temperature (in the range of 150°C to 200°C for silicon devices) above which the transistor is destroyed. A high power-conversion efficiency is also required to prolong the battery life of portable electronics, to permit a smaller, lower-cost power supply, or to obviate the need for cooling fans.
We begin this chapter with a study of the various output-stage configurations employed in amplifiers that handle both low and high power. In this context, “high power” generally means greater than 1 W. Examples include the transmitter of a cell phone, which is typically required to deliver 1 W of power to its antenna, and a stereo system that delivers hundreds of watts of audio power to its speakers.
921
922 Chapter 12
Output Stages and Power Amplifiers
A power amplifier is simply an amplifier with a high-power output stage. Examples of discrete-andintegrated-circuitpoweramplifierswillbepresented.Ofparticularinterest is the class D amplifier; it combines analog and digital techniques to achieve very high power-conversion efficiencies.
The chapter concludes with a study of power BJTs and MOSFETs. These are the devices employed in the various circuits studied in this chapter.
12.1 Classification of Output Stages
Output stages are classified according to the collector-current waveform that results when an input signal is applied. Figure 12.1 illustrates the classification for the case of a sinusoidal input signal. The class A stage, whose associated waveform is shown in Fig. 12.1(a), is biased atacurrentIC thatisgreaterthantheamplitudeofthesignalcurrent,Iˆc.Thusthetransistorin a class A stage conducts for the entire cycle of the input signal; that is, the conduction angle is 360°. In contrast, the class B stage, whose associated waveform is shown in Fig. 12.1(b),
Figure 12.1 Collector-current waveforms for transistors operating in (a) class A, (b) class B, (c) class AB, and (d) class C amplifier stages.
is biased at zero dc current. Thus a transistor in a class B stage conducts for only half the cycle of the input sine wave, resulting in a conduction angle of 180°. As will be seen later, the negative halves of the sinusoid will be supplied by another transistor that also operates in the class B mode and conducts during the alternate half-cycles.
An intermediate class between A and B, appropriately named class AB, involves biasing the transistor at a nonzero dc current much smaller than the peak current of the sine-wave signal. As a result, the transistor conducts for an interval slightly greater than half a cycle, as illustrated in Fig. 12.1(c). The resulting conduction angle is greater than 180° but much less than 360°. The class AB stage has another transistor that conducts for an interval slightly greater than that of the negative half-cycle, and the currents from the two transistors are combined in the load. It follows that, during the intervals near the zero crossings of the input sinusoid, both transistors conduct.
Figure 12.1(d) shows the collector-current waveform for a transistor operated as a class C amplifier. Observe that the transistor conducts for an interval shorter than that of a half-cycle; that is, the conduction angle is less than 180°. The result is the periodically pulsating current waveform shown. To obtain a sinusoidal output voltage, this current is passed through a parallel LC circuit, tuned to the frequency of the input sinusoid. The tuned circuit acts as a bandpass filter (Chapter 17) and provides an output voltage proportional to the amplitude of the fundamental component in the Fourier-series representation of the current waveform.
Class A, AB, and B amplifiers are studied in this chapter. They are employed as output stages of op amps and audio power amplifiers. In the latter application, class AB is the preferred choice, for reasons that will be explained in the sections to follow. A variation on the class AB, called the class G/H amplifier, utilizes two pairs of power supplies (e.g., the regular ±30-V supply and a higher-voltage supply of ±70 V). The higher-voltage supply is called upon only occasionally—for instance, to provide a short burst of high output power for a drum roll. Since the high-voltage supply operates infrequently, it can be of a low-cost design. Also, this is a more power-efficient arrangement than would be obtained if a class AB circuit were used and operated continuously from the higher-voltage supply.
Class C amplifiers are usually employed for radio-frequency (RF) power amplification (required, e.g., in mobile phones and radio and TV transmitters). The design of class C amplifiers is a rather specialized topic and is not included in this book. However, we should point out that the tuned-resonator oscillator circuits described in Chapter 18 operate inherently in the class C mode.
Another important type of output stage is the class D switching amplifier. It utilizes the power transistors as on-off switches and thus achieves much higher power efficiency than that obtained in the other amplifier classes. The class D amplifier will be studied briefly in Section 12.9. Although the BJT in Fig. 12.1 has been used to illustrate the definition of the various output-stage classes, the same classification applies to output stages implemented with MOSFETs. Furthermore, the classification above extends to amplifier stages other than those used at the output. In this regard, all the common-emitter, common-base, and common-collector amplifiers (and their FET counterparts) studied in earlier chapters fall into the class A category.
12.2 Class A Output Stage
Because of its low output resistance, the emitter follower is the most popular class A output stage. We have already studied the emitter follower in Chapter 7; in the following we consider its large-signal operation.
12.2 Class A Output Stage 923
924 Chapter 12
Output Stages and Power Amplifiers
12.2.1 Transfer Characteristic
Figure 12.2 shows an emitter follower Q1 biased with a constant current I supplied by transistor Q2 . Since the emitter current iE 1 = I + iL , the bias current I must be greater than the largest negative load current; otherwise, Q1 cuts off and class A operation will no longer be maintained.
The transfer characteristic of the emitter follower of Fig. 12.2 is described by
vO =vI −vBE1 (12.1)
wherevBE1 dependsontheemittercurrentiE1 andthusontheloadcurrentiL.Ifweneglectthe relatively small changes in vBE1 (60 mV for every factor-of-10 change in emitter current), the linear transfer curve shown in Fig. 12.3 results. As indicated, the positive limit of the linear region is determined by the saturation of Q1; thus
vOmax =VCC −VCE1sat (12.2) In the negative direction, depending on the values of I and RL , the limit of the linear region is
determined either by Q1 turning off,
or by Q2 saturating,
vOmin = −IRL (12.3)
vOmin =−VCC +VCE2sat (12.4) The absolutely lowest (most negative) output voltage is that given by Eq. (12.4) and is achieved
provided the bias current I is greater than the magnitude of the corresponding load current,
I ≥ |−VCC +VCE2sat | (12.5)
RL
Figure 12.2 An emitter follower (Q1 ) biased with a constant current I supplied by transistor Q2.
12.2 Class A Output Stage 925
Figure12.3 TransfercharacteristicoftheemitterfollowerinFig.12.2.Thislinearcharacteristicisobtained by neglecting the change in vBE1 with iL. The maximum positive output is determined by the saturation of Q1. In the negative direction, the limit of the linear region is determined either by Q1 turning off or by Q2 saturating, depending on the values of I and RL .
EXERCISES
D12.1 For the emitter follower in Fig. 12.2, VCC = 15 V, VCE sat = 0.2 V, VBE = 0.7 V and constant, and β is very high. Find the value of R that will establish a bias current sufficiently large to allow the largest possible output signal swing for RL = 1 k. Determine the resulting output signal swing and the minimum and maximum emitter currents for Q1.
Ans. 0.97 k; –14.8 V to +14.8 V; 0 to 29.6 mA
12.2 For the emitter follower of Exercise 12.1, in which I = 14.8 mA and RL = 1 k, consider the case
in which vO is limited to the range –10V to +10V. Let Q1 have vBE =0.6V at iC =1mA, and assume α ≃1. Find vI corresponding to vO = −10 V, 0 V, and +10 V. At each of these points, use small-signal analysis to determine the voltage gain vo/vi. Note that the incremental voltage gain gives the slope of the vO-versus-vI characteristic.
Ans. –9.36 V, 0.67 V, 10.68 V; 0.995 V/V, 0.998 V/V, 0.999 V/V
12.2.2 Signal Waveforms
Consider the operation of the emitter-follower circuit of Fig. 12.2 for sine-wave input. Neglecting VCEsat, we see that if the bias current I is properly selected, the output voltage canswingfrom−VCC to+VCC withthequiescentvaluebeingzero,asshowninFig.12.4(a).
926 Chapter 12
Output Stages and Power Amplifiers
(d)
Figure 12.4 Maximum signal waveforms in the class A output stage of Fig. 12.2 under the condition I = VCC /RL or, equivalently, RL = VCC /I . Note that the transistor saturation voltages have been neglected.
Figure 12.4(b) shows the corresponding waveform of vCE1 = VCC − vO. Now, assuming that the bias current I is selected to allow a maximum negative load current of VCC /RL , that is,
I = VCC /RL
the collector current of Q1 will have the waveform shown in Fig. 12.4(c). Finally, Fig. 12.4(d)
shows the waveform of the instantaneous power dissipation in Q1,
pD1 ≡ vCE1iC1 (12.6)
12.2.3 Power Dissipation
Figure 12.4(d) indicates that the maximum instantaneous power dissipation in Q1 is VCC I. This is equal to the power dissipation in Q1 with no input signal applied, that is, the quiescent power dissipation. Thus the emitter-follower transistor dissipates the largest amount of power when vO =0. Since this condition (no input signal) can easily prevail for prolonged periods of time, transistor Q1 must be able to withstand a continuous power dissipation of VCC I.
The power dissipation in Q1 depends on the value of RL. Consider the extreme case of an output open circuit, that is, RL =∞. In this case, iC1 =I is constant and the instantaneous power dissipation in Q1 will depend on the instantaneous value of vO. The maximum power dissipation will occur when v O = −VCC , for in this case v CE 1 is a maximum of 2VCC and pD1 =2VCC I. This condition, however, would not normally persist for a prolonged interval, so the design need not be that conservative. Observe that with an open-circuit load, the
average power dissipation in Q1 is VCC I. A far more dangerous situation occurs at the other extreme of RL—specifically, RL =0. In the event of an output short circuit, a positive input voltage would theoretically result in an infinite load current. In practice, a very large current may flow through Q1, and if the short-circuit condition persists, the resulting large power dissipation in Q1 can raise its junction temperature beyond the maximum allowed, causing permanent damage. To guard against such a situation, output stages are usually equipped with short-circuit protection, as will be explained later.
The power dissipation in Q2 also must be taken into account in designing an emitter-follower output stage. Since Q2 conducts a constant current I, and the maximum value of v CE 2 is 2VCC , the maximum instantaneous power dissipation in Q2 is 2VCC I. This maximum, however, occurs when vO =VCC, a condition that would not normally prevail for a prolonged period of time. A more significant quantity for design purposes is the average power dissipation in Q2, which is VCCI.
Example 12.1
Consider the emitter follower in Fig. 12.2 with VCC = 10 V, I = 100 mA, and RL = 100 .
(a) Find the power dissipated in Q1 and Q2 under quiescent conditions vO = 0 .
(b) For a sinusoidal output voltage of maximum possible amplitude (neglecting VCEsat), find the average
power dissipation in Q1 and Q2. Also find the load power.
Solution
(a) Under quiescent conditions vO = 0, and each of Q1 and Q2 conducts a current I = 100 mA =0.1 A andhasavoltageVCE =VCC =10V,thus
PD1 =PD2 =VCCI =10×0.1=1W
(b) For a sinusoidal output voltage of maximum possible amplitude (i.e., 10-V peak), the instantaneous power dissipation in Q1 will be as shown in Fig. 12.4(d). Thus the average power dissipation in Q1 will be
PD1 = 1 VCC I = 1 × 10 × 0.1 = 0.5 W 22
For Q2 , the current is constant at I = 0.1 A and the voltage at the collector will have an average value of 0 V. Thus the average voltage across Q2 will be VCC and the average dissipation will be
P =I×v
D2 CE average
=I×VCC =0.1×10=1W Finally, the power delivered to the load can be found from
V2 PL = orms
12.2 ClassAOutputStage 927
RL √ 2
=(10/ 2) =0.5W 100
928 Chapter 12
Output Stages and Power Amplifiers
12.2.4 Power-Conversion Efficiency
The power-conversion efficiency of an output stage is defined as
η ≡ Load power(PL ) (12.7)
Supply power(PS)
For the emitter follower of Fig. 12.2, assuming that the output voltage is a sinusoid with the
= 2 R (12.8) LL
Since the current in Q2 is constant (I), the power drawn from the negative supply1 is VCC I. The average current in Q1 is equal to I, and thus the average power drawn from the positive supply is VCC I. Thus the total average supply power is
peak value Vˆo, the average load power will be
(Vˆo/√2)2 1 Vˆo2
PL = R
PS =2VCCI Equations (12.8) and (12.9) can be combined to yield
η=1 Vˆo2
4 IRL VCC
= 1 Vˆo Vˆo 4 IRL VCC
Since Vˆ o ≤ VCC and Vˆ o ≤ IRL , maximum efficiency is obtained when Vˆo =VCC =IRL
(12.9)
(12.10)
(12.11)
The maximum efficiency attainable is 25%. Because this is a rather low figure, the class A output stage is rarely used in high-power applications (>1 W). Note also that in practice the output voltage swing is limited to lower values to avoid transistor saturation and associated nonlinear distortion. Thus the efficiency achieved in practice is usually in the 10% to 20% range.
EXERCISE
12.3 For the emitter follower of Fig. 12.2, let VCC = 10 V, I = 100 mA, and RL = 100 . If the output voltage is an 8-V-peak sinusoid, find the following: (a) the power delivered to the load; (b) the average power drawn from the supplies; (c) the power-conversion efficiency. Ignore the loss in Q3 and R.
Ans. 0.32 W; 2 W; 16%
1 This does not include the power drawn by the biasing resistor R and the diode-connected transistor Q3 .
12.3 Class B Output Stage
Figure 12.5 shows a class B output stage. It consists of a complementary pair of transistors (an npn and a pnp) connected in such a way that both cannot conduct simultaneously.
12.3.1 Circuit Operation
When the input voltage vI is zero, both transistors are cut off and the output voltage vO is zero. As vI goes positive and exceeds about 0.5 V, QN conducts and operates as an emitter follower. In this case v O follows v I (i.e., v O = v I − v BEN ) and QN supplies the load current. Meanwhile, the emitter–base junction of QP will be reverse biased by the VBE of QN , which is approximately 0.7 V. Thus QP will be cut off.
If the input goes negative by more than about 0.5 V, QP turns on and acts as an emitter follower. Again vO follows vI (i.e., vO =vI + vEBP), but in this case QP supplies the load current (in the direction opposite to that of iL, since vO will be negative), and QN will be cut off.
We conclude that the transistors in the class B stage of Fig. 12.5 are biased at zero current and conduct only when the input signal is present. The circuit operates in a push–pull fashion: QN pushes (sources) current into the load when vI is positive, and QP pulls (sinks) current from the load when vI is negative.
12.3.2 Transfer Characteristic
A sketch of the transfer characteristic of the class B stage is shown in Fig. 12.6. Note that there exists a range of vI centered around zero where both transistors are cut off and vO is zero. This dead band results in the crossover distortion illustrated in Fig. 12.7 for the case of an input sine wave. The effect of crossover distortion will be most pronounced when the amplitude of the input signal is small. Crossover distortion in audio power amplifiers gives rise to unpleasant sounds.
Figure 12.5 A class B output stage.
12.3 Class B Output Stage 929
930 Chapter 12
Output Stages and Power Amplifiers
Figure 12.6 Transfer characteristic for the class B output stage in Fig. 12.5.
Figure 12.7 Illustrating how the dead band in the class B transfer characteristic results in crossover distortion.
12.3.3 Power-Conversion Efficiency
To calculate the power-conversion efficiency, η, of the class B stage, we neglect the crossover distortion and consider the case of an output sinusoid of peak amplitude Vˆo. The average load power will be
(12.12)
PL = 2 R
L
1 Vˆ o2
The current drawn from each supply will consist of half-sine waves of peak amplitude (Vˆ o /RL ). Thus the average current drawn from each of the two power supplies will be Vˆ o /π RL . It follows that the average power drawn from each of the two power supplies will be the same,
PS+ = PS− = 1 Vˆo VCC π RL
PS = 2 Vˆo VCC π RL
(12.13)
(12.14)
(12.15)
12.3 Class B Output Stage 931
and the total supply power will be
Thus the efficiency will be given by
η= 1Vˆo2 2VˆoVCC =π Vˆo 2 RL π RL 4 VCC
It follows that the maximum efficiency is obtained when Vˆ o is at its maximum. This maximum is limited by the saturation of QN and QP to VCC − VCEsat ≃ VCC . At this value of peak output voltage, the power-conversion efficiency is
ηmax = π = 78.5% (12.16) 4
This value is much larger than that obtained in the class A stage (25%). Finally, we note that the maximum average power available from a class B output stage is obtained by substituting Vˆo =VCC inEq.(12.12),
1 V2
PLmax = CC (12.17)
2 RL
12.3.4 Power Dissipation
Unlike the class A stage, which dissipates maximum power under quiescent conditions (vO =0), the quiescent power dissipation of the class B stage is zero. When an input signal is applied, the average power dissipated in the class B stage is given by
PD = PS − PL
Substituting for PS from Eq. (12.14) and for PL from Eq. (12.12) results in
(12.18)
(12.19) From symmetry we see that half of PD is dissipated in QN and the other half in QP . Thus QN
and QP must be capable of safely dissipating 1 PD watts. Since PD depends on Vˆo, we must 2
find the worst-case power dissipation, PDmax. Differentiating Eq. (12.19) with respect to Vˆo and equating the derivative to zero gives the value of Vˆo that results in maximum average power dissipation as
Vˆo|PDmax = 2 VCC (12.20) π
2 Vˆ o 1 Vˆ o2 PD=πR VCC−2R
LL
932 Chapter 12
Output Stages and Power Amplifiers
Figure 12.8 Power dissipation of the class B output stage versus amplitude of the output sinusoid. Substituting this value in Eq. (12.19) gives
Thus,
2V2 PDmax = CC
(12.21)
(12.22)
PDNmax =PDPmax = CC π2RL
At the point of maximum power dissipation, the efficiency can be evaluated by substituting for Vˆo from Eq. (12.20) into Eq. (12.15); hence, η = 50%.
Figure 12.8 shows a sketch of PD (Eq. 12.19) versus the peak output voltage Vˆo. Curves
such as this are usually given on the data sheets of IC power amplifiers. [Usually, however,
PD is plotted versus PL, as PL = 1(Vˆo2/RL) rather than Vˆo.] An interesting observation 2
follows from Fig. 12.8: Increasing Vˆ o beyond 2VCC /π decreases the power dissipated in the class B stage while increasing the load power. The price paid is an increase in nonlinear distortionasaresultofapproachingthesaturationregionofoperationofQN andQP.Transistor saturation flattens the peaks of the output sine waveform. Unfortunately, this type of distortion cannot be significantly reduced by the application of negative feedback (see Section 11.2), and thus transistor saturation should be avoided in applications requiring low THD.
Example 12.2
It is required to design a class B output stage to deliver an average power of 20 W to an 8- load. The power supply is to be selected such that VCC is about 5 V greater than the peak output voltage. This avoids transistor saturation and the associated nonlinear distortion, and allows for including short-circuit protection circuitry. (The latter will be discussed in Section 12.6.) Determine the supply voltage required,
π2RL
V2
the peak current drawn from each supply, the total supply power, and the power-conversion efficiency. Also determine the maximum power that each transistor must be able to dissipate safely.
Solution
Since
then
= 2×20×8=17.9V The peak current drawn from each supply is
Iˆo=Vˆo =17.9=2.24A RL 8
Since each supply provides a current waveform of half-sinusoids, the average current drawn from each supply will be Iˆo/π. Thus the average power drawn from each supply is
PS+ =PS− = 1 ×2.24×23=16.4W π
for a total supply power of 32.8 W. The power-conversion efficiency is η= PL = 20 ×100=61%
PS 32.8
The maximum power dissipated in each transistor is given by Eq. (12.22); thus,
L
The crossover distortion of a class B output stage can be reduced substantially by employing a high-gain op amp and overall negative feedback, as shown in Fig. 12.9. The ±0.7-V dead band is reduced to ±0.7/A0 volt, where A0 is the dc gain of the op amp. Nevertheless, the slew-rate limitation of the op amp will cause the alternate turning on and off of the output transistors to be noticeable, especially at high frequencies. A more practical method for reducing and almost eliminating crossover distortion is found in the class AB stage, which will be studied in the next section.
Therefore we select VCC = 23 V.
P L = 1 Vˆ o2 2 RL
Vˆ o = 2 P L R L √
12.3 Class B Output Stage 933
V2 PDNmax =PDPmax = CC
π2R
= π 2 × 8 = 6.7 W
(23)2
12.3.5 Reducing Crossover Distortion
934 Chapter 12
Output Stages and Power Amplifiers
Figure 12.9 Class B circuit with an op amp connected in a negative-feedback loop to reduce crossover distortion.
Figure 12.10 Class B output stage operated with a single power supply.
12.3.6 Single-Supply Operation
The class B stage can be operated from a single power supply, in which case the load is capacitively coupled, as shown in Fig. 12.10. Note that to make the formulas derived in Section 12.3.4 directly applicable, the single power supply is denoted 2VCC .
EXERCISE
12.4 FortheclassBoutputstageofFig.12.5,letVCC=6VandRL=4.Iftheoutputisasinusoidwith 4.5-V peak amplitude, find (a) the output power; (b) the average power drawn from each supply; (c) the power efficiency obtained at this output voltage; (d) the peak currents supplied by vI , assuming that βN =βP =50; and (e) the maximum power that each transistor must be capable of dissipating safely.
Ans. (a) 2.53 W; (b) 2.15 W; (c) 59%; (d) 22.1 mA; (e) 0.91 W
12.4 Class AB Output Stage
Crossover distortion can be virtually eliminated by biasing the complementary output transistors at a small nonzero current. The result is the class AB output stage shown in Fig. 12.11. A bias voltage VBB is applied between the bases of QN and QP. For vI =0, vO =0, andavoltageVBB/2appearsacrossthebase–emitterjunctionofeachofQN andQP.Assuming matched devices,
iN = iP = IQ = ISeVBB /2VT (12.23) The value of VBB is selected to yield the required quiescent current IQ.
12.4.1 Circuit Operation
When vI goes positive by a certain amount, the voltage at the base of QN increases by the same amount, and the output becomes positive at an almost equal value,
vO =vI +VBB −vBEN (12.24) 2
The positive vO causes a current iL to flow through RL, and thus iN must increase; that is,
iN =iP +iL (12.25)
The increase in iN will be accompanied by a corresponding increase in vBEN (above the quiescent value of VBB /2). However, since the voltage between the two bases remains constant
Figure 12.11 Class AB output stage. A bias voltage VBB is applied between the bases of QN and QP , giving rise to a bias current IQ given by Eq. (12.23). Thus, for small vI, both transistors conduct and crossover distortion is almost completely eliminated.
12.4 Class AB Output Stage 935
936 Chapter 12
Output Stages and Power Amplifiers
at VBB , the increase in v BEN will result in an equal decrease in v EBP relationship between iN and iP can be derived as follows:
vBEN +vEBP =VBB
VT lniN +VT lniP =2VT lnIQ
IS IS IS iNiP =IQ2
and hence in iP . The
(12.26)
Thus, as iN increases, iP decreases by the same ratio while the product remains constant. Equations (12.25) and (12.26) can be combined to yield iN for a given iL as the solution to the quadratic equation
iN2 −iLiN −IQ2 =0 (12.27)
From the equations above, we can see that for positive output voltages, the load current is suppliedbyQN,whichactsastheoutputemitterfollower.Meanwhile,QP willbeconductinga current that decreases as vO increases; for large vO the current in QP can be ignored altogether.
For negative input voltages the opposite occurs: The load current will be supplied by QP , which acts as the output emitter follower, while QN conducts a current that gets smaller as vI becomes more negative. Equation (12.26), relating iN and iP, holds for negative inputs as well.
We conclude that the class AB stage operates in much the same manner as the class B circuit, with one important exception: For small vI, both transistors conduct, and as vI is increased or decreased, one of the two transistors takes over the operation. Since the transition is a smooth one, crossover distortion will be almost totally eliminated. Figure 12.12 shows the transfer characteristic of the class AB stage.
Figure 12.12 Transfer characteristic of the class AB stage in Fig. 12.11.
Thus,
VV V Rout = T T = T
12.4 Class AB Output Stage 937
Figure12.13 Determiningthesmall-signaloutputresistanceof the class AB circuit of Fig. 12.11.
The power relationships in the class AB stage are almost identical to those derived for the class B circuit in Section 12.3. The only difference is that under quiescent conditions the class AB circuit dissipates a power of VCC IQ per transistor. Since IQ is usually much smaller than the peak load current, the quiescent power dissipation is usually small. Nevertheless, it can be taken into account easily. Specifically, we can simply add the quiescent dissipation per transistor to its maximum power dissipation with an input signal applied, to obtain the total power dissipation that the transistor must be able to handle safely.
12.4.2 Output Resistance
IfweassumethatthesourcesupplyingvI isideal,thentheoutputresistanceoftheclassAB stage can be determined from the circuit in Fig. 12.13 as
Rout =reN∥reP (12.28)
where reN and reP are the small-signal emitter resistances of QN and QP, respectively. At a given input voltage, the currents iN and iP can be determined, and reN and reP are given by
reN = VT iN
reP = VT iP
(12.29)
(12.30)
(12.31)
iN iP iP +iN
SinceasiN increases,iP decreases,andviceversa,theoutputresistanceremainsapproximately constant in the region around vI =0. This, in effect, is the reason for the virtual absence of crossoverdistortion.Atlargerloadcurrents,eitheriN oriP willbesignificant,andRout decreases as the load current increases.
938 Chapter 12 Output Stages and Power Amplifiers
Example 12.3
In this example we explore the details of the transfer characteristic, vO versus vI , of the class AB circuit in Fig.12.11. For this purpose let VCC =15V, IQ =2mA, and RL =100 . Assume that QN and QP are matched and have IS = 10−13 A. First, determine the required value of the bias voltage VBB . Then, find the transfer characteristic for vO in the range −10 V to +10 V.
Solution
To determine the required value of VBB we use Eq. (12.23) with IQ = 2 mA and IS = 10−13 A. Thus,
VBB =2VT ln IQ/IS
=2×0.025ln 2×10−3/10−13 =1.186V
The easiest way to determine the transfer characteristic is to work backward; that is, for a given vO we determine the corresponding value of vI . We shall outline the process for positive vO:
1. Assume a value for vO.
2. Determine the load current iL ,
iL =vO/RL
3. Use Eq. (12.27) to determine the current conducted by QN , iN .
4. Determine vBEN from
5. Determine vI from
vBEN =VT ln iN/IS
vI =vO +vBEN −VBB/2 ItisalsousefultofindiP andvEBP asfollows:
iP =iN −iL
vEBP =VT ln iP/IS
A similar process can be employed for negative vO. However, symmetry can be utilized, obviating the need to repeat the calculations. The results obtained are displayed in the following table:
12.4 Class AB Output Stage 939
vO (V) +10.0
+5.0 +1.0 +0.5 +0.2 +0.1
vBEN (V) 0.691
0.673 0.634 0.619 0.605 0.599 0.593 0.587 0.581 0.567 0.552 0.513 0.495
50 10 5 2 1 0 0
iP (mA) 50.08 0.08
0.50 1.00 2.32 0.98 4.03 0.96 5.58 0.95 6.07 0.94 6.25 0.94 6.07 0.94 5.58 0.95 4.03 0.96 2.32 0.98 0.50 1.00 0.25 1.00
–0.1 –0.2 –0.5 –1.0 –5.0
–10.0
–1 –2 –5
–10
–50 –100
10.39 0.39 5.70 0.70 3.24 1.24 2.56 1.56 2 2 1.56 2.56 1.24 3.24 0.70 5.70 0.39 10.39 0.08 50.08 0.04 100.04
iL (mA) 100
iN (mA)
100.04 0.04
vEBP (V) 0.495
0.513 0.552 0.567 0.581 0.587 0.593 0.599 0.605 0.619 0.634 0.673 0.691
well as
vi RL +Rout
vI (V) vO/vI 10.1 0.99
5.08 0.98 1.041 0.96 0.526 0.95 0.212 0.94 0.106 0.94 0 —
–0.106 0.94 –0.212 0.94 –0.526 0.95 –1.041 0.96 –5.08 0.98
–10.1 0.99
incremental gain
Rout () vo/vi 0.25 1.00
The table
values of vO. The incremental gain is computed as follows
also provides
values for the dc
gain
as
v O /v I vo= RL
the
v o /v i
at the
various
where Rout is the small-signal output resistance of the amplifier, given by Eq. (12.31). The incremental
gain is the slope of the voltage-transfer characteristic, and the magnitude of its variation over the
range of v is an indication of the linearity of the output stage. Observe that for 0 ≤ v ≤ 10 V, OO
the incremental gain changes from 0.94 to 1.00, about 6%. Also observe as vO becomes positive, QN supplies more and more of iL and the current in QP is correspondingly reduced. The opposite happens for negative vO.
EXERCISE
12.5 To increase the linearity of the class AB output stage, the quiescent current IQ is increased. The price paid is an increase in quiescent power dissipation. For the output stage considered in Example 12.3:
(a) Find the quiescent power dissipation. (b) If IQ is increased to 10 mA, find vo/vi at vO = 0 and at vO
= 10 V, and hence the percentage
change. Compare to the case in Example 12.3.
(c) Find the quiescent power dissipation for the case in (b).
Ans. (a) 60 mW; (b) 0.988 to 1.00; for a change of 1.2% compared to the 6% change in Example 12.3; (c) 300 mW
940 Chapter 12
Output Stages and Power Amplifiers
12.5 Biasing the Class AB Circuit
In this section we discuss two approaches for generating the voltage VBB required for biasing the class AB output stage.
12.5.1 Biasing Using Diodes
Figure 12.14 shows a class AB circuit in which the bias voltage VBB is generated by passing a constant current IBIAS through a pair of diodes, or diode-connected transistors, D1 and D2. In circuits that supply large amounts of power, the output transistors are large-geometry devices. The biasing diodes, however, need not be large devices, and thus the quiescent current IQ established in QN and QP will be IQ =nIBIAS, where n is the ratio of the emitter–junction area of the output devices to the junction area of the biasing diodes. In other words, the saturation (or scale) current IS of the output transistors is n times that of the biasing diodes. Area ratioing is simple to implement in integrated circuits but difficult to realize in discrete-circuit designs.
When the output stage of Fig. 12.14 is sourcing current to the load, the base current of QN increases from IQ/βN (which is usually small) to approximately iL/βN. This base current drive must be supplied by the current source IBIAS. It follows that IBIAS must be greater than the maximum anticipated base drive for QN. This sets a lower limit on the value of IBIAS. Now, since n = IQ/IBIAS, and since IQ is usually much smaller than the peak load current (<10%), we see that we cannot make n a large number. In other words, we cannot make the diodes much smaller than the output devices. This is a disadvantage of the diode biasing scheme.
From the discussion above we see that the current through the biasing diodes will decrease when the output stage is sourcing current to the load. Thus the bias voltage VBB will also decrease, and the analysis of Section 12.4 must be modified to take this effect into account.
The diode biasing arrangement has an important advantage: It can provide thermal stabilization of the quiescent current in the output stage. To appreciate this point, recall that the class AB output stage dissipates power under quiescent conditions. Power dissipation
IBIAS
D1 D2
Figure 12.14 A class AB output stage utiliz- ing diodes for biasing. If the junction area of the output devices, QN and QP, is n times that of the biasing devices D1 and D2, a quiescent current IQ = nIBIAS flows in the output devices.
raises the internal temperature of the BJTs. From Chapter 6 we know that a rise in transistor temperatureresultsinadecreaseinitsVBE (approximately–2mV/°C)ifthecollectorcurrent is held constant. Alternatively, if VBE is held constant and the temperature increases, the collector current increases. The increase in collector current increases the power dissipation, which in turn increases the junction temperature and hence, once more, the collector current. Thus a positive-feedback mechanism exists that can result in a phenomenon called thermal runaway. Unless checked, thermal runaway can lead to the ultimate destruction of the BJT. Diode biasing can be arranged to provide a compensating effect that can protect the output transistors against thermal runaway under quiescent conditions. Specifically, if the diodes are in close thermal contact with the output transistors, their temperature will increase by the same amount as that of QN and QP . Thus VBB will decrease at the same rate as VBEN + VEBP , with the result that IQ remains constant. Close thermal contact is easily achieved in IC fabrication. It is obtained in discrete circuits by mounting the bias diodes on the metal case of QN or QP. Finally, it is important to note that thermal runaway does not occur in MOS circuits.
Example 12.4
Consider the class AB output stage under the conditions that VCC = 15 V, RL = 100 , and the output is sinusoidal with a maximum amplitude of 10 V. Let QN and QP be matched with IS = 10−13 A and β = 50. Assume that the biasing diodes have one-third the junction area of the output devices. Find the value of IBIAS that guarantees a minimum of 1 mA through the diodes at all times. Determine the quiescent current and the quiescent power dissipation in the output transistors (i.e., at vO = 0). Also find VBB for vO = 0, +10 V, and −10 V.
Solution
The maximum current through QN is approximately equal to iLmax = 10 V/0.1 k = 100 mA. Thus the maximumbasecurrentinQN isapproximately2mA.Tomaintainaminimumof1mAthroughthediodes, we select IBIAS = 3 mA. The area ratio of 3 yields a quiescent current of 9 mA through QN and QP . The quiescent power dissipation is
PDQ =2×15×9=270mW
ForvO =0,thebasecurrentofQN is9/51≃0.18mA,leavingacurrentof3−0.18=2.82mAtoflow
through the diodes. Since the diodes have I = 1 × 10−13 A, the voltage V will be S3 BB
VBB =2VT ln 2.82mA =1.26V IS
At vO = +10 V, the current through the diodes will decrease to 1 mA, resulting in VBB ≃ 1.21 V. At the other extreme of vO = −10 V, QN will be conducting a very small current; thus its base current will be negligibly small and all of IBIAS (3 mA) flows through the diodes, resulting in VBB ≃ 1.26 V.
12.5 Biasing the Class AB Circuit 941
942 Chapter 12 Output Stages and Power Amplifiers
EXERCISES
12.6 For the circuit of Example 12.4, find iN and iP for vO = +10 V and vO = −10 V. (Hint: Use the VBB values found in Example 12.4.)
Ans. 100.1 mA, 0.1 mA; 0.8 mA, 100.8 mA
12.7 If the collector current of a transistor is held constant, its vBE decreases by 2 mV for every 1°C rise intemperature.Alternatively,ifvBE isheldconstant,theniC increasesbyapproximatelygm×2mV for every 1°C rise in temperature. For a device operating at IC = 10 mA, find the change in collector current resulting from an increase in temperature of 5°C.
Ans. 4 mA
12.5.2 Biasing Using the VBE Multiplier
An alternative biasing arrangement that provides the designer with considerably more flexibility in both discrete and integrated designs is shown in Fig. 12.15. The bias circuit consists of transistor Q1 with a resistor R1 connected between base and emitter and a feedback resistor R2 connected between collector and base. The resulting two-terminal network is fed with a constant-current source IBIAS. If we neglect the base current of Q1, then R1 and R2 will carry the same current IR, given by
IR = VBE1 (12.32) R1
IBIAS
Figure 12.15 A class AB output stage utilizing a VBE multiplier for biasing.
and the voltage VBB across the bias network will be
VBB =IR(R1 +R2) R
=VBE1 1+ 2 R1
(12.33)
12.5 Biasing the Class AB Circuit 943
IBIAS
Figure 12.16 A discrete-circuit class AB output stage with a potentiometer used in the VBE multiplier. The potentiometerisadjustedtoyieldthedesiredvalueofquiescentcurrentinQN andQP.
Thus the circuit simply multiplies VBE1 by the factor (1+R2/R1) and is known as the “VBE multiplier.” The multiplication factor is obviously under the designer’s control and can be used to establish the value of VBB required to yield a desired quiescent current IQ . In IC design it is relatively easy to control accurately the ratio of two resistances. In discrete-circuit design, a potentiometer can be used, as shown in Fig. 12.16, and is manually set to produce the desired value of IQ.
The value of VBE 1 in Eq. (12.33) is determined by the portion of IBIAS that flows through the collector of Q1; that is,
IC1 = IBIAS − IR (12.34) VBE1 = VT ln IC1 (12.35)
IS1
where we have neglected the base current of QN , which is normally small both under quiescent conditions and when the output voltage is swinging negative. However, for positive vO, especially at and near its peak value, the base current of QN can become sizable and will
944 Chapter 12 Output Stages and Power Amplifiers
reduce the current available for the VBE multiplier. Nevertheless, since large changes in IC 1 correspond to only small changes in VBE 1 , the decrease in current will be mostly absorbed by Q1, leaving IR, and hence VBB, almost constant.
EXERCISE
12.8 Consider a VBE multiplier with R1 = R2 = 1.2 k, utilizing a transistor that has VBE = 0.6 V at IC = 1 mA, and a very high β. (a) Find the value of the current I that should be supplied to the multiplier to obtain a terminal voltage of 1.2 V. (b) Find the value of I that will result in the terminal voltage changing (from the 1.2-V value) by +50 mV, +100 mV, +200 mV, –50 mV, –100 mV, –200 mV.
Ans. (a) 1.5 mA; (b) 3.24 mA, 7.93 mA, 55.18 mA, 0.85 mA, 0.59 mA, 0.43 mA
Like the diode biasing network, the VBE –multiplier circuit can provide thermal stabilization of IQ. This is especially true if R1 =R2, and Q1 is in close thermal contact with the output transistors.
Example 12.5
It is required to redesign the output stage of Example 12.4 utilizing a VBE multiplier for biasing. Use a small-geometrytransistorforQ1 withIS=10−14 AanddesignforaquiescentcurrentIQ=2mA.
Solution
Sincethepeakpositivecurrentis100mA,thebasecurrentofQN canbeashighas2mA.Weshalltherefore select IBIAS = 3 mA, thus providing the multiplier with a minimum current of 1 mA.
Underquiescentconditions(vO=0andiL=0)thebasecurrentofQN canbeneglectedandallofIBIAS flows through the multiplier. We now must decide on how this current (3 mA) is to be divided between IC1 andIR.IfweselectIR greaterthan1mA,thetransistorwillbealmostcutoffatthepositivepeakofvO. Therefore,weshallselectIR =0.5mA,leaving2.5mAforIC1.
To obtain a quiescent current of 2 mA in the output transistors, VBB should be 2×10−3
VBB = 2VT ln 10−13 = 1.19 V We can now determine R1 + R2 as follows:
At a collector current of 2.5 mA, Q1 has
VBE1 = VT ln 10−14 = 0.66 V
R1+R2=VBB =1.19=2.38k IR 0.5
2.5 × 10−3
The value of R1 can now be determined as
R1 = 0.66 = 1.32 k
and R2 as
0.5
R2 = 2.38−1.32 = 1.06 k
12.6 Variations on the Class AB Configuration 945
12.6 Variations on the Class AB Configuration
In this section, we discuss a number of circuit improvements and protection techniques for the BJT class AB output stage.
12.6.1 Use of Input Emitter Followers
Figure 12.17 shows a class AB circuit biased using transistors Q1 and Q2 , which also function as emitter followers, thus providing the circuit with a high input resistance. In effect, the
Figure12.17 AclassABoutputstagewithaninputbuffer.Inadditiontoprovidingahighinputresistance, the buffer transistors Q1 and Q2 bias the output transistors Q3 and Q4.
946 Chapter 12
Output Stages and Power Amplifiers
Q1–Q2 circuit functions as a unity-gain buffer amplifier. Since all four transistors are usually matched, and neglecting the effect of R3 and R4, we see that the quiescent current (vI =0, RL = ∞) in Q3 and Q4 is equal to that in Q1 and Q2 . Resistors R3 and R4 are usually very small and are included to compensate for possible mismatches between Q3 and Q4 and to guard against the possibility of thermal runaway due to temperature differences between the input- and output-stage transistors. The latter point can be appreciated by noting that an increase in the current of, say, Q3 causes an increase in the voltage drop across R3 and a corresponding decrease in VBE3. Thus R3 provides negative feedback that helps stabilize the current through Q3.
Because the circuit of Fig. 12.17 requires high-quality pnp transistors, it is not suitable for implementation in conventional monolithic IC technology. However, excellent results have been obtained with this circuit implemented in hybrid thick-film technology (Wong and Sherwin, 1979). This technology permits component trimming, for instance, to minimize the output offset voltage. The circuit can be used alone or together with an op amp to provide increased output driving capability.
EXERCISE
12.9 (Note: Although rather long, this exercise is very instructive.) Consider the circuit of Fig. 12.17 with R1 =R2 =5 k, R3 =R4 =0 , and VCC =15 V. Let the transistors be matched with IS =3.3 ×10−14 A and β = 200. (These are the values used in the LH002 manufactured by National Semiconductor, except that R3 =R4 = 2 there.) (a) For vI =0 and RL = ∞, find the quiescent current in each of the four transistors and vO. (b) For RL = ∞, find iC1, iC2, iC3, iC4, and vO for vI = + 10 V and −10 V. (c) Repeat (b) for RL =100 .
Ans. (a) 2.87 mA; 0 V; (b) for vI = +10 V: 0.88 mA, 4.87 mA, 1.95 mA, 1.95 mA, +9.98 V; forvI=−10V:4.87mA,0.88mA,1.95mA,1.95mA,−9.98V;(c)forvI =+10V:0.38mA, 4.87 mA, 100 mA, 0.02 mA, +9.86 V; for vI = − 10 V: 4.87 mA, 0.38 mA, 0.02 mA, 100 mA, −9.86 V
12.6.2 Use of Compound Devices
To increase the current gain of the output-stage transistors, and thus reduce the required base current drive, the Darlington configuration shown in Fig. 12.18 is frequently used to replace the npn transistor of the class AB stage. The Darlington configuration is equivalent to a single npn transistor having β ≃ β1β2, but almost twice the value of VBE.
The Darlington configuration can be also used for pnp transistors, and this is indeed done in discrete-circuit design. In IC design, however, the lack of good-quality pnp transistors prompted the use of the alternative compound configuration shown in Fig. 12.19. This compound device is equivalent to a single pnp transistor having β ≃ β1β2. When fabricated with standard IC technology, Q1 is usually a lateral pnp having a low β (β = 5 − 10) and poor high-frequency response ( fT ≃ 5 MHz); see Appendix A and Appendix K. The compound
12.6 Variations on the Class AB Configuration 947
Figure 12.18 The Darlington configuration.
Figure 12.19 The compound-pnp configuration.
device, although it has a relatively high equivalent β, still suffers from a poor high-frequency response. It also suffers from another problem: The feedback loop formed by Q1 and Q2 is prone to high-frequency oscillations (with frequency near fT of the pnp device, i.e., about 5 MHz). Methods exist for preventing such oscillations. The subject of feedback-amplifier stability was studied in Chapter 11.
To illustrate the application of the Darlington configuration and of the compound pnp, we show in Fig. 12.20 an output stage utilizing both. Class AB biasing is achieved using a VBE multiplier. Note that the Darlington npn adds one more VBE drop, and thus the VBE multiplier is required to provide a bias voltage of about 2 V. The design of this class AB stage is investigated in Problem 12.39.
948 Chapter 12 Output Stages and Power Amplifiers
IBIAS
Figure 12.20 A class AB output stage utilizing a Darlington npn and a compound pnp. Biasing is obtained usingaVBE multiplier.
EXERCISE
12.10 (a) Refer to Fig. 12.19. Show that, for the composite pnp transistor, iB≃ iC
and
Hence show that
βN βP iE ≃iC
i ≃β I evEB/VT C NSP
and thus the transistor has an effective scale current
IS =βNISP
where ISP is the scale current of the pnp transistor Q1.
(b) For βP =20, βN =50, ISP =10−14 A, find the effective current gain of the compound device and its vEB wheniC=100mA.
Ans. (b) 1000; 0.651 V
12.6 Variations on the Class AB Configuration 949
IBIAS
vO
Figure 12.21 A class AB output stage with short-circuit protection. The protection circuit shown operates in the event of an output short circuit while vO is positive.
12.6.3 Short-Circuit Protection
Figure 12.21 shows a class AB output stage equipped with protection against the effect of short-circuiting the output while the stage is sourcing current. The large current that flows through Q1 in the event of a short circuit will develop a voltage drop across RE 1 of sufficient value to turn Q5 on. The collector of Q5 will then conduct most of the current IBIAS, robbing Q1 of its base drive. The current through Q1 will thus be reduced to a safe operating level.
This method of short-circuit protection is effective in ensuring device safety, but it has the disadvantage that under normal operation about 0.5 V drop might appear across each RE . This means that the voltage swing at the output will be reduced by that much, in each direction. On the other hand, the inclusion of emitter resistors provides the additional benefit of protecting the output transistors against thermal runaway.
EXERCISE
D12.11 In the circuit of Fig. 12.21 let IBIAS =2 mA. Find the value of RE1 that causes Q5 to turn on and absorb all 2 mA when the output current being sourced reaches 150 mA. For Q5 , IS = 10−14 A. If the normal peak output current is 100 mA, find the voltage drop across RE1 and the collector current of Q5.
Ans. 4.3 ; 430 mV; 0.3 μA
950 Chapter 12
Output Stages and Power Amplifiers
12.6.4 Thermal Shutdown
Figure 12.22 Thermal-shutdown circuit.
In addition to short-circuit protection, most IC power amplifiers are usually equipped with a circuit that senses the temperature of the chip and turns on a transistor in the event that the temperature exceeds a safe preset value. The turned-on transistor is connected in such a way that it absorbs the bias current of the amplifier, thus virtually shutting down its operation.
Figure 12.22 shows a thermal-shutdown circuit. Here, transistor Q2 is normally off. As the chip temperature rises, the combination of the positive temperature coefficient of zener diode Z1 and the negative temperature coefficient of VBE 1 causes the voltage at the emitter of Q1 to rise. This in turn raises the voltage at the base of Q2 to the point at which Q2 turns on.
12.7 CMOS Class AB Output Stages
In this section we study CMOS class AB output stages. We begin with the CMOS counterpart of the BJT class AB output stage studied in Section 12.5. As we shall see, this circuit suffers from a relatively low output signal swing, a serious limitation, especially in view of the shrinking power-supply voltages characteristic of modern deep-submicron CMOS technologies. We will then look at an attractive alternative circuit that overcomes this problem.
12.7.1 The Classical Configuration
Figure 12.23 shows the classical CMOS class AB output stage. The circuit is the exact counterpart of the bipolar circuit shown in Fig. 12.14 with the biasing diodes implemented with diode-connected transistors Q1 and Q2. The constant current IBIAS flowing through Q1 and Q2 establishes a dc bias voltage VGG between the gates of QN and QP . This voltage in turn establishesthequiescent(vO =0)currentIQ inQN andQP.UnliketheBJTcircuitinFig.12.14, here the zero dc gate current of QN results in the current through Q1 and Q2 remaining constant
VDD
IBIAS VDD Q1 QN
12.7 CMOS Class AB Output Stages 951
VGG
vI
vO iL
Q2 QPRL
VSS
Figure 12.23 Classical CMOS class AB output stage. This circuit is the CMOS counterpart of the BJT circuit in Fig. 11.14 with the biasing diodes implemented with diode-connected MOSFETs Q1 and Q2
at IBIAS irrespective of the value of vO and the load current iL. Thus VGG remains constant and the circuit is more like the idealized bipolar case shown in Fig. 12.11.
The value of IQ can be determined by utilizing the iD−vGS equations for the four MOS transistors for the case vO = 0. Neglecting channel-length modulation, we can write for Q1,
and for Q2,
ID1 =IBIAS = 1kn′(W/L)1(VGS1 −Vtn)2 (12.36) 2
I =I =1k′(W/L)(V −V )2 (12.37) D2 BIAS 2p 2 SG2 tp
Equations (12.36) and (12.37) can be used to find VGS1 and VSG2, which when summed yield VGG; thus,
V =V +V =V+V+2I 1 + 1 (12.38)
(12.39)
(12.40)
GG GS1 SG2 tn tp BIAS kn′ (W/L)1 kp′ (W/L)2 WecanfollowasimilarprocessforQN andQP,which,forvO =0,areconductingthequiescent
current IQ; thus,
VGG =VGSN +VSGP =Vtn +Vtp+ 2IQ 1 + 1
kn′ (W/L)n kp′ (W/L)p Equations (12.38) and (12.39) can be combined to obtain
2 1 kn′(W/L)1 +1 kp′(W/L)2
IQ =IBIAS 1k′(W/L) +1k′(W/L) nnpp
952 Chapter 12
Output Stages and Power Amplifiers
which indicates that IQ is determined by IBIAS together with the (W/L) ratios of the four transistors. For the case Q1 and Q2 are matched, that is,
kp′ (W/L)2 = kn′ (W/L)1 and QN and QP are matched, that is,
(12.41)
(12.42)
(12.43)
Equation (12.40) simplifies to
kp′ (W/L)p = kn′ (W/L)n I = I (W/L)n
Q BIAS (W/L)1 which is an intuitively appealing result.
EXERCISE
12.12 For the CMOS class AB output stage of Fig. 12.23, consider the case of matched Q1 and Q2 , and matched QN and QP. If IQ =1 mA and IBIAS =0.2mA, find (W/L) for each of Q1, Q2, QN, and QP so that in the quiescent state each transistor operates at an overdrive voltage of 0.2 V. Let VDD =VSS =2.5V,kn′ =250μA/V2,kp′ =100μA/V2,andVtn =−Vtp =0.5V.AlsofindVGG.
Ans. 40; 100; 200; 500; 1.4 V
A drawback of the CMOS class AB circuit of Fig. 12.23 is the restricted range of output voltage swing. To find the maximum possible value of vO, refer to Fig. 12.23 and assume that across the bias current source is a dc voltage of VBIAS. We can write for vO,
vO =VDD −VBIAS −vGSN (12.44)
The maximum value of vO will be limited by the need to keep VBIAS to a minimum of VOV of the transistor supplying IBIAS (otherwise the current-source transistor no longer operates in saturation); thus,
vOmax =VDD −VOV |BIAS −vGSN (12.45) Note that when vO is at its maximum value, QN will be supplying most or all of iL, and vGSN
will be large, thus
vOmax =VDD −VOV |BIAS −Vtn −vOVN (12.46) wherevOVN istheoverdrivevoltageofQN whenitissupplyingiLmax.
12.7 CMOS Class AB Output Stages 953
EXERCISE
12.13 For the circuit specified in Exercise 12.12, find vOmax when iLmax = 10 mA. Assume that QN is supplyingallofiLmax andthatVOV|BIAS =0.2V.
Ans. 1.17 V
The minimum allowed value of vO can be found in a similar way. Here we note that the transistorsupplyingvI (notshown)willneedaminimumvoltageacrossitofVOV|I.Thus,
v =−V+V|+V+|v| (12.47) Omin SS OV I tp OVP
where |vOVP| is the overdrive voltage of QP when sinking the maximum negative value of iL. Finally, we observe that the reason for the lower allowable range of vO in the CMOS circuit is the relatively large value of vOVN and |vOVP|; that is, the large values of vGSN and vSGP required to supply the large output currents. In the BJT circuit the corresponding voltages, vBEN and vEBP, remain close to 0.7 V. The overdrive voltages vOVN and |vOVP| can be reduced by making the W/L ratios of QN and QP large. This, however, can lead to impractically large
devices.
12.7.2 An Alternative Circuit Utilizing Common-Source Transistors
The allowable range of vO can be increased by replacing the source followers with a pair of complementary transistors connected in the common-source configuration, as shown in Fig. 12.24. Here QP supplies the load current when vO is positive and allows vO to go as high as(VDD−|vOVP|),amuchhighervaluethanthatgivenbyEq.(12.46).FornegativevO,QN sinks the load current and allows v O to go as low as −VSS + v OVN . This also is larger in magnitude than the value given by Eq. (12.47). Thus, the circuit of Fig. 12.24 provides an output voltage
VDD
QP
QN RL
VSS
vO iL
Figure 12.24 An alternative CMOS output stage utiliz- ing a pair of complementary MOSFETs connected in the common-source configuration. The driving circuit is not shown.
954 Chapter 12
Output Stages and Power Amplifiers
vI
m
VDD
QP
iDP
iL
iDN
RL
vO
m QN
VSS
Figure 12.25 Inserting an amplifier in the negative feedback path of each of QN and QP reduces the output
resistance and makes vO ≃ vI ; both are desirable properties for the output stage.
range that is within an overdrive voltage of each of the supplies. The disadvantage of the
circuit, however, is its high output resistance,
Rout =ron∥rop (12.48)
To reduce the output resistance, negative feedback is employed as shown in Fig. 12.25. Here anamplifierwithgainμisinsertedbetweendrainandgateofeachofQN andQP.Toverifythat the feedback around each amplifier is negative, assume that vO increases. The top amplifier will cause the gate voltage of QP to increase, thus its vSG decreases and iDP decreases. The decrease in iDP causes vO to decrease, which is opposite to the initially assumed change, thus verifying that the feedback is negative. A similar process can be used to verify that the feedback around the bottom amplifier also is negative.
From our study of feedback in Chapter 11, we observe that each of the two feedback loops is of the series–shunt type, which is the topology appropriate for a voltage amplifier. Thus, as we shall show shortly, the feedback will reduce the output resistance of the amplifier. Also, observe that if the loop gain is large, the voltage difference between the two input terminals of each feedback amplifier, the error voltage, will be small, resulting in vO ≃ vI . For this reason, the two amplifiers μ are known as error amplifiers.
Both the low output resistance and the near-unity dc gain are highly desirable properties for an output stage.
Output Resistance To derive an expression for the output resistance Rout, we consider each half of the circuit separately, find its output resistance, Routp for the top half and Routn for the bottom half, and then obtain the overall output resistance as the parallel equivalent of the two resistances,
Rout = Routn ∥ Routp (12.49)
vI
m
VDD
Q P
(a)
12.7 CMOS Class AB Output Stages 955
RL
vO
vf RL vo
(b)
vi
Routp
m
Rof
Q P
vo RL
Ro
Figure 12.26 Determining the output resistance. (a) The top half of the output stage showing the definition of Routp and Rof . (b) The β circuit and (c) the A circuit.
Figure 12.26(a) shows the top half of the circuit. Observe that feedback is applied by connecting the output back to the input. Thus the feedback network is the two-port shown in Fig. 12.26(b) and the feedback factor is
β = 1 (12.50)
Including the loading effects of the feedback network results in the A circuit shown in Fig. 12.26(c). Note that since we are now interested in incremental quantities, we have replaced VDD with a short circuit to ground. The open-loop gain A can be found from the circuit in Fig. 12.26(c) as
A≡vo =μgmp(rop∥RL) (12.51) vi
where we have utilized implicitly the small-signal model of QP . The values of the small-signal parametersgmp androp aretobeevaluatedatthecurrentatwhichQP isoperating.Theopen-loop output resistance Ro is found by inspection as
Ro = RL ∥rop (12.52)
(c)
956 Chapter 12
Output Stages and Power Amplifiers
The output resistance with feedback Rof can now be found as Rof = Ro = (RL ∥rop)
1+Aβ 1+μgmp(rop∥RL)
and the output resistance Routp is found by excluding RL from Rof , that is,
(12.53)
(12.54)
(12.55)
1 1 Routp=1 R −R
of L
which results in
1 1
Routp = ropμg ≃ μg mp
mp
which can be quite low. A similar development applied to the bottom half of the circuit in Fig. 12.25 results in
Routn ≃ 1/μgmn (12.56) Combining Eqs. (12.55) and (12.56) gives
Rout ≃ 1/μ gmp + gmn (12.57)
The Voltage-Transfer Characteristic Next we derive an expression for the voltage- transfer characteristic, vO versus vI , of the class AB common-source buffer. Toward that end, we first consider the circuit in the quiescent state, shown in Fig. 12.27(a). Here vI = 0 and vO = 0. Each of the error amplifiers is designed to deliver to the gate of its associated MOSFET the dc voltage required to establish the desired value of quiescent current IQ.
Note that these voltages at the outputs of the error amplifiers are the dc bias or quiescent values. These voltages will undergo incremental changes when the input voltages of the amplifiers change from zero. To obtain class AB operation, IQ is usually selected to be 10%
VDD
(VDD –VSGP)
VSGP
(VDD – VSGP) VDD +m(vO –vI)
vSGP
m QP
iDP
iDN
0
m QP IQ
IQ
0 V vI
vO
iL
RL RL m QN m QN
VGSN (–VSS + VGSN)
V (a)
SS
(–VSS + VGSN) + m(vO – vI)
(b)
vGSN
V SS
Figure 12.27 Analysis of the CMOS output stage to determine vO versus vI . (a) Quiescent conditions. (b) The situation with vI applied.
12.7 CMOS Class AB Output Stages 957 or so of the maximum output current. Referring to Fig. 12.27(a), we can write for QP ,
1 W IDP=IQ= kp′ (VSGP−Vtp)2
2Lp
Substituting V = V + V , where V is the magnitude of the quiescent overdrive voltage
SGP tp OV OV
of QP, gives
Similarly, we obtain for QN
Usually the two transistors are matched,
1 W
I = k′ V2
(12.58)
(12.59)
Q 2p L OV p
1 W
I = k′ V2
Q 2n L OV n
W W k p′ = k n′
Lp Ln I = 1kV2
= k
Thus,
(12.60) Next consider the situation with vI applied, illustrated in Fig. 12.27(b). The voltage at the
Q 2 OV
output of each of the error amplifiers increases by μ(v O − v I ).
Thus
v SGP
decreases by
(12.61)
(12.62)
μ(vO−vI)andvGSN increasesbyμ(vO−vI),andwecanwrite iDP = 1k[VOV −μ(vO −vI)]2
2
1 v−v2 =kV21−μO I
2 OV VOV v−v2
=IQ 1−μO I VOV
and
At the output node we have
v−v2 iDN =IQ 1+μ O I
resulting equation to obtain vO, results in
vO = vI
VOV iL = iDP − iDN
(12.63) Substituting for iL = v O /RL and for iDP and iDN from Eqs. (12.61) and (12.62), and solving the
Usually
VOV /4μIQ RL
1+ VOV 4μIQ RL
≪ 1, enabling us to express v O as V
vO ≃vI 1− OV 4μIQ RL
(12.64)
(12.65)
958 Chapter 12
Output Stages and Power Amplifiers
Thus the gain error is
Since at the quiescent point,
the gain error can be expressed as
Gainerror≡vO −1=− VOV vI 4μIQRL
gmp = gmn = gm = 2IQ VOV
Gain error = − 1 2μgm RL
(12.66)
(12.67)
(12.68)
Thus selecting a large value for μ results in reducing both the gain error and the output resistance. However, a large μ can make the quiescent current IQ too dependent on the input offset voltages that are inevitably present in the error amplifiers. Typically, μ is selected in the range 5 to 10. Trade-offs are also present in the selection of IQ: A large IQ reduces crossover distortion, Rout , and gain error, at the expense of increased quiescent power dissipation.
Example 12.6
In this example we explore the design and operation of a class AB common-source output stage of the type shown in Fig. 12.25, required to operate from a ±2.5-V power supply to feed a load resistance RL = 100 . The transistors available have Vtn = −Vtp = 0.5 V and kn′ = 2.5kp′ = 250 μA/V2 . The gain error is required tobelessthan2.5%andIQ =1mA.
Solution
The gain error is given by Eq. (12.66),
Gain error = − VOV 4μIQ RL
We are given the required maximum gain error of −0.025, I = 1 mA, and R = 100 . In order to keep QL
μ low and also obtain as high a gm as possible gm = 2IQ /VOV , we select VOV to be as low as possible. Practically speaking, VOV is usually 0.1 V to 0.2 V. Selecting VOV = 0.1 V results in
which yields
0.025 = 0.1 4×μ×1×10−3 ×100
μ=10
which is within the typically recommended range.
Figure 12.28(a) shows the circuit in the quiescent state with the various dc voltages and currents
indicated. Note that the dc voltages (±1.9 V) at the output of the error amplifiers are the dc bias values,
obtained with zero input signals applied at the amplifier inputs. The required (W/L) ratios of QN and QP can be found as follows:
I=1k′ W V2 Q 2p L OV
p
1×10−3 = 1 ×0.1×10−3 W ×(0.1)2
2Lp 2.5 V
12.7 CMOS Class AB Output Stages 959
1.9 V
10 QP
1 mA
1 mA 0
0V
0 V
RL = 100
0.41 V
0.01 V
10
10
1.8 V
2 V
0.4 V
10 QN 1.9 V
2.5 V (a)
2.5 V
QP
4 mA
4 mA
100
0
QN
2.5 V (b)
Figure 12.28 (a) Circuit in the quiescent state; (b) circuit at the point at which QN turns off; (c) conditions atvO =vOmax.
960
Chapter 12 Output Stages and Power Amplifiers
Example 12.6 continued
2.5 V vOmaxVtp
10
Vtp
QP vOVmax
At the edge of
iDP
triode region
vOmax
vImax
Figure 12.28 continued Thus,
iLmax 100
W
0
(c)
= 2000
W = (W/L)p = 2000 = 800
Lp
L n kn′ /kp′ 2.5
Thus QN and QP are very large transistors, not an unusual situation in a high-power output stage. To obtain the output resistance at the quiescent point, we use Eq. (12.57),
where
Thus
Rout=1 μ gmp +gmn
gmp =gmn = 2IQ = 2×1 =20mA/V VOV 0.1
Rout = 1 10(0.02 + 0.02)
=2.5
Next we wish to determine the maximum and minimum allowed values of vO. Since the circuit is symmetrical, we need to consider only the positive-output or the negative-output case. For vO positive, QP conducts more of the output current iL. Eventually, QN turns off and QP conducts all of iL. To find
the value of vO at which this occurs, note that QN turns off when the voltage at its gate drops from the quiescentvalueof−1.9V[seeFig.12.28(a)]to−2V,atwhichpointvGSN =Vtn.Anequalchangeof−0.1V appears at the output of the top amplifier, as shown in Fig. 12.28(b). Analysis of the circuit in Fig. 12.28(b) shows that
iDP = 1 ×0.1×10−3 ×2000×(0.2)2 =4mA 2
iL =iDP =4mA
vO =iLRL =4×10−3 ×100=0.4V
vI =vO+(0.1/10)=0.41V
ForvO>0.4V,QP mustconductallthecurrentiL.ThesituationatvO=vOmax isillustratedinFig.12.28(c).
Analysis of this circuit results in
and
EXERCISE
vOmax ≃ 2.05 V
iLmax = 20.5 mA
12.8 ICPowerAmplifiers 961
12.14 Suppose it is required to reduce the W/L ratios of QN and QP in the circuit considered in the above example by a factor of 2 while keeping IQ at 1 mA. What value should be used for VOV ? What is the newvalueforthegainerrorandforRout atthequiescentpoint?
Ans. 0.14 V; −3.5%; 3.5
12.8 IC Power Amplifiers
A variety of IC power amplifiers are available. Most consist of a high-gain, small-signal amplifier followed by a class AB output stage. Some have overall negative feedback already applied, resulting in a fixed closed-loop voltage gain. Others do not have on-chip feedback and are, in effect, op amps with large output-power capability. In fact, the output current-driving capability of any general-purpose op amp can be increased by cascading it with a class B or class AB output stage and applying overall negative feedback. The additional output stage can be either a discrete circuit or a hybrid IC such as the buffer discussed in Section 12.6. In the following we discuss some power-amplifier examples.
962 Chapter 12 Output Stages and Power Amplifiers
EARLY POWER-OP-AMP PRODUCT:
In 1985 Robert J. Widlar (1937–1991) and Mineo Yamatake at National Semiconductor introduced the LM12, probably the first very-high-power monolithic operational amplifier, offering an order-of-magnitude improvement over its predecessors. Nominally rated at 150-W output, this op amp could sustain 90 W of continuous sine-wave output with a 40- load, while handling up to 800 W of short-term dynamic loading. The design operated from ±35-V supplies to provide a ±25-V signal with a ±10-A output. This monolithic amplifier employed polycrystalline film resistors for thermal stability. It incorporated a variety of novel protection features involving disconnection of the load from the output terminal, turn-on delay while awaiting internal stabilization, overtemperature control, and output-current limiting. It was internally unity-gain compensated with a unity-gain bandwidth of 700 kHz. While now obsolete, the LM12 was a clear forerunner of a modern approach to a vast array of special applications in audio and motor control.
12.8.1 A Fixed-Gain IC Power Amplifier
Our first example is the LM380 (a product of National Semiconductor Corporation), which is a fixed-gain monolithic power amplifier. A simplified version of the internal circuit of the amplifier2 is shown in Fig. 12.29. The circuit consists of an input differential amplifier utilizing Q1 and Q2 as emitter followers for input buffering, and Q3 and Q4 as a differential pair with an emitter resistor R3. The two resistors R4 and R5 provide dc paths to ground for the base currents of Q1 and Q2, thus enabling the input signal source to be capacitively coupled to either of the two input terminals.
The differential amplifier transistors Q3 and Q4 are biased by two separate currents: Q3 is biased by a current from the dc supply VS through the diode-connected transistor Q10, and resistor R1; Q4 is biased by a dc current from the output terminal through R2. Under quiescent conditions (i.e., with no input signal applied) the two bias currents will be equal, and the current through and the voltage across R3 will be zero. For the emitter current of Q3 we can write
I3 ≃ VS −VEB10 −VEB3 −VEB1 R1
where we have neglected the small dc voltage drop across R4. Assuming, for simplicity, all VEB to be equal,
I3 ≃ VS − 3VEB R1
For the emitter current of Q4 we have
I4 = VO −VEB4 −VEB2 ≃ VO −2VEB
R2 R2
(12.69)
(12.70)
2The main objective of showing this circuit is to point out some interesting design features. The circuit is not a detailed schematic diagram of what is actually on the chip.
12.8 IC Power Amplifiers 963
D1
D2
Figure 12.29 The simplified internal circuit of the LM380 IC power amplifier. (Courtesy National Semiconductor Corporation.)
where VO is the dc voltage at the output, and we have neglected the small drop across R5. Equating I3 and I4 and using the fact that R1 = 2R2 results in
VO = 1VS + 1VEB (12.71) 22
Thus the output is biased at approximately half the power-supply voltage, as desired for maximum output voltage swing. An important feature is the dc feedback from the output to the emitter of Q4, through R2. This dc feedback acts to stabilize the output dc bias voltage at the value in Eq. (12.71). Qualitatively, the dc feedback functions as follows: If for some reason VO increases, a corresponding current increment will flow through R2 and into the emitter of Q4. Thus the collector current of Q4 increases, resulting in a positive increment in the voltage at the base of Q12. This, in turn, causes the collector current of Q12 to increase, thus bringing down the voltage at the base of Q8 and hence VO.
Continuing with the description of the circuit in Fig. 12.29, we observe that the differential amplifier (Q3 , Q4 ) has a current-mirror load composed of Q5 and Q6 (refer to Chapter 9, Section 9.5). The single-ended output voltage signal of the first stage appears at the collector of Q6 and thus is applied to the base of the second-stage common-emitter amplifier Q12. Transistor Q12 is biased by the constant-current source Q11, which also acts as its active load. In actual operation, however, the load of Q12 will be dominated by the reflected resistance due to RL . Capacitor C provides frequency compensation (see Chapter 11).
964 Chapter 12
Output Stages and Power Amplifiers
7 vi R1/2
0 R125k
2
2 vi
R3 1 k 0 V 5
vi 6
R3 0 V
R2 25 k
vo 9 R2
vi vo 3
1vi Q3 Q4 4
Q1 Q2 0 V
vi R4
R3 R2 10
12
R5
A vo 8
11 vi R3
Q5
v
14 i 0
R3
16 vo
vi
R3 13
Q6
A0 15
vi R3
Figure12.30 Small-signalanalysisofthecircuitinFig.12.29.Thecirclednumbersindicatetheorderofthe analysis steps.
The output stage is class AB, utilizing a compound pnp transistor (Q8 and Q9). Negative feedback is applied from the output to the emitter of Q4 via resistor R2 . To find the closed-loop gain consider the small-signal equivalent circuit shown in Fig. 12.30. Here, we have replaced the second-stage common-emitter amplifier and the output stage with an inverting amplifier block with gain A. We shall assume that the amplifier A has high gain and high input resistance, and thus the input signal current into A is negligibly small. Under this assumption, Fig. 12.30 shows the analysis details with an input signal vi applied to the inverting input terminal. The order of the analysis steps is indicated by the circled numbers. Note that since the input differential amplifier has a relatively large resistance, R3, in the emitter circuit, most of the applied input voltage appears across R3. In other words, the signal voltages across the emitter–base junctions of Q1 , Q2 , Q3 , and Q4 are small in comparison to the voltage across R3. Accordingly, the voltage gain can be found by writing a node equation at the collector of Q6:
which yields
vi +vo +vi =0 R3 R2 R3
vo =−2R2 ≃−50V/V vi R3
12.8 IC Power Amplifiers 965
EXERCISE
12.15 Denoting the total resistance between the collector of Q6 and ground by R, show, using Fig. 12.30, that
vo −2R2/R3
v =1+R/AR
which reduces to
−2R2 /R3
i2
under the condition that AR ≫ R2 .
As was demonstrated in Chapter 11, one of the advantages of negative feedback is the reduction of nonlinear distortion. This is the case in the circuit of the LM380.
TheLM380isdesignedtooperatefromasinglesupplyVS intherangeof12Vto22V.The
selectionofsupplyvoltagedependsonthevalueofRL andtherequiredoutputpowerPL.The
manufacturer supplies curves for the device power dissipation versus output power for a given
load resistance and various supply voltages. One such set of curves for RL = 8 is shown in
Fig. 12.31. Note the similarity to the class B power dissipation curve of Fig. 12.8. In fact, the
reader can easily verify that the location and value of the peaks of the curves in Fig. 12.31 are
accurately predicted by Eqs. (12.20) and (12.21), respectively (where VCC = 1 VS ). The line 2
labeled “3% distortion level” in Fig. 12.31 is the locus of the points on the various curves at
Figure 12.31 Power dissipation (PD) versus output power (PL) for the LM380 with RL =8 . (Courtesy National Semiconductor Corporation.)
966 Chapter 12 Output Stages and Power Amplifiers
which the distortion (THD) reaches 3%. A THD of 3% represents the onset of peak clipping
due to output-transistor saturation.
EXERCISE
D12.16 It is required to use the LM380 to drive an 8- loudspeaker. Use the curves of Fig. 12.31 to determine the maximum power supply possible while limiting the maximum power dissipation to 2.9W.Ifforthisapplicationa3%THDisallowed,findPL andthepeak-to-peakoutputvoltage. Ans. 20 V; 4.2 W; 16.4 V
12.8.2 The Bridge Amplifier
We conclude this section with a discussion of a circuit configuration that is popular in high-power applications. This is the bridge amplifier configuration shown in Fig. 12.32 utilizing two power op amps, A1 and A2. While A1 is connected in the noninverting configuration with a gain K = 1 + (R2/R1), A2 is connected as an inverting amplifier with a gain of equal magnitude K = R4/R3. The load RL is floating and is connected between the output terminals of the two op amps.
IfvI isasinusoidwithamplitudeVˆi,thevoltageswingattheoutputofeachopampwill be ±KVˆi, and that across the load will be ±2KVˆi. Thus, with op amps operated from ±15-V supplies and capable of providing, say, a ±12-V output swing, an output swing of ±24 V can be obtained across the load of the bridge amplifier.
In designing bridge amplifiers, note should be taken of the fact that the peak current drawn from each op amp is 2KVˆi/RL. This effect can be taken into account by considering the load seen by each op amp (to ground) to be RL /2.
R2
R
vO 1 KVˆ 1i
vO1 vO
A1 0
ˆ
vI 0
t 2KVi vI 4 0
ˆ
Vi
t
R RL vO t
vO 2 KVˆ 3i
A2 v0 t O2
R4 1R2 K R3 R1
R
Figure 12.32 The bridge amplifier configuration.
12.9 Class D Power Amplifiers 967
EXERCISE
12.17 ConsiderthecircuitofFig.12.32withR1 =R3 =10k,R2 =5k,R4 =15k,andRL =8.Findthe voltagegainandtheinputresistance.Thepowersupplyusedis±18V.IfvI isa20-Vpeak-to-peak sine wave, what is the peak-to-peak output voltage? What is the peak load current? What is the load power?
Ans. 3V/V;10k;60V;3.75A;56.25W
12.9 Class D Power Amplifiers
The class A, B, and AB output stages studied in the previous sections are linear amplifiers. They operate basically as voltage followers, reproducing across the load a replica of the input signal. The output transistors in these amplifiers can dissipate considerable power. This occurs because when providing a large current to the load, the voltage across the transistors can be relatively large. The result is a relatively low power-conversion efficiency, ranging from a theoretical maximum of 25% for the class A stage to 78.5% for the class B and AB stages. In practice, only 50% to 60% efficiencies are achieved in the class B and AB stages.
A very different approach to power amplification, utilized frequently in audio amplifier design, is found in the class D stage. Here, the power dissipated in the output transistors is reduced, theoretically to zero, by operating the transistors as on-off switches.3 For this to be possible, the audio-frequency signal is converted to a pulse format and the pulses are utilized to operate the output transistor switches. Commonly, pulsewidth modulation (PWM) is utilized. The PWM signal has a frequency at least 10 times higher than the highest audio frequency signal to be amplified. While the amplitude and frequency of the PWM signal remain constant, the magnitude of the audio signal is encoded in the width of the pulses. Specifically, the width of successive pulses is made proportional to the corresponding instantaneous magnitude of the audio signal vA.
Figure 12.33(a) shows how a PWM signal can be generated. The magnitude of the audio signal vA is compared to that of a triangular wave vT whose frequency in the example shown is 10 times that of vA. The comparison is performed by a circuit building block known as a comparator, shown in Fig. 12.33(c) as a black box. We shall study comparators in Chapter 18. Observe that whenever the magnitude of vA exceeds that of vT , the comparator output will be at its high level, V + . Conversely, when the magnitude of vA falls below that of vT , the comparator output goes to its low level, V−. Thus, at the output of the comparator we obtain the pulse waveform shown in Fig. 12.33(b). This waveform has the same frequency fs of the triangular wave and has standard high and low levels determined by the comparator design. The width of each pulse, tP , and hence the duty ratio (tP /T ), where T = 1/fs , is proportional to the corresponding instantaneous value of vA. This is the PWM signal.
3 An ideal switch has a zero “on” resistance and thus dissipates no power when it is closed and delivering the high load current. Also, it has infinite off resistance and thus dissipates zero power when it is open.
968 Chapter 12
Output Stages and Power Amplifiers
V
V
vT vA
PWM
Comparator
(a)
(b)
PWM
t
t
vA
vA
vT
LPF
fP
PWM
(c)
(d)
Figure 12.33 (a) By comparing the magnitude of the audio signal vA to that of a triangular wave vT , the PWM signal in (b) can be generated by using the comparator in (c). (d) The original signal vA can be recovered fromthePWMsignalbymeansofalow-passfilterwithapassbandfrequencyfP slightlylargerthanthehighest audio-frequency component of vA.
Since the average of a pulse waveform is determined by its duty ratio, the original audio signal vA can be recovered from the PWM signal by taking the time average of the latter. This in turn can be achieved by passing the PWM signal through a low-pass filter (LPF) whose cutoff frequency is just above the highest frequency of the audio signal.4 This is shown in block-diagram form in Fig. 12.33(d). The design of low-pass filters will be studied in Chapter 17.
HANS CAMENZIND—THE INVENTOR OF
THE CLASS D AMPLIFIER:
In 1966, while working for Mallory (now Duracell), Swiss-born engineer Hans Camenzind (1934–2012) filed a patent on “Pulse-Width Modulation Circuits,” introducing the two-state or class D amplifier. Camenzind had begun his U.S. career in 1960, at Transitron, an early semiconductor manufacturer. Later, in 1969, while at Mallory, he filed a second patent on a “Two-State Amplifier.” The class D amplifier has revolutionized the field of high-efficiency compact amplifiers. Today these devices, ubiquitous in mobile phones, also see application at enormous power levels for live-performance sound systems with thousands of watts per channel.
4The PWM signal has frequency components at fs and its harmonics, all of which will be higher than the frequency of the audio signal and thus can be easily removed by the low-pass filter.
VDD
QP
QN
PWM
12.9
Class D Power Amplifiers 969
PWM
LPF
(a)
Loudspeaker (Load)
VDD
Q3
Q4
PWM
VDD
Q1
Q2
PWM
(b)
Figure12.34 TwoschemesfordrivingtheloadofaclassDamplifier.Thedifferentialschemein(b)results in doubling the voltage excursion across the load.
Having obtained a pulse waveform in which the audio signal is encoded, we now show how the PWM signal can be used to drive the switches that supply the load power. Two alternative schemes for accomplishing this task are shown in Fig. 12.34. In Fig. 12.34(a), the logical inverse of PWM, denoted PWM and obtained from the comparator by simply exchanging the terminals to which vA and vT are applied, is used to drive two complementary MOS switches QP and QN . These switches connect the output node alternatively to VDD and ground, in effect producing a high-power version of PWM at their drain node. This is the signal applied to the load (shown as a loudspeaker) through a low-pass filter. It follows that vA appears across the load and the large current required by the low-resistance load is supplied by QP and QN .
To double the voltage excursion across the load, the scheme in Fig. 12.34(b) can be utilized. Here both PWM and its logical inverse PWM are used in a differential driving arrangement. When PWM is high and thus PWM is low, Q3 and Q2 are turned on while Q1 and Q4 are off. Thus current flows from VDD to ground through the load (from right to left). The opposite happens when PWM is low. Thus the voltage across the load will be twice that obtained with
970 Chapter 12
Output Stages and Power Amplifiers
the arrangement in Fig. 12.34(a). The circuit of the differential driving arrangement is known as an H bridge5 and can result in a maximum sinusoidal output voltage of amplitude VDD.
The description above leads to the conclusion that the power-conversion efficiency of a class D amplifier is 100%. This, of course, is only a theoretical limit. In practice, the power transistors exhibit finite on-resistances that lead to conduction losses. Also, every time the power MOSFETs are turned on and off, the gate and load capacitances are charged and discharged, resulting in power loss in the driving circuit. In addition, due to the finite switching speed of power MOSFETs, there will be a momentary short between VDD and ground during every switching cycle. The resulting shoot-through current is exactly the same as that encountered in a CMOS inverter (see Chapter 14), but it could be of much larger magnitude owing to the large transistor size. All these sources of power dissipation cause the power-conversion efficiency to be in the 85% to 95% range, still much larger than is achieved in a class AB stage.
As a final note, distortion in the class D amplifier can be contributed by the PWM modulation scheme, by inaccuracy of the duty ratio at the output node due to finite switching speeds of the power MOSFETs, and by the quality factor of the L and C elements in the output filter. Class D amplifiers typically exhibit THD of 0.1% to 1% at best. Another imperfection of the class D amplifiers is the generation of unwanted switching noise, usually in the inaudible range as electromagnetic interference. As a result, class D amplifiers are most useful in applications where power-conversion efficiency is of paramount importance. Class A and AB amplifiers can achieve THD figures of less than 0.01% and are mostly used in high-fidelity applications.
EXERCISES
12.18 Consider the comparator in Fig. 12.33(c) with the triangular wave vT having ±10 V peak voltages and comparator output levels of ±10 V. Find the duty ratio D and the average of the output voltage for the case in which vA is a constant voltage of magnitude (a) 0 V; (b) +5 V; (c) +10 V; (d) −5 V; (e) −10 V
Ans. (a)50%,0V;(b)75%,+5V;(c)100%,+10V;(d)25%,−5V;(e)0%;−10V
12.19 If the audio signal vA has a frequency spectrum of 20 Hz to 20 kHz, what is an appropriate value for fs ? Now if the low-pass filter is of second order, with its passband edge at 20 kHz and its gain falling off at 40 dB/decade, what is the attenuation encountered by the PWM component with frequency fs ?
Ans. 200 kHz; 40 dB
12.20 If the differential switching scheme shown in Fig. 12.34(b) is utilized and vA is a sine wave, what is
themaximumpeakamplitudeachievedacrossRL andwhatisthemaximumpowerdeliveredtoRL?
Evaluate these quantities for VDD = 35 V and RL = 8 . Now, if the power-conversion efficiency is
90%, what is the power delivered by the power supplies? V2
Ans. VDD, DD ;35V,76.6W;85.1W 2RL
5The name H arises from the resemblance of the circuit diagram to the letter H: The switches represent the vertical strokes of H and the load with the filter represents the horizontal stroke.
DRAIN (FLANGE)
12.10 Power Transistors 971
12.10 Power Transistors
The BJTs and MOSFETs that are utilized in the design of the output stages and power amplifiers studied in this chapter can be called upon to conduct currents in the ampere range, to support voltages in excess of 100 V, and to withstand power dissipation in the tens-of-watts range. Hence, they are called power transistors. In this section, we study the characteristics, specifications, and thermal operation of power transistors.6
12.10.1 Packages and Heat Sinks
Power transistors are basically larger versions of their small-signal counterparts; hence they retain similar characteristics. However, as will be explained shortly, their structures are modified for optimal voltage and current capabilities. Also, discrete power transistors are housed in special packages such as those shown in Fig. 12.35. The packages are usually mounted on heat sinks, special metal surfaces whose function is to facilitate the conduction of heat away from the transistor, thus keeping its internal temperature within safe operating limits. We shall have more to say about thermal issues in Section 12.10.4. A typical heat sink is shown in Fig. 12.36.
SOURCE DRAIN
GATE
(a)
(b)
Figure 12.35 Most popular packages for power transistors: (a) TO-03 metal package; (b) TO-220 plastic package.
Figure 12.36 Typical heat sink.
6Other semiconductor devices utilized in power electronic applications include thyristors and silicon-controlled rectifiers (SCRs). These are usually used in applications requiring much higher current and voltage ratings than those studied in this chapter. As well, a more recent device, the insulated-gate bipolar transistor, or IGBT, has a merged MOS/bipolar structure and combines the advantages of both. It is used in very high current applications and is not studied in this book.
972 Chapter 12
Output Stages and Power Amplifiers
12.10.2 Power BJTs
Device Structure The power BJT utilizes a variation on the basic structure in Fig. 6.7.
Specifically:
1. To increase the current-handling capability of the BJT while maintaining the current density at a reasonable level, the emitter area is made much larger. This is accomplished by utilizing multiple emitter regions (called “emitter fingers”) and connecting them together, as shown in the simplified device cross section in Fig. 12.37. To reduce the extrinsic base resistance rx , the width of each emitter finger is kept small.
2. To support higher voltages without device breakdown, the base is made wider (with the attendant reduction in β), and the collector is made thicker and its doping lighter. Again, these features are indicated in Fig. 12.37.
Device Parameters As a result of the structural differences, the parameters of power BJTs can differ somewhat from those of small-signal devices. Important differences include the following.
1. The current gain β is low, typically in the range of 10 to 80, but can be as low as 5. Here it is important to recall that β is a function of current and has a positive temperature coefficient (refer to Fig. 6.34).
2. The maximum collector current ICmax is typically in the ampere range but can be as high as 100 A.
3. The breakdown voltage (BVCEO ; refer to Fig. 6.33) is typically 50 V to 100 V but can be as high as 500 V.
4. ICBO is large (a few tens of microamps) and, as usual, doubles for every 10◦C rise in temperature.
Base
Emitter
p+ n+ n+ n+ p+
Thick base
n–
p
Thick collector
n+ substrate
Collector
Figure 12.37 Cross section of a power BJT.
5. At high currents, rπ becomes small (a few ohms) and the extrinsic base resistance rx becomes important.
6. The transition frequency fT is low (a few megahertz), Cμ is large (hundreds of picofarads),andCπ isevenlarger.
7. At high currents, the exponential iC –vBE relationship exhibits a factor-of-2 reduction in the exponent: that is, iC = IS evBE /2VT .
At large collector currents, the low β results in the requirement for a large base current. This can complicate the design of the circuit that drives the output transistors. The Darlington configuration discussed in Section 12.6 can be employed to provide a higher effective β.
The BJT Safe Operating Area The power dissipated in a BJT results in an increase in its temperature and thus power dissipation must be limited. The manufacturer specifies the maximum power that can be safely dissipated. In addition, the manufacturer provides a plot of the safe operating area (SOA) in the iC−vCE plane. The SOA specification takes the form shown in Fig. 12.38; the following paragraph numbers correspond to the boundaries on the sketch.
1. The maximum allowable current ICmax. Exceeding this current on a continuous basis can result in melting the wires that bond the device to the package terminals.
2. The maximum power dissipation hyberbola. This is the locus of the points for which vCEiC = PDmax. The specified PDmax corresponds to a specific temperature of the transistor case, TC 0 . If the case temperature TC is higher than TC 0 , a lower value of PDmax and a correspondingly lower hyberbola apply. This point will be explained in Section 12.10.4. Although the operating point can be allowed to move temporarily above the hyberbola, the average power dissipation should not be allowed to exceed the applicable PDmax.
3. The second-breakdown limit. Second breakdown is a phenomenon that results because current flow across the emitter–base junction is not uniform. Rather, the current density is greatest near the periphery of the junction. This “current-crowding” gives rise to increased localized power dissipation and hence temperature rise (at
BVCEO
12.10 Power Transistors 973
Figure 12.38 Safe operating area (SOA) of a BJT.
974 Chapter 12
Output Stages and Power Amplifiers
locations called hot spots). Since a temperature rise causes an increase in current, a
localized form of thermal runaway can occur, leading to junction destruction.
4. The collector-to-emitter breakdown voltage BVCEO. The instantaneous value of vCE should never be allowed to exceed BVCEO; otherwise, avalanche breakdown of the
collector–base junction may occur (Section 6.4).
Finally,itshouldbenotedthatlogarithmicscalesareusuallyusedforiC andvCE leadingtoa safe-operating-area boundary that consists of straight lines.
12.10.3 Power MOSFETs
Power MOSFETs have in the past number of years gained popularity in the design of power electronic circuits. This is a result of the following properties.
1. Unlike BJTs, MOSFETs do not require dc gate drive current. This greatly simplifies the design of the driving circuitry.
2. MOSFETs can operate at much higher switching speeds than BJTs, a definite advantage for power circuits employing switching, such as class D amplifiers.
3. MOSFETs do not suffer from secondary breakdown, thus benefiting from an extension of SOA.
4. The thermal characteristics of the MOSFET, as we shall see shortly, are superior to those of the BJT.
Structure of the Power MOSFET The MOSFET structure studied in Chapter 5 (Fig. 5.1) is not suitable for high-power applications. To appreciate this fact, recall that the drain current of an n-channel MOSFET operating in the saturation region is given by
1 W
iD = 2μnCox L (vGS−Vt)2 (12.72)
It follows that to increase the current capability of the MOSFET, its width W should be made large and its channel length L should be made as small as possible. Unfortunately, however, reducing the channel length of the standard MOSFET structure results in a drastic reduction in its breakdown voltage. Specifically, the depletion region of the reverse-biased body-to-drain junction spreads into the short channel, resulting in breakdown at a relatively low voltage. Thus the resulting device would not be capable of handling the high voltages typical of power-transistor applications. For this reason, new structures had to be found for fabricating short-channel (1- to 2-μm) MOSFETs with high breakdown voltages.
At the present time the most popular structure for a power MOSFET is the double-diffused or DMOS transistor shown in Fig. 12.39. As indicated, the device is fabricated on a lightly doped n-type substrate with a heavily doped region at the bottom for the drain contact. Two diffusions7 are employed, one to form the p-type body region and another to form the n-type source region.
The DMOS device operates as follows. Application of a positive gate voltage, v GS , greater than the threshold voltage Vt , induces a lateral n channel in the p-type body region underneath the gate oxide. The resulting channel is short; its length is denoted L in Fig. 12.39. Current is then conducted by electrons from the source moving through the resulting short channel
7See Appendix A for a description of the IC fabrication process.
Figure 12.39 Double-diffused verti- cal MOS transistor (DMOS).
to the substrate and then vertically down the substrate to the drain. This should be contrasted with the lateral current flow in the standard small-signal MOSFET structure (Chapter 5).
Even though the DMOS transistor has a short channel, its breakdown voltage can be very high (as high as 600 V). This is because the depletion region between the substrate and the body extends mostly in the lightly doped substrate and does not spread into the channel. The result is a MOS transistor that simultaneously has a high current capability (50 A is possible) as well as the high breakdown voltage just mentioned. Finally, we note that the vertical structure of the device provides efficient utilization of the silicon area.
Many unit devices such as that in Fig. 12.39 are usually fabricated on a chip and connected in parallel to achieve the required high current capability. Various layout and packing arrangements have been utilized, including an efficient design utilizing hexagons, termed HEXFET and available from International Rectifier.
Characteristics of Power MOSFETs In spite of their radically different structure, power MOSFETs exhibit characteristics that are quite similar to those of the small-signal MOSFETs studied in Chapter 5. Important differences exist, however, and these are discussed next.
Power MOSFETs have threshold voltages in the range of 1 V to 4 V. In saturation, the drain current is related to vGS by the square-law characteristic of Eq. (12.72). However, the iD –v GS characteristic becomes linear for larger values of v GS . The linear portion of the characteristic occurs as a result of the high electric field along the short channel, causing the velocity of charge carriers to reach an upper limit, a phenomenon known as velocity satu- ration.8 The linear iD–vGS relationship implies a constant gm in the velocity-saturation region.
Of considerable interest in the design of MOS power circuits is the variation of the MOSFET characteristics with temperature, illustrated in Fig. 12.40. Observe that there is a value of vGS (in the range of 4V to 6V for most power MOSFETs) at which the temperaturecoefficientofiD iszero.AthighervaluesofvGS,iD exhibitsanegativetemperature coefficient. This is a significant property: It implies that a MOSFET operating beyond the zero-temperature-coefficient point does not risk the possibility of thermal runaway. This is not the case, however, at low currents (i.e., lower than the zero-temperature-coefficient point). In
8Velocity saturation occurs also in standard MOSFET structures when the channel length is in the submicron range. We shall discuss velocity saturation in some detail in Section 15.1.
12.10 Power Transistors 975
976 Chapter 12
Output Stages and Power Amplifiers
Figure 12.40 The iD–vGS characteristic curve of a power MOS transistor (IRF 630, Siliconix) at case temperatures of –55°C, +25°C, and +125°C. (Courtesy of Siliconix Inc.)
the (relatively) low-current region, the temperature coefficient of iD is positive, and the power MOSFET can easily suffer thermal runaway (with unhappy consequences). Since class AB output stages are biased at low currents, means must be provided to guard against thermal runaway.
The reason for the positive temperature coefficient of iD at low currents is that vOV =(vGS−Vt)isrelativelylow,andthetemperaturedependenceisdominatedbythenegative temperature coefficient of Vt (in the range of –3 mV/°C to –6 mV/°C), which causes vOV to rise with temperature.
12.10.4 Thermal Considerations
Power transistors dissipate large amounts of power. The dissipated power is converted into heat,whichraisesthejunctiontemperature.However,thejunctiontemperatureTJ mustnotbe allowed to exceed a specified maximum, TJ max ; otherwise the transistor could suffer permanent damage. For silicon devices, TJmax is in the range of 150°C to 200°C.
Thermal Resistance Consider first the situation of a transistor operating in free air—that is, with no special arrangements for cooling. The heat dissipated in the transistor will be conducted away from the junction to the transistor case, and from the case to the surrounding environment. In a steady state in which the transistor is dissipating PD watts, the temperature rise of the junction relative to the surrounding ambience can be expressed as
TJ −TA =θJAPD (12.73)
where θJA is the thermal resistance between junction and ambience, having the units of degrees Celsius per watt. Note that θJA simply gives the rise in junction temperature over the ambient temperature for each watt of dissipated power. Since we wish to be able to dissipate large amounts of power without raising the junction temperature above TJmax, it is desirable to have, for the thermal resistance θJA, as small a value as possible. For operation in free air, θJA depends primarily on the type of case in which the transistor is packaged. The value of θJA is usually specified on the transistor data sheet.
Equation (12.73), which describes the thermal-conduction process, is analogous to Ohm’s law, which describes the electrical-conduction process. In this analogy, power dissipation corresponds to current, temperature difference corresponds to voltage difference, and thermal resistance corresponds to electrical resistance. Thus, we may represent the thermal-conduction process by the electric circuit shown in Fig. 12.41.
Power Dissipation versus Temperature The transistor manufacturer usually specifies the maximum junction temperature TJmax, the maximum allowable power dissipation at a particularambienttemperatureTA0 (usually25°C),andthethermalresistanceθJA.Inaddition, a graph such as that shown in Fig. 12.42 is usually provided. The graph simply states that for operation at ambient temperatures below TA0, the device can safely dissipate the rated value of PD0 watts. However, if the device is to be operated at higher ambient temperatures, the maximum allowable power dissipation must be derated according to the straight line shown in Fig. 12.42. The power-derating curve is a graphical representation of Eq. (12.73). Specifically, note that if the ambient temperature is TA0 and the power dissipation is at the maximum allowed (PD0), then the junction temperature will be TJmax. Substituting these quantities in Eq. (12.73) results in
θJA = TJmax −TA0 (12.74) PD0
Figure 12.41 Electrical equivalent circuit of the thermal- conduction process; TJ −TA =PDθJA.
12.10 Power Transistors 977
Figure12.42 MaximumallowablepowerdissipationversusambienttemperatureforaBJToperatedinfree air. This is known as a “power-derating” curve.
978 Chapter 12
Output Stages and Power Amplifiers
which is the inverse of the slope of the power-derating straight line. At an ambient temperature TA, higher than TA0, the maximum allowable power dissipation PDmax can be obtained from Eq. (12.73) by substituting TJ =TJmax; thus,
PDmax = TJmax −TA (12.75) θJA
Observe that as TA approaches TJmax, the allowable power dissipation decreases; the lower thermal gradient limits the amount of heat that can be removed from the junction. In the extreme situation of TA =TJmax, no power can be dissipated because no heat can be removed from the junction.
Example 12.7
A BJT is specified to have a maximum power dissipation PD 0 of 2 W at an ambient temperature TA 0 of 25°C, and a maximum junction temperature TJmax of 150°C. Find the following:
(a) the thermal resistance θJA
(b) the maximum power that can be safely dissipated at an ambient temperature of 50°C (c) the junction temperature if the device is operating at TA = 25°C and is dissipating 1 W
Solution
(a) θJA = TJmax −TA0 = 150−25 =62.5°C/W PD0 2
(b) PDmax=TJmax−TA =150−50=1.6W θJA 62.5
(c) TJ =TA +θJAPD =25+62.5×1=87.5°C
Transistor Case and Heat Sink
θJA, can be expressed as
The thermal resistance between junction and ambience,
θJA =θJC +θCA (12.76)
where θJC is the thermal resistance between junction and transistor case (package) and θCA is the thermal resistance between case and ambience. For a given transistor, θJC is fixed by the device design and packaging. The device manufacturer can reduce θJC by encapsulating the device in a relatively large metal case, such as that in Fig. 12.35(a), and placing the collector (where most of the heat is dissipated) in direct contact with the case.
Although the circuit designer has no control over θJC (once a particular transistor has been selected), the designer can considerably reduce θCA below its free-air value (specified by the manufacturer as part of θJA). Reduction of θCA can be effected by providing means to facilitate heat transfer from case to ambience. A popular approach is to bolt the transistor to
the chassis or to an extended metal surface such as the heat sink shown in Fig. 12.36. Heat is easily conducted from the transistor case to the heat sink; that is, the thermal resistance θCS is usually very small. Also, heat is efficiently transferred (by convection and radiation) from the heat sink to the ambience, resulting in a low thermal resistance θSA. Thus, if a heat sink is utilized, the case-to-ambience thermal resistance given by
θCA =θCS +θSA (12.77)
can be small because its two components can be made small by the choice of an appropriate heat sink. For example, in very high-power applications the heat sink is usually equipped with fins that further facilitate cooling by radiation and convection.
The electrical analog of the thermal-conduction process when a heat sink is employed is shown in Fig. 12.43, from which we can write
TJ −TA =PD(θJC +θCS +θSA) (12.78)
As well as specifying θJC , the device manufacturer usually supplies a derating curve for PDmax versus the case temperature, TC . Such a curve is shown in Fig. 12.44. Note that the slope of the power-derating straight line is −1/θJC . For a given transistor, the maximum power dissipation at a case temperature TC0 (usually 25°C) is much greater than that at an ambient temperature
Figure 12.43 Electricalanalogofthethermal-conduction process when a heat sink is utilized.
Figure 12.44 Maximum allowable power dissipation versus transistor-case temperature.
12.10 Power Transistors 979
980 Chapter 12 Output Stages and Power Amplifiers
TA0 (usually 25°C, because θJC ≪ θJA ). If the device can be maintained at a case temperature
TC,TC0 ≤TC ≤TJmax,thenthemaximumsafepowerdissipationisobtainedwhenTJ =TJmax,
PDmax = TJmax −TC θJC
(12.79)
Example 12.8
A BJT is specified to have TJmax =150°C and to be capable of dissipating maximum power as follows: 40 W at TC = 25°C
2WatTA =25°C
Above 25°C, the maximum power dissipation is to be derated linearly with θJC =3.12°C/W and
θJA =62.5°C/W. Find the following:
(a) The maximum power that can be dissipated safely by this transistor when operated in free air at TA = 50°C.
(b) The maximum power that can be dissipated safely by this transistor when operated at an ambient temperature of 50°C, but with a heat sink for which θCS =0.5°C/W and θSA =4°C/W. Find the temperature of the case and of the heat sink.
(c) The maximum power that can be dissipated safely if an infinite heat sink is used and TA = 50°C.
Solution
(a)
(b) With a heat sink, θJA becomes
Thus,
θJA =θJC +θCS +θSA =3.12+0.5+4=7.62°C/W
PDmax = 150−50 =13.1 W 7.62
PDmax = TJmax −TA = 150−50 =1.6 W θJA 62.5
Figure 12.45 shows the thermal equivalent circuit with the various temperatures indicated.
(c) Aninfiniteheatsink,ifitexisted,wouldcausethecasetemperatureTC toequaltheambienttemperature TA. The infinite heat sink has θCA =0. Obviously, one cannot buy an infinite heat sink; nevertheless, this terminology is used by some manufacturers to describe the power-derating curve of Fig. 12.44.
The abscissa is then labeled TA and the curve is called “power dissipation versus ambient temperature with an infinite heat sink.” For our example, with infinite heat sink,
PDmax=TJmax−TA =150−50=32W θJC 3.12
Figure 12.45 Thermal equivalent circuit for Example 12.8.
The advantage of using a heat sink is clearly evident from Example 12.8: With a heat sink, the maximum allowable power dissipation increases from 1.6 W to 13.1 W. Also note that although the transistor considered can be called a “40-W transistor,” this level of power dissipation cannot be achieved in practice; that would require an infinite heat sink and an ambient temperature TA ≤ 25°C.
EXERCISE
12.21 The2N6306powertransistorisspecifiedtohaveTJmax=200°CandPDmax=125WforTC≤25°C. For TC ≥ 25°C, θJC = 1.4°C/W. If in a particular application this device is to dissipate 50 W and operate at an ambient temperature of 25°C, find the maximum thermal resistance of the heat sink that must be used (i.e., θSA ). Assume θCS = 0.6°C/W. What is the case temperature, TC ?
Ans. 1.5°C/W; 130°C
12.10 Power Transistors 981
982 Chapter 12 Output Stages and Power Amplifiers Summary
Output stages are classified according to the transistor conduction angle: class A (360°), class AB (slightly more than 180°), class B (180°), and class C (less than 180°).
The most common class A output stage is the emitter follower. It is biased at a current greater than the peak load current.
The class A output stage dissipates its maximum power under quiescent conditions (vO = 0). It achieves a maximum power-conversion efficiency of 25%.
The class B stage is biased at zero current, and thus dissipates no power in quiescence.
The class B stage can achieve a power-conversion efficiency as high as 78.5%. It dissipates its maximum powerforVˆo =(2/π)VCC.
The class B stage suffers from crossover distortion.
The class AB output stage is biased at a small current; thus both transistors conduct for small input signals, and crossover distortion is virtually eliminated.
Except for an additional small quiescent power dissipa- tion, the power relationships of the class AB stage are similar to those in class B.
To guard against the possibility of thermal runaway, the bias voltage of the class AB circuit is made to vary with temperatureinthesamemannerasdoesVBE oftheoutput transistors.
Use of the Darlington configuration in the class AB output stage reduces the base-current drive requirement. In integrated circuits, the compound pnp configuration is commonly used.
Output stages are usually equipped with circuitry that, in the event of a short circuit, can turn on and limit the base-current drive, and hence the emitter current, of the output transistors.
The classical CMOS class AB output stage suffers from reduced output signal swing. This problem can be overcome by replacing the source-follower output transistors with a pair of complementary devices operating in the common-source configuration.
The CMOS class AB output stage with common-source transistors allows the output voltage to swing to within an overdrive voltage from each of the two power supplies. Utilizing amplifiers in the feedback path of each of the output transistors reduces both the output resistance and the gain error of the stage.
IC power amplifiers consist of a small-signal voltage amplifier cascaded with a high-power output stage. Overall feedback is applied either on-chip or externally.
The bridge amplifier configuration provides, across a floating load, a peak-to-peak output voltage that is twice that possible from a single amplifier with a grounded load.
Class D amplifiers convert the audio signal into a pulsewidth-modulated (PWM) signal. The latter is then used to drive complementary MOS switches that supply the load with power. A low-pass filter is utilized to eliminate the high-frequency components introduced by the switching waveform. Power-conversion efficiences in the range of 85% to 90% are achieved.
MOSFETs have gained popularity over BJTs in the design of high-power output stages. This is due to their higher speed of operation and to the fact that they do not need a steady supply of gate currents, which allows the use of relatively simple driving circuitry.
The DMOS transistor is a short-channel power device capable of both high-current and high-voltage operation.
The drain current of a power MOSFET exhibits a positive temperature coefficient at low currents, and thus the device can suffer thermal runaway. At high currents the temperature coefficient of iD is negative.
To facilitate the removal of heat from the silicon chip, power devices are usually mounted on heat sinks. The maximum power that can be safely dissipated in the device is given by
PDmax =
TJmax −TA θJC +θCS +θSA
where TJmax and θJC are specified by the manufacturer, while θCS and θSA depend on the heat-sink design.
Computer Simulation Problems
Problems identified by the Multisim/PSpice icon are intended to demonstrate the value of using SPICE simulation to verify hand analysis and design, and to investigate important issues such as allowable signal swing and amplifier nonlinear distortion. Instructions to assist in setting up PSpice and Multisim simulations for all the indicated problems can be found in the corresponding files on the website. Note that if a particular parameter value is not specified in the problem statement, you are to make a reasonable assumption.
Section 12.2: Class A Output Stage
12.1 A class A emitter follower, biased using the circuit shown in Fig. 12.2, uses VCC =10 V, R = RL =1 k, with all transistors (including Q3 ) identical. Assume VBE = 0.7 V, VCE sat = 0.3 V, and β to be very large. For linear operation, what are the upper and lower limits of output voltage, and the corresponding inputs? How do these values change if the emitter–base junction area of Q3 is made twice as big as that of Q2? Half as big?
12.2 A source-follower circuit using NMOS transistors is constructed following the pattern shown in Fig. 12.2. All three transistors used are identical, with Vt = 0.5 V and μn Cox W/L = 20 mA/V2; VCC =2.5 V, R = RL =1 k. For linear operation, what are the upper and lower limits of the output voltage, and the corresponding inputs?
D 12.3 Using the follower configuration shown in Fig. 12.2 with ±5-V supplies, provide a design capable of ±3-V outputs with a 1-k load, using the smallest possible total supply current. You are provided with four identical, high-β BJTs and a resistor of your choice. Select a standard resistor value of 5% tolerance, and specify the maximum power drawn from the negative supply.
D 12.4 An emitter follower using the circuit of Fig. 12.2,
for which the output voltage range is ±5 V, is required using
variation in the emitter-follower transistor is no greater than a factor of 15, for load resistances as low as 100 . What is the value of R required? Find the incremental voltage gain of the resulting follower at vO =+5, 0, and –5 V, with a 100- load. What is the percentage change in gain over this range of vO?
*12.5 Consider the operation of the follower circuit of Fig. 12.2 for which RL = VCC /I , when driven by a square wave such that the output ranges from +VCC to −VCC (ignoring VCE sat ). For this situation, sketch the equivalent of Fig. 12.4 for vO, iC1, and pD1. Repeat for a square-wave output that has peak levels of ±VCC /2. What is the average power dissipation in Q1 in each case? Compare these results to those for sine wavesofpeakamplitudeVCC andVCC/2,respectively.
V = 10 V. The circuit is to be designed such that the current
CC t
average power loss in the current-source transistor Q2.
12.7 Reconsider the situation described in Exercise 12.3 for variation in VCC —specifically for VCC = 16 V, 12 V, 10 V, and 8 V. Assume VCE sat is nearly zero. What is the power-conversion efficiency in each case?
D 12.8 The emitter-follower output stage of Fig. 12.2 is designed to provide a maximum output swing of ±Vˆ volts, across the load RL. Neglecting the saturation voltage, what are the minimum required values of VCC and I? Now, if the output voltage is a sine wave of peak amplitude (Vˆ /2), what is the power-conversion efficiency realized?
Section 12.3: Class B Output Stage
12.9 Consider the circuit of a complementary-BJT class B output stage. For what amplitude of input signal does the crossover distortion represent a 10% loss in peak amplitude?
12.10 Consider the feedback configuration with a class B
output stage shown in Fig. 12.9. Let the amplifier gain A0 =
100 V/V. Derive an expression for v versus v , assuming that OI
VBE = 0.7 V. Sketch the transfer characteristic vO versus vI , and compare it with that without feedback.
PROBLEMS
12.6 Consider the situation described in Problem 12.5. For square-wave outputs having ±V levels and ± 1 V levels,
CC 2 CC
and for sine waves of the same peak-to-peak values, find the
12.11 Consider the class B output stage, using MOSFETs, shown in Fig. P12.11. Let the devices have V = 0.5 V and μCox W/L = 2 mA/V2 . With a 10-kHz sine-wave input of 5-V peak and a high value of load resistance, what peak output would you expect? What fraction of the sine-wave period does the crossover interval represent? For what value of load resistor is the peak output voltage reduced to half the input?
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
984 Chapter 12 5 V
Output Stages and Power Amplifiers
5 V Figure P12.11
RL and employing power supplies ±VSS. Neglecting the effectsoffiniteVBE andVCEsat,determinetheloadpower,the supply power, the power-conversion efficiency, the maximum attainable power-conversion efficiency and the corresponding value of Vˆo, and the maximum available load power. Also find the value of Vˆo at which the power dissipation in the transistors reaches its peak, and the corresponding value of power-conversion efficiency.
12.16 Sketchagraphforthesmall-signalvoltagegainofthe class B circuit of Fig. 12.5 as a function of vI , for vI both positive and negative.
Section 12.4: Class AB Output Stage
12.17 A class AB output stage, such as that in Fig. 12.11, utilizing transistors with IS = 10−14 A, is biased at a quiescent current IQ = 1 mA. Find VBB, the output resistance Rout at vI = 0, and the corresponding small-signal voltage gain. The load resistance RL = 100 . What does the incremental gain become when vO = 10 V?
D 12.18 Design the quiescent current of a class AB BJT output stage so that the incremental voltage gain for vI in the vicinity of the origin is in excess of 0.97 V/V for loads larger than 100 . Assume that the BJTs have VBE of 0.7 V at a current of 100 mA and determine the value of VBB required.
D 12.19 A class AB output stage, such as that in Fig. 12.11, drivesaloadresistanceRL of100.WhatbiascurrentIQ will serve to limit the variation in the small-signal voltage gain to 5%asiL changesfrom0to50mA?
12.20 For the class AB output stage considered in Exam- ple 12.3, add two columns to the table of results as follows: the totalinputcurrentdrawnfromvI (iI,mA);andthelarge-signal input resistance Rin ≡vI /iI . Assume βN =βP =β =49. Com- parethevaluesofRin totheapproximatevalueobtainedusing the resistance-reflection rule, Rin ≃ βRL.
12.21 In this problem we investigate an important trade-off in the design of the class AB output stage of Fig. 12.11: Increasing the quiescent current IQ reduces the nonlinearity of the transfer characteristic at the expense of increased quiescent power dissipation. As a measure of nonlinearity, we use the maximum deviation of the stage incremental gain, which occurs at vO = 0, namely,
e= 1−vo/vivO=0
CHAPTER 12 PROBLEMS
12.12 Consider the complementary-BJT class B output stage and neglect the effects of finite VBE and VCE sat . For ±10-V power supplies and an 8- load resistance, what is the maximum sine-wave output power available? What supply power corresponds? What is the power-conversion efficiency? For output signals of half this amplitude, find the output power, the supply power, and the power-conversion efficiency.
D 12.13 A class B output stage operates from ±10-V supplies. Assuming relatively ideal transistors, what is the output voltage for maximum power-conversion efficiency? What is the output voltage for maximum device dissipation? If each of the output devices is individually rated for 2-W dissipation, and a factor-of-2 safety margin is to be used, what is the smallest value of load resistance that can be tolerated, if operation is always at full output voltage? If operation is allowed at half the full output voltage, what is the smallest load permitted? What is the greatest possible output power available in each case?
D 12.14 A class B output stage is required to deliver an average power of 50 W into an 8- load. The power supply should be 4 V greater than the corresponding peak sine-wave output voltage. Determine the power-supply voltage required (to the nearest volt in the appropriate direction), the peak current from each supply, the total supply power, and the power-conversion efficiency. Also, determine the maximum possible power dissipation in each transistor for a sine-wave input.
12.15 Consider the class B BJT output stage with a square-wave output voltage of amplitude Vˆo across a load
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
CHAPTER 12 PROBLEMS
(a) Show that e is given by
e= R +V /2I
output stage in Fig. 12.14. To simplify matters, assume the small-signal resistances of D1 and D2 to be negligibly small. Replace each of QN and QP with its hybrid-π model and neglect ro. Hence show that the class AB stage is equivalent, from a small-signal point of view, to an emitter-follower transistor whose rπ = rπN ∥rπP and gm = gmN +gmP, and hence re =reN∥reP andβ=(gmN +gmP)(rπN∥rπP).Nowshowthat
VT /2IQ LTQ
Problems 985
which for 2IQ RL ≫ VT can be approximated by e≃VT/2IQRL
(b) Ifthestageisoperatedfrompowersuppliesof±VCC,find the quiescent power dissipation, PD .
(c) Show that for given VCC and RL, the product of the quiescent power dissipation and the gain error is a constant given by
eP≃V VCC DTR
L
(d) For VCC = 10 V and RL = 100 , find the required values
ofPD andIQ ifeistobe5%,2%,and1%.
*12.22 A class AB output stage, resembling that in
Fig. 12.11 but utilizing a single supply of +10 V and biased
at V = 6 V, is capacitively coupled to a 100- load. For I
transistors for which VBE = 0.7 V at 1 mA and for a bias voltage VBB = 1.4 V, what quiescent current results? For a step change in output from 0 to –1 V, what input step is required? Assuming transistor-saturation voltages of zero, find the largest possible positive-going and negative-going steps at the output.
Section 12.5: Biasing the Class AB Circuit
D 12.23 Consider the diode-biased class AB circuit of Fig. 12.14. For IBIAS = 200 μA, find the relative size (n) that should be used for the output devices (in comparison to the biasing devices) to ensure that an output resistance of 8 or less is obtained in the quiescent state. Neglect the resistance of the biasing diodes.
D*12.24 A class AB output stage using a two-diode bias
network as shown in Fig. 12.14 utilizes diodes having the
same junction area as the output transistors. For V = 10 V, CC
IBIAS=1mA,RL=100,βN=50,and VCEsat =0V,whatis the quiescent current? What are the largest possible positive and negative output signal levels? To achieve a positive peak output level equal to the negative peak level, what value of βN is needed if IBIAS is not changed? What value of IBIAS is needed if βN is held at 50? For this value, what does IQ become?
D 12.25 It is required to evaluate the small-signal input resistance and small-signal voltage gain of the class AB
and
vo= RL
vi RL +(reN ∥reP)
R ≃β[R +(r ∥r )] in L eN eP
12.26 Figure P12.26 shows a class AB output stage with a common-emitter transistor added to increase the voltage gain and reduce the current that vI has to supply. Neglecting the small-signal resistances of D1 and D2, find the small-signal voltage gain vo /vi . (Hint: Use the expressions for voltage gain and input resistance of the class AB stage without Q3, given in the statement for Problem 12.25.)
IBIAS
D1 D2
VCC
QN
QP
VCC
vO
RL
vI
Q3
Figure P12.26
12.27 It is required to find an expression for the output resistance Rout of the class AB output stage in Fig. P12.26. Toward that end, neglect the small-signal resistance of each of D1 and D2 and assume the current source supplying IBIAS has an
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986 Chapter 12 Output Stages and Power Amplifiers
output resistance RBIAS . Transistors QN and QP are equivalent to a single transistor with rπ = rπN ∥rπP, re = reN ∥reP, and gm =gmN +gmP.
**12.28 A class AB output stage using a two-diode bias
network as shown in Fig. 12.14 utilizes diodes having the
same junction area as the output transistors. At a room
R2 +(R1∥rπ) r = 1 + gm (R1 ∥ rπ )
Evaluate r for the case R1 = R2 = 1.2 k, with the transistor operating at IC = 1 mA and having β = 100.
Section 12.6: Variations on the Class AB Configuration
12.32 Use the results given in the answer to Exercise 12.9 to determine the input current of the circuit in Fig. 12.17 for v I = 0 and ±10 V with infinite and 100- loads.
12.33 For the circuit in Fig 12.17, operated near vI = 0 and fed with a signal source having zero resistance, show that the output resistance is given by
1 Rout=2R3+re3+R1∥re1 /β3+1
Assume that the top and bottom halves of the circuit are perfectly matched.
D ***12.34 Consider the circuit of Fig. 12.17 in which Q1
and Q2 are matched, and Q3 and Q4 are matched but have
three times the junction area of the others. Resistors R3 and
R4 also are matched. For VCC = 10 V, find values for resistors
R1 through R4 that allow for a base current of at least 10 mA
in Q3 (and Q4) at vI =+5V (vI = −5V), when a load
demands it, with at most a 2-to-1 variation in currents in
Q1 (and Q2). The quiescent current in Q3 is to be 40 mA.
Let β1,2 ≥ 150 and β3,4 ≥ 50. For input voltages around
0 V, estimate the output resistance of the overall follower
driven by a source having zero resistance. For an input
temperature of about 20°C the quiescent current is 1 mA and
V = 0.6 V. Through a manufacturing error, the thermal BE
coupling between the output transistors and the biasing diode-connected transistors is omitted. After some output activity, the output devices heat up to 70°C while the biasing devices remain at 20°C. Thus, while the VBE of each device remains unchanged, the quiescent current in the output devices increases. To calculate the new current value, recallthattherearetwoeffects:IS increasesbyabout14%/°C and VT = k T /q changes, where T = 273° + temperature in °C, and VT = 25 mV only at 20°C. However, you may assume thatβN remainsalmostconstant.Thisassumptionisbasedon the fact that β increases with temperature but decreases with current. What is the new value of IQ? If the power supply is ±20 V, what additional power is dissipated? If thermal runaway occurs, and the temperature of the output transistors increases by 10°C for every watt of additional power dissipation, what additional temperature rise and current increase result?
D 12.29 Repeat Example 12.5 for the situation in which the peak positive output current is 250 mA. Use the same general approach to safety margins. What are the values of R1 and R2 you have chosen?
**12.30 A VBE multiplier is designed with equal resistances for nominal operation at a terminal current of 1 mA, with half the current flowing in the bias network. The initial design is based on β = ∞ and VBE =0.7 V at 1 mA.
(a) Find the required resistor values and the terminal voltage.
(b) Find the terminal voltage that results when the terminal
current increases to 2 mA. Assume β = ∞.
(c) Repeat (b) for the case the terminal current becomes
10 mA.
(d) Repeat (c) using the more realistic value of β = 100.
*12.31 By replacing the transistor in the VBE multiplier by its hybrid-π, small-signal model (with ro neglected), show that the incremental resistance between the two terminals of the multiplier is given by
voltage of +1 V and a load resistance of 2 , what output
CHAPTER 12 PROBLEMS
voltage results? Q and Q have V of 0.7 V at a current 1 2 BE
of 10 mA.
12.35 Figure P12.35 shows a variant of the class AB circuit of Fig. 12.17. Assume that all four transistors are matched and have β = 100.
(a) For vI = 0, find the quiescent current in Q3 and Q4, the input current iI , and the output voltage v O .
(b) Since the circuit has perfect symmetry, the small-signal performance around v I = 0 can be determined by con- sidering either the top or bottom half of the circuit only. In this case, the load on the half-circuit must be 2RL , the input resistance found is 2Rin , and the output resistance
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
found is 2Rout. Using this approach, find Rin, vo/vi, and Rout (assumingthatthecircuitisfedwithazero-resistance source).
(b) (c)
Problems 987 Find the small-signal current ic that results from an input
signal vi, and hence find the voltage gain vo/vi. Find the input resistance Rin .
CHAPTER 12 PROBLEMS
VCC 1 mA
Q1
iI VCC
Q3
2 M
5 V
2 k
Q1 ic Q2
vo
vi
vI
V CC
vO RL 200
Q
Rin
Figure P12.37
2
Q4 1 mA
VCC
**12.38 The BJTs in the circuit of Fig. P12.38 have
β =10,β =100,V =0.7V,andV =100V. P N BE A
Figure P12.35
(a) (b)
(c)
Find the dc collector current of each transistor and the value of VC .
Replacing each BJT with its hybrid-π model, show that
vo ≃g r ∥β (r ∥R) v m1 o1 N o2 f
i
Find the values of vo/vi and Rin.
12.36 For the Darlington configuration shown in Fig. 12.18, showthatforβ1 ≫1andβ2 ≫1:
(a) Theequivalentcompositetransistorhasβ≃β1β2.
(b) IfthecompositetransistorisoperatedatacurrentIC,then Q2 will be operating at a collector current approximately equaltoIC,andQ1 willbeoperatingatacollectorcurrent
approximately equal to IC /β2 .
(c) The composite transistor has a base–emitter voltage
VBE ≃2VT ln IC/IS −VT ln β2 ,whereIS isthesaturation
current of each of Q1 and Q2.
(d) The composite transistor has an equivalent r ≃
π
2β1β2 VT/IC .
(e) The composite transistor has an equivalent g ≃
m
*12.37 ForthecircuitinFig.P12.37inwhichthetransistors haveVBE =0.7Vandβ=100:
(a) Find the dc collector current for each of Q1 and Q2 .
1 I /V . 2CT
Figure P12.38
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988 Chapter 12 Output Stages and Power Amplifiers
D **12.39 Consider the compound-transistor class AB out- put stage shown in Fig. 12.20 in which Q2 and Q4 are matched transistorswithVBE =0.7Vat10mAandβ=100,Q1 andQ5 have VBE = 0.7 V at 1-mA currents and β = 100, and Q3 has VEB = 0.7 V at a 1-mA current and β = 10. Design the circuit foraquiescentcurrentof2mAinQ2 andQ4,IBIAS thatis100 times the standby base current in Q1, and a current in Q5 that is nine times that in the associated resistors. Find the values of the input voltage required to produce outputs of ±10 V for a1-kload.UseVCC of15V.
*12.40 Figure P12.40 shows a variant on the class AB amplifier known as class G. Here, in addition to the
the threshold value, Q3 is turned off and D1 turns on, thus connecting Q1 to its normal supply VCC 1 . A similar process happens in the negative direction, with D2 and Q4 taking the placeofD1 andQ3.LetVCC1 =35 V,VCC2 =70 V,VZ1 =3.3 V, and the voltage of the VBE multiplier VBB = 1.2 V.
(a) Find the positive threshold value of vI at which Q3 is turned on.
(b) If for 95% of the time vI is in the vicinity of 30V and only 5% of the time it is in the vicinity of 65 V, use Eq. (12.19) to estimate the average power dissipated in the transistors, PD. Compare to the value of PD dissipated in a class AB stage operated from a ±70 V supply.
12.41 Repeat Exercise 12.11 for a design variation in which transistor Q5 is increased in size by a factor of 20, all other conditions remaining the same.
12.42 Repeat Exercise 12.11 for a design in which the limiting output current and normal peak current are 100 mA and 75 mA, respectively.
D 12.43 The circuit shown in Fig. P12.43 operates in a manner analogous to that in Fig. 12.21 to limit the output
IBIAS
Figure P12.43
current from Q3 in the event of a short circuit or other mishap. It has the advantage that the current-sensing resistor R does
CHAPTER 12 PROBLEMS
VCC 2 IBIAS
Z1
Z2
IBIAS
VCC 2
Q3
VCC1
R2 R1
Q5
D1 Q1
Q2
D2 Q4
vO
–VCC1
RL
vI
Figure P12.40
normal power supply ±VCC1, the circuit is equipped with a highervoltagesupply±VCC2.Thelattersupplyisutilizedonly infrequently. The circuit operates as follows. Normally, D1 andD2 areturnedonandthusconnectthe±VCC1 supplytothe classABstagetransistorsQ1 andQ2.Simultaneously,Q3 and Q4 are off. For vI positive and exceeding a certain threshold, Q3 turns on, D1 turns off, and Q1 is then effectively operating from the higher voltage supply VCC2. This continues as long as vI is larger than the specified threshold. As vI decreases below
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CHAPTER 12 PROBLEMS
not appear directly at the output. Find the value of R that causes Q5 to turn on and absorb all of IBIAS = 2 mA, when the current being sourced reaches 100 mA. For Q5 , IS = 10−14 A. If the normal peak output current is 75 mA, find the voltage drop across R and the collector current in Q5.
D 12.44 Consider the thermal shutdown circuit shown in Fig. 12.22. At 25°C, Z1 is a 6.8-V zener diode with a TC of 2 mV/°C, and Q1 and Q2 are BJTs that display VBE of 0.7 V at a current of 100 μA and have a TC of –2 mV/°C. Design the circuit so that at 125°C, a current of 200 μA flows in each of Q1 and Q2. What is the current in Q2 at 25°C?
Section 12.7: CMOS Class AB Output Stages
D 12.45 (a) Show that for the class AB circuit in Fig. 12.23, the small-signal output resistance in the quiescent state is given by
Rout ≃ 1
gmn +gmp
(a) Specify the W/L ratio for each of the four transistors.
(b) In the quiescent state with vO = 0, what must vI be?
(c) If QN is required to supply a maximum load current
of 10 mA, find the maximum allowable output voltage. Assume that the transistor supplying IBIAS needs a minimum of 0.2 V to operate properly.
D 12.48 Consider the design of the class AB output stage of Fig. 12.23 for the following conditions. The stage is operated from ±2.5-V power supplies and is required to provide a minimum output voltage swing of ±1.5 V while supplying a maximum current equal to 10 times the quiescent current IQ. Assume that QN and QP are matched and Q1 and Q2 are matched, that all devices have |Vt | = 0.5 V, and that in the quiescent state all transistors are operated at the same overdrive voltage. What is the value of VOV required, and what VGG is needed?
12.49 The class AB output stage in Fig. 12.24 utilizes two matched transistors with k = k = 200 mA/V2 and is operated
np
from ±2.5-V power supplies. If the stage is required to supply a maximum current of ±20 mA, what is the output voltage swing realized?
12.50 For the CMOS output stage of Fig. 12.25 with I = Q
2mA, VOV =0.2V for each of QP and QN at the quiescent point, and μ = 5, find the output resistance at the quiescent point.
which for matched devices becomes Rout = 1
Problems 989
2gm
(b) For a circuit that utilizes MOSFETs with V = 0.5 V and
t
k′(W/L) = 200 mA/V2, find the voltage VGG that results in
R =20.Also,findI . out Q
D 12.46 (a) For the circuit in Fig. 12.23 in which Q1 and Q2 are matched, QN and QP are matched, and all devices have the same |Vt |, show that the small-signal voltage gain at the quiescent condition is given by
vo RL
v = R +2/g
where gm is the transconductance of each of QN and QP and where channel-length modulation is neglected. (b)ForthecaseIBIAS =0.2mA,RL =1k,kn =kp =nk1 = nk2 , where k = μCox (W/L), and k1 = 20 mA/V2 , find the ratio n that results in an incremental gain of 0.98. Also find the quiescent current IQ.
D 12.47 Design the circuit of Fig. 12.23 to operate at I
QP OQL
12.51
(a) Show that for the CMOS output stage of Fig. 12.25, |Gain error| = Rout
RL
iLm
= 1 mA with IBIAS = 0.1 mA. Let μnCox = 250 μA/V2, μpCox =100μA/V2,Vtn=−Vtp=0.45V,andVDD = VSS = 2.5 V. Design so that Q1 and Q2 are matched and QN and QP are matched, and that in the quiescent state each operates at an overdrive voltage of 0.15 V.
that one of the transistors turns off when iL
reaches 4IQ.
(b) For a stage that drives a load resistance of 100 with a gain error of less than 3%, find the overdrive voltage at which QP andQN shouldbeoperated.LetIQ =2.5mAandμ=5.
12.52 Show that in the CMOS class AB common-source output stage (Fig. 12.25), Q turns off when v = 4I R and
NOQL
Q turns off when v = −4I R . This is equivalent to saying
D *12.53 It is required to design the circuit of Fig. 12.25 to drive a load resistance of 50 while exhibiting an output resistance, around the quiescent point, of 2.5 .
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
990 Chapter 12 Output Stages and Power Amplifiers Operate Q and Q at I =1.5mA and V =0.15 V. The
employing BJTs for biasing and in the driver stage. The latter consists of complementary Darlington emitter followers formed by Q1 through Q4 and has the low output resistance necessary for driving the output MOSFETs at high speeds. Of special interest is the bias circuit utilizing two VBE multipliersformedbyQ5 andQ6 andtheirassociatedresistors. Transistor Q6 is placed in direct thermal contact with the output transistors and thus has the same temperature as that ofQN andQP.
(a) Show that VGG is given by RR
NPQ OV
technology utilized is specified to have kn′ = 250 μA/V2 ,
kp′ = 100 μA/V2 , Vtn = − Vtp = 0.5 V, and VDD = VSS = 2.5 V.
(a) Specify (W/L) for each of QN and QP.
(b) Specify the required value of μ.
(c) What is the expected error in the stage gain?
(d) Inthequiescentstate,whatdcvoltagemustappearatthe
output of each of the error amplifiers?
(e) At what value of positive vO will QP be supplying all the
load current? Repeat for negative vO and QN supplying
all the load current.
(f) What is the linear range of v ?
VGG = 1+ 3 VBE6+ 1+ 1 VBE5−4VBE O R4R2
CHAPTER 12 PROBLEMS
*12.54 Figure P12.54 shows a class AB output stage uti-
lizing a pair of complementary MOSFETs (QN , QP ) and show that
(b) NotingthatVBE6 isthermallycoupledtotheoutputdevices while the other BJTs remain at constant temperature,
IBIAS
Figure P12.54
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
∂V R∂V GG = 1+ 3 BE6
∂T R4 ∂T
(c) To keep the overdrive voltages of QN and QP, and hence their quiescent current, constant with temperature variation, ∂VGG/∂T is made equal to ∂(VtN + VtP)/∂T. Find R3/R4 that provides this temperature stabiliza- tion when |Vt| changes by −3mV/◦C and ∂VBE/∂T= − 2 mV/◦ C.
(d) Using the value of R3/R4 found in (c) and assuming that thenominalvalueofVBE is0.7VandthattheMOSFETs have |Vt| = 3 V and μCox(W/L) = 2 A/V2, find |VGS|, VGG , R, and R1 /R2 to establish a quiescent current of 100 mA in the output transistors and 20 mA in the driver stage.
Section 12.8: IC Power Amplifiers
D 12.55 In the power-amplifier circuit of Fig. 12.29, two
resistors are important in controlling the overall voltage gain.
Which are they? Which controls the gain alone? Which affects
both the dc output level and the gain? A new design is being
considered in which the output dc level is approximately 2 V 3S
(rather than approximately 1 V ) with a gain of 50 (as before). 2S
What changes are needed?
12.56 Consider the front end of the circuit in Fig. 12.29.
For VS=22V, calculate approximate values for the bias
currents in Q through Q . Assume β = 100, β = 20, and 1 6 npn pnp
VBE = 0.7 V. Also find the dc voltage at the output.
D 12.57 It is required to use the LM380 power amplifier to drive an 8- loudspeaker while limiting the maximum possible device dissipation to 2 W. Use the graph of Fig. 12.31 to determine the maximum possible power-supply voltage that can be used. (Use only the given graphs; do not interpolate.) If the maximum allowed THD is to be 3%, what is the maximum possible load power? To deliver this power to the load what peak-to-peak output sinusoidal voltage is required?
12.58 For the circuit in Fig. P12.58, assuming all transistors to have large β, show that iO = vI /R. [This voltage-to-current converter is an application of a versatile circuit building block known as the current conveyor; see Sedra and Roberts (1990).] For β = 100, by what approximate percentage is iO actually lower than this ideal value?
Figure P12.58
D 12.59 For the bridge amplifier of Fig. 12.32, let R1 = R3 = 10 k. Find R2 and R4 to obtain an overall gain of 8 V/V.
D 12.60 An alternative bridge amplifier configuration, with high input resistance, is shown in Fig. P12.60. [Note the similarity of this circuit to the front end of the instrumentation amplifier circuit shown in Fig. 2.20(b).] What is the gain vO/vI? For op amps (using ±15-V supplies) that limit at ±13 V, what is the largest sine wave you can provide across RL ? Using 1 k as the smallest resistor, find resistor values that make v O /v I = 8 V/V. Make sure that the signals at the outputs of the two amplifiers are complementary.
Figure P12.60
Problems 991
CHAPTER 12 PROBLEMS
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
992 Chapter 12 Output Stages and Power Amplifiers Section 12.9 Class D Power Amplifiers
12.61 Sketch diagrams resembling those in Figs. 12.33(a), (b). Let vT have ±10 V peaks and assume vA is a sine wave with 5-V peak amplitude. Let the frequency of vT be 5 times that of vA. The comparator output levels are ±10 V.
12.62 A pulse waveform swinging between ±10 V has a duty ratio of 0.65. What is its average value? If the duty ratio is changed to 0.35, what does the average value become?
12.63 For the circuit in Fig. 12.34(b):
(a) If vA is a sine wave, what is the maximum power supplied
to a load of resistance R, in terms of VDD?
(b) The power loss is mostly due to the repeated charging
and discharging of a capacitance C across the load. It can
be shown that this switching power is given by 4f C V 2 . s DD
Find an expression for the power-conversion efficiency η and evaluate the value of η for the case fs = 250 kHz and C = 1000 pF.
Section 12.10 Power Transistors
12.64 A power MOSFET is specified to have IDmax = 5 A, VDSmax =50V,andPDmax =50W.
(a) Sketch the SOA boundaries.
(b) If the MOSFET is used in the common-source configu- ration as shown in Fig. P12.64, show that the maximum current occurs when VDS = 0, the maximum VDS occurs when ID = 0, and the maximum power dissipation occurs whenVDS =VDD/2.
(c) For VDD = 40 V, find the smallest resistance R for which the operating point is always within the SOA. What are the corresponding values of IDmax and PDmax?
(d) Repeat (c) for VDD = 30 V.
(e) Repeat (c) for VDD = 15 V.
VDD
ID R
VGS
VGS
Figure P12.64
CHAPTER 12 PROBLEMS
D 12.65 A particular transistor having a thermal resistance θJA = 2.5°C/W is operating at an ambient temperature of 30°C with a collector–emitter voltage of 20 V. If long life requires a maximum junction temperature of 130°C, what is the corresponding device power rating? What is the greatest average collector current that should be considered?
12.66 A particular transistor has a power rating at 25°C of 10 W, and a maximum junction temperature of 150°C. What is its thermal resistance? What is its power rating when operated at an ambient temperature of 50°C? What is its junction temperature when dissipating 5 W at an ambient temperature of 50°C?
12.67 A power transistor operating at an ambient tempera- ture of 50°C, and an average emitter current of 3 A, dissipates 20 W. If the thermal resistance of the transistor is known to be less than 3°C/W, what is the highest junction temperature you would expect? If the transistor VBE measured using a pulsed emitter current of 3 A at a junction temperature of
25°C is 0.80 V, what average V
normal operating conditions? (Use a temperature coefficient of –2 mV/°C.)
12.68 For a particular application of the transistor specified in Example 12.7, extreme reliability is essential. To improve reliability, the maximum junction temperature is to be limited to 100°C. What are the consequences of this decision for the conditions specified?
BE
would you expect under
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
12.69 A power transistor is specified to have a maximum junction temperature of 150°C. When the device is operated at this junction temperature with a heat sink, the case temperature is found to be 97°C. The case is attached to the heat sink with a bond having a thermal resistance θCS =0.5°C/W and the thermal resistance of the heat sink θSA =0.1°C/W. If the ambient temperature is 25°C, what is the power being dissipated in the device? What is the thermal resistance of the device, θJC , from junction to case?
12.70 A power transistor for which TJ max = 180°C can dissipate 50 W at a case temperature of 30°C. If it is connected to a heat sink using an insulating washer for which the thermal resistance is 0.6°C/W, what heat-sink temperature is necessary to ensure safe operation at 30 W? For an ambient temperature of 27°C, what heat-sink thermal resistance is required? If, for a particular extruded-aluminum-finned heat sink, the thermal resistance in still air is 6°C/W per centimeter of length, how long a heat sink is needed?
Problems 993
CHAPTER 12 PROBLEMS
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
CHAPTER 13
Operational-Amplifier Circuits
Introduction 995 13.4
13.1 The Two-Stage CMOS Op Amp 996
13.2 The Folded-Cascode CMOS Op Amp 1016
13.3 The 741 BJT Op Amp 1028
Modern Techniques for the Design of BJTOpAmps 1054
Summary 1073 Problems 1074
IN THIS CHAPTER YOU WILL LEARN
1. The design and analysis of the two basic CMOS op-amp architectures: the two-stage circuit and the single-stage, folded-cascode circuit.
2. The complete circuit of an analog IC classic: the 741 BJT op amp. Though over 40 years old, the 741 circuit includes so many interesting and useful design techniques that its study is still a must.
3. Interesting and useful applications of negative feedback within op-amp circuits to achieve bias stability and increased CMRR.
4. How to break a large analog circuit into its recognizable blocks to be able to make the analysis amenable to a pencil-and-paper approach, which is the best way to learn design.
5. Some of the modern techniques employed in the design of low-voltage, single-supply BJT op amps.
6. Most important, how the different topics we studied in the preceding chapters come together in the design of the most important analog IC, the op amp.
Introduction
In this chapter, we shall study the internal circuitry of the most important analog IC, namely, the operational amplifier. The terminal characteristics and some circuit applications of op amps were covered in Chapter 2. Here, our objective is to expose the reader to some of the ingenious techniques that have evolved over the years for combining elementary analog circuit building blocks to realize a complete op amp. We shall study both CMOS and bipolar op amps.
The CMOS op-amp circuits considered find application primarily in the design of analog and mixed-signal VLSI circuits. Because these op amps are usually designed with a specific application in mind, they can be optimized to meet a subset of the list of desired specifications, such as high dc gain, wide bandwidth, or large output-signal swing. For instance, many CMOS op amps are utilized within an IC and do not connect to the outside terminals of the chip. As a result, the loads on their outputs are usually limited to small capacitances of at most a few picofarads. Internal CMOS op amps therefore do not need to have low output resistances, and their design rarely incorporates an output stage. Also, if the op-amp input terminals are not connected to the chip terminals, there will be no danger of static charge damaging the gate oxide of the input MOSFETs. Hence, internal CMOS op amps do not need input
995
996 Chapter 13
Operational-Amplifier Circuits
clamping diodes for gate protection and thus do not suffer from the leakage effects of such diodes. In other words, the advantage of near-infinite input resistance of the MOSFET is fully realized.
While CMOS op amps are extensively used in the design of VLSI systems, the BJT remains the device of choice in the design of general-purpose op amps. These are op amps that are utilized in a wide variety of applications and are designed to fit a wide range of specifications. As a result, the circuit of a general-purpose op amp represents a compromise among many performance parameters. We shall study in detail one such circuit, the 741-type op amp. Although the 741 has been available for over 40 years, its internal circuit remains as relevant and interesting today as it ever was. Nevertheless, changes in technology have introduced new requirements, such as the need for general-purpose op amps that operate from a single power supply of only 2 V to 3 V. These new requirements have given rise to exciting challenges to op-amp designers. The result has been a wealth of new ideas and design techniques. We shall present a sample of these modern design techniques in the last section.
In addition to exposing the reader to some of the ideas that make analog IC design such an exciting topic, this chapter should serve to tie together many of the concepts and methods studied thus far.
THE GENIE OF ANALOG:
The need for precision in analog ICs supported a generation of highly skilled circuit and process engineers. Their creative approaches to overcoming the limitations of available technology led to celebrity status among their peers. Perhaps most famous of all was Robert Widlar, who teamed with process engineer Dave Talbert to bootstrap the analog business in the 1960s with highly successful designs for Fairchild and National Semiconductor. Widlar’s pranks, including threatening to cut through bureaucracy with an axe, and buying a sheep to trim National’s unkempt lawns, remain Silicon Valley legends.
Robert John Widlar was already a legendary chip designer at age 33 (but died at 53), and a pioneer of linear analog integrated-circuit design: the creator of the Widlar current source, the Widlar bandgap voltage reference, the Widlar output stage, and a host of op-amp designs, including the first mass-produced operational amplifier ICs (Fairchild μA702, μA709), the first integrated voltage regulator (μA723, National LM100), the first fully internally compensated operational amplifier (LM101), the field-effect input (LM101A), and the super-beta input (LM108). Each of Widlar’s designs became a product champion in its class, undoubtedly because they all had at least one feature that was far ahead of the crowd.
The Two-Stage CMOS Op Amp
13.1
The first op-amp circuit we shall study is the two-stage CMOS topology shown in Fig. 13.1. This simple but elegant circuit has become a classic and is used in a variety of forms in the design of VLSI systems. We have already studied this circuit in Section 9.6.1 as an example of a multistage CMOS amplifier. We urge the reader to review Section 9.6.1 before proceeding further. Here, our detailed study will emphasize the performance characteristics of the circuit and the trade-offs involved in its design.
13.1 The Two-Stage CMOS Op Amp 997
I
CC
Figure 13.1 The basic two-stage CMOS op-amp configuration.
13.1.1 The Circuit
The circuit consists of two gain stages: The first stage is formed by the differential pair Q1 –Q2 together with its current-mirror load Q3 –Q4 . This differential-amplifier circuit, studied in detail in Section 9.5, provides a voltage gain that is typically in the range of 20 V/V to 60 V/V, as well as performing conversion from differential to single-ended form while providing a reasonably high common-mode rejection ratio (CMRR).
The differential pair is biased by current source Q5 , which is one of the two output transistors of the current mirror formed by Q8 , Q5 , and Q7 . The current mirror is fed by a reference current IREF, which can be generated by simply connecting a precision resistor (external to the chip) to the negative supply voltage –VSS or to a more precise negative voltage reference if one is available in the same integrated circuit. Alternatively, for applications with more stringent requirements,IREF canbegeneratedusingacircuitsuchasthatstudiedlaterinthissection(see Fig. 13.8).
The second gain stage consists of the common-source transistor Q6 and its current-source load Q7 . The second stage typically provides a gain of 50 V/V to 80 V/V. In addition, it takes part in the process of frequency compensating the op amp. From Section 11.10 the reader will recall that to guarantee that the op amp will operate in a stable fashion (as opposed to oscillating) when negative feedback of various amounts is applied, the open-loop gain is made to roll off with frequency at the uniform rate of –20 dB/decade. This in turn is achieved by introducing a pole at a relatively low frequency and arranging for it to dominate the frequency-response determination. In the circuit we are studying, this is implemented using acompensationcapacitanceCC connectedinthenegative-feedbackpathofthesecond-stage amplifyingtransistorQ6.Aswillbeseen,CC (togetherwiththemuchsmallercapacitanceCgd6 across it) is Miller-multiplied by the gain of the second stage, and the resulting capacitance at the input of the second stage interacts with the total resistance there to provide the required dominant pole (more on this later).
998 Chapter 13
Operational-Amplifier Circuits
Unless properly designed, the CMOS op-amp circuit of Fig. 13.1 can exhibit a systematic output dc offset voltage. This point was discussed in Section 9.6.1, where it was found that the systematic dc offset can be eliminated by sizing the transistors so as to satisfy the following constraint:
(W/L)6 =2(W/L)7 (13.1) (W/L)4 (W/L)5
Finally, we observe that the CMOS op-amp circuit of Fig. 13.1 does not have an output stage. This is because it is usually required to drive only small on-chip capacitive loads.1
13.1.2 Input Common-Mode Range and Output Swing
Refer to Fig. 13.1 and consider the situation when the two input terminals are tied together
andconnectedtoavoltageVICM.ThelowestvalueofVICM hastobesufficientlylargetokeep
Q andQ insaturation.Thus,thelowestvalueofV shouldnotbelowerthanthevoltage 1 2 ICM
atthedrainofQ1 (−VSS+VGS3 =–VSS+Vtn+VOV3)bymorethan Vtp ,thus
V ≥−V+V+V −V (13.2)
The highest value of VICM should ensure that Q5 remains in saturation; that is, the voltage across Q5, VSD5, should not decrease below |VOV5|. Equivalently, the voltage at the drain of Q5 should not go higher than VDD – |VOV5|. Thus the upper limit of VICM is
or equivalently
VICM ≤VDD −|VOV5|−VSG1
V ≤V −|V |−V −|V | (13.3)
ICM SS tn OV3 tp
ICM DD OV5 tp OV1
The expressions in Eqs. (13.2) and (13.3) can be combined to express the input common-mode
range as
−V +V +V −V ≤V ≤V −V −|V |−|V | (13.4) SS OV3 tn tp ICM DD tp OV1 OV5
As expected, the overdrive voltages, which are important design parameters, subtract from the dc supply voltages, thereby reducing the input common-mode range. It follows that from a VICM range point of view, it is desirable to select the values of VOV as low as possible. WeobservefromEq.(13.4)thatthelowerlimitofVICM isapproximatelywithinanoverdrive voltageof–VSS.Theupperlimit,however,isnotasgood;itislowerthanVDD bytwooverdrive voltages and a threshold voltage.
The extent of the signal swing allowed at the output of the op amp is limited at the lower end by the need to keep Q6 saturated and at the upper end by the need to keep Q7 saturated, thus
−VSS +VOV6 ≤vO ≤VDD −|VOV7| (13.5)
Thus the output voltage can swing to within an overdrive voltage of each of the supply rails. This is a reasonably wide output swing and can be maximized by selecting values for |VOV | of Q6 and Q7 as low as possible.
1If the amplifier is required to drive low-resistance loads and thus a low output resistance is needed, a source follower can be connected to the output of the second stage.
An important requirement of an op-amp circuit is that it be possible for its output terminal to be connected back to its negative input terminal so that a unity-gain amplifier is obtained. For such a connection to be possible, there must be a substantial overlap between the allowable range of vO and the allowable range of VICM . This is usually the case in the CMOS amplifier circuit under study.
EXERCISE
13.1 For a particular design of the two-stage CMOS op amp of Fig. 13.1, ±1.65-V supplies are utilized
and all transistors except for Q6 and Q7 are operated with overdrive voltages of 0.3-V magnitude;
13.1 The Two-Stage CMOS Op Amp 999
Q and Q use overdrive voltages of 0.5-V magnitude. The fabrication process employed provides 67
Vtn =Vtp=0.5V.Findtheinputcommon-moderangeandtherangeallowedforvO.
Ans. –1.35 V to 0.55 V; –1.15 V to +1.15 V
13.1.3 DC Voltage Gain
To determine the dc voltage gain and the frequency response, consider a simplified equivalent-circuit model for the small-signal operation of the CMOS amplifier (Fig. 13.2), where each of the two stages is modeled as a transconductance amplifier. As expected, the input resistance is practically infinite,
Rin =∞
The first-stage transconductance Gm1 is equal to the transconductance of each of Q1 and Q2
(see Section 9.5),
Gm1 = gm1 = gm2 (13.6) SinceQ1 andQ2 areoperatedatequalbiascurrents(I/2)andequaloverdrivevoltages,|VOV1|=
|VOV 2 |,
Gm1 = 2(I/2) = I (13.7) |VOV1| |VOV1|
CC
D2 D6
R1 C1 Vi2 Gm2Vi2 R2 C2 Vo
Vid Gm1Vid
Figure 13.2 Small-signal equivalent circuit for the op amp in Fig. 13.1.
1000 Chapter 13
Operational-Amplifier Circuits
Resistance R1 represents the output resistance of the first stage, thus R1 =ro2∥ro4
(13.8)
(13.9)
(13.10)
(13.11) (13.12)
(13.13)
where
and
ro2 = |VA2| I/2
ro4=VA4 I/2
The dc gain of the first stage is thus
A1 =−Gm1R1
=−gm1(ro2∥ro4) 21 1
=−|V | |V |+V OV1 A2 A4
Observe that the magnitude of A1 is increased by operating the differential-pair transistors, Q1 and Q2, at a low overdrive voltage, and by choosing longer channel lengths for Q1, Q2, Q3, and Q4 so as to obtain larger Early voltages, |VA|.
Returning to the equivalent circuit in Fig. 13.2 and leaving the discussion of the various model capacitances until Section 13.1.5, we note that the second-stage transconductance Gm2 is given by
Gm2 = gm6 = 2ID6 VOV6
Resistance R2 represents the output resistance of the second stage, thus R2 =ro6∥ro7
(13.14)
(13.15)
(13.16)
(13.17)
(13.18) (13.19)
(13.20)
where
and
ro6 = VA6 ID6
ro7 = |VA7| = |VA7| ID7 ID6
The voltage gain of the second stage can now be found as A2 =−Gm2R2
=−gm6(ro6∥ro7) 21 1
=−V V +|V | OV6 A6 A7
Here again we observe that to increase the magnitude of A2, Q6 has to be operated at a low overdrive voltage, and the channel lengths of Q6 and Q7 should be made longer.
The overall dc voltage gain can be found as the product A1A2, Av =A1A2
= Gm1R1Gm2R2 (13.21) = gm1(ro2 ∥ro4)gm6(ro6 ∥ro7) (13.22)
Note that Av is of the order of (gmro)2. Thus the value of Av will be in the range of 500 V/V to 5000 V/V.
Finally, we note that the output resistance of the op amp is equal to the output resistance of the second stage,
Ro =ro6∥ro7 (13.23)
Hence Ro can be large (i.e., in the tens-of-kilohms range). Nevertheless, as we learned from the study of negative feedback in Chapter 11, application of negative feedback that samples the op-amp output voltage results in reducing the output resistance by a factor equal to the amount of feedback (1 + Aβ ). Also, as mentioned before, CMOS op amps are rarely required to drive heavy resistive loads.
EXERCISES
13.2 The CMOS op amp of Fig. 13.1 is fabricated in a process for which V ′ = V ′ = 20 V/μm. Find AnAp
A1, A2, and Av if all devices are 1 μm long, VOV1 = 0.2 V, and VOV6 = 0.5 V. Also, find the op-amp output resistance obtained when the second stage is biased at 0.5 mA.
Ans. –100 V/V; –40 V/V; 4000 V/V; 20 k
13.3 IftheCMOSopampinFig.13.1isconnectedasaunity-gainbuffer,showthattheclosed-loopoutput resistance is given by
13.1 The Two-Stage CMOS Op Amp 1001
Rout ≃ 1/gm6 gm1 ro2 ∥ ro4
13.1.4 Common-Mode Rejection Ratio (CMRR)
The CMRR of the two-stage op amp of Fig. 13.1 is determined by the first stage. This was analyzed in Section 9.5.5 and the result is given in Eq. (9.158), namely,
CMRR = [gm1 (ro2 ∥ ro4 )][2gm3 RSS ] (13.24)
where RSS is the output resistance of the bias current source Q5(ro5). Observe that CMRR is of the order of (gmro)2 and thus can be reasonably high. Also, since gmro is proportional to VA/VOV = VA′ L/VOV , the CMRR is increased if long channels are used, especially for Q5, and the transistors are operated at low overdrive voltages.
1002 Chapter 13
Operational-Amplifier Circuits
13.1.5 Frequency Response
Refer to the equivalent circuit in Fig. 13.2. Capacitance C1 is the total capacitance between the output node of the first stage and ground, thus
C1 = Cgd2 + Cdb2 + Cgd4 + Cdb4 + Cgs6 (13.25) Capacitance C2 represents the total capacitance between the output node of the op amp and
groundandincludeswhateverloadcapacitanceCL thattheamplifierisrequiredtodrive,thus
C2 = Cdb6 + Cdb7 + Cgd7 + CL (13.26)
Usually, CL is larger than the transistor capacitances, with the result that C2 becomes much larger than C1. As mentioned before, capacitor CC is deliberately included for the purpose of equipping the op amp with a uniform –6-dB/octave frequency response. In the following, we shall see how this is possible and how to select a value for CC . Finally, note that in the equivalent circuit of Fig. 13.2 we should have included Cgd 6 in parallel with CC . Usually, however, CC ≫ Cgd6, which is the reason we have neglected Cgd6.
To determine Vo , analysis of the circuit in Fig. 13.2 proceeds as follows. Writing a node equation at node D2 yields
Gm1Vid + Vi2 +sC1Vi2 +sCC(Vi2 −Vo)=0 R1
Writing a node equation at node D6 yields
Gm2Vi2 + Vo +sC2Vo +sCC(Vo −Vi2)=0
R2
(13.27)
(13.28)
To eliminate Vi2 and thus determine Vo in terms of Vid , we use Eq. (13.28) to express Vi2 in terms of Vo and substitute the result into Eq. (13.27). After some straightforward manipulations we obtain the amplifier transfer function
Vo = Gm1(Gm2 −sCC)R1R2
Vid 1+s[C1R1 +C2R2 +CC(Gm2R1R2 +R1 +R2)]+s2[C1C2 +CC(C1 +C2)]R1R2
(13.29)
First we note that for s = 0 (i.e., dc), Eq. (13.29) gives Vo/Vid = (Gm1R1)(Gm2R2), which is what we should have expected. Second, the transfer function in Eq. (13.29) indicates that the amplifier has a transmission zero at s = sZ , which is determined from
Thus,
Gm2 − sZ CC = 0 sZ = Gm2
CC Inotherwords,thezeroisonthepositiverealaxiswithafrequencyωZ of
ωZ = Gm2 CC
(13.30)
(13.31)
Also, the amplifier has two poles that are the roots of the denominator polynomial of Eq. (13.29). If the frequencies of the two poles are denoted ωP1 and ωP2, then the denominator polynomial can be expressed as
s s 1 1 s2 D(s)=1+ω 1+ω =1+sω+ω +ωω
P1P2 P1P2P1P2
Now if one of the poles is dominant, say with frequency ωP1, then ωP1 ≪ ωP2, and D(s) can
be approximated by
s s2
D(s)≃1+ω +ω ω (13.32)
P1 P1P2
The frequency of the dominant pole, ωP1, can now be determined by equating the coefficients
13.1 The Two-Stage CMOS Op Amp 1003
of the s terms in the denominator in Eq. (13.29) and in Eq. (13.32), ωP1 = 1
C1R1 +C2R2 +CC(Gm2R2R1 +R1 +R2)
= 1 (13.33)
R1[C1 +CC(1+Gm2R2)]+R2(C2 +CC)
We recognize the first term in the denominator as arising at the interface between the first and second stages. Here, R1, the output resistance of the first stage, is interacting with the total capacitance at the interface. The latter is the sum of C1 and the Miller capacitance CC(1+Gm2R2),whichresultsfromconnectingCC inthenegative-feedbackpathofthesecond stage whose gain is Gm2R2. Now, since R1 and R2 are usually of comparable value, we see that the first term in the denominator will be much larger than the second and we can approximate ωP1 as
ωP1 ≃ 1
R1[C1 +CC(1+Gm2R2)]
A further approximation is possible because C1 is usually much smaller than the Miller capacitance and Gm2R2 ≫ 1, thus
ωP1 ≃ 1 (13.34) R1CCGm2R2
The frequency of the second, nondominant pole can be found by equating the coefficients of the s2 terms in the denominator of Eq. (13.29) and in Eq. (13.32) and substituting for ωP1 from Eq. (13.34). The result is
ωP2 = Gm2CC
C1C2 +CC(C1 +C2)
Since C1 ≪ C2 and C1 ≪ CC , ωP2 can be approximated as ωP2 ≃ Gm2
C2
(13.35)
To provide the op amp with a uniform gain rolloff of –20 dB/decade down to 0 dB, the value of the compensation capacitor CC is selected so that the resulting value of ωP1 (Eq. 13.34),
1004 Chapter 13
Operational-Amplifier Circuits
when multiplied by the dc gain (Gm1R1Gm2R2), results in a unity-gain frequency ωt lower than
ωZ and ωP2. Specifically
which must be lower than ωZ = Gm2 and ωP2 ≃ Gm2 . Thus, the design must satisfy the
ωt =(Gm1R1Gm2R2)ωP1 = Gm1 (13.36) CC
following two conditions:
CC
C2
Gm1 < Gm2 CC C2
Gm1 < Gm2
(13.37) (13.38)
EXERCISE
D13.4 Consider the frequency response of the op amp analyzed in Chapter 9 (see Example 9.6). Let C1 =0.1pFandC2 =2pF.FindthevalueofCC thatresultsinft =10MHzandverifythatft islower than fZ and fP2 . Recall from the results of Example 9.6 that Gm1 = 0.3 mA/V and Gm2 = 0.6 mA/V. Ans. CC =4.8pF; fZ =20MHz; fP2 =48MHz
Simplified Equivalent Circuit The uniform –20-dB/decade gain rolloff obtained at frequencies f ≫fP1 but lower than fP2 and fZ suggests that at these frequencies, the op amp can be represented by the simplified equivalent circuit shown in Fig. 13.3. Observe that this attractive simplification is based on the assumption that the gain of the second stage, |A2|, is large, and hence a virtual ground appears at the input terminal of the second stage. The second stage then effectively acts as an integrator that is fed with the output current signal of the first stage; Gm1 Vid . Although derived for the CMOS amplifier, this simplified equivalent circuit is general and applies to a variety of two-stage op amps, including the first two stages of the 741-type bipolar op amp studied later in this chapter.
CC
0V
Vid Gm1Vid Vo
Figure13.3 Anapproximatehigh-frequencyequivalentcircuitofthetwo-stageopamp.Thiscircuitapplies for frequencies f ≫ fP1 but lower than fP2 and fZ .
20 log A (dB) 20 log Av
0
f
0 90o 180o
fP2 fZ
Figure 13.4 Typical frequency response of the two-stage op amp.
fP1 ft
f (log scale)
f (log scale)
Phase margin
13.1 The Two-Stage CMOS Op Amp 1005
Phase Margin The frequency compensation scheme utilized in the two-stage CMOS amplifier is of the pole-splitting type, studied in Section 11.10.3: It provides a dominant low-frequency pole with frequency fP1 and shifts the second pole beyond ft. Figure 13.4 shows a representative Bode plot for the gain magnitude and phase. Note that at the unity-gain frequency ft, the phase lag exceeds the 90° caused by the dominant pole at fP1. This so-called excess phase shift is due to the second pole,
and the right-half-plane zero,
φP2 =−tan−1 φZ =−tan−1
f t
fP2 f
t fZ
(13.39)
(13.40)
(13.41)
Thus the phase lag at f = ft will be
φtotal =90°+tan−1(ft/fP2)+tan−1(ft/fZ)
and thus the phase margin will be
Phase margin = 180° − φtotal
=90°−tan−1(ft/fP2)−tan−1(ft/fZ) (13.42)
1006 Chapter 13
Operational-Amplifier Circuits
CC
R
with CC .
From our study of the stability of feedback amplifiers in Section 11.9.2, we know that the magnitudeofthephasemarginsignificantlyaffectstheclosed-loopgain.2 Therefore,obtaining a desired minimum value of phase margin is usually a design requirement.
The problem of the additional phase lag provided by the right-half-plane zero has a rather simple and elegant solution: By including a resistance R in series with CC, as shown in Fig. 13.5, the transmission zero can be moved to other less harmful locations. To find the new location of the transmission zero, set Vo = 0. Then, the current through CC and R will be Vi2 /(R + 1/sCC ), and a node equation at the output yields
Vid Gm1Vid
R1 C1 Vi2 Gm2Vi2 R2 C2 Vo
Figure13.5 Small-signalequivalentcircuitoftheopampinFig.13.1witharesistanceRincludedinseries
Thus the zero is now at
Vi2 = Gm2Vi2 R+1
sCC
1 s=1 CC G −R
m2
(13.43)
(13.44)
We observe that by selecting R = 1/Gm2 , we can place the zero at infinite frequency. An even better choice would be to select R greater than 1/Gm2, thus placing the zero at a negative real-axis location where the phase it introduces becomes a phase lead and thus adds to the phase margin.
EXERCISE
13.5 A particular implementation of the CMOS amplifier of Figs. 13.1 and 13.2 provides Gm 1 = 1 mA/V, Gm2 =2mA/V,ro2 =ro4 =100k,ro6 =ro7 =40k,andC2 =1pF.
(a) Find the value of CC that results in ft = 100 MHz. What is the 3-dB frequency of the open-loop
gain?
(b) FindthevalueoftheresistanceRthatwhenplacedinserieswithCC causesthetransmissionzero
to be located at infinite frequency.
(c) Find the frequency of the second pole and hence find the excess phase lag at f = ft , introduced
by the second pole, and the resulting phase margin assuming that the situation in (b) pertains.
Ans. 1.6 pF; 50 kHz; 500 ; 318 MHz; 17.4°; 72.6°
2The magnitude of the phase margin also affects the step response of the closed-loop amplifier.
13.1.6 Slew Rate
The slew-rate limitation of op amps is discussed in Chapter 2. Here, we shall illustrate the origin of the slewing phenomenon in the context of the two-stage CMOS amplifier under study.
Consider the unity-gain follower of Fig. 13.6 with a step of, say, 1 V applied at the input.
Because of the amplifier dynamics, its output will not change in zero time. Thus, immediately
after the input is applied, the entire value of the step will appear as a differential signal between
the two input terminals. In all likelihood, such a large signal will exceed the voltage required
√
2VOV 1 : see earlier illustration in Chapter 9, Fig. 9.6) and switch the entire bias current I to the other side. Reference to Fig. 13.1 shows that for our example, Q2 will turn off, and Q1 will conduct the entire current I. Thus Q4 will sink a current I that will be pulled from CC , as shown in Fig. 13.7. Here, as we did in Fig. 13.3, we are modeling the second stage as an ideal integrator. We see that the output voltage will
to turn off one side of the input differential pair (
be a ramp with a slope of I/CC :
Thus the slew rate, SR, is given by
vO(t)= I t CC
SR= I CC
13.1 The Two-Stage CMOS Op Amp 1007
(13.45)
It should be pointed out, however, that this is a rather simplified model of the slewing process.
Relationship Between SR and ft A simple relationship exists between the unity-gain bandwidthft andtheslewrateSR.ThisrelationshipcanbefoundbycombiningEqs.(13.36) and (13.45) and noting that Gm 1 = gm 1 = I/VOV 1 , to obtain
SR = 2π ft VOV 1
(13.46)
Figure 13.6 A unity-gain follower with a large step input. Since the output voltage cannot change immediately, a large differential voltage appears between the op-amp input terminals.
1V
I
0
0V iD4 I vo
CC
Figure 13.7 Model of the two-stage CMOS op-amp of Fig. 13.1 when a large differential voltage is applied.
1008 Chapter 13
Operational-Amplifier Circuits
or equivalently,
SR=VOV1ωt (13.47)
Thus, for a given ωt , the slew rate is determined by the overdrive voltage at which the first-stage transistors are operated. A higher slew rate is obtained by operating Q1 and Q2 at a larger VOV . Now, for a given bias current I, a larger VOV is obtained if Q1 and Q2 are p-channel devices. This is an important reason for using p-channel rather than n-channel devices in the first stage of the CMOS op amp. Another reason is that it allows the second stage to employ an n-channel device. Now, since n-channel devices have greater transconductances than corresponding p-channel devices, Gm2 will be high, resulting in a higher second-pole frequency and a correspondingly higher ωt . However, the price paid for these improvements is a lower Gm1 and hence a lower dc gain.
EXERCISE
13.6 FindSRfortheCMOSopampofFig.13.1forthecaseft =100MHzandVOV1 =0.2V.IfCC =1.6pF, what must the bias current I be?
Ans. 126 V/μs; 200 μA
13.1.7 Power-Supply Rejection Ratio (PSRR)
CMOS op amps are usually utilized in what are known as mixed-signal circuits: IC chips that combine analog and digital circuits. In such circuits, the switching activity in the digital portion usually results in increased ripple on the power supplies. A portion of the supply ripple can make its way to the op-amp output and thus corrupt the output signal. The traditional approach for reducing supply ripple by connecting large capacitances between the supply rails and ground is not viable in IC design, as such capacitances would consume most of the chip area. Instead, the analog IC designer has to pay attention to another op-amp specification that so far we have ignored, namely, the power-supply rejection ratio (PSRR).
The PSRR is defined as the ratio of the amplifier differential gain to the gain experienced byachangeinthepower-supplyvoltage(vdd andvss).Forcircuitsutilizingtwopowersupplies, we define
and
where
PSRR+ ≡ Ad A+
PSRR− = Ad A−
A+ ≡ vo vdd
A− = vo vss
(13.48)
(13.49)
(13.50) (13.51)
Obviously, to minimize the effect of the power-supply ripple, we require the op amp to have a large PSRR.
A detailed analysis of the PSRR of the two-stage CMOS op amp is beyond the scope of this book (see Gray et al., 2009). Nevertheless, we make the following brief remarks. It can be shown that the circuit is remarkably insensitive to variations in VDD, and thus PSRR+ is very high. This is not the case, however, for the negative-supply ripple vss, which is coupled to the output primarily through the second-stage transistors Q6 and Q7. In particular, the portion of vss that appears at the op-amp output is determined by the voltage divider formed by the output resistances of Q6 and Q7,
Thus,
v =v ro7
o ss ro6 + ro7
A− ≡ vo = ro7 vss ro6 +ro7
(13.52)
(13.53)
NowutilizingAd fromEq.(13.22)gives
PSRR− ≡ Ad = gm1(ro2 ∥ro4)gm6ro6
13.1 The Two-Stage CMOS Op Amp 1009
(13.54) Thus, PSRR− is of the form (gmro)2 and therefore is maximized by selecting long channels L
A− (to increase |VA |), and operating at low |VOV |.
13.1.8 Design Trade-Offs
The performance parameters of the two-stage CMOS amplifier are primarily determined by two design parameters:
1. The length L used for the channel of each MOSFET.
2. The overdrive voltage |VOV | at which each transistor is operated.
Throughout this section, we have found that a larger L and correspondingly larger |VA| increases the amplifier gain, CMRR and PSRR. We also found that operating at a lower |VOV | increases these three parameters as well as increasing the input common-mode range and the allowable range of output swing. Also, although we have not analyzed the offset voltage of the op amp here, we know from our study of the subject in Section 9.4.1 that a number of the components of the input offset voltage that arises from random device mismatches are proportional to |VOV | at which the MOSFETs of the input differential pair are operated. Thus the offset is minimized by operating at a lower |VOV |.
There is, however, an important MOSFET performance parameter that requires the selection of a larger |VOV |, namely, the transition frequency fT , which determines the high-frequency performance of the MOSFET (see Section 10.2.1),
fT = gm (13.55) 2π Cgs +Cgd
1010 Chapter 13
Operational-Amplifier Circuits
For an n-channel MOSFET, it can be shown that3
fT ≃ 1.5μnVOV (13.56)
2πL2
A similar relationship applies for the PMOS transistor, with μp and |VOV | replacing μn and VOV,respectively.ThustoincreasefT andimprovethehigh-frequencyresponseoftheopamp, we need to use a larger overdrive value and, not surprisingly, shorter channels. A larger |VOV | also results in a higher op-amp slew rate SR (Eq. 13.46). Finally, note that the selection of a larger |VOV | results, for the same bias current, and thus the same power dissipation, in a smaller W/L, which combined with a short L leads to smaller devices and hence lower values of MOSFET capacitances and higher frequencies of operation.
In conclusion, the selection of |VOV | presents the designer with a trade-off between improving the low-frequency performance parameters on the one hand and the high-frequency performance on the other. For modern submicron technologies, which require operation from power supplies of 1 V to 1.5 V, overdrive voltages between 0.1 V and 0.3 V are typically utilized. For these process technologies, analog designers typically use channel lengths that are at least 1.5 to 2 times the specified value of Lmin, and even longer channels are used for current-source bias transistors.
13.1.9 A Bias Circuit for the Two-Stage CMOS Op Amp
We now present a circuit for generating the bias current IREF of the two-stage CMOS op amp of Fig. 13.1. As will be seen, the value of the bias current generated is independent of both the supply voltage and the threshold voltage of the MOSFETs. As well, the transconductance of each MOSFET biased by this circuit (i.e., by a multiple of IREF) has a value determined by only a single resistor and the device dimensions.
The bias circuit is shown in Fig.13.8. It consists of two deliberately mismatched transistors, Q12 and Q13, with Q12 usually about four times wider than Q13. A resistor RB is connected in series with the source of Q12. Since, as will be shown, RB determines both
VDD
Q9 IREF
Q11
Q13
Q8
Q10
Q12 RB
IREF
VSS
Figure 13.8 Bias circuit for the CMOS op amp. Note that Q8 is the same Q8 in the circuit of Fig. 13.1.
3See Appendix G on the companion website.
the bias current IREF and the transconductance gm12, its value should be accurate and stable; in most applications, RB would be an off-chip resistor. In order to minimize the channel-length modulation effect on Q12 , we include a cascode transistor Q10 and a matched diode-connected transistor Q11 to provide a bias voltage for Q10. Finally, a p-channel current mirror formed by a pair of matched devices, Q8 and Q9, both replicates the current IB back to Q11 and Q13 and provides a bias line for Q5 and Q7 of the CMOS op-amp circuit of Fig. 13.11.
Thecircuitoperatesasfollows:Thecurrentmirror(Q8,Q9)causesQ13 toconductacurrent equal to that in Q12, that is, IREF. Thus,
and,
1 W
(VGS12 −Vt)2 (VGS13 −Vt)2
IREF = 2μnCox L
1 W
(13.57)
(13.58)
IREF = 2μnCox L
From the circuit, we see that the gate-source voltages of Q12 and Q13 are related by
VGS13 =VGS12 +IREFRB
SubtractingVt frombothsidesofthisequationandusingEqs.(13.57)and(13.58)toreplace (VGS12 –Vt)and(VGS13 –Vt)resultsin
2IREF = μn Cox (W/L) 13
This equation can be rearranged to yield IREF = 2
2IREF
μn Cox (W/L)12
+ IREFRB 2
(13.59)
(13.60)
12
13.1 The Two-Stage CMOS Op Amp 1011
13
μn Cox (W/L)12 RB2
(W/L)12 −1 (W/L)13
from which we observe that IREF is determined by the dimensions of Q12 and the value of RB and by the ratio of the dimensions of Q12 and Q13. Furthermore, Eq. (13.60) can be rearranged to the form
RB = 2 (W/L)12 −1
2μn Cox (W/L)12 IREF (W/L)13
in which we recognize the factor
gm12 = 2 (W/L)12 −1
(13.61) and the ratio of the
μnCox(W/L)12IREF as gm12; thus,
RB (W/L)13
This is a very interesting result: g is determined solely by the value of R
ID(W/L), each transistor biased by the circuit of Fig. 13.8; that is, each transistor whose bias current is derived from IREF will have a gm value that is a multiple of gm12. Specifically, the ith n-channel
m12
dimensions of Q12 and Q13. Furthermore, since gm of a MOSFET is proportional to
B
MOSFET will have
g = g
mi m12
IDi(W/L)i (13.62) IREF (W/L)12
1012 Chapter 13
Operational-Amplifier Circuits
and the ith p-channel device will have
g = g
mi m12
μpIDi(W/L)i (13.63) μn IREF (W/L)12
Finally, it should be noted that the bias circuit of Fig. 13.8 employs positive feedback, and thus care should be exercised in its design to avoid unstable performance. Instability is avoided by making Q12 wider than Q13, as has already been pointed out. Nevertheless, some form of instability may still occur; in fact, the circuit can operate in a stable state in which all currents are zero. To get it out of this state, current needs to be injected into one of its nodes, to “kick start” its operation. Feedback and stability are studied in Chapter 11.
EXERCISES
13.7 Consider the bias circuit of Fig. 13.8 for the case of (W/L)8 = (W/L)9 = (W/L)10 = (W/L)11 = (W/L)13 = 20 and (W/L)12 = 80. The circuit is fabricated in a process technology for which μnCox = 90 μA/V2. Find the value of RB that results in a bias current IREF = 10 μA. Also, find the transconductance gm12.
Ans. 5.27 k; 0.379 mA/V
D13.8 Design the bias circuit of Fig. 13.8 to operate with the CMOS op amp of Example 9.6. Use Q8 and
Q9 asidenticaldeviceswithQ8 havingthedimensionsgiveninExample9.6.TransistorsQ10,Q11, andQ13 aretobeidentical,withthesamegm asQ8 andQ9.TransistorQ12 istobefourtimesaswide as Q13. Find the required value of RB. What is the voltage drop across RB? Also give the values of the dc voltages at the gates of Q12, Q10, and Q8.
Ans. 1.67 k; 150 mV; −1.5 V; −0.5 V; +1.4 V
Example 13.1
We conclude our study of the two-stage CMOS op amp with a design example. Let it be required to
design the circuit to obtain a dc gain of 4000 V/V. Assume that the available fabrication technology is of
the0.5-μmtypeforwhichV =V =0.5V,k′ =200μA/V2,k′ =80μA/V2,V′ =V′ =20V/μm, tntp n p AnAp
and V = V = 1.65 V. To achieve a reasonable dc gain per stage, use L = 1 μm for all devices. Also, DD SS
for simplicity, operate all devices at the same VOV , in the range of 0.2 V to 0.4 V. Use I = 200 μA, and to obtain a higher Gm2, and hence a higher fP2, use ID6 =0.5mA. Specify the W/L ratios for all transistors. Also give the values realized for the input common-mode range, the maximum possible output swing, Rin and Ro . Also determine the CMRR and PSRR realized. If C1 = 0.2 pF and C2 = 0.8 pF, find the required values of CC and the series resistance R to place the transmission zero at s = ∞ and to obtain the highest possible ft consistent with a phase margin of 85°. Evaluate the values obtained for ft and SR.
Solution
Using the voltage-gain expression in Eq. (13.22),
Av =gm1(ro2∥ro4)gm6(ro6∥ro7)
=2(I/2)×1× VA ×2ID6 ×1×VA VOV 2 (I/2) VOV 2 ID6
V 2 =A
VOV To obtain Av = 4000, given VA = 20 V,
13.1 The Two-Stage CMOS Op Amp 1013
To obtain the required (W/L) ratios of Q1 and Q2,
4000 = 400 V2
OV
VOV =0.316V
Thus,
and
For Q3 and Q4 we write
to obtain
For Q5,
I =1k′ W V2 D1 2p L OV
1
100=1×80 W ×0.3162 2L1
W 25 μm L =1μm
1
W 25 μm L =1μm
2
100=1×200 W ×0.3162 2L3
W W 10 μm L = L =1μm
200=1×80 W ×0.3162 2L5
34
1014
Chapter 13 Operational-Amplifier Circuits
Example 13.1 continued Thus,
5
Since Q7 is required to conduct 500 μA, its (W/L) ratio should be 2.5 times that of Q5 ,
W 50 μm L =1μm
W W 125 μm L =2.5 L = 1μm
500= 1 ×200× W ×0.3162 2L6
W 50 μm L =1μm
6
For Q6 we write
Thus,
75
At this point we should check that condition (13.1) is satisfied, which is indeed the case, ensuring that there will be no systematic output offset voltage.
Finally, let’s select IREF = 20 μA, thus
W W 5 μm
L
The input common-mode range can be found using the expression in Eq. (13.4) as −1.33V≤VICM ≤0.52V
The maximum signal swing allowable at the output is found using the expression in Eq. (13.5) as −1.33 V ≤ vO ≤1.33 V
The input resistance is practically infinite, and the output resistance is
Ro = ro6 ∥ro7 = 1 × 20 = 20 k 2 0.5
= 0.1 L = 1 μm 85
The CMRR is determined using Eq. (13.24),
CMRR = gm1 ro2 ∥ ro4 2gm3 RSS
where RSS = ro5 = VA/I. Thus,
CMRR=2(I/2)×1× VA ×2×2(I/2)×VA VOV 2 (I/2) VOV I
V 2 20 2
=2A=2 =8000 VOV 0.316
Expressed in decibels, we have
CMRR=20 log 8000=78dB The PSRR is determined using Eq. (13.53):
PSRR = gm1 ro2 ∥ ro4 gm6 ro6
=2(I/2)×1× VA ×2ID6 ×VA VOV 2 (I/2) VOV ID6 V 2 20 2
=2A=2 =8000 VOV 0.316
13.1 The Two-Stage CMOS Op Amp 1015
or, expressed in decibels,
PSRR = 20log8000 = 78 dB TodeterminefP2 weuseEq.(13.35)andsubstituteforGm2,
Thus,
Gm2 =gm6 = 2ID6 = 2×0.5 =3.2mA/V VOV 0.316
3.2 × 10−3
fP2 = 2π×0.8×10−12 =637MHz
To move the transmission zero to s = ∞, we select the value of R as R= 1 = 1 =316
tan−1 ft =5° fP2
Thus,
ft =637×tan5°=55.7MHz ThevalueofCC canbefoundusingEq.(13.36),
CC = Gm1 2πft
Gm2 3.2 × 10−3
For a phase margin of 85°, the phase shift due to the second pole at f = ft must be 5°, that is,
1016
Chapter 13 Operational-Amplifier Circuits
Example 13.1 continued where
Thus,
Gm1 =gm1 = 2×100μA =0.63mA/V 0.316 V
0.63 × 10−3
CC1 = 2π×55.7×106 =1.8pF
The value of SR can now be found using Eq. (13.46) as SR=2π×55.7×106 ×0.316
=111V/μs
13.2 The Folded-Cascode CMOS Op Amp
In this section we study another type of CMOS op-amp circuit: the folded cascode. The circuit is based on the folded-cascode amplifier studied in Section 8.5.5. There, it was mentioned that although composed of a CS transistor and a CG transistor of opposite polarity, the folded-cascode configuration is generally considered to be a single-stage amplifier. Similarly, the op-amp circuit that is based on the cascode configuration is considered to be a single-stage op amp. Nevertheless, it can be designed to provide performance parameters that equal and in some respects exceed those of the two-stage topology studied in the preceding section. Indeed, the folded-cascode op-amp topology is currently as popular as the two-stage structure.
13.2.1 The Circuit
Figure 13.9 shows the structure of the CMOS folded-cascode op amp. Here, Q1 and Q2 form
the input differential pair, and Q3 and Q4 are the cascode transistors. Recall that for differential
input signals, each of Q1 and Q2 acts as a common-source amplifier. Also note that the gate
terminals of Q3 and Q4 are connected to a constant dc voltage (VBIAS1) and hence are at signal
ground. Thus, for differential input signals, each of the transistor pairs Q1–Q3 and Q2–Q4 acts
as a folded-cascode amplifier, such as the one in Fig. 8.36. Note that the input differential
pair is biased by a constant-current source I. Thus each of Q1 and Q2 is operating at a bias
current I/2. A node equation at each of their drains shows that the bias current of each of Q3
and Q4 is (IB −I/2). As will be seen shortly, both the dc gain and the unity-gain frequency
are proportional to gm of each of Q1 and Q2. Thus, the bias current I is usually made large
to obtain a high value for gm1,2. For a given power dissipation and thus a given total current
2IB, the current that biases each of Q3 and Q4 (IB − I ) will of necessity be small. It turns out, 2
however, that this is advantageous, as it results in a large ro for Q4 and thus a large output resistance and a correspondingly large dc gain for the op amp. As a rule of thumb, the ratio of ID1,2 to ID3,4 can be selected as large as 4.
VDD
13.2
The Folded-Cascode CMOS Op Amp 1017
IB
IB
Cascode transistors
Q3
Q4
Q1 Q2
VBIAS1
vo
Cascode current mirror
Input differential pair
I
CL
Q5
Q7
Q6
Q8
VSS Figure 13.9 Structure of the folded-cascode CMOS op amp.
EXERCISE
13.9 To limit the power dissipation in the op-amp circuit of Fig. 13.9 to an acceptable level, the total dc current is limited to 0.3 mA. If it is desired to bias each of Q1 and Q2 at a dc current four times the bias current of each of Q3 and Q4, find the values of IB, I, ID1,2, and ID3,4.
Ans. 150 μA; 240 μA; 120 μA; 30 μA
As we learned in Chapter 8, if the full advantage of the high output resistance achieved through cascoding is to be realized, the output resistance of the current-source load must be equally high. This is the reason for using the cascode current mirror Q5 to Q8 in the circuit of Fig. 13.9. (This current-mirror circuit was studied in Section 8.6.1.) Finally, note that capacitance CL denotes the total capacitance at the output node. It includes the internal transistor capacitances, an actual load capacitance (if any), and possibly an additional capacitance deliberately introduced for the purpose of frequency compensation. In many cases, however, the load capacitance will be sufficiently large, obviating the need to provide additional capacitance to achieve the desired frequency compensation. This topic will be discussed shortly. For the time being, we note that unlike the two-stage circuit, which requires
1018 Chapter 13
Operational-Amplifier Circuits
VDD Q9
Q10
VBIAS2
Q3 Q4 Ro4
Q1 Q2
VBIAS1
vO
Ro6
Q5 Q CL
VBIAS3 Q
11 6
Q7 Q8
VSS
Figure 13.10 A more complete circuit for the folded-cascode CMOS amplifier of Fig. 13.9.
the introduction of a separate compensation capacitor CC , here the load capacitance contributes to frequency compensation.
A more complete circuit for the CMOS folded-cascode op amp is shown in Fig. 13.10. Here we show the two transistors Q9 and Q10, which provide the constant bias currents IB, and transistor Q11, which provides the constant current I utilized for biasing the differential pair. Observe that the details for generating the bias voltages VBIAS1, VBIAS2, and VBIAS3 are not shown. Nevertheless, we are interested in how the values of these voltages are to be selected. Toward that end, we evaluate the input common-mode range and the allowable output swing.
13.2.2 Input Common-Mode Range and Output Swing
To find the input common-mode range, let the two input terminals be tied together and connectedtoavoltageVICM.ThemaximumvalueofVICM islimitedbytherequirementthat Q1 and Q2 operate in saturation at all times. Thus VICMmax should be at most Vtn volts above the voltage at the drains of Q1 and Q2. The latter voltage is determined by VBIAS1 and must allow for a voltage drop across Q9 and Q10 at least equal to their overdrive voltage, |VOV9| = |VOV10|. Assuming that Q9 and Q10 are indeed operated at the edge of saturation, VICM max will be
VICMmax =VDD −|VOV9|+Vtn (13.64)
which can be larger than VDD , a significant improvement over the case of the two-stage circuit. The value of VBIAS2 should be selected to yield the required value of IB while operating Q9 and Q10 at a small value of |VOV | (e.g., 0.2 V or so). The minimum value of VICM is limited by the need to keep Q11 operating in saturation at all times, which is assured by keeping the voltage
across it no smaller than VOV 11 at all times. Thus
VICMmin =−VSS +VOV11 +VOV1 +Vtn
(13.65)
The presence of the threshold voltage Vtn in this expression indicates that VICMmin is not sufficiently low. Later in this section we shall describe an ingenious technique for solving this problem. For the time being, note that the value of VBIAS3 should be selected to provide the required value of I while operating Q11 at a low overdrive voltage. Combining Eqs. (13.64) and (13.65) provides
−VSS +VOV11 +VOV1 +Vtn ≤VICM ≤VDD −|VOV9|+Vtn (13.66)
The upper end of the allowable range of vO is determined by the need to maintain Q10 and Q4 in saturation. Note that Q10 will operate in saturation as long as an overdrive voltage, |VOV10|, appears across it. It follows that to maximize the allowable positive swing of vO (and alsoVICMmax),weshouldselectthevalueofVBIAS1 sothatQ10 operatesattheedgeofsaturation, that is,
VBIAS1 =VDD −|VOV10|−VSG4 (13.67) The upper limit of vO will then be
vOmax = VDD −|VOV10|−|VOV4| (13.68)
which is two overdrive voltages below VDD . The situation is not as good, however, at the other end: Since the voltage at the gate of Q6 is –VSS + VGS7 + VGS5 or equivalently –VSS + VOV7 + VOV5 + 2Vtn, the lowest possible vO is obtained when Q6 reaches the edge of saturation, namely, when vO decreases below the voltage at the gate of Q6 by Vtn, that is,
vOmin =−VSS +VOV7 +VOV5 +Vtn (13.69)
Note that this value is two overdrive voltages plus a threshold voltage above −VSS . This is a drawback of utilizing the cascode mirror. The problem can be alleviated by using a modified mirror circuit, as we shall shortly see.
EXERCISE
13.10 For a particular design of the folded-cascode op amp of Fig. 13.10, ±1.65-V supplies are utilized
13.2 The Folded-Cascode CMOS Op Amp 1019
and all transistors are operated at overdrive voltages of 0.3-V magnitude. The fabrication process
employed provides V = V = 0.5 V. Find the input common-mode range and the range allowed tn tp
for vO.
Ans. –0.55 V to +1.85 V; –0.55 V to +1.05 V
1020 Chapter 13
Operational-Amplifier Circuits
13.2.3 Voltage Gain
The folded-cascode op amp is simply a transconductance amplifier with an infinite input resistance, a transconductance Gm, and an output resistance Ro. In addition, Gm is equal to gm of each of the two transistors of the differential pair,
Thus,
Gm = gm1 = gm2 (13.70)
Gm = 2(I/2) = I (13.71) VOV1 VOV1
The output resistance Ro is the parallel equivalent of the output resistance of the cascode amplifier and the output resistance of the cascode mirror, thus
Ro =Ro4∥Ro6 (13.72) Reference to Fig. 13.10 shows that the resistance Ro4 is the output resistance of the CG
transistor Q4. The latter has a resistance (ro2 ∥ro10) in its source lead, thus
Ro4 ≃(gm4ro4)(ro2∥ro10) (13.73)
The resistance Ro6 is the output resistance of the cascode mirror and is thus given by Eq. (8.94), thus
Ro6 ≃ gm6ro6ro8 Combining Eqs. (13.72) to (13.74) gives
Ro = [gm4ro4(ro2 ∥ro10)]∥(gm6ro6ro8) The dc open-loop gain can now be found using Gm and Ro, as
(13.74)
(13.75)
(13.76)
(13.77)
Thus,
Av =GmRo
Av = gm1{[gm4ro4(ro2 ∥ro10)]∥(gm6ro6ro8)}
Figure 13.11 shows the equivalent-circuit model including the load capacitance CL , which we shall take into account shortly.
Because the folded-cascode op amp is a transconductance amplifier, it has been given the name operational transconductance amplifier (OTA). Its very high output resistance, which is of the order of gm ro2 (see Eq. 13.75) is what makes it possible to realize a relatively high voltage gain in a single amplifier stage. However, such a high output resistance may be
Vid
Vo
GmVid
Ro CL
Figure 13.11 Small-signal equivalent cir- cuit of the folded-cascode CMOS amplifier. Note that this circuit is in effect an opera- tional transconductance amplifier (OTA).
a cause of concern to the reader; after all, in Chapter 2, we stated that an ideal op amp has a zero output resistance! To alleviate this concern somewhat, let us find the closed-loop output resistance of a unity-gain follower formed by connecting the output terminal of the circuit of Fig. 13.10 back to the negative input terminal. Since this feedback is of the voltage sampling type,itreducestheoutputresistancebythefactor(1+Aβ),whereA=Av andβ=1,thatis,
Rof = Ro ≃ Ro (13.78) 1+Av Av
SubstitutingforAv fromEq.(13.76)gives
Rof ≃ 1 (13.79)
Gm
which is a general result that applies to any OTA to which 100% voltage feedback is applied. For our particular circuit, Gm = gm1, thus
Rof =1/gm1 (13.80)
Since gm 1 is of the order of 1 mA/V, Rof will be of the order of 1 k. Although this is not very small, it is reasonable in view of the simplicity of the op-amp circuit as well as the fact that this type of op amp is not usually intended to drive low-valued resistive loads.
EXERCISE
13.11 The CMOS op amp of Figs. 13.9 and 13.10 is fabricated in a process for which V ′ An
= V ′ = Ap
13.2 The Folded-Cascode CMOS Op Amp 1021
20 V/μm. If all devices have 1-μm channel length and are operated at equal overdrive voltages of 0.2-V magnitude, I = 240 μA, and IB = 150 μA, find the voltage gain and the value of Ro obtained. Ans. 16,000 V/V; 13.3 M
13.2.4 Frequency Response
From Section 10.5, we know that one of the advantages of the cascode configuration is its excellent high-frequency response. It has three poles: one at the input, one at the connection between the CS and CG transistors (i.e., at the source terminals of Q3 and Q4), and the third at the output terminal. Normally, the first two poles are at very high frequencies, especially when the resistance of the signal generator that feeds the differential pair is small. Since the primary purpose of CMOS op amps is to feed capacitive loads, CL is usually large, and the pole at the output becomes dominant. Even if CL is not large, we can increase it deliberately to give the op amp a dominant pole and thus an open-loop gain that decreases at the uniform rate of −20 dB/decade down to the unity-gain frequency ft , ensuring stable operation when feedback is applied. From Fig. 13.11 we can write
Vo = GmRo Vid 1+sCLRo
Thus, the dominant pole has a frequency fP ,
fP = 1 2πCLRo
(13.81)
(13.82)
1022 Chapter 13
Operational-Amplifier Circuits
and the unity-gain frequency ft will be
ft=GmRofP= Gm (13.83)
2π CL
From a design point of view, the value of CL should be such that at f = ft the excess phase resulting from the nondominant poles is small enough to permit the required phase margin to be achieved. If CL is not large enough to achieve this purpose, it can be augmented.
It is important to note the difference in the effect of increasing the load capacitance on the operation of each of the two op-amp circuits we have studied. In the two-stage circuit, if CL is increased, the frequency of the second pole decreases, the excess phase shift at f = ft increases, and the phase margin is reduced. Here, on the other hand, when CL is increased, ft decreases, but the phase margin increases. In other words, a heavier capacitive load decreases the bandwidth of the folded-cascode amplifier but does not impair its response (which happens whenthephasemargindecreases).Ofcourse,ifanincreaseinCL isanticipatedinthetwo-stage op-ampcase,thedesignercanincreaseCC,thusdecreasingft andrestoringthephasemargin to its required value.
13.2.5 Slew Rate
As discussed in Section 13.1.6, slewing occurs when a large differential signal appears at the op-amp input. Refer to Fig. 13.9 and consider the case when Vid is large and turns Q2 off. Transistor Q1 will then attempt to conduct the entire bias current I. This, however, would not be possible, since I is usually larger than IB. Consideration of the drain node of Q1 indicates that for the node equation to be satisfied, not only must the current in Q3 reduce to zero, but also the current of Q1 must reduce to equal IB. For this to happen, both Q1 and the transistor supplying I must enter the triode mode of operation, and the voltages at their drains must fall accordingly. Now, the zero current in Q3 causes the input current of the mirror to be zero, and correspondingly its output current, in the drain of Q6, will be zero. Meanwhile, the zero current in the drain of Q2 forces the entire current IB to flow through Q4 and into CL. This causes the output voltage vO to ramp with a slope of IB /CL , which is the slew rate,
SR= IB (13.84) CL
After the slewing process is completed, before the amplifier can return to its normal linear operation, both Q1 and the transistor that supplies the bias current I must leave the triode mode and return to the saturation mode of operation. This, however, can take some time and may introduce additional distortion in the output signal. As usual, however, creative circuit design comes to the rescue! Problem 13.27 investigates an ingenious way to deal with this issue.
Example 13.2
Consideradesignofthefolded-cascodeopampofFig.13.10forwhichI=240μA,I =150μA,and ′ B 2′
V for all transistors is 0.25 V. Assume that the fabrication process provides k = 100 μA/V , k = 40 OV n p
μA/V2,VA′=20V/μm,VDD =VSS =2.5V,andVt=0.75V.LetalltransistorshaveL=1μmand assume that CL = 5 pF. Find ID , gm , ro , and W/L for all transistors. Find the allowable range of VICM and of
the output voltage swing. Determine the values of Av , ft , fP , and SR. What is the power dissipation of the op amp?
Solution
From the given values of I and IB we can determine the drain current ID for each transistor. The transconductance of each device is found using
and the output resistance ro from
gm = 2ID = 2ID VOV 0.25
V 20 ro= A =
13.2 The Folded-Cascode CMOS Op Amp 1023
ID ID The W/L ratio for each transistor is determined from
W =2IDi L k′V2
Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 ID(μA) 120 120 30 30 30 30 30 30 150 150 240
The results are as follows:
i OV
gm (mA/V) ro (k) W/L
0.96 0.96 167 167 38.4 38.4
0.24 0.24 667 667 24 24
0.24 0.24 667 667 9.6 9.6
0.24 0.24 1.2 667 667 133 9.6 9.6 120
1.2 1.92 133 83 120 76.8
Note that for all transistors,
Using the expression in Eq. (13.66), the input common-mode range is found to be −1.25V≤VICM ≤3V
The output voltage swing is found using Eqs. (13.68) and (13.69) to be −1.25V≤vO ≤2V
gmro =160V/V VGS =1.0V
1024
Chapter 13 Operational-Amplifier Circuits
Example 13.2 continued
To obtain the voltage gain, we first determine Ro4 using Eq. (13.73) as
Ro4 =160(167∥133)=11.85M
and Ro6 using Eq. (13.74) as
Ro6 =106.7M The output resistance Ro can then be found as
and the voltage gain
Ro = Ro4 ∥Ro6 = 10.7M
Av =GmRo =0.96×10−3 ×10.7×106
= 10, 240 V/V
The unity-gain bandwidth is found using Eq. (13.83),
0.96 × 10−3
ft = 2π×5×10−12 =30.6MHz
Thus, the dominant-pole frequency must be
fP=ft =30.6MHz=3kHz
Av 10, 240 The slew rate can be determined using Eq. (13.84),
IB 150 × 10−6
SR=C = 5×10−12 =30V/μs
L
Finally, to determine the power dissipation we note that the total current is 300 μA = 0.3 mA, and the total supply voltage is 5 V, thus
PD =5×0.3=1.5mW
13.2.6 Increasing the Input Common-Mode Range: Rail-to-Rail Input Operation
In Section 13.2.2 we found that while the upper limit on the input common-mode range exceeds the supply voltage VDD, the magnitude of the lower limit is significantly lower than VSS. The opposite situation occurs if the input differential amplifier is made up of PMOS transistors. It follows that an NMOS and a PMOS differential pair placed in parallel would provide an input stage with a common-mode range that exceeds the power-supply voltage in both directions. This is known as rail-to-rail input operation. Figure 13.12 shows such an
VDD
13.2 The Folded-Cascode CMOS Op Amp 1025
IB IB
QQ
Q5
Q6
12
I
I
Q4 Q3
Q
Q8
7
Figure 13.12 A folded-cascode op amp that employs two parallel complementary input stages to achieve rail-to-rail input common-mode operation. Note that the two “+” terminals are connected together and the two “–” terminals are connected together.
arrangement. To keep the diagram simple, we have not shown the parallel connection of the two differential pairs: The two positive-input terminals are to be connected together and the two negative-input terminals are to be tied together. Transistors Q5 and Q6 are the cascode transistorsfortheQ1–Q2 pair,andtransistorsQ7 andQ8 arethecascodedevicesfortheQ3–Q4 pair. The output voltage Vo is shown taken differentially between the drains of the cascode devices. To obtain a single-ended output, a differential-to-single-ended conversion circuit should be connected in cascade.
Figure 13.12 indicates by arrows the direction of the current increments that result from the application of a positive differential input signal Vid . Each of the current increments indicated is equal to Gm (Vid /2) where Gm = gm1 = gm2 = gm3 = gm4 . Thus the total current feeding each of the two output nodes will be Gm Vid . Now, if the output resistance between each of the two nodes and ground is denoted Ro, the output voltage will be
Thus the voltage gain will be
Vo =2GmRoVid
Av =2GmRo (13.85)
This, however, assumes that both differential pairs will be operating simultaneously. This in turn occurs only over a limited range of VICM . Over the remainder of the input common-mode range, only one of the two differential pairs will be operational, and the gain drops to half of the
VBIAS1
Vo
VBIAS2
VSS
IB IB
1026 Chapter 13 Operational-Amplifier Circuits
value in Eq. (13.85). This rail-to-rail, folded-cascode structure is utilized in a commercially
available op amp.4
EXERCISE
13.12 For the circuit in Fig. 13.12, assume that all transistors, including those that implement the current sources, are operating at equal overdrive voltages of 0.3-V magnitude and have V = 0.7 V and
t
that VDD = VSS = 2.5 V.
(a) Find the range over which the NMOS input stage operates.
(b) Find the range over which the PMOS input stage operates.
(c) Find the range over which both operate (the overlap range).
(d) Find the input common-mode range.
(Note that to operate properly, each of the current sources requires a minimum voltage of VOV across its terminals.)
Ans. –1.2Vto+2.9V;–2.9Vto+1.2V,–1.2Vto+1.2V;–2.9Vto+2.9V
13.2.7 Increasing the Output Voltage Range: The Wide-Swing Current Mirror
In Section 13.2.2 it was found that while the output voltage of the circuit of Fig. 13.10 can swing to within 2|VOV | of VDD , the cascode current mirror limits the negative swing to [2|VOV | + Vt ] above –VSS. In other words, the cascode mirror reduces the voltage swing by Vt volts. This point is further illustrated in Fig. 13.13(a), which shows a cascode mirror (with VSS = 0, for simplicity) and indicates the voltages that result at the various nodes. Observe that because the voltage at the gate of Q3 is 2Vt + 2VOV , the minimum voltage permitted at the output (while Q3 remains saturated) is Vt + 2VOV , hence the extra Vt . Also, observe that Q1 is operating with a drain-to-source voltage Vt + VOV , which is Vt volts greater than it needs to operate in saturation.
The observations above lead us to the conclusion that to permit the output voltage at the drain of Q3 to swing as low as 2VOV , we must lower the voltage at the gate of Q3 from 2Vt + 2VOV to Vt + 2VOV . This is exactly what is done in the modified mirror circuit in Fig. 13.13(b): The gate of Q3 is now connected to a bias voltage VBIAS = Vt + 2VOV . Thus the output voltage can go down to 2VOV with Q3 still in saturation. Also, the voltage at the drain of Q1 is now VOV and thus Q1 is operating at the edge of saturation. The same is true of Q2 and thus the current tracking between Q1 and Q2 will be assured. Note, however, that we can no longer connect the gate of Q2 to its drain. Rather, it is connected to the drain of Q4. This establishes a voltage of Vt + VOV at the drain of Q4 , which is sufficient to operate Q4 in saturation (as long asVt isgreaterthanVOV,whichisusuallythecase).Thiscircuitisknownasthewide-swing current mirror. Finally, note that Fig. 13.13(b) does not show the circuit for generating VBIAS . There are a number of possible circuits to accomplish this task, one of which is explored in Exercise 13.13.
4The Texas Instruments OPA357.
13.2 The Folded-Cascode CMOS Op Amp 1027
IREF IO IREF
Vt VOV
IO
Q4 Q3 Q3 Vt VOV VOV
Q2 Q1 Q1
Q4
Q2
2Vt 2VOV
Vt VOV
t OV
(a) (b)
Figure 13.13 (a) Cascode current mirror with the voltages at all nodes indicated. Note that the minimum voltage allowed at the output is Vt + 2VOV . (b) A modification of the cascode mirror that results in the reduction of the minimum output voltage to VOV . This is the wide-swing current mirror. The circuit requires a bias voltage VBIAS.
EXERCISE
13.13 Show that if transistor Q5 in the circuit of Fig. E13.13 has a W/L ratio equal to one-quarter that of the transistors in the wide-swing current mirror of Fig. 13.13(b), and provided the same value of IREF is utilized in both circuits, then the voltage generated, V5 , is Vt + 2VOV , which is the value of VBIAS needed for the gates of Q3 and Q4.
VBIAS Vt 2VOV VOV
VV
IREF V5
Q5
Figure E13.13
1028 Chapter 13
Operational-Amplifier Circuits
13.3 The 741 BJT Op Amp
Our study of BJT op amps is in two parts: The first part, in this section, is focused on an analog IC classic, the 741 op-amp circuit; the second part, in Section 13.4, presents some of the more recent design techniques.
13.3.1 The 741 Circuit
Figure 13.14 shows the 741 op-amp circuit. In keeping with the IC design philosophy, the circuit uses a large number of transistors, but relatively few resistors and only one capacitor. This philosophy is dictated by the economics (silicon area, ease of fabrication, quality of realizable components) of the fabrication of active and passive components in IC form (see Section 8.1 and Appendix A).
As in the case of most general-purpose IC op amps, the 741 requires two power supplies, +VCC and −VEE . Normally, VCC = VEE = 15 V, but the circuit also operates satisfactorily with the power supplies reduced to much lower values (such as ±5 V).5 It is important to observe that no circuit node is connected to ground, the common terminal of the two supplies.
With a relatively large circuit like that shown in Fig. 13.14, the first step in the analysis is to identify its recognizable parts and their functions. Thus, we begin with a qualitative description of the circuit. Our description is aided by the division of the circuit into its various parts, as indicated in the diagram.
Bias Circuit The reference bias current of the 741 circuit, IREF , is generated in the branch at the extreme left of Fig. 13.14, consisting of the two diode-connected transistors Q11 and Q12 and the resistance R5. Using a Widlar current source formed by Q11, Q10, and R4, bias current for the first stage is generated in the collector of Q10. Another current mirror formed by Q8 and Q9 takes part in biasing the first stage.
ThereferencebiascurrentIREF isusedtoprovidetwoproportionalcurrentsinthecollectors of Q13 . This double-collector lateral6 pnp transistor can be thought of as two transistors whose base–emitter junctions are connected in parallel. Thus Q12 and Q13 form a two-output current mirror: One output, the collector of Q13B, provides bias current and acts as a current-source load for Q17, and the other output, the collector of Q13A, provides bias current for the output stage of the op amp.
Two more transistors, Q18 and Q19, take part in the dc bias process. The purpose of Q18 and Q19 is to establish two VBE drops between the bases of the output transistors Q14 and Q20.
Short-Circuit-Protection Circuitry The 741 circuit includes a number of transistors that are normally off and conduct only if one attempts to draw a large current from the op-amp output terminal. This happens, for example, if the output terminal is short-circuited to one of the two supplies. The short-circuit-protection network (shown in color in Fig. 13.14) consists of R6, R7, Q15, Q21, Q24, R11, and Q22. In the following we shall assume that these transistors are off. Operation of the short-circuit-protection network will be explained in Section 13.3.3.
5 The 741 is fabricated in what is known as the “standard high-voltage technology.” See Appendix K for the parameter values of devices fabricated in this process.
6 See Appendix A for a description of lateral pnp transistors. Also, their characteristics are given in Appendix K.
13.3 The 741 BJT Op Amp 1029
Reference current
First stage Second stage Output stage
–VEE (15 V)
VCC (15 V)
Figure 13.14 The 741 op-amp circuit: Q11, Q12, and R5 generate a reference bias current, IREF. Q10, Q9, and Q8 bias the input stage, which is composed of Q1 to Q7. The second gain stage is composed of Q16 and Q17 with Q13B acting as active load. The class AB output stage is formed by Q14 and Q20 with biasing devices Q13A, Q18, and Q19, and an input buffer Q23. Transistors Q15, Q21, Q24, and Q22 serve to protect the amplifier against output short circuits and are normally cut off.
1030 Chapter 13
Operational-Amplifier Circuits
The Input Stage The 741 circuit consists of three stages: an input differential stage, an intermediate single-ended high-gain stage, and an output-buffering stage. The input stage consists of transistors Q1 through Q7, with biasing performed by Q8, Q9, and Q10. Transistors Q1 and Q2 act as emitter followers, causing the input resistance to be high and delivering the differential input signal to the differential common-base amplifier formed by Q3 and Q4. Thus the input stage is the differential version of the common-collector, common-base configuration discussed in Section 8.7.3.
Transistors Q5, Q6, and Q7 and resistors R1, R2, and R3 form the load circuit of the input stage. This is an elaborate current-mirror-load circuit, which we will analyze in Section 13.3.3. The circuit is based on the base-current-compensated mirror studied in Section 8.2.3, but it includes two emitter-degeneration resistors R1 and R2, and a large resistor R3 in the emitter of Q7. As is the case with current-mirror loads, this circuit not only provides a high-resistance load for Q4 but also converts the signal from differential to single-ended form with no loss in gain or common-mode rejection. The output of the input stage is taken single-endedly at the collector of Q4.
As mentioned in Section 9.6.2, every op-amp circuit includes a level shifter whose function is to shift the dc level of the signal so that the signal at the op-amp output can swing positive and negative. In the 741, level shifting is done in the first stage using the lateral pnp transistors Q3 and Q4. Although lateral pnp transistors have poor high-frequency performance, their use in the common-base configuration (which is known to have good high-frequency response) does not seriously impair the op-amp frequency response.
The use of the lateral pnp transistors Q3 and Q4 in the first stage results in an added advantage: protection of the input-stage transistors Q1 and Q2 against emitter–base junction breakdown. Since the emitter–base junction of an npn transistor breaks down at about 7 V of reverse bias (see Section 6.4.1), regular npn differential stages suffer such a breakdown if, say, the supply voltage is accidentally connected between the input terminals. Lateral pnp transistors, however, have high emitter–base breakdown voltages (about 50 V), and because theyareconnectedinserieswithQ1 andQ2,theyprovideprotectionofthe741inputtransistors, Q1 andQ2.
Finally, note that except for using input buffer transistors, the 741 input stage is essentially a current-mirror-loaded differential amplifier. It is quite similar to the input stage of the CMOS amplifier in Fig. 13.1.
The Second Stage The second or intermediate stage is composed of Q16, Q17, Q13B, and the two resistors R8 and R9. Transistor Q16 acts as an emitter follower, thus giving the second stage a high input resistance. This minimizes the loading on the input stage and avoids loss of gain. Also, adding Q16 with its 50-k emitter resistance (which is similar to Q7 and R3) increases the symmetry of the first stage and thus improves its CMRR. Transistor Q17 acts as a common-emitter amplifier with a 100- resistor in the emitter. Its load is composed of the high output resistance of the pnp current source Q13B in parallel with the input resistance of the output stage (seen looking into the base of Q23). Using a transistor current source as a load resistance (active load) enables one to obtain high gain without resorting to the use of large resistances, which would occupy a large chip area and require large power-supply voltages.
TheoutputofthesecondstageistakenatthecollectorofQ17.CapacitorCC isconnected in the feedback path of the second stage to provide frequency compensation using the Miller compensation technique studied in Section 11.10.3. It will be shown in Section 13.3.4 that the relatively small capacitor CC gives the 741 a dominant pole at about 4 Hz. Furthermore, pole splitting causes other poles to be shifted to much higher frequencies, giving the op amp a uniform –20-dB/decade gain rolloff with a unity-gain bandwidth of about 1 MHz. It should
13.3 The 741 BJT Op Amp 1031 be pointed out that although CC is small in value, the chip area that it occupies is about 13
times that of a standard npn transistor!
THE CREATOR OF THE μA741—DAVID FULLAGAR:
David Fullagar was at Fairchild Semiconductor in 1967 when he designed the μA741, perhaps the most successful op amp ever. Fairchild, TI, and National still sell updated versions of this ubiquitous device. Fullagar, educated at Cambridge, U.K., and formerly employed at Ferranti, had joined Fairchild in 1966 following Widlar’s departure after the μA702 and μA709 designs. Fullagar’s μA741 creation incorporated internal compensation, short-circuit protection, and a novel high-impedance input stage to resolve shortcomings of the earlier designs. After leaving Fairchild, he joined Intersil as the company’s first analog IC designer. The engineer-designer cofounded and became a vital technical contributor to Maxim Integrated Products in 1983; he retired
in 1999.
The purpose of the output stage (Chapter 12) is to provide the amplifier with a low output resistance. In addition, the output stage should be able to supply relatively large load currents without dissipating an unduly large amount of power in the IC. The 741 uses an efficient class AB output stage, which we shall study in Section 13.3.3.
The Output Stage
The output stage of the 741 consists of the complementary pair Q14 and Q20, where Q20 is a substrate pnp (see Appendix A). Transistors Q18 and Q19 are fed by current source Q13 A and bias the output transistors Q14 and Q20. Transistor Q23 (which is another substrate pnp) acts as an emitter follower, thus minimizing the loading effect of the output stage on the second stage.
Device Parameters In the following sections and in the exercises and end-of-chapter problems we shall carry out a detailed analysis of the 741 circuit. For the standard npn and pnp transistors, the following parameters will be used:
npn: IS=10−14A,β=200,VA=125V pnp: IS=10−14A,β=50,VA=50V
Inthe741circuitthenonstandarddevicesareQ13,Q14,andQ20.TransistorQ13 willbeassumed to be equivalent to two transistors, Q13A and Q13B, with parallel base–emitter junctions and having the following saturation currents:
ISA =0.25×10−14 A ISB =0.75×10−14 A
Transistors Q14 and Q20 will be assumed to each have an area three times that of a standard device. Output transistors usually have relatively large areas, to be able to supply large load currents and dissipate relatively large amounts of power with only a moderate increase in device temperature.
1032 Chapter 13 Operational-Amplifier Circuits
EXERCISE
13.14 For the standard npn transistor whose parameters are given in Section 13.3.1, find approximate valuesforthefollowingparametersatIC =0.1mA:VBE,gm,re,rπ,andro.
Ans. 575 mV; 4 mA/V; 250 ; 50 k; 1.25 M
13.3.2 DC Analysis
In this section, we shall carry out a dc analysis of the 741 circuit to determine the bias point of each device. For the dc analysis of an op-amp circuit, the input terminals are grounded. Theoretically speaking, this should result in zero dc voltage at the output. However, because the op amp has very large gain, any slight approximation in the analysis will show that the outputvoltageisfarfrombeingzeroandisclosetoeither+VCC or−VEE.Inactualpractice,an op amp left open-loop will have an output voltage saturated close to one of the two supplies. To overcome this problem in the dc analysis, it will be assumed that the op amp is connected in a negative feedback loop that stabilizes the output dc voltage to zero volts.
Reference Bias Current The reference bias current IREF is generated in the branch composed of the two diode-connected transistors Q11 and Q12 and resistor R5. Thus,
IREF = VCC −VEB12 −VBE11 −(−VEE) R5
ForVCC =VEE =15VandVBE11 =VEB12 ≃0.7V,wehaveIREF = 0.73mA.
Input-Stage Bias Transistors Q11 and Q10 and resistor R4 form a Widlar current source
(Section 8.6.4), thus
VT lnIREF =IC10R4 (13.86) IC 10
13.15 Use Eq. (13.86) to determine the value of IC10 by trial and error. Note that IREF = 0.73 mA and R4 =5k.
Ans. IC10 = 19 μA
Having determined IC10, we proceed to determine the dc current in each of the input-stage transistors. For this purpose, we show in Fig. 13.15 the centerpiece of the input stage: As will
EXERCISE
I
Figure 13.15 The dc analysis of the 741 input stage.
I
be seen shortly, this is a negative-feedback circuit that stabilizes the bias current of each of Q1 to Q4 at a value approximately equal to IC10/2. Refer to the analysis indicated in the diagram (where βN is assumed to be high). The sum of the collector currents of Q1 and Q2 (2I) is fed to (or sensed by) the input of the current mirror Q8−Q9. The output current of the mirror, which for large βP is approximately equal to 2I, is compared to IC10 at node X. The difference between the two currents (2I/βP) establishes the base currents of Q3 and Q4. This is the error signal of the feedback loop. For large βP , this current approaches zero and a node equation at X gives 2I ≃ IC10, and thus I ≃ IC10/2.
To verify the action of the negative-feedback loop in stabilizing the value of I, assume that for some reason I increases. We see that the input current of the Q8−Q9 mirror increases and, correspondingly, its output current increases. Assuming that IC10 remains constant, consideration of node X reveals that the base currents in Q3 and Q4 must decrease. This in turn decreases the value of I, which is opposite to the originally assumed change.
EXERCISES
13.16 Using the value of IC10 found in Exercise 13.15, find the value of the bias current of each of Q1, Q2, Q3, and Q4.
Ans. 9.5 μA
13.3 The 741 BJT Op Amp 1033
1034
Chapter 13 Operational-Amplifier Circuits
13.17 It is required to determine the loop gain of the feedback loop in Fig. 13.15. Break the loop at the input of the Q8−Q9 mirror. Since the input resistance of the mirror is low, ground the connection of thecollectorsofQ1 andQ2.Applyaninputtestcurrentit tothecurrentmirrorandfindthefeedback current that appears in the combined connection of the collectors of Q1 and Q2. Assume IC10 remains constant.
Ans. Loop gain ≃ βP
Continuing with the dc analysis of the input stage, we show in Fig. 13.16 the current-mirror load (Q5, Q6, and Q7) and the input transistor of the second stage (Q16). The current-mirror load is fed by IC3 = IC4 ≃ I. The analysis is illustrated in the figure and shows that for large βN , each of Q5 and Q6 is biased at a current approximately equal to I . The bias current of Q7 is somewhat higher, as shown in Exercise 13.18.
IC4 I
Q7 Q16
IB16 0 I
Q6 R3 I R
VEE
Figure 13.16 Continuation of the dc analysis of the 741 input stage.
I
IC3 I
0
Q5 I R
I/ N 12
I/ N
EXERCISES
13.18 RefertoFig.13.16andrecallthatI=9.5μA,R1 =R2 =1k,R3 =50k,βN =200,andIS (for all three transistors) is 10−14 A. Find VBE6, VB6, and IC7.
Ans. 517 mV; 526.5 mV; 10.5 μA
13.19 Recalling from Chapters 2 and 9 that the input bias current of an op amp is the average of its two input currents, thus
IB = 1(IB1 +IB2) 2
IOS =|IB1−IB2|
find IB and IOS for the 741 if β1 and β2 are nominally 200 but can deviate from nominal by as much as ±5%.
Ans. 47.5 nA; 4.75 nA
Input Common-Mode Range The input common-mode range is the range of input common-mode voltages over which the input stage remains in the linear active mode. Refer to Fig. 13.14. We see that in the 741 circuit the input common-mode range is determined at the upper end by saturation of Q1 and Q2, and at the lower end by saturation of Q3 and Q4.
EXERCISE
13.20 Neglect the voltage drops across R1 and R2 and assume that VCC = VEE = 15 V. Show that the input common-moderangeofthe741isapproximately–12.9Vto+14.7V.(AssumethatVBE ≃0.6Vand that to avoid saturation VCB ≥ −0.3 V for an npn transistor, and VBC ≥ −0.3 V for a pnp transistor.)
Second-Stage Bias Reference to Fig. 13.14 shows that if we neglect the base current of Q23, the collector current of Q17 will be equal to the current supplied by Q13B. We can then use IC17 to determine VBE17, VB17, the current through R9 and hence IE16, and finally IC16 ≃ IE16.
EXERCISE
13.21 RecallingthatQ13B hasascalecurrent0.75timesthatofQ12,findIC13B andhenceIC17.AssumeβP ≫1. Then determine VBE17, IC16, and IB16. (Recall that IREF = 0.73 mA, IS = 10−14 A, and βN = 200.) Ans. 550 μA; 550 μA; 618 mV; 16.2 μA; 0.08 μA
Output-Stage Bias Figure 13.17 shows the output stage of the 741 with the short-circuit- protection circuitry omitted. Current source Q13A delivers a current of 0.25IREF (because IS of Q13A is 0.25 times the IS of Q12 ) to the network composed of Q18 , Q19 , and R10 . As mentioned in Section 13.3.1, the purpose of the Q18–Q19 network is to establish two VBE drops between
13.3 The 741 BJT Op Amp 1035
and the input offset current is
1036 Chapter 13
Operational-Amplifier Circuits
0.25IREF
Figure 13.17 The 741 output stage without the short-circuit-protection devices.
the bases of the output transistors Q14 and Q20. If we neglect the base currents of Q14 and Q20, then the emitter current of Q23 will also be equal to 0.25IREF .
The determination of the bias currents of the output-stage transistors is illustrated by the following example.
Example 13.3
Determine IC23, IB23, VBB = VBE18 +VBE19, IC14, and IC20. Recall that Q14 and Q20 are nonstandard devices with IS14 =IS20 =3×10−14 A.
Solution
Reference to Fig. 13.7 shows that
IC23 ≃IE23 ≃0.25IREF =180μA
ThusweseethatthebasecurrentofQ23 isonly180/50=3.6μA,whichisnegligiblecomparedtoIC17, as we assumed before.
If we assume that VBE 18 is approximately 0.6 V, we can determine the current in R10 as 15 μA. The emitter current of Q18 is therefore
Also,
IE18 =180−15=165μA
IC18 ≃ IE18 = 165μA
At this value of current we find that VBE 18 = 588 mV, which is quite close to the value assumed. The base current of Q18 is 165/200 = 0.8 μA, which can be added to the current in R10 to determine the Q19 current as
IC19 ≃IE19 =15.8μA
The voltage drop across the base–emitter junction of Q19 can now be determined as
VBE19 =VT lnIC19 =530mV IS
The voltage drop VBB can now be calculated as
VBB =VBE18 +VBE19 =588+530=1.118V
Since VBB appears across the series combination of the base–emitter junctions of Q14 and Q20, we can write
VBB =VT lnIC14 +VT lnIC20 IS14 IS20
Using the calculated value of VBB and substituting IS 14 = IS20 = 3 × 10−14 A, we determine the collector currents as
IC14 = IC20 = 154μA
This is the small current (relative to the load currents that the output stage is called upon to supply) at
which the class AB output stage is biased.
Summary For future reference, Table 13.1 provides a listing of the values of the collector bias currents of the 741 transistors.
13.3 The 741 BJT Op Amp 1037
1038 Chapter 13
Operational-Amplifier Circuits
Table 13.1
DC Collector Currents of the 741 Circuit (μA)
Q1 9.5 Q8 19
Q2 9.5 Q9 19
Q3 9.5 Q10 19
Q4 9.5 Q11 730
Q5 9.5 Q12 730
Q6 9.5 Q13A 180
Q7 10.5
Q13B 550 Q14 154
Q15 0 Q16 16.2 Q17 550 Q18 165
Q19 15.8
Q20 154
Q21 0
Q22 0
Q23 180
Q24 0
EXERCISE
13.22 If in the circuit of Fig. 13.17 the Q18 –Q19 network is replaced by two diode-connected transistors, findthecurrentinQ14 andQ20.Assumethatthediode-connectedtransistorsutilizestandarddevices with IS = 10−14 A, while the nonstandard Q14 and Q20 have IS = 3 × 10−14 A.
Ans. 540 μA
13.3.3 Small-Signal Analysis
The Input Stage Figure 13.18 shows part of the 741 input stage for the purpose of performing small-signal analysis. Note that since the collectors of Q1 and Q2 are connected to a constant dc voltage, they are shown grounded. Also, the constant-current biasing of the bases of Q3 and Q4 is equivalent to having the common-base terminal open-circuited.
The differential signal vi applied between the input terminals effectively appears across four equal emitter resistances connected in series—those of Q1, Q2, Q3, and Q4. As a result,
Rid
Figure 13.18 Small-signal analysis of the 741 input stage.
emitter signal currents flow as indicated in Fig. 13.18 with
ie = vi 4re
where re denotes the emitter resistance of each of Q1 through Q4. Thus re = VT
I
(13.87)
Gm1 ≡ io = α = 1 gm1 vi 2re 2
where gm1 is the transconductance of each of the four transistors Q1, Q2, Q3, and Q4.
(13.90)
13.3 The 741 BJT Op Amp 1039
Thus the four transistors Q1 through Q4 supply the load circuit with a pair of complementary current signals αie, as indicated in Fig. 13.18.
The input differential resistance of the op amp can be obtained from Fig. 13.18 as
Rid =4(βN +1)re (13.88)
Proceeding with the input-stage analysis, we show in Fig. 13.19 the current-mirror-load circuit fed with the complementary pair of current signals found earlier. The analysis, together with the order of the steps in which it is performed, is indicated on the diagram. As expected, the current mirror provides an output current io,
io = 2αie (13.89) Combining Eqs. (13.87) and (13.89) provides the transconductance of the input stage as
ie
2 ie
Q5
ie
Q6
io2ie 4
Q7
1 0
ie 3
Ro1
R3
1 50 k 2
R
1 k 1 k
R
Figure13.19 Thecurrent-mirror-loadcircuitoftheinputstagefedbythetwocomplementarycurrentsignals generated by Q1 through Q4 in Fig. 13.18. Circled numbers indicate the order of the analysis steps.
1040 Chapter 13 Operational-Amplifier Circuits
EXERCISES
13.23 Recallingthateachoftheinput-stagetransistorsisbiasedatacurrentI=9.5μAandthatβN =200, find re, gm1, Gm1, and Rid .
Ans. 2.63 k; 0.38 mA/V; 0.19 mA/V; 21 M
13.24 For the circuit in Fig. 13.19, find the following in terms of ie : (a) the signal voltage at the base of
Q6; (b) the signal current in the emitter of Q7; (c) the signal current in the base of Q7; (d) the signal voltage at the base of Q7; (e) the input resistance seen by the left-hand-side signal current source αie . For simplicity, assume that IC 7 ≃ IC 5 = IC 6 , and use the results of Exercise 13.23.
Ans. (a) 3.63 k × ie; (b) 0.08ie; (c) 0.0004ie; (d) 3.84 k × ie; (e) 3.84 k
To complete our modeling of the 741 input stage, we must find its output resistance Ro1. This is the resistance seen “looking back” into the output terminal of the circuit in Fig. 13.19. Thus Ro1 is the parallel equivalent of the output resistance of the current source supplying the signal current αie, and the output resistance of Q6. The first component is the resistance looking into the collector of Q4 in Fig. 13.18. Finding this resistance is considerably simplified if we assume that the common bases of Q3 and Q4 are at a virtual ground. This of course happens only when the input signal vi is applied in a complementary fashion. Nevertheless, making this assumption does not result in a large error.
Assuming that the base of Q4 is at virtual ground, the resistance we are after is Ro4, indicated in Fig. 13.20(a). This is the output resistance of a common-base transistor that has a resistance (re of Q2 ) in its emitter. To find Ro4 we use the following expression (Eq. 8.70):
Ro =ro 1+gm Re∥rπ (13.91)
where Re = re and ro = VAp/I.
The second component of the output resistance is that seen looking into the collector of Q6
in Fig. 13.19 with the αie generator set to 0. Although the base of Q6 is not at signal ground, we shall assume that the signal voltage at the base is small enough to make this approximation valid. The circuit then takes the form shown in Fig. 13.20(b), and Ro6 can be determined using Eq. (13.91) with Re = R2.
Figure 13.20 Simplified circuits for finding the two components of the output resistance Ro1 of the first stage.
13.3 The 741 BJT Op Amp 1041 Figure 13.21 shows the equivalent circuit that we have derived for the input stage.
Figure 13.21 Small-signal equivalent circuit for the input stage of the 741 op amp.
EXERCISES
13.25 Find the values of Ro4 and Ro6 and thus the output resistance of the first stage, Ro1. Recall that I=9.5μA,VAn =125V,VAp =50V,R2 =1k,βN =200,andβP =50.
Ans. 10.5 M; 18.2 M; 6.7 M
13.26 Use the equivalent circuit of Fig. 13.21 together with the value of Gm1 found in Exercise 13.23 and the value of Ro1 found in Exercise 13.25 to determine the open-circuit voltage gain of the 741 input stage.
Ans. |Avo |= Gm1Ro1 = 1273 V/V
Example 13.4
We wish to find the input offset voltage resulting from a 2% mismatch between the resistances R1 and R2 in Fig. 13.14.
Solution
Considerfirstthesituationwhenbothinputterminalsaregrounded,andassumethatR1 =RandR2 =R+ R, where R/R = 0.02. From Fig. 13.22 we see that while Q5 still conducts a current equal to I, the current in Q6 will be smaller by I. The value of I can be found from
Thus
VBE5 +IR=VBE6 +(I−I)(R+R)
VBE5 − VBE6 = IR − I(R + R) (13.92)
The quantity on the left-hand side is in effect the change in VBE due to a change in IE of I. We may therefore write
VBE5 −VBE6 ≃Ire (13.93)
1042
Chapter 13 Operational-Amplifier Circuits
Example 13.4 continued
Equations (13.92) and (13.93) can be combined to obtain
I = R (13.94) I R+R+re
Substituting R = 1 k and re = 2.63 k shows that a 2% mismatch between R1 and R2 gives rise to an output current I = 5.5 × 10−3 I . To reduce this output current to zero we have to apply an input voltage VOS givenby
VOS = I = 5.5×10−3I (13.95) Gm1 Gm1
Substituting I = 9.5 μA and Gm1 = 0.19 mA/V results in the offset voltage VOS ≃ 0.3 mV.
It should be pointed out that the offset voltage calculated is only one component of the input offset voltage of the 741. Other components arise because of mismatches in transistor characteristics. The 741
offset voltage is specified to be typically 2 mV.
Figure 13.22 Input stage with both inputs grounded and a mismatch R between R1 and R2 .
Example 13.5
It is required to find the CMRR of the 741 input stage. Assume that the circuit is balanced except for
mismatches in the current-mirror load that result in an error e in the mirror’s current-transfer ratio; that
is, the ratio becomes 1 − em .
m
Solution
In Section 9.5.5 we analyzed the common-mode operation of the current-mirror-loaded differential amplifier and derived an expression for its CMRR. The situation in the 741 input stage, however, differs substantially because of the feedback loop that regulates the bias current. Since this feedback loop is sensitive to the common-mode signal, as will be seen shortly, the loop operates to reduce the common-mode gain and, correspondingly, to increase the CMRR. Hence, its action is referred to as common-mode feedback.
Figure13.23showsthe741inputstagewithacommon-modesignalvicm appliedtobothinputterminals. We have assumed that as a result of vicm, a signal current i flows as shown. Since the stage is balanced, both sides carry the same current i.
13.3 The 741 BJT Op Amp 1043
Q9 2i
2i 0
vicm
Y
Q8 2i
ii
Q1 Q2
vicm
io emi
ii
vicm
2i/b Q3 P
i/bP
i/bP
Q4
Out
i
Q10 R4
vicm /Ro Ro
In
i
i (1 em) Gmcm emi
Current mirror
vicm
Figure 13.23 Example 13.5: Analysis of the common-mode gain of the 741 input stage. Note that Ro = Ro9 ∥ Ro10 has been “pulled out” and shown separately, leaving behind ideal current sources Q9 and Q10 .
Our objective now is to determine how i relates to v icm . Toward that end, observe that for common-mode inputs, both sides of the differential amplifier, that is, Q1−Q3 and Q2−Q4, act as followers, delivering a signal almost equal to vicm to the common-base node of Q3 and Q4. Now, this node Y is connected to the collectors of two current sources, Q9 and Q10. Denoting the total resistance between node Y and ground Ro, we write
Ro =Ro9∥Ro10 (13.96)
1044
Chapter 13 Operational-Amplifier Circuits
Example 13.5 continued
In Fig. 13.23 we have “pulled Ro out,” thus leaving behind ideal current sources Q9 and Q10 . Since the current in Q10 is constant, we show Q10 in Fig. 13.23 as having a zero incremental current. Transistor Q9, on the other hand, provides a current approximately equal to that fed into Q8, which is 2i. This is the feedback current. Since Q8 senses the sum of the currents in the two sides of the differential amplifier, the feedback loop operates only on the common-mode signal and is insensitive to any difference signal.
Proceeding with the analysis, we now can write a node equation at Y, 2i+ 2i = vicm
(13.97)
(13.98)
Assuming βP ≫ 1, this equation simplifies to
βP Ro i ≃ vicm
2Ro
Having determined i, we now proceed to complete our analysis by finding the output current io. From the
circuit in Fig. 13.23, we see that
io =emi
Thus the common-mode transconductance of the input stage is given by
(13.99)
Gmcm≡io =emi v icm v icm
and the common-mode transconductance Gmcm,
CMRR ≡ Gm1 = gm1 Ro /em
Gmcm
where gm1 is the transconductance of Q1. Now substituting for Ro from Eq. (13.96), we obtain
CMRR = gm1 Ro9 ∥ Ro10 /em
Before leaving this example, we observe that if the feedback were not present, the 2i term in Eq. (13.97)
would be absent and the current i would become βP vicm/2Ro , which is βP times higher than that when feedback is present. In other words, common-mode feedback reduces i, hence the common-mode transconductanceandthecommon-modegain,byafactorβP.ItcanbeshownthatβP isthemagnitudeof the loop gain. (See Exercise 13.17.)
Substituting for i from Eq. (13.98) gives
Gmcm = em 2Ro
(13.100) Finally, the CMRR can be found as the ratio of the differential transconductance Gm1 found in Eq. (13.90)
(13.101)
(13.102)
13.3 The 741 BJT Op Amp 1045
EXERCISES
13.27 Show that if the source of the imbalance in the current-mirror load is that while R1 = R, R2 = R + R, the error em is given by
em= R R+re5 +R
Evaluateem forR/R=0.02.
Ans. em = 5.5 × 10−3
13.28 Refer to Fig. 13.23 and assume that the bases of Q9 and Q10 are at approximately constant voltages
(signal ground). Find Ro9 , Ro10 , and hence Ro . Use VA = 125 V for npn and 50 V for pnp transistors. Use the bias current values in Table 13.1.
Ans. Ro9 = 2.63 M; Ro10 = 31.1 M; Ro = 2.43 M
13.29 Use the results of Exercises 13.27 and 13.28 to determine Gmcm and CMRR of the 741 input stage. What would the CMRR be if the common-mode feedback were not present? Assume βP = 50. Ans. Gmcm =1.13×10−6 mA/V;CMRR=1.68×105 or104.5dB;withoutcommon-modefeedback, CMRR = 70.5 dB
The Second Stage Figure 13.24(a) shows the 741 second stage prepared for small-signal analysis, and Fig. 13.24(b) shows its small-signal model. The three model parameters Ri2, Gm2, and Ro2 can be determined as follows.
The input resistance Ri2 can be found by inspection to be
Ri2 =(β16 +1){re16 +[R9∥(β17 +1)(re17 +R8)]} (13.103)
From the equivalent circuit of Fig. 13.24(b), we see that the transconductance Gm2 is the ratio of the short-circuit output current to the input voltage. Short-circuiting the output terminal of the second stage (Fig. 13.24a) to ground makes the signal current through the output resistance of Q13B zero, and the output short-circuit current becomes equal to the collector signal current of Q17 (ic17). This latter current can be easily related to vi2 as follows:
ic17 = αvb17 re17 +R8
v = v (R9 ∥Ri17) b17 i2 (R9∥Ri17)+re16
Gm2 ≡ ic17 (13.107) vi2
To determine the output resistance Ro2 of the second stage in Fig. 13.24(a), we ground the input terminal and find the resistance looking back into the output terminal. It follows that Ro2
(13.104)
(13.105)
(13.106) where we have neglected ro16 because ro16 ≫ R9. These equations can be combined to obtain
Ri17 =(β17 +1)(re17 +R8)
1046 Chapter 13 Operational-Amplifier Circuits
Ri17
Figure 13.24 (a) The 741 second stage prepared for small-signal analysis. (b) Equivalent circuit.
(b)
Ro2 =(Ro13B∥Ro17)
where Ro13B is the resistance looking into the collector of Q13B while its base and emitter are
connected to ground. It can be easily seen that
Ro13B = ro13B (13.109)
The second component in Eq.(13.108), Ro17, is the resistance seen looking into the collector of Q17. Since the resistance between the base of Q17 and ground is relatively small (approximately equal to re16 ), one can considerably simplify matters by assuming that the base is grounded. Doing this, we can use Eq. (13.91) to determine Ro 17 .
(a)
is given by
(13.108)
EXERCISES
In the following exercises use IC13B = 550 μA, IC16 = 16.2 μA, IC17 = 550 μA, βN = 200 , βP = 50,
VAn =125V,VAp =50V,R9 =50k,andR8 =100. 13.30 Determine the value of Ri2.
Ans. 4 M
13.31 Determine the value of Gm2.
Ans. 6.5 mA/V
13.32 Determine the values of Ro13B, Ro17, and Ro2.
Ans. 90.9 k; 787 k; 81 k
13.33 Determine the value of the open-circuit voltage gain of the second stage. Ans. −526.5 V/V
The Output Stage The 741 output stage is shown in Fig. 13.25 without the short-circuit- protection circuitry. The stage is shown driven by the second-stage transistor Q17 and loaded with a 2-k resistance. The circuit is of the AB class (Section 12.4), with the network composed of Q18 , Q19 , and R10 providing the bias of the output transistors Q14 and Q20 . The use of this network rather than two diode-connected transistors in series enables biasing the output transistors at a low current (0.15 mA) in spite of the fact that the output devices are three times as large as the standard devices. This result is obtained by arranging that the current in Q19 is verysmallandthusitsVBE isalsosmall.WeanalyzedthedcbiasinSection13.3.2.
Another feature of the 741 output stage worth noting is that the stage is driven by an emitter follower Q23. As will be shown, this emitter follower provides added buffering, which makes the op-amp gain almost independent of the parameters of the output transistors.
Let’s first determine the allowable range of output voltage swing. The maximum positive output voltage is limited by the saturation of current-source transistor Q13A. Thus,
vOmax =VCC −|VCEsat|−VBE14 (13.110) which is about 1V below VCC. The minimum output voltage (i.e., maximum negative
amplitude) is limited by the saturation of Q17 . Neglecting the voltage drop across R8 , we obtain vOmin = −VEE + VCEsat + VEB23 + VEB20 (13.111)
which is about 1.5 V above –VEE .
Figure 13.25 The 741 output stage without the short-circuit-protection circuitry.
13.3 The 741 BJT Op Amp 1047
1048 Chapter 13
Operational-Amplifier Circuits
Figure 13.26 Model for the 741 output stage in Fig. 13.25.
Next, we consider the small-signal analysis of the output stage. Specifically, we model the output stage using the equivalent circuit in Fig. 13.26 and determine the model parameters as follows. Note that the model is shown fed with the open-circuit voltage of the second stage vo2,wherefromFig.13.24(b),vo2 =−Gm2Ro2vi2.
To determine the input resistance Rin3, we take into account the load resistance RL and assume that one of the output transistors is conducting, as illustrated in the following example.
Example 13.6
Assuming that Q14 is off and Q20 is conducting a current of 5 mA to a load RL = 2 k, determine the value of Rin3 . Using Gm2 = 6.5 mA/V and Ro2 = 81 k, determine the voltage gain of the second stage.
Solution
Refer to Fig. 13.25. The input resistance looking into the base of Q20 is approximately β20 RL = 50 × 2 = 100 k. This resistance appears in parallel with the series combination of ro13A = VAp /IC 13A = 50 V/180 μA = 280 k, and the resistance of the Q18 –Q19 network. The latter resistance is very small (about 160 ; see later: Exercise 13.35). Thus, the total resistance in the emitter of Q23 is approximately (100 k∥280 k) or 74 k, and the input resistance Rin3 is obtained as
Rin3 =β23 ×74k=50×74=3.7M
We thus see that Rin3 ≫ Ro2 , and the value of Rin3 will have little effect on the performance of the op amp.
Still we can determine the gain of the second stage as
A ≡vi3 =−G R Rin3
2 v m2o2R+R
i2 in3 o2
= −6.5 × 81 3700 = −515 V/V
Continuing with the determination of the equivalent-circuit model parameters, we note from Fig. 13.26 that Gvo3 is the open-circuit overall voltage gain of the output stage,
v
Gvo3 = o (13.112)
3700 + 81
Rout Rin3 Gv o3vo2
vo2 RL=∞
With RL = ∞, the gain of the emitter-follower output transistor (Q14 or Q20 ) will be nearly unity. Also, with RL = ∞ the resistance in the emitter of Q23 will be very large. This means that the gain of Q23 will be nearly unity and the input resistance of Q23 will be very large. We thus conclude that Gvo3 ≃ 1.
Next, we shall find the value of the output resistance of the op amp, Rout. For this purpose refer to the circuit shown in Fig. 13.27. In accordance with the definition of Rout from Fig. 13.26, the input source feeding the output stage is grounded, but its resistance (which is the output resistance of the second stage, Ro2 ) is included. We have assumed that the output voltage vO is negative, and thus Q20 is conducting most of the current; transistor Q14 has therefore been eliminated. The exact value of the output resistance will of course depend on which transistor (Q14 or Q20) is conducting and on the value of load current. Nevertheless, we wish to find an estimate of Rout . The analysis for doing so is shown in Fig. 13.27. It should be noted, however, that to the value of Rout given in the figure we must add the resistance R7 (27 ) (see Fig. 13.14), which is included for short-circuit protection, in order to obtain the total output resistance of the 741.
Figure13.27 CircuitforfindingtheoutputresistanceRout.
EXERCISES
13.3 The 741 BJT Op Amp 1049
Rout
13.34 Find the value of Ro23, Rout, and the total output resistance of the 741 op amp. Use Ro2 = 81 k, β23 = β20 = 50, and IC23 = 180 μA, and assume that Q20 is conducting a load current of 5 mA. Ans. 1.73 k; 39 ; 66
13.35 Using a simple (rπ, gm) model for each of the two transistors Q18 and Q19 in Fig.E13.35, find the small-signal resistance between A and A′. (Note: From Table 13.1, IC18 = 165 μA and IC19 ≃ 16 μA. Also, βN = 200.)
Ans. 163
1050 Chapter 13
Operational-Amplifier Circuits
Figure E13.35
Output Short-Circuit Protection If the op-amp output terminal is short-circuited to one of the power supplies, one of the two output transistors could conduct a large amount of current. Such a large current can result in sufficient heating to cause burnout of the IC (Chapter 12). To guard against this possibility, the 741 op amp is equipped with a special circuit for short-circuit protection. The function of this circuit is to limit the current in the output transistors in the event of a short circuit.
Refer to Fig. 13.14 and note that the short-circuit-protection circuitry is highlighted in color. Resistance R6 together with transistor Q15 limits the current that would flow out of Q14 in the event of a short circuit. Specifically, if the current in the emitter of Q14 exceeds about 20 mA, the voltage drop across R6 exceeds 540 mV, which turns Q15 on. As Q15 turns on, its collector robs some of the current supplied by Q13A, thus reducing the base current of Q14. This mechanism thus limits the maximum current that the op amp can source (i.e., supply from the output terminal in the outward direction) to about 20 mA.
Limiting of the maximum current that the op amp can sink, and hence the current through Q20, is done by a mechanism similar to the one discussed above. The relevant circuit is composed of R7, Q21, Q24, and Q22. For the components shown, the current in the inward direction is limited also to about 20 mA.
Overall Voltage Gain The overall small-signal gain can be found from the cascade of the equivalent circuits derived above for the three op-amp stages. This cascade is shown in Fig. 13.28, loaded with RL = 2 k, which is the typical value used in measuring
13.3 The 741 BJT Op Amp 1051 Rout
Rin3
Gv o3vo2
Figure 13.28 Cascading the small-signal equivalent circuits of the individual stages for the evaluation of the overall voltage gain.
and specifying the 741 data. The overall gain can be expressed as
vo = vi2 vo2 vo vi vi vi2 vo2
=−G (R ∥R )(−G R )G RL
m1 o1 i2 m2 o2 vo3 RL +Rout
Using the values found earlier yields for the overall open-circuit voltage gain, A0 ≡ v o = −476.1 × (−526.5) × 0.97 = 243,147 V/V
vi
= 107.7 dB
13.3.4 Frequency Response
(13.113) (13.114)
(13.115)
The 741 is an internally compensated op amp. It employs the Miller compensation technique, studied in Section 11.10.3, to introduce a dominant low-frequency pole. Specifically, a 30-pF capacitor (CC ) is connected in the negative-feedback path of the second stage. An approximate estimate of the frequency of the dominant pole can be obtained as follows.
From Miller’s theorem (Section 10.3.3), we see that the effective capacitance due to CC between the base of Q16 and ground is (see Fig. 13.14)
Cin =CC(1+|A2|) (13.116)
where A2 is the second-stage gain. Use of the value calculated for A2 found in Example 13.6, A2 = −515, results in Cin = 15,480 pF. Since this capacitance is quite large, we shall neglect all other capacitances between the base of Q16 and signal ground. The total resistance between this node and ground is
Rt =Ro1∥Ri2
= 6.7M∥4M = 2.5M
Thus the dominant pole has a frequency fP given by
fP = 1 =4.1Hz
2π Cin Rt
(13.117)
(13.118)
It should be noted that this approach is equivalent to using the approximate formula in Eq. (11.93).
1052 Chapter 13
Operational-Amplifier Circuits
Figure 13.29 Bode plot for the 741 gain, neglecting nondominant poles.
As discussed in Section 11.10.3, Miller compensation provides an additional advantageous effect, namely, pole splitting. As a result, the other poles of the circuit are moved to very high frequencies. This has been confirmed by computer-aided analysis (see Gray et al., 2000).
Assuming that all nondominant poles are at very high frequencies, the calculated values give rise to the Bode plot shown in Fig. 13.29, where f3dB = fP . The unity-gain bandwidth ft can be calculated from
Thus,
ft = A0 f3dB (13.119)
ft =243,147×4.1≃1MHz (13.120)
AlthoughthisBodeplotimpliesthatthephaseshiftatft is–90°andthusthatthephasemargin is 90°, in practice a phase margin of about 80° is obtained. The excess phase shift (about 10°) is due to the nondominant poles. This phase margin is sufficient to provide stable operation of closed-loop amplifiers with any value of feedback factor β. This convenience of use of the internally compensated 741 is achieved at the expense of a great reduction in open-loop gain and hence in the amount of negative feedback. In other words, if one requires a closed-loop amplifier with a gain of 1000, then the 741 is overcompensated for such an application, and one would be much better off designing one’s own compensation (assuming, of course, the availability of an op amp that is not already internally compensated).
A Simplified Model The simplified model of the 741 op amp shown in Fig. 13.30 is similar to what we used for the CMOS two-stage op amp (Section 13.1.5). Here, however, the high-gain second stage, with its feedback capacitance CC , is modeled by an ideal integrator. In this model, the gain of the second stage is assumed to be sufficiently large that a virtual ground appears at its input. For this reason the output resistance of the input stage and the input resistance of the second stage have been omitted. Furthermore, the output stage is assumed to be an ideal unity-gain follower. (Of course, the two-stage CMOS amplifier does not have an output stage.)
13.3 The 741 BJT Op Amp 1053
Figure 13.30 A simple model for the 741 based on modeling the second stage as an integrator.
Analysis of the model in Fig. 13.30 gives
A(s) ≡ Vo(s) = Gm1 Vi(s) sCC
ωt = Gm1 CC
Substituting Gm 1 = 0.19 mA/V and CC = 30 pF yields ft = ωt ≃ 1 MHz
2π
(13.121)
(13.122)
(13.123)
(13.124)
Thus,
A(jω) =
and the magnitude of gain becomes unity at ω = ωt , where
Gm1 jωCC
which is equal to the value calculated before. It should be pointed out, however, that this model is valid only at frequencies f ≫ f3dB . At such frequencies, the gain falls off with a slope of –20 dB/decade (Fig. 13.29), just like that of an integrator.
13.3.5 Slew Rate
The slew-rate limitation of op amps is discussed in Chapter 2, and expressions for SR are derived for the two-stage CMOS op amp in Section 13.1 and for the folded-cascode CMOS op amp in Section 13.2. The 741 slewing is very similar to that of the two-stage CMOS op amp. Thus, following an identical procedure, we can show that for the 741 op amp,
SR = 2I (13.125) CC
when 2I is the total bias current of the input differential stage.7 For the 741, I = 9.5 μA, and CC = 30 pF, resulting in SR = 0.63 V/μs.
7Note that in the CMOS two-stage op amp, the total bias current of the input stage is denoted I; hence the apparent discrepancy between the expressions in Eqs. (13.125) and (13.45).
1054 Chapter 13
Operational-Amplifier Circuits
Also, as we have done for the two-stage CMOS op amp, we can derive a relationship between SR and ωt . For the 741 case, we can show that
SR = 4VT ωt (13.126) whereVT isthethermalvoltage(approximately25mVatroomtemperature).Asacheck,for
the 741 we have
SR=4×25×10−3 ×2π×106 =0.63V/μs
which is the result obtained previously. Observe that Eq. (13.126) is of the same form as Eq. (13.47), which applies to the two-stage CMOS op amp. Here, 4VT replaces VOV . Since, typically, VOV will be two to three times the value of 4VT , a two-stage CMOS op amp with an ft equal to that of the 741 exhibits a slew rate that is two to three times as large as that of the 741.
EXERCISE
13.36 Use the value of the slew rate calculated above to find the full-power bandwidth fM of the 741 op amp. Assume that the maximum output is ±10 V.
Ans. 10 kHz
13.4 Modern Techniques for the Design of BJT Op Amps
Although the ingenious techniques employed in the design of the 741 op amp have stood the test of time, they are now more than 40 years old! Technological advances have resulted in changes in the user requirements of general-purpose bipolar op amps. The resulting more demanding specifications have in turn posed new challenges to analog IC designers, who, as they have done repeatedly before, are responding with new and exciting circuits. In this section we present a sample of recently developed design techniques. For more on this rather advanced topic the reader is referred to the Analog Circuits section of the bibliography in Appendix I.
13.4.1 Special Performance Requirements
Many of the special performance requirements stem from the need to operate modern op amps from power supplies of much lower voltages. Thus while the 741-type op amp operated from ±15-V power supplies, many modern BJT op amps are required to operate from a single power supply of only 2 V to 3 V. This is done for a number of reasons, including the following.
1. Modern small-feature-size IC fabrication technologies require low power-supply voltages.
2. Compatibility must be achieved with other parts of the system that use low-voltage supplies.
3. Power dissipation must be minimized, especially for battery-operated equipment.
VCC 15 V VCC 3 V
741 Modern
VEE 15 V
Figure 13.31 Power-supply requirements have changed considerably. Modern BJT op amps are required to operate from a single supply VCC of 2 V to 3 V.
13.4 Modern Techniques for the Design of BJT Op Amps 1055
As Fig. 13.31 indicates, there are two important changes: the use of a single ground-referenced power supply VCC , and the low value of VCC . Both of these requirements give rise to changes in performance specifications and pose new design challenges. In the following we discuss two of the resulting changes.
Rail-to-Rail Input Common-Mode Range Recall that the input common-mode range of an op amp is the range of common-mode input voltages for which the op amp operates properly and meets its performance specifications, such as voltage gain and CMRR. Op amps of the 741 type operate from ±15-V supplies and exhibit an input common-mode range that extends to within a couple of volts of each supply. Such a gap between the input common-mode range and the power supply is obviously unacceptable if the op amp is to be operated from a single supply that is only 2 V to 3 V. Indeed we will now show that these single-supply, low-voltage op amps need to have an input common-mode range that extends over the entire supply voltage, 0 to VCC , referred to as rail-to-rail input common-mode range.
Consider first the inverting op-amp configuration shown in Fig. 13.32(a). Since the positive input terminal is connected to ground (which is the voltage of the negative supply rail), ground voltage has to be within the allowable input common-mode range. In fact, because for positive output voltages the voltage at the inverting input terminal can go slightly negative, the input common-mode range should extend below the negative supply rail (ground).
Next consider the unity-gain voltage follower obtained by applying 100% negative feedback to an op amp, as shown in Fig. 13.32(b). Here the input common-mode voltage is equal to the input signal vI . To maximize the usefulness of this buffer amplifier, its input signalvI shouldbeallowedtoextendfrom0toVCC,especiallysinceVCC isonly2Vto3V. Thus the input common-mode range should include also the positive supply rail. As will be seen shortly, modern BJT op amps can operate over an input common-mode voltage range that extends a fraction of a volt beyond its two supply rails: that is, more than rail-to-rail operation!
R2
R1 VCC VCC
vI v v
OO
v I
(a)
(b)
Figure 13.32 (a) In the inverting configuration, the positive op-amp input is connected to ground; thus it is imperative that the input common-mode range includes ground voltage. (b) In the unity-gain follower configuration, vICM = vI ; thus it is highly desirable for the input common-mode range to include ground voltage and VCC .
1056 Chapter 13
Operational-Amplifier Circuits
Near Rail-to-Rail Output Signal Swing In the 741 op amp, we were satisfied with an output that can swing to within 2 V or so of each of the supply rails. With a supply of ±15 V, this capacity resulted in a respectable ±13-V output range. However, to limit the output swing to within 2 V of the supply rails in an op amp operating from a single 3-V supply would result in an unusable device! Thus, here too, we require near rail-to-rail operation. As we shall see in Sec- tion 13.4.5, this requirement forces us to adopt a whole new approach to output-stage design.
Device Parameters The technology we shall use in the examples, exercises, and problems for this section has the following characteristics:
npntransistors : β = 40 VA = 30 V pnptransistors : β = 10 |VA| = 20 V
For both, |VBE | ≃ 0.7 V and |VCE sat | ≃ 0.1 V. It is important to note that we will assume that for this technology, the transistor will remain in the active mode for |VCE | as low as 0.1 V (in other words, that 0.6 V is needed to forward-bias the CBJ).
13.4.2 Bias Design
As in the 741 circuit, the bias design of modern BJT amplifiers makes extensive use of current mirrors and current-steering circuits (Sections 8.2 and 8.6). Typically, however, the bias currents are small (in the microamp range). Thus, the Widlar current source (Section 8.6.4) is especially popular here. As well, emitter-degeneration resistors (in the tens-of-kilohm range) are frequently used.
Figure 13.33 shows a self-biased current-reference source that utilizes a Widlar circuit formed by Q1, Q2, and R2, and a current mirror Q3−Q4 with matched emitter-degeneration resistors R3 and R4. The circuit establishes a current I in each of the four transistors, with the value of I determined as follows. Neglecting base currents and ro’s for simplicity, we write
I VBE1=VTln IS1
I VBE2=VTln IS2
VCC
Q1
R4
R3 Q3
I
Q2 R2
Q4 I
VBIAS 2
VBIAS 1
Figure 13.33 A self-biased current-reference source utilizing a Widlar circuit to generate I = (VT /R2)ln(IS2/IS1). The bias voltagesVBIAS1 andVBIAS2 areutilizedinotherpartsoftheop-amp circuit for biasing other transistors.
Thus,
But,
Thus,
I VBE1−VBE2=VTln S2
IS1 VBE1 −VBE2 =IR2
V I I=Tln S2
R2 IS1
13.4 Modern Techniques for the Design of BJT Op Amps 1057
(13.127)
Thus the value of I is determined by R2 and the ratio of the emitter areas of Q1 and Q2. Also, observe that I is independent of VCC , a highly desirable outcome. Neglecting the temperature dependence of R2 , we see that I is directly PTAT (proportional to the absolute temperature T). It follows that transistors biased by I or mirrored versions of it will exhibit gm’s that are constant independent of temperature!
EXERCISE
D13.37 Design the circuit in Fig. 13.33 to generate a current I = 10 μA. Utilize transistors Q1 and Q2 having their areas in a 1:2 ratio. Assume that Q3 and Q4 are matched and design for a 0.2-V drop across each of R3 and R4. Specify the values of R2, R3, and R4.
Ans. 1.73 k; 20 k; 20 k
The circuit in Fig. 13.33 provides a bias line VBIAS1 with a voltage equal to VBE 1 . This can be used to bias other transistors and thus generate currents proportional to I by appropriately scaling their emitter areas. Similarly, the circuit provides a bias line VBIAS2 at a voltage (IR3 +VEB3) below VCC. This bias line can be used to bias other transistors and thus generate constant currents proportional to I by appropriately scaling emitter areas and emitter-degeneration resistances. These ideas are illustrated in Fig. 13.34.
EXERCISE
D13.38 Refer to the circuit in Fig. 13.34 and assume that the VBIAS2 line is connected to the corresponding line in Fig. 13.33. It is required to generate currents I8 = 10 μA, I9 = 20 μA, and I10 = 5 μA. Specify the required emitter areas of Q8, Q9, and Q10 as ratios of the emitter area of Q3. Also specify the values required for R8, R9, and R10. Use the values of R3 and R4 found in Exercise 13.37. Ignore base currents.
Ans. 1,2,0.5;20 k,10 k,40 k
1058 Chapter 13
Operational-Amplifier Circuits
VBIAS 2
I8
VBIAS 1
R8 Q8
I9
VCC R9
Q9
I10
R10 Q10
I5 I6 I7 Q7
Q5 Q6
R5 R6 R7
Figure 13.34 The bias lines V
provided by the circuit in Fig. 13.33 are utilized to bias other transistors and generate constant currents I5 to I10. Both the transistor area and the emitter-degeneration resistance value have to be appropriately scaled.
BIAS1
and V BIAS2
13.4.3 Design of the Input Stage to Obtain Rail-to-Rail VICM
The classical differential input stage with current-mirror load is shown in Fig. 13.35(a). This is essentially the core of the 741 input stage, except that here we are using a single positive power supply. As well, the CMOS counterpart of this circuit is utilized in nearly every CMOS op-amp design (see Section 13.1). Unfortunately, this very popular circuit does not meet our requirement of rail-to-rail common-mode operation.
Consider first the low end of the input common-mode range. The value of VICMmin is limited by the need to keep Q1 in the active mode. Specifically, since the collector of Q1 is at a voltage VBE3 ≃ 0.7 V, we see that the voltage applied to the base of Q1 cannot go lower than 0.1 V without causing the collector–base junction of Q1 to become forward biased.
VCC VCC
VQ5 VQ5 BIAS BIAS
II
Q1Q2 Q1Q2 vo vo
Q3
(a)
Q4
RC RC
(b)
Figure 13.35 For the input common- mode range to include ground voltage, the classical current-mirror-loaded input stage in (a) has to be replaced with the resistively loaded configuration in (b) with the dc voltage drop across RC limited to 0.2 V to 0.3 V.
Thus VICMmin = 0.1 V, and the input common-mode range does not include ground voltage as required.
The only way to extend VICMmin to 0 V is to lower the voltage at the collector of Q1. This in turn can be achieved only by abandoning the use of the current-mirror load and utilizing instead resistive loads, as shown in Fig. 13.35(b). Observe that in effect we are going back to the resistively loaded differential pair with which we began our study of differential amplifiers in Chapter 9!
TheminimumallowedvalueofVICM inthecircuitofFig.13.35(b)isstillofcourselimited by the need to keep Q1 and Q2 in the active mode. This in turn is achieved by avoiding VICM values that cause the base voltages of Q1 and Q2 to go below their collector voltages by more than 0.6 V,
VICMmin =VRC −0.6V
where VRC is the voltage drop across each of RC1 and RC2. Now if VRC is selected to be 0.2 V to 0.3 V, then VICMmin will be −0.4 V to −0.3 V, which is exactly what we need.
The major drawback of replacing the current-mirror load with resistive loads is that the differential gain realized is considerably reduced,
vo =−gm1,2RC vid
=−I/2RC =−VRC VT VT
where we have neglected ro for simplicity. Thus for VRC = 0.3 V, the gain realized is only 12 V/V. As we will see shortly, this low-gain problem can be solved by cascoding.
Next consider the upper end of the input common-mode range. Reference to the circuit in Fig. 13.35(b) shows that the maximum voltage that can be applied to the bases of Q1 and Q2 is limited by the need to keep the current-source transistor in the active mode. This in turn is achieved by ensuring that the voltage across Q5, VEC5, does not fall below 0.1 V or so. Thus the maximum value of VICM will be a voltage VEB1,2 or approximately 0.7 V lower,
VICMmax =VCC −0.1−0.7=VCC −0.8
That is, the upper end of the input common-mode range is at least 0.8 V below VCC , a severe limitation.
To recap, while the circuit in Fig. 13.35(b) has VICMmin of a few tenths of a volt below the negativepower-supplyrail(atgroundvoltage),theupperendofVICM isratherfarfromVCC,
−0.3≤VICM ≤VCC −0.8
where we have assumed VRC = 0.3 V. To extend the upper end of VICM , we adopt a solution similar to that used in the CMOS case (Section 13.2.6, Fig. 13.12), namely, we utilize a parallel complementary input stage. Toward that end, note that the npn version of the circuit of Fig. 13.35(b), shown in Fig. 13.36, has a common-input range of
0.8≤VICM ≤VCC +0.3
where we have assumed that VRC = 0.3 V. Thus, as expected, the high end meets our specifications and in fact is above the positive supply rail by 0.3 V. The lower end, however, does not, but this should cause us no concern because the lower end will be looked after by the
13.4 Modern Techniques for the Design of BJT Op Amps 1059
1060 Chapter 13
Operational-Amplifier Circuits
VCC
RC RC vo
Q3 Q4
V Q6 BIAS
Figure13.36 ThecomplementofthecircuitinFig.13.35(b).While the input common-mode range of the circuit in Figure 13.35(b) extends below ground, here it extends above VCC. Connecting the two circuits in parallel, as will be shown, results in a rail-to-rail VICM range.
pnppair.Finally,notethatthereisarangeofVICM inwhichboththepnpandthenpncircuits will be active and properly operating,
0.8≤VICM ≤VCC −0.8
Figure 13.37 shows an input stage that achieves more than rail-to-rail input common-mode range by utilizing a pnp differential pair (Q1, Q2) and an npn differential pair (Q3, Q4), connected in parallel. To keep the diagram simple, we are not showing the parallel connection of the input terminals; the + input terminals are assumed to be connected together, and similarly for the – input terminals. In order to increase the gain obtained from the resistively loaded differential pairs, a folded-cascode stage is added. Here R7 and R8 are the resistive loads of the pnp pair Q1−Q2, and Q7−Q8 are its cascode transistors. Similarly, R9 and R10 are
VBIAS 1
Q1
Q5
VCC
R9 R10
Q10 Q2 vO1 vod vO2
Q9
VBIAS 3
Q3 Q4
Q6
VBIAS2
npn pair
pnp pair
Q Q8
7 VB
R7 R8 Cascode
Figure13.37 Inputstagewithrail-to-railinputcommon-moderangeandafolded-cascodestagetoincrease the gain. Note that all the bias voltages including VBIAS3 and VB are generated elsewhere on the chip.
13.4 Modern Techniques for the Design of BJT Op Amps 1061
the resistive loads of the npn pair Q3−Q4, and Q9−Q10 are its cascode transistors. Observe that the cascode transistors do “double duty.” For instance, Q7−Q8 operate as the cascode devices for Q1 −Q2 and at the same time as current-source loads for Q9 −Q10 . A similar statement can be made about Q9−Q10. The output voltage of the first stage, vod, is taken between the collectors of the cascode devices.
ForVICM ≪0.8V,thenpnstagewillbeinactiveandthegainisdeterminedbythetranscon- ductanceGm oftheQ1−Q2 pairtogetherwiththeoutputresistanceseenbetweenthecollectors ofthecascodetransistors.AttheotherendofVICM,thatis,VICM ≫VCC −0.8,theQ1−Q2 stage will be inactive, and the gain will be determined by the transconductance Gm of the Q3−Q4 pair and the output resistance between the collectors of the cascode devices. In the overlap region 0.8 ≤ VICM ≤ VCC − 0.8, both the pnp and npn stages will be active and their effective transconductancesGm addup,thusresultinginahighergain.Thedependenceofthedifferential gainontheinputcommon-modeVICM isusuallyundesirableandcanbereducedconsiderably by arranging that one of the two differential pairs is turned off when the other one is active.8
Example 13.7
It is required to find the input resistance and the voltage gain of the input stage shown in Fig. 13.37.
LetVICM ≪0.8VsothattheQ3−Q4 pairisoff.AssumethatQ5 supplies10μA,thateachofQ7 to
Q10 is biased at 10 μA, and that all four cascode transistors are operating in the active mode. The input
resistanceofthesecondstageoftheopamp(notshown)isRL =2M.Theemitter-degenerationresistances
are R =R =20k, and R =R =30k. Recall that the device parameters are β =40, β =10, 7 8 9 10 N P
VAn =30V, VAp =20V. Solution
Since the stage is fully balanced, we can use the differential half-circuit shown in Fig. 13.38(a). The input resistance Rid is twice the value of rπ1,
where
Thus,
Rid = 2rπ1 = 2βP/gm1 IC1 5 × 10−6
gm1=V =25×10−3 =0.2mA/V T
Rid = 2×10 =100k 0.2
To find the short-circuit transconductance, we short the output to ground as shown in Fig. 13.38(b) and find Gm1 as
Gm1= io vid/2
8This is done in the NE5234 op amp, whose circuit is described and analyzed in great detail in Gray et al. (2009).
1062
Chapter 13 Operational-Amplifier Circuits
Example 13.7 continued
R9
Q9
Q7
R7 (a)
io
Rid2
id Q1 v
v
Ro9
Ro7 RL 2 gm1vid r Q
2
v id Q1
od 2 ro1
2 2 o7 7
re7 R7
≪0.8V.(b)Determining
X
(b)
ie7
Figure13.38 (a)Differentialhalf-circuitfortheinputstageshowninFig.13.37withV
Gm1 =io/ vid/2
At node X we have four parallel resistances to ground,
ICM
V 20V
ro1 = Ap = =4M
IC1 5μA R7 =20k
ro7=VAn = 30V =3M IC7 10 μA
re7≃ 1 =VT =25mV=2.5k gm7 IC7 10 μA
Obviously ro1 and ro7 are very large and can be neglected. Then, the portion of gm1 vid/2 that flows into the emitter proper of Q7 can be found from
v
=0.89g id m1 2
io ≃ ie7 = 0.89gm1 vid /2
v R i≃gid 7
e7 m12R7+re7
v 20 =g id
m1 2 20+2.5 and the output short-circuit current io is
Thus,
13.4 Modern Techniques for the Design of BJT Op Amps 1063
Gm1 ≡ io =0.89gm1 =0.89×0.2=0.18mA/V vid/2
To find the voltage gain we need to determine the total resistance between the output node and ground for the circuit in Fig. 13.38(a),
R=Ro9∥Ro7∥ RL/2
The resistance Ro9 is the output resistance of Q9, which has an emitter-degeneration resistance R9. Thus
Ro9 can be found using Eq. (8.68), where
Thus
Ro9 =ro9 + R9∥rπ9 1+gm9ro9
V 20V
ro9= Ap = =2M
IC9 10 μA
gm9 = IC9 = 10μA =0.4mA/V
VT 25mV
rπ9 = βP = 10 =25k
gm9 0.4 mA/V
Ro9 =2+(30∥25)×10−3 1+0.4×2×103 = 12.9 M
The resistance Ro7 is the output resistance of Q7 , which has an emitter-degeneration resistance R7 ∥ ro1 ≃ R7. Thus,
where
Thus,
Ro7 =ro7 + R7∥rπ7 1+gm7ro7 ro7=VAn = 30V =3M
IC7 10 μA
gm7 = IC7 = 10μA =0.4mA/V
VT 25mV rπ7=βN =40=100k
gm7 0.4 Ro7 =3+(20∥100)×10−3
=23M
RL =2M=1M 22
1+0.4×3×103
1064
Chapter 13 Operational-Amplifier Circuits
Example 13.7 continued
The total resistance R can now be found as
R = 12.9∥23∥1 = 0.89M Finally, we can find the voltage gain as
Ad =vod/2=Gm1R vid/2
=0.18×0.89×103 =160V/V
13.4.4 Common-Mode Feedback to Control the DC Voltage at the Output of the Input Stage
For the cascode circuit in Fig. 13.37 to operate properly and provide high output resistance and thus high voltage gain, the cascode transistors Q7 through Q10 must operate in the active mode at all times. However, relying solely on matching will not be sufficient to ensure that the currents supplied by Q9 and Q10 are exactly equal to the currents supplied by Q7 and Q8. Any small mismatch I between the two sets of currents will be multiplied by the large output resistance between each of the collector nodes and ground, and thus there will be large changes in the voltages vO1 and vO2. These changes in turn can cause one set of the current sources (i.e., Q7−Q8 or Q9−Q10) to saturate. We therefore need a circuit that detects the change in the dc or common-mode component VCM of vO1 and vO2,
VCM = 1(vO1 +vO2) (13.128) 2
and adjusts the bias voltage on the bases of Q7 and Q8, VB, to restore current equality. This negative-feedback loop should be insensitive to the differential signal components of vO1 and vO2; otherwise it would reduce the differential gain. Thus the feedback loop should provide common-mode feedback (CMF).
Figure 13.39 shows the cascode circuit with the CMF circuit as a black box. The CMF circuit accepts vO1 and vO2 as inputs and provides the bias voltage VB as output. In a particular implementation we will present shortly, the CMF circuit has the transfer characteristic
VB =VCM +0.4 (13.129)
By keeping VB higher than VCM by only 0.4 V, the CMF circuit ensures that Q7 and Q8 remain active (0.6 V is needed for saturation).
The nominal value of VB is determined by the quiescent current of Q7 through Q10, the quiescent value of I1 and I2, and the value of R7 and R8. The resulting nominal value of VB and the corresponding value of VCM from Eq. (13.129) are designed to ensure that Q9 and Q10 operate in the active mode. Here, it is important to recall that VBIAS3 is determined by the rest of the op-amp bias circuit.
VCC
13.4 Modern Techniques for the Design of BJT Op Amps 1065
I3
VBIAS3 (determined by
the op-amp bias network)
Out
R9
I4 Q9
vO1
Q7
I1
R10
Q10 vO2
Q8 VB I2
R8
R7
Figure 13.39 The cascode output circuit of the input stage and the CMF circuit that responds to the common-mode component V = 1 v + v by adjusting V so that Q −Q conduct equal currents to
Common-mode feedback circuit
In
CM 2 O1 O2 B 7 8 Q9−Q10, and Q7−Q10 operate in the active mode.
To see how the CMF circuit regulates the dc voltage VCM , assume that for some reason VB is higher than it should be and as a result the currents of Q7 and Q8 exceed the currents supplied by Q9 and Q10 by an increment I. When multiplied by the total resistance between each of the output nodes and ground, the increment I will result in a large negative voltage increment in vO1 and vO2. The CMF circuit responds by lowering VB to the value that restores the equality of currents. The change in VB needed to restore equilibrium is usually small (see Example13.8below)andaccordingtoEq.(13.129)thecorrespondingchangeinVCM willbe equally small. Thus we see negative feedback in action: It minimizes the initial change and thus keeps VCM nearly constant at its nominal value, which is designed to operate Q7 through Q10 in the active region.
We conclude by considering briefly a possible implementation of the CMF circuit. Figure 13.40 shows the second stage of an op-amp circuit. The circuit is fed by the outputs of the input stage, vO1 and vO2,
vO1 =VCM +vd/2 vO2 =VCM −vd/2
In addition to amplifying the differential component of vd, the circuit generates a dc voltage VB,
VB =VCM +0.4
To see how the circuit works, note that Q11 and Q12 are emitter followers that minimize the loading of the second stage on the input stage. The emitter followers deliver to the bases of the differential pair Q13−Q14 voltages that are almost equal to vO1 and vO2 but dc shifted
1066 Chapter 13
Operational-Amplifier Circuits
vo3
D
Q14
vO1 Q11 VB
Q13 ID
VE
Q12 vO2
VBIAS Q15
Figure13.40 Anop-ampsecondstageincorporatingthecommon-modefeedbackcircuitfortheinputstage. Note that the circuit generates the voltage VB needed to bias the cascode circuit in the first stage. Diode D is a Schottky-barrier diode, which exhibits a forward voltage drop of about 0.4 V.
by VEB11,12. Thus the voltage at the emitters of Q13−Q14 will be VE = VCM + VEB11,12 − VBE13,14
which reduces to
VE ≃VCM
The voltage VB is simply equal to VE plus the voltage drop of diode D1. The latter is a
Schottky-barrier diode (SBD), which features a low forward drop of about 0.4 V. Thus, VB =VE +VD =VCM +0.4
as required.
Example 13.8
Consider the operation of the circuit in Fig. 13.39. Assume that VICM ≪ 0.8 V and thus the npn input pair (Fig. 13.37) is off. Hence I3 = I4 = 0. Also assume that only dc voltages are present and thus I1 = I2 = 5 μA. EachofQ7 toQ10 isbiasedat10μA,VCC =3V,VBIAS3 =VCC −1,R7 =R8 =20k,andR9 =R10 =30k. Neglect base currents and neglect the loading effect of the CMF circuit on the output nodes of the cascode circuit. The CMF circuit provides VB = VCM + 0.4.
13.4 Modern Techniques for the Design of BJT Op Amps 1067
(a) Determine the nominal values of VB and VCM . Does the value of VCM ensure operation in the active mode for Q7 through Q10?
(b) If the CMF circuit were not present, what would be the change in vO1 and vO2 (i.e., in VCM ) as a result of a current mismatch I = 0.3 μA between Q7 −Q8 and Q9 −Q10 ? Use the output resistance values found in Example 13.7.
(c) Now,iftheCMFcircuitisconnected,whatchangewillitcauseinVB toeliminatethecurrentmismatch I?WhatisthecorrespondingchangeinVCM fromitsnominalvalue?
Solution
(a) The nominal value of VB is found as follows:
VB=VBE7+IE7+I1 R7 ≃0.7+(10+5)×10−3 ×20 =1V
ThenominalvalueofVCM cannowbefoundfrom
VCM =VB −0.4=1−0.4=0.6V
For Q7−Q8 to be active,
that is,
For Q9−Q10 to be active
That is,
resulting in
VCM > VB7,8 − 0.6
VCM >0.4V
VCM < VBIAS3 + 0.6
VCM
(b)
vO VOH
NML VOL
0
NMH
VOL
VIL VIH
VOH vI
Figure14.13 Voltage-transfercharacteristicofaninverter.TheVTCisapproximatedbythreestraight-line segments. Note the four parameters of the VTC (VOH , VOL , VIL , and VIH ) and their use in determining the noise margins(NMH andNML).
nonlinear curve such as that in Fig. 14.12. Observe that the output high level, denoted VOH , does not depend on the exact value of vI as long as vI does not exceed the value labeled VIL; when vI exceeds VIL, the output decreases and the inverter enters its amplifier region of operation, also called the transition region. It follows that VIL is an important parameter of the inverter VTC: It is the maximum value that vI can have while being interpreted by the inverter as representing a logic 0.
Similarly, we observe that the output low level, denoted VOL , does not depend on the exact value of vI as long as vI does not fall below VIH . Thus VIH is an important parameter of the inverterVTC:ItistheminimumvaluethatvI canhavewhilebeinginterpretedbytheinverter as representing a logic 1.
14.2.2 Noise Margins
The insensitivity of the inverter output to the exact value of vI within allowed regions is a great advantage that digital circuits have over analog circuits. To quantify this insensitivity property, consider the situation that occurs often in a digital system where an inverter (or a logic gate based on the inverter circuit) is driving another similar inverter, as shown in Fig. 14.14.
vO1 vI2
G1 G2
Figure14.14 NoisevoltagevN iscoupledtothe v interconnection between the output of inverter G1
N and the input of inverter G2.
14.2 Digital Logic Inverters 1101
1102 Chapter 14
CMOS Digital Logic Circuits
Table 14.1 Important Parameters of the VTC of the Logic Inverter (Refer to Fig. 14.13)
VOL : VOH : VIL : VIH : NML : NMH :
Output low level
Output high level
Maximum value of input interpreted by the inverter as a logic 0 Minimum value of input interpreted by the inverter as a logic 1 Noise margin for low input = VIL – VOL
Noise margin for high input = VOH – VIH
Here we assume that a noise or interference signal vN is somehow coupled to the interconnection between the output of inverter G1 and the input of inverter G2 with the result that the input of G2 becomes
vI2 =vO1 +vN (14.7)
wherethenoisevoltagevN canbeeitherpositiveornegative.NowconsiderthecasevO1 =VOL; that is, inverter G2 is driven by a logic-0 signal. Reference to Fig. 14.13 indicates that in this case G2 will continue to function properly as long as its input vI2 does not exceed VIL. Equation(14.7)thenindicatesthatvN canbeashighasVIL−VOL whileG2 continuestofunction properly. Thus, we can say that inverter G2 has a noise margin for low input, NML , of
NML = VIL − VOL (14.8)
Similarly, if vO1 = VOH , the driven inverter G2 will continue to see a high input as long as vI2 does not fall below VIH . Thus, in the high-input state, inverter G2 can tolerate a negative vN of magnitude as high as VOH − VIH . We can thus state that G2 has a high-input noise margin, NMH , of
NMH =VOH −VIH (14.9)
In summary, four parameters, VOH, VOL, VIH, and VIL, define the VTC of an inverter and determine its noise margins, which in turn measure the ability of the inverter to tolerate variations in the input signal levels. In this regard, observe that changes in the input signal level within the noise margins are rejected by the inverter. Thus noise is not allowed to propagate further through the system, a definite advantage of digital over analog circuits. Alternatively, we can think of the inverter as restoring the signal levels to standard values (VOL and VOH ) even when it is presented with corrupted input signal levels (within the noise margins). As a summary, useful for future reference, we present a listing and definitions of the important parameters of the inverter VTC in Table 14.1.
TheformaldefinitionsofthethresholdvoltagesVIL andVIH aregiveninFig.14.15.Observe that VIL and VIH are defined as the VTC points at which the slope is −1 V/V. As vI exceeds VIL, the magnitude of the inverter gain increases and the VTC enters its transition region. Similarly, as vI falls below VIH , the inverter enters the transition region and the magnitude of the gain increases. Finally, note that Fig. 14.15 shows the definition of another important point on the VTC; this is point M at which vO = vI . Point M is loosely considered to be the midpoint of the VTC and thus the point at which the inverter switches from one state to the other. Point M plays an important role in the definition of the time delay of the inverter, as we shall see shortly.
14.2 Digital Logic Inverters 1103
VM M
Slope 1
VIL VM
Figure 14.15 Typical voltage-transfer characteristic (VTC) of a logic inverter, illustrating the definition of
the critical points.
14.2.3 The Ideal VTC
What constitutes an ideal VTC for an inverter? The answer to this naturally arising question follows directly from the preceding discussion: An ideal VTC is one that maximizes the output signal swing and the noise margins. For an inverter operated from a power supply VDD , maximum signal swing is obtained when
and
VOH =VDD VOL =0
To obtain maximum noise margins, we first arrange for the transition region to be made as narrow as possible and ideally of zero width. Then, the two noise margins are equalized by arranging for the transition from high to low to occur at the midpoint of the power supply, that is, at VDD /2. The result is the VTC shown in Fig. 14.16, for which
VIL =VIH =VM =VDD/2
Observe that the sharp transition at VDD/2 indicates that if the inverter were to be used as an amplifier, its gain would be infinite. Again, we point out that while the analog designer’s interest would be focused on the transition region of the VTC, the digital designer would prefer the transition region to be as narrow as possible, as is the case in the ideal VTC of Fig. 14.16. Finally, we will see in Section 14.3 that inverters implemented using CMOS technology come very close to realizing the ideal VTC.
14.2.4 Inverter Implementation
Inverters are implemented using transistors (Chapters 5 and 6) operating as voltage-controlled switches. The simplest inverter implementation is shown in Fig. 14.17(a). The switch is
1104 Chapter 14
CMOS Digital Logic Circuits
vO
VOH VDD
VOL 0
Figure 14.16 The VTC of an ideal inverter.
VIL VIH VM VDD 2
VDD
vI
VDD VDD
VDD
R
RR
vI
Ron
vO vO vO
vI low vI high
(a)
(b)
(c)
Figure 14.17 (a) The simplest implementation of a logic inverter using a voltage-controlled switch; (b)equivalentcircuitwhenvI islow;(c)equivalentcircuitwhenvI ishigh.Notethattheswitchisassumed to close when vI is high.
controlled by the inverter input voltage vI: When vI is low, the switch will be open and vO = VDD, since no current flows through R. When vI is high, the switch will be closed and, assuming an ideal switch, vO will be 0.
Transistor switches, however, as we know from Chapters 5 and 6, are not perfect. Although their off-resistances are very high, and thus an open switch closely approximates an open circuit, the “on” switch has a finite closure, or on-resistance, Ron. The result is that when vI
14.2 Digital Logic Inverters 1105 is high, the inverter has the equivalent circuit shown in Fig. 14.17(c), from which VOL can
be found.1
V=V Ron OL DD R + Ron
We observe that the circuit in Fig. 14.12(a) is a direct implementation of the inverter in Fig. 14.17. In this case, Ron is equal to rDS of the MOSFET evaluated at its operating point in the triode region with VGS = VDD .
EXERCISE
D14.1 Design the inverter in Fig. 14.12(a) to provide VOL = 90 mV and to draw a supply current of 30 μA in the low-output state. Let the transistor be specified to have Vt = 0.4 V, μnCox = 125 μA/V2, and λ = 0. The power supply VDD = 1.8 V. Specify the required values of W/L and RD . How much power is drawn from VDD when the switch is open? Closed?
Hint: Recall that for small vDS,
rDS ≃1 μnCox L VGS −Vt
Ans. 1.9; 57 k; 0; 54 μW
More elaborate implementations of the logic inverter exist, and we show two of these in Fig. 14.18(a) and 14.19. The circuit in Fig. 14.18(a) utilizes a pair of complementary switches, the “pull-up” (PU) switch connects the output node to VDD, and the “pull-down” (PD)switchconnectstheoutputnodetoground.WhenvI islow,thePUswitchwillbeclosed and the PD switch open, resulting in the equivalent circuit of Fig. 14.18(b). Observe that in this case Ron of PU connects the output to VDD, thus establishing VOH = VDD. Also observe that no current flows, and thus no power is dissipated, in the circuit. Next, if vI is raised to the logic-1 level, the PU switch will open while the PD switch will close, resulting in the equivalent circuit shown in Fig. 14.18(c). Here Ron of the PD switch connects the output to ground, thus establishing VOL = 0. Here again no current flows, and no power is dissipated. The superiority of this inverter implementation over that using the single pull-down switch andaresistor(knownasapull-upresistor)shouldbeobvious:WithVOL =0andVOH =VDD, the signal swing is at its maximum possible, and the power dissipation is zero in both states. This circuit constitutes the basis of the CMOS inverter that we synthesized in the previous section [Fig. 14.2(b)] and will study in detail in Section 14.3.
1 If a BJT is used to implement the switch in Fig. 14.17(a), its equivalent circuit in the closed position includes in addition to the resistance Ron = RCEsat an offset voltage of about 50 mV to 100 mV [see Fig. 6.20(c)]. We shall not pursue this subject any further here, since the relatively long delay time needed to turn off a saturated BJT has caused the use of BJT switches operated in saturation to all but disappear from the digital IC world.
W
1106 Chapter 14
CMOS Digital Logic Circuits
VDD
VDD VDD
Ron
R
PU
PU
v PDv PDvRon v
vI low vI high
IOOO
(a)
(b)
(c)
Figure14.18 Amoreelaborateimplementationofthelogicinverterutilizingtwocomplementaryswitches. This is the basis of the CMOS inverter that we synthesized in the previous section [Fig. 14.2(b)] and shall study in Section 14.3.
VCC
RC1
RC2
vO1
vO2
vI
IEE
VEE
Figure 14.19 Another inverter implementation utilizing a double-throw switch to steer the constant current IEE to RC1 (when vI is high) or RC2 (when vI is low). This is the basis of the emitter-coupled logic (ECL) studied briefly in Chapter 15.
Finally, consider the inverter implementation of Fig. 14.19. Here a double-throw switch is usedtosteertheconstantcurrentIEE intooneoftworesistorsconnectedtothepositivesupply VCC. The reader is urged to show that if a high vI results in the switch being connected to RC1, then a logic inversion function is realized at vO1. Note that the output voltage is independent of the switch resistance. This current-steering or current-mode logic arrangement is the basis of the fastest available digital logic circuits, called emitter-coupled logic (ECL), which we shall study briefly in Section 15.6.1. In fact, ECL is the only BJT logic-circuit type that is currently employed in new designs and the only one studied in this book.
14.2 Digital Logic Inverters 1107
EXERCISE
14.2 For the current-steering circuit in Fig. 14.19, let VCC = 5 V, IEE = 1 mA, and RC1 = RC2 = 2 k. What are the high and low logic levels obtained at the outputs?
Ans. VOH =5V;VOL =3V
Example 14.2 Resistively Loaded MOS Inverter For the simple MOS inverter in Fig. 14.12(a):
(a) Derive expressions for VOH , VOL , VIL , VIH , and VM . For simplicity, neglect channel-length modulation (i.e., assume λ = 0). Show that these inverter parameters can be expressed in terms of V , V , and
−1 DD t
kn RD . The latter parameter has the dimension of V , and to simplify the expressions, denote kn RD ≡
1/Vx.
(b) Show that Vx can be used as a design parameter for the inverter circuit. In particular, find the value of
Vx thatresultsinVM =VDD/2.
(c) Find numerical values for all parameters and for the inverter noise margins for VDD = 1.8 V, Vt = 0.5 V,
andVx settothevaluefoundin(b).
(d) For kn′ = 300 μA/V2 and W/L = 1.5, find the required value of RD and use it to determine the average
power dissipated in the inverter, assuming that the inverter spends half of the time in each of its two
states.
(e) Comment on the characteristics of this inverter circuit vis-a`-vis the ideal characteristics as well as on
its suitability for implementation in integrated-circuit form.
Solution
(a) Refer to Fig. 14.20. For vI < Vt, the MOSFET is off, iD = 0, and vO = VDD. Thus
VOH =VDD (14.10)
As vI exceeds Vt, the MOSFET turns on and operates initially in the saturation region. Assuming λ=0,
and
i =1kv−V2 D2nIt
v=V −Ri=V −1kRv−V2 O DD DD DD2nDI t
substituting kn RD = 1/Vx , the BC segment of the VTC is described by v =V − 1 v −V2
(14.11)
O DD 2V I t x
1108 Chapter 14 CMOS Digital Logic Circuits
Example 14.2 continued
vO
VOHA B 1
VVM M DD
iD RD
vO
vI Q VOL
C
1
D
(a)
0 Vt VV VvI MIH DD
NML VIL NMH (b)
Figure 14.20 The resistively loaded MOS inverter and its VTC (Example 14.2).
TodetermineVIL,wedifferentiateEq.(14.11)andsetdvO/dvI =−1,
which results in
dvO =−1v−V dv V I t
Ix
−1=−1V −V VIL t
x
VIL =Vt +Vx
To determine the coordinates of the midpoint M, we substitute vO = vI = VM in Eq. (14.11), thus obtaining
V −V = 1 V −V2 (14.13) DD M 2V M t
x
(14.12)
which can be solved to obtain
(14.14) The boundary of the saturation-region segment BC, point C, is determined by substituting v O = v I − Vt
in Eq. (14.11) and solving for vO to obtain
2 VM=Vt+ 2VDD−Vt Vx+Vx −Vx
14.2 Digital Logic Inverters 1109
and
V = 2V V+V2−V OC DDxxx
V =V+ 2V V+V2−V IC t DDx x x
(14.15)
(14.16)
Beyond point C, the transistor operates in the triode region, thus 1
iD=kn vI−Vt vO−2vO2 and the output voltage is obtained as
1 1 vO=VDD−V vI−Vt vO−2vO2
x
(14.17) which describes the segment CD of the VTC. To determine VIH , we differentiate Eq. (14.17) and set
dvO/dvI =−1:
which results in
dv 1 dv dv O=− v−V O+v−v O
dv V I tdv O Odv IxII
−1=− 1 −V −V+2v V IH t O
x
VIH −Vt =2vO −Vx
Substituting in Eq. (14.17) for vI with the value of VIH from Eq. (14.18) results in an equation in the
value of vO corresponding to vI = VIH , which can be solved to yield v =0.816V V
(14.18)
(14.19)
(14.20)
OvI=VIH which can be substituted in Eq. (14.18) to obtain
DD x
VIH =Vt +1.63 VDDVx −Vx
1110
Chapter 14 CMOS Digital Logic Circuits
Example 14.2 continued
To determine VOL we substitute vI = VOH = VDD in Eq. (14.17):
1 1
V =V − V −V V − V2 (14.21)
OL DD V DD t OL 2OL x
Since we expect VOL to be much smaller than 2 VDD − Vt , we can approximate Eq. (14.21) as V ≃V −1V −VV
which results in
(14.22) It is interesting to note that the value of VOL can alternatively be found by noting that at point D, the
(14.23)
(14.24)
OL DD V DD t OL x
VOL= VDD 1+ VDD−Vt /Vx
MOSFET switch has a closure resistance rDS ,
rDS=1
kn VDD−Vt
andVOL canbeobtainedfromthevoltagedividerformedbyRD andrDS,
VDD
(1.8/2 − 0.5)2
1.8 = 0.089 V
VOH =1.8V VOL =0.12V VIL =0.59V VIH =1.06V
V =V rDS = VDD
OL DD RD +rDS 1+RD/rDS
SubstitutingforrDS fromEq.(14.23)givesanexpressionforVOL identicaltothatinEq.(14.22).
(b) We observe that all the inverter parameters derived above are functions of VDD, Vt, and Vx only. Since VDD and Vt are determined by the process technology, the only design parameter available is Vx ≡ 1/kn RD . To place VM at half the supply voltage VDD , we substitute VM = VDD /2 in Eq. (14.13) to
obtainthevalueVx musthaveas
Vx
V /2−V2
= DD t (14.25)
VM = VDD/2
(c) For VDD = 1.8 V and Vt = 0.5, we use Eq. (14.25) to obtain
Vx VM = 0.9 V =
FromEq.(14.10): FromEq.(14.22): FromEq.(14.12): FromEq.(14.20):
NML = VIL − VOL = 0.47 V NMH =VOH −VIH =0.74V
(d) To determine RD, we use
Thus,
11.24 =25k
The inverter dissipates power only when the output is low, in which case the current drawn from the
supply is
IDD=VDD−VOL =1.8−0.12=67μA RD 25 k
and the power drawn from the supply during the low-output interval is PD =VDDIDD =1.8×67=121μW
Since the inverter spends half of the time in this state,
PDaverage = 1 PD = 60.5 μW 2
(e) We now can make a few comments on the characteristics of this inverter circuit in comparison to the ideal characteristics:
1. The output signal swing, though not equal to the full power supply, is reasonably good: VOH = 1.8 V, VOL = 0.12 V.
2. The noise margins, though of reasonable values, are far from the optimum value of VDD/2. This is particularly the case for NML .
3. Mostseriously,thegatedissipatesarelativelylargeamountofpower.Toappreciatethispoint,consider an IC chip with a million inverters (a small number by today’s standards): Its power dissipation will be 61 W. This is too large, especially given that this is “static power,” unrelated to the switching activity of the gates (more on this later).
We consider this inverter implementation to be entirely unsuitable for IC fabrication because each inverter requires a load resistance of 25 k, a value that needs a large chip area (see Appendix A). To overcome this problem, we investigate in Example 14.3 the replacement of the passive resistance RD with a PMOS transistor.
knRD = 1 = Vx
1 =11.24 0.089
14.2 Digital Logic Inverters 1111
R = 11.24 =
D kn′ (W/L) 300 × 10−6 × 1.5
1112 Chapter 14 CMOS Digital Logic Circuits
EXERCISES
D14.3 In an attempt to reduce the required value of RD to 10 k, the designer of the inverter in Example 14.2 decides to keep the parameter Vx unchanged but increases W/L. What is the new value required for W/L? Do the noise margins change? What does the power dissipation become? Ans. 3.75; no; 151 μW
D14.4 In an attempt to reduce the required value of RD to 10 k, the designer of the inverter in Example 14.2 decides to change Vx while keeping W/L unchanged. What new value of Vx is needed? What do the noise margins become? What does the power dissipation become?
Ans. Vx =0.22V;NML =0.46V,NMH =0.49V;139μW
Example 14.3
The Pseudo-NMOS Inverter
To eliminate the problem associated with the need for a large resistance RD in the circuit of Fig. 14.20(a), studiedinExample14.2,RD canbereplacedbyaMOSFET.OnesuchpossibilityisthecircuitinFig.14.21, where the load is a PMOS transistor QP whose gate is tied to ground in order to turn it on. Because of its resemblance to an earlier form of logic (NMOS logic, now obsolete) in which the load is an NMOS transistor, this circuit is known as a pseudo-NMOS inverter.
(a) Assumingλ1 =λ2 =0,Vtn =−Vtp =Vt,andkn =5kp,findVOH andVOL.
(b) For kn = 300 μA/V2, Vt = 0.4 V, and VDD = 1.8 V, evaluate the values of VOH and VOL and
find the average power dissipated in the inverter, assuming it spends half the time in each of its two states.
VDD
QP
iDP
vO
iDN vI QN
Figure 14.21 Pseudo-NMOS inverter for Example 14.3.
Solution
(a) TofindVOH,wesetvI =0.ClearlyQN willbeoffandconductingzerocurrent.TransistorQP alsowill be conducting zero current but because its VSG = VDD , it will be operating in the triode region with a zero voltage between its source and drain; thus the output voltage will be equal to VDD,
VOH =VDD
Next,wefindVOL bysettingvI =VDD.TransistorQN willbeconducting.SincetheoutputvoltageVOL
willlikelybelowandthuslowerthanVt,QP willbeoperatinginthesaturationregion,thus iDP = 1 kp(VDD −Vt)2
2
QN willbeoperatinginthetrioderegion,thus
i =k (V −V)V −1V2 DN n DD t OL 2OL
Equating iDP and iDN yields a quadratic equation in VOL that can be solved to obtain
VOL =(VDD −Vt) 1− 1−(kp/kn)
Here we have rejected the other root of the quadratic equation on the assumption that its value will be greaterthanVt andthuscontraveningouroriginalassumption.Thenumericalvaluescanbeusedto check these assumptions.
(b) Substituting the given numerical values we obtain
VOH =1.8V
VOL =0.15V
WenotethatVOL isindeedlowerthanVt,asoriginallyassumed.
The inverter dissipates power in only one of its two states; namely, when its output is low. In this case, QP is operating in saturation and
iDP = 1 kp(VDD −Vt)2 2
= 1 × 300 (1.8−0.4)2 25
= 58.8 μA and the power dissipation can be found from
P=iDPVDD =58.8×1.8=105.8μW The average power dissipation can now be found as
Pav = 1 ×105.8=52.9μW 2
14.2 Digital Logic Inverters 1113
1114 Chapter 14 CMOS Digital Logic Circuits
EXERCISE
14.5 It is required to find VM for the pseudo-NMOS inverter of Fig. 14.21. Recall that VM is defined as a value of vI that results in vO = VM . Convince yourself that because VM > Vt , QN will be operating in saturation and QP will be operating in the triode region. Hence show that
VDD −Vt VM =Vt + √r+1
when r ≡ kn/kP.
EvaluateVM forVDD =1.8V,Vt =0.4V,andr=5. Ans. 0.97 V
14.3 The CMOS Inverter
In this section we study the inverter circuit of the most widely used digital IC technology: CMOS. The basic CMOS inverter, synthesized in Section 14.1.2, is shown in Fig. 14.22. It utilizes two MOSFETs: one, QN , with an n channel and the other, QP , with a p channel. The body of each device is connected to its source, and thus no body effect arises. As will be seen shortly, the CMOS circuit realizes the conceptual inverter implementation studied in the previous section (Fig. 14.18), where a pair of switches are operated in a complementary fashion by the input voltage vI .
14.3.1 Circuit Operation
Wefirstconsiderthetwoextremecases:whenvI isatlogic-0level,whichis0V,andwhenvI is at logic-1 level, which is VDD volts. In both cases, for ease of exposition we shall consider the n-channel device QN to be the driving transistor and the p-channel device QP to be the
Figure 14.22 The CMOS inverter.
14.3 The CMOS Inverter 1115
VDD
vO0 rDSN
(a) (b)
Figure 14.23 Operation of the CMOS inverter when vI is high: (a) circuit with vI = VDD (logic-1 level, or
VOH ); (b) graphical construction to determine the operating point; (c) equivalent circuit.
load. However, since the circuit is symmetric, this assumption is obviously arbitrary, and the reverse would lead to identical results.
Figure 14.23 illustrates the case when v I = VDD , showing the iD −v DS characteristic curve for QN with vGSN = VDD. (Note that iD = i and vDSN = vO.) Superimposed on the QN characteristic curve is the load curve, which is the iD−vSD curve of QP for the case vSGP =0 V. Since vSGP < |Vt|, the load curve will be a horizontal straight line at zero current level. The operating point will be at the intersection of the two curves, where we note that the output voltage is zero and the current through the two devices is also zero. This means thatthepowerdissipationinthecircuitiszero.Note,however,thatalthoughQN isoperating at zero current and zero drain-source voltage (i.e., at the origin of the iD−vDS plane), the operating point is on a steep segment of the iD−vDS characteristic curve. Thus QN provides a low-resistance path between the output terminal and ground, with the resistance obtained using Eq. (5.13b) as
W
(c)
rDSN =1 kn′
Figure 14.23(c) shows the equivalent circuit of the inverter when the input is high.2 This circuit confirms that vO ≡ VOL = 0 V and that the power dissipation in the inverter is zero.
The other extreme case, when vI =0 V, is illustrated in Fig. 14.24. In this case QN is operating at v GSN = 0; hence its iD −v DS characteristic is a horizontal straight line at zero current level. The load curve is the iD−vSD characteristic of the p-channel device with vSGP = VDD. As shown, at the operating point the output voltage is equal to VDD, and the current in the two devices is still zero. Thus the power dissipation in the circuit is zero in both extreme states.
2InSection14.1wereferredtorDSN (andrDSP forp-channeldevices)asRon.
Ln
(VDD−Vtn) (14.26)
1116 Chapter 14 CMOS Digital Logic Circuits
VDD
rDSP
vO VDD
(a) (b)
Figure 14.24 Operation of the CMOS inverter when vI is low: (a) circuit with vI = 0 V (logic-0 level, or
VOL ); (b) graphical construction to determine the operating point; (c) equivalent circuit.
Figure 14.24(c) shows the equivalent circuit of the inverter when the input is low. Here we see that QP provides a low-resistance path between the output terminal and the dc supply VDD, with the resistance given by
W
rDSP = 1 kp′
The equivalent circuit confirms that in this case vO ≡ VOH = VDD and that the power dissipation in the inverter is zero.
It should be noted, however, that in spite of the fact that the quiescent current is zero, the load-driving capability of the CMOS inverter is high. For instance, with the input high, as in the circuit of Fig. 14.23, transistor QN can sink a relatively large load current. This current can quickly discharge the load capacitance, as will be seen shortly. Because of its action in sinkingloadcurrentandthuspullingtheoutputvoltagedowntowardground,transistorQN is known as the pull-down device. Similarly, with the input low, as in the circuit of Fig. 14.24, transistor QP can source a relatively large load current. This current can quickly charge up a load capacitance, thus pulling the output voltage up toward VDD. Hence, QP is known as the pull-up device. The reader will recall that we used this terminology in connection with the conceptual inverter circuit of Fig. 14.18 and in Section 14.1 as well.
From the above, we conclude that the basic CMOS logic inverter behaves as an ideal inverter. In summary:
1. The output voltage levels are 0 and VDD, and thus the signal swing is the maximum possible. This, coupled with the fact that the inverter can be designed to provide a symmetrical voltage-transfer characteristic, results in wide noise margins.
2. The static power dissipation in the inverter is zero (neglecting the dissipation due to leakage currents) in both of its states. This is because no dc path exists between the power supply and ground in either state.
3. A low-resistance path exists between the output terminal and ground (in the low-output state) or VDD (in the high-output state). These low-resistance paths ensure that the output voltage is 0 or VDD independent of the exact values of the W/L ratios or
(c)
Lp
VDD − Vtp (14.27)
other device parameters. Furthermore, the low output resistance makes the inverter
less sensitive to the effects of noise and other disturbances.
4. The active pull-up and pull-down devices provide the inverter with high output-driving
capability in both directions. As will be seen in Section 14.4, this speeds up the
operation considerably.
5. The input resistance of the inverter is infinite (because IG = 0). Thus the inverter can
drive an arbitrarily large number of similar inverters with no loss in signal level. Of course, each additional inverter increases the load capacitance on the driving inverter and slows down the operation. In Section 14.4, we will consider the inverter switching times.
W 1 iDN=kn′ (vI−Vtn)vO− v2O
Ln2
forvO≤vI−Vtn
forvO ≥vI −Vtn
(14.28)
(14.29)
(14.30)
(14.31)
14.3 The CMOS Inverter 1117
FRANK MARION WANLESS—THE INVENTOR OF CMOS:
While working for Fairchild Semiconductor in 1963, Frank Wanless filed the first patent on CMOS logic, heralding the new age of zero-static-power logic. In 1964, as director of research and engineering at General Microelectronics (a start-up later bought by Philco-Ford), he created the first commercial CMOS integrated circuit. The symmetry of the logic form Wanless had invented was at first emphasized by the use of the name COmplementary Symmetry MOS, or COS-MOS, but the simpler CMOS shorthand soon prevailed.
14.3.2 The Voltage-Transfer Characteristic (VTC)
The complete voltage-transfer characteristic (VTC) of the CMOS inverter can be obtained by repeating the graphical procedure, used above in the two extreme cases, for all intermediate values of vI. In the following, we shall calculate the critical points of the resulting voltage-transfercurve.Forthisweneedthei−vrelationshipsofQN andQP.ForQN,
and
For QP,
and
1 W iDN = kn′
2Ln
(vI −Vtn)2
iDP =kp′
Lp
VDD −vI − Vtp
1
(VDD −vO)− (VDD −vO)2
W
2
forvO ≥vI + Vtp
1
W
VDD−vI−Vtp
2
iDP= kp′ 2Lp
forvO≤vI+Vtp
1118 Chapter 14
CMOS Digital Logic Circuits
Slope 1
VM VDD 2
M
QN and QP in saturation
M
Figure 14.25 The voltage-transfer characteristic of the CMOS inverter when QN and QP are matched. The CMOS inverter is usually designed to have V = V = V . Also, although this is not
tn tp t
always the case, we shall assume that QN and QP are matched; that is, kn′ (W/L)n = kp′ (W/L)p.
It should be noted that since μp is 0.25 to 0.5 times the value of μn, to make k′(W/L) of the two devices equal, the width of the p-channel device is made two to four times that of the n-channel device. More specifically, the two devices are designed to have equal lengths, with widths related by
Wp = μn (14.32) Wn μp
This will result in kn′ (W/L)n = kp′ (W/L)p, and the inverter will have a symmetric transfer characteristic and equal current-driving capability in both directions (pull-up and pull-down). WithQN andQP matched,theCMOSinverterhasthevoltage-transfercharacteristicshown in Fig. 14.25. As indicated, the transfer characteristic has five distinct segments corresponding to different combinations of modes of operation of QN and QP. The vertical segment BC is obtained when both QN and QP are operating in the saturation region. Because we are neglecting the finite output resistance in saturation, that is, assuming λN = λP = 0, the inverter gain in this region is infinite. From symmetry, this vertical segment occurs at vI = VDD/2 and is bounded by vO(B)=VDD/2+Vt, at which value QP enters the triode region and vO(C)=
VDD/2−Vt,atwhichvalueQN entersthetrioderegion.
ThereaderwillrecallfromSection14.2.1thatinadditiontoVOL andVOH,twootherpoints on the transfer curve determine the noise margins of the inverter. These are the maximum permitted logic-0 or “low” level at the input, VIL , and the minimum permitted logic-1 or “high” level at the input, VIH . These are formally defined as the two points on the transfer curve at which the incremental gain is unity (i.e., the slope is – 1 V/V).
TodetermineVIH,wenotethatQN isinthetrioderegion,andthusitscurrentisgivenby Eq. (14.28), while QP is in saturation and its current is given by Eq. (14.31). Equating iDN and iDP, and assuming matched devices, gives
(vI −Vt)vO − 1v2O = 1(VDD −vI −Vt)2 22
DifferentiatingbothsidesrelativetovI resultsin
(v −V)dvO +v −v dvO =−(V −v −V)
in which we substitute vI = VIH and dvO/dvI = −1 to obtain vO =VIH −VDD
2
Substituting vI = VIH and for vO from Eq. (14.34) in Eq. (14.33) gives
VIH = 1(5VDD −2Vt) 8
(14.33)
(14.34)
(14.35)
14.3 The CMOS Inverter 1119
I tdv O Odv DD I t II
VIL can be determined in a manner similar to that used to find VIH . Alternatively, we can use the symmetry relationship
VIH − VDD = VDD − VIL 22
togetherwithVIH fromEq.(14.35)toobtain
VIL = 1(3VDD +2Vt)
8
The noise margins can now be determined as follows:
NMH =VOH −VIH
= VDD − 1 (5VDD − 2Vt )
8
= 1(3VDD +2Vt) 8
NML =VIL −VOL
= 1(3VDD +2Vt)−0
8
= 1(3VDD +2Vt) 8
(14.36)
(14.37)
(14.38)
1120 Chapter 14
CMOS Digital Logic Circuits
As expected, the symmetry of the voltage-transfer characteristic results in equal noise margins. Of course, if QN and QP are not matched, the voltage-transfer characteristic will no longer be symmetric, and the noise margins will not be equal.
14.3.3 The Situation When QN and QP Are Not Matched
In the above we assumed that QN and QP are matched; that is, in addition to Vtn = Vtp , the transconductance parameters kn and kp are made equal by selecting Wp/Wn according to Eq. (14.32). The result is a symmetrical VTC that switches at the midpoint of the supply; that is, VM = VDD /2. The symmetry, as we have seen, equalizes and maximizes the noise margins.
The price paid for obtaining a perfectly symmetric VTC is that the width of the p-channel device can be three to four times as large as that of the n-channel device. This can result in a relatively large silicon area, which, besides being wasteful of silicon real estate, can also result in increased device capacitances and a corresponding increase in the propagation delay of the inverter (Section 14.4). It is useful, therefore, to inquire into the effect of not matching QN andQP.TowardthatendwederiveanexpressionfortheswitchingvoltageVM asfollows.
Since at M, both QN and QP operate in saturation, their currents are given by Eqs. (14.29) and (14.31), respectively. Substituting vI = vO = VM , and equating the two currents results in
where
r+1
kp = μpWp kn μnWn
rV −V +V
tn
VM =
r =
DD tp
(14.39)
(14.40)
where we have assumed that QN and QP have the same channel length L, which is usually the
case with L equal to the minimum available for the given process technology. Note that the
matchedcasecorrespondstor=1.ForV =V ,andr=1,Eq.(14.39)yieldsV =V /2, tp tn M DD
as expected. For a given process, that is, given values for VDD, Vtn, and Vtp, one can plot VM versus the matching parameter r. Such a plot, for a 0.18-μm process, is shown in Fig. 14.26. We make the following two observations:
VM (V)
1.2 Vtn Vtp 0.5 V 1.0
0.8
0.6
0.4
0.2
VDD 1.8 V
0.5 1.0
1.5 2.0
r
Figure 14.26 Variation of the inverter switching voltage, VM , with the parameter r =
kp /kn .
1. VM increases with r. Thus, making kp > kn shifts VM toward VDD . Conversely, making kp < kn shifts VM toward 0.
2. VM is not a strong function of r. For the particular case shown, lowering r by a factor of2(from1to0.5),reducesVM byonly0.13V.
Observation 2 implies that if one is willing to tolerate a small reduction in NML , substantial savings in silicon area can be obtained. This point is illustrated in Example 14.4.
14.3 The CMOS Inverter 1121
Example 14.4 CMOS Inverter Static Characteristics and Design
Consider a CMOS inverter fabricated in a 0.18-μm process for which V = 1.8 V, V = V = 0.5 V,
DD tntp μn = 4μp, and μnCox = 300 μA/V2. In addition, QN and QP have L = 0.18 μm and (W/L)n = 1.5.
(a) Find Wp that results in VM = VDD /2 = 0.9 V. What is the silicon area utilized by the inverter in this case?
(b) Forthematchedcasein(a),findthevaluesofVOH,VOL,VIH,VIL,andthenoisemarginsNML andNMH. ForvI =VIH,whatvalueofvO results?Thiscanbeconsideredtheworst-casevalueofVOL.Similarly, forvI =VIL,findvO thatistheworst-casevalueofVOH.Now,usetheseworst-casevaluestodetermine more conservative values for the noise margins.
(c) For the matched case in (a), find the output resistance of the inverter in each of its two states.
(d) If λ = λ = 0.2 V−1, what is the inverter gain at v = V ? If a straight line is drawn through the point
np IM
vI = vO = VM with a slope equal to the gain, at what values of vI does it intercept the horizontal lines
vO = 0 and vO = VDD? Use these intercepts to estimate the width of the transition region of the VTC.
(e) If Wp = Wn, what value of VM results? What do you estimate the reduction of NML (relative to the
matched case) to be? What is the percentage savings in silicon area (relative to the matched case)?
(f) Repeat (e) for the case Wp = 2Wn . This case, which is frequently used in industry, can be considered
to be a compromise between the minimum-area case in (e) and the matched case.
Solution
(a)ToobtainVM =VDD/2=0.9V,weselectWp accordingtoEq.(14.32), Wp =μn =4
Wn μp SinceWn/L=1.5,Wn =1.5×0.18=0.27μm.Thus,
For this design, the silicon area is
Wp =4×0.27=1.08μm
A=WnL+WpL=L Wn +Wp
= 0.18(0.27 + 1.08) = 0.243 μm2
(b) VOH =VDD =1.8V VOL =0V
1122
Chapter 14 CMOS Digital Logic Circuits
Example 14.4 continued ToobtainVIH weuseEq.(14.35),
V = 15V −2V= 1(5×1.8−2×0.5)=1 V IH 8 DD t 8
ToobtainVIL weuseEq.(14.36),
V = 13V +2V= 1(3×1.8+2×0.5)=0.8 V
IL 8 DD t 8 We can now compute the noise margins as
NMH =VOH −VIH =1.8−1.0=0.8V NML =VIL −VOL =0.8−0=0.8V
As expected, NMH = NML , and their value is very close to the optimum value of VDD /2 = 0.9 V. For vI = VIH = 1V, we can obtain the corresponding value of vO by substituting in Eq. (14.34),
vO=VIH−VDD =1−1.8=0.1V 22
Thus,theworst-casevalueofVOL,thatis,VOLmax,is0.1V,andthenoisemarginNML reducesto NML =VIL −VOLmax =0.8−0.1=0.7V
From symmetry, we can obtain the value of vO corresponding to vI = VIL as vO =VDD −0.1=1.7V
Thustheworst-casevalueofVOH,thatis,VOHmin,is1.7V,andthenoisemarginNMH reducesto NMH =VOHmin−VIH =1.7−1=0.7V
Note that the reduction in the noise margins is slight.
(c) The output resistance of the inverter in the low-output state is
rDSN = 1 μnCox(W/L)n VDD −Vtn
= 1
300×10−6 ×1.5(1.8−0.5)
= 1.71 k
Since QN and QP are matched, the output resistance in the high-output state will be equal, that is, rDSP = rDSN = 1.71 k
(d) If the inverter is biased to operate at vI = vO = VM = 0.9 V, then each of QN and QP will be operating at an overdrive voltage VOV = VM − Vt = 0.9 − 0.5 = 0.4 V and will be conducting equal dc currents ID of
I=1μC W V2 D 2 n ox L OV
N
= 1 ×300×1.5×0.42 2
= 36 μA Thus, QN and QP will have equal transconductances:
gmn =gmp = 2ID = 2×36 =0.18mA/V2 VOV 0.4
Transistors QN and QP will have equal output resistances ro, V 1 1
ron =rop = A = ID
We can now compute the voltage gain at M as
|λ|ID
= =139k 0.2 × 36
14.3 The CMOS Inverter 1123
Av =− gmn +gmp ron∥rop
= −(0.18 + 0.18)(139 ∥ 139) = −25 V/V
When the straight line at M of slope −25 V/V is extrapolated, it intersects the line v O = 0 at [0.9 + 0.9/25] = 0.936 V and the line vO = VDD at 0.9 − 0.9/25 = 0.864 V. Thus the width of the transition region can be considered to be (0.936 − 0.864) = 0.072 V.
(e) For Wp = Wn , the parameter r can be found from Eq. (14.40),
r= μpWp = 1×1=0.5 μnWn 4
ThecorrespondingvalueofVM canbedeterminedfromEq.(14.39)as
VM =0.5(1.8−0.5)+0.5=0.77V 0.5+1
1124
Chapter 14 CMOS Digital Logic Circuits
Example 14.4 continued
Thus VM shifts by only −0.13 V. Without recalculating VIL we can estimate the reduction in NML to be approximatelyequaltotheshiftinVM,thatis,NML becomes0.8−0.13=0.67V.Thesiliconareaforthis design can be computed as follows:
A=L Wn +Wp =0.18(0.27+0.27) = 0.0972 μm2
This represents a 60% reduction from the matched case! (f) For Wp = 2Wn,
Thus, relative to the matched case, the shift in VM is only −0.07 V. We estimate that NML will decrease from0.8Vbythesameamount;thusNML becomes0.73V.Inthiscase,thesiliconarearequiredis
A=L Wn +Wp =0.18(0.27+0.54) = 0.146 μm2
which represents a 40% reduction relative to the matched case!
EXERCISES
14.6 Consider a CMOS inverter fabricated in a 0.13-μm process for which VDD = 1.2 V, Vtn = −Vtp = 0.4V, μn/μp = 4, and μnCox = 430 μA/V2. In addition, QN and QP have L = 0.13 μm and
11
r=
VM =0.707(1.8−0.5)+0.5=0.83V
×2=√ =0.707 2
4
0.707 + 1
(W/L)n = 1.0.
(a) Find Wp that results in VM = 0.6 V.
(b) For the matched case in (a), find the values of VOH, VOL, VIH, VIL, NMH, and NML.
(c) For the inverter in (a), find the output resistance in each of its two states.
(d) For a minimum-size inverter for which (W/L)p = (W/L)n = 1.0, find VM .
Ans. (a) 0.52 μm; (b) 1.2 V, 0 V, 0.65 V, 0.55 V, 0.55 V, 0.55 V; (c) 2.9k, 2.9k; (d) 0.53 V
D14.7 A CMOS inverter utilizes V =5 V, V =V =1 V, and μ C =2μ C =50 μA/V2. Find DDtntp noxpox
(W/L)n and (W/L)p so that VM = 2.5 V and so that for vI = VDD, the inverter can sink a current of 0.2 mA with the output voltage not exceeding 0.2 V.
Ans. (W/L)n ≃ 5; (W/L)p ≃ 10
14.4 Dynamic Operation of the CMOS Inverter 1125 14.4 Dynamic Operation of the CMOS Inverter
The speed of operation of a digital system (e.g., a computer) is determined by the propagation delay of the logic gates used to construct the system. Since the inverter is the basic logic gate of any digital IC technology, the propagation delay of the inverter is a fundamental parameter in characterizing the speed of a given technology. We begin our study of the dynamic operation of CMOS in Section 14.4.1 by considering the propagation delay of a general inverter circuit. There, we introduce key definitions and analysis methods that are applied in the CMOS case in Sections 14.4.2 and 14.4.3.
14.4.1 Propagation Delay
The propagation delay is the time the inverter takes to respond to a change at its input. To be specific, let us consider an inverter fed with the ideal pulse shown in Fig. 14.27(a). The resulting output signal of the inverter is shown in Fig. 14.27(b). We make the following two observations.
1. The output signal is no longer an ideal pulse. Rather, it has rounded edges; that is, the pulse takes some time to fall to its low value and to rise to its high value. We speak of this as the pulse having finite fall and rise times. We will provide a precise definition of these shortly.
2. There is a time delay between each edge of the input pulse and the corresponding change in the output of the inverter. If we define the “switching point” of the output as the time at which the output pulse passes through the half-point of its excursion, then we can define the propagation delays of the inverter as indicated in Fig. 14.27(b). Note that there are two propagation delays, which are not necessarily equal: the propagation delay for the output going from high to low, tPHL , and the propagation delay for the
vI VDD
0
VDD VDD
2
0
t
(a)
tPHL tPLH
(b)
t
Figure14.27 Aninverterfedwiththe ideal pulse in (a) provides at its output the pulse in (b). Two delay times are defined as indicated.
1126 Chapter 14
CMOS Digital Logic Circuits
output going from low to high, tPLH . The inverter propagation delay tP is defined as the average of the two,
tP ≡ 1(tPLH +tPHL) (14.41) 2
Having defined the inverter propagation delay, we now consider the maximum switching frequency of the inverter. From Fig. 14.27(b) we can see that the minimum period for each cycle is
Tmin = tPHL + tPLH = 2tP (14.42) Thus the maximum switching frequency3 is
fmax = 1 = 1 (14.43) Tmin 2tP
At this point the reader is no doubt wondering about the cause of the finite propagation time of the inverter. It is simply a result of the time needed to charge and discharge the various capacitances in the circuit. These include the MOSFET capacitances, the wiring capacitance, and the input capacitances of all the logic gates driven by the inverter. We will have a lot more to say about these capacitances and about the determination of tP shortly. For the time being, however, we make two important points:
1. A fundamental relationship in analyzing the dynamic operation of a circuit is
It = Q = CV (14.44)
That is, a current I flowing through a capacitance C for an interval t deposits a
charge Q on the capacitor, which causes the capacitor voltage to increase by V .
2. A thorough familiarity with the time response of single-time-constant (STC) circuits is of great help in the analysis of the dynamic operation of digital circuits. A review of this subject is presented in Appendix E. For our purposes here, we remind the reader
of the key equation in determining the response to a step function:
Consider a step-function input applied to an STC circuit of either the low-pass or high-pass type, and let the circuit have a time constant τ . The output at any time t is given by
y(t) = Y − Y − Y e−t/τ (14.45) ∞ ∞ 0+
where Y∞ is the final value, that is, the value toward which the response is heading, and Y0+ is the value of the response immediately after t = 0. This equation states that the output at any time t is equal to the difference between the final value Y∞ and a gap whose initial value is Y∞ – Y0+ and that is shrinking exponentially.
3This is a theoretical upper bound; practical circuits are operated at frequencies 10 to 20 times lower.
VDD
R
SC
(a)
0t vO
14.4 Dynamic Operation of the CMOS Inverter 1127
Example 14.5 Calculating the Propagation Delay of a Simple Inverter
Return to the inverter of Fig. 14.17(a) and consider the case where a capacitor C is connected between the
outputnodeandground.Ifatt=0,v goeslow,andassumingthattheswitchopensinstantaneously,find I
the time for v to reach 1 V + V . This is the low-to-high propagation time, t . Calculate the value
O 2OHOL
oftPLH forthecaseR=25kandC=10fF.
PLH
vI
vO
VDD
VOH 12 (VOH VOL )
VOL
t
0 tPLH
Figure14.28 Example14.5:(a)Theinvertercircuitaftertheswitchopens(i.e.,fort≥0+).(b)WaveformsofvI and vO. Observe that the switch is assumed to operate instantaneously. vO rises exponentially, starting at VOL and heading toward VOH .
Solution
Before the switch opens, vO = VOL. When the switch opens at t = 0, the circuit takes the form shown in Fig. 14.28(a). Since the voltage across the capacitor cannot change instantaneously, at t = 0+ the output will still be VOL. Then the capacitor charges through R, and vO rises exponentially toward VDD. The output waveform will be as shown in Fig. 14.28(b), and its equation can be obtained by substituting in Eq.(14.45):vO(∞)=VOH =VDD andvO(0+)=VOL.Thus,
v (t)=V −V −V e−t/τ O OH OH OL
where τ = CR. To find tPLH , we substitute
vt =1V +V
(b)
Thus,
which results in
O PLH 2 OH OL
1V +V =V −V −V e−tPLH/τ
OH OL OH OH OL
2
tPLH =τln2=0.69τ
1128
Chapter 14 CMOS Digital Logic Circuits
Example 14.5 continued
NotethatthisexpressionisindependentofthevaluesofVOL andVOH.Forthenumericalvaluesgiven,
tPLH =0.69RC
=0.69×25×103 ×10×10−15 = 173 ps
EXERCISES
14.8 A capacitor C whose initial voltage is 0 is charged to a voltage V
by a constant-current source I. Find the time tPLH at which the capacitor voltage reaches VDD /2 . What value of I is required to obtain
a 10-ps propagation delay with C = 10 fF and VDD = 1.8 V?
Ans. tPLH =CVDD/2I;0.9mA
14.9 For the inverter of Fig. 14.18(a), let the on-resistance of PU be 20 k and that of PD = 10 k. If the
capacitance C = 10 fF, find tPLH , tPHL , and tP . Ans. 138 ps; 69 ps; 104 ps
We conclude this section by showing in Fig. 14.29 the formal definition of the propagation delay of an inverter. As shown, an input pulse with finite (nonzero) rise and fall times is applied. The inverted pulse at the output exhibits finite rise and fall times (labeled tTLH and tTHL , where the subscript T denotes transition, LH denotes low to high, and HL denotes high to low). There is also a delay time between the input and output waveforms. The usual way to specify the propagation delay is to take the average of the high-to-low propagation delay, tPHL , and the low-to-high propagation delay, tPLH . As indicated, these delays are measured between the 50% points of the input and output waveforms. Also note that the transition times are specified using the 10% and 90% points of the output excursion (VOH − VOL ).
EXERCISE
14.10 AcapacitorC=100fFisdischargedfromavoltageVDD tozerothrougharesistanceR=2k.Find the fall time tf of the capacitor voltage.
Ans. tf ≃ 2.2CR = 0.44 ns
DD
14.4 Dynamic Operation of the CMOS Inverter 1129
Figure 14.29 Definitions of propagation delays and transition times of the logic inverter.
14.4.2 Determining the Propagation Delay of the CMOS Inverter
Our strategy for determining the propagation delay of the CMOS inverter consists of two steps:
1. Replace all the capacitances in the circuit; that is, the various capacitances associated with QN and QP, the capacitance of the wire that connects the output of the inverter to other circuits, and the input capacitance of the logic gates the inverter drives, by a single equivalent capacitance C connected between the output node of the inverter and ground.
2. Analyze the resulting capacitively loaded inverter to determine its tPLH and tPHL , and hence tP.
We shall study these two separable steps in reverse order. Thus, in this section we show how the propagation delay can be determined. Then, in Section 14.4.3, we show how to calculate the value of C.
Figure 14.30(a) shows a CMOS inverter with a capacitance C connected between its output node and ground. To determine the propagation delays tPHL and tPLH , we apply to the input an ideal pulse, that is, one with zero rise and fall times, as shown in Fig. 14.30(b). Since the circuit has a symmetric structure, the analyses to determine the two propagation delays will besimilar.Therefore,wewillderivetPHL indetailandextrapolatetheresulttodeterminetPLH.
Just prior to the leading edge of the input pulse (i.e., at t = 0−), the output voltage is equal to VDD and capacitor C is charged to this voltage. At t = 0, vI rises to VDD, causing QP to turn off and QN to turn on. From then on, the circuit is equivalent to that shown in Fig. 14.30(c), with the initial value of v O = VDD . Thus, at t = 0+, QN will operate in the saturation region and will supply a relatively large current to begin the process of discharging C. Figure 14.30(d) showsthetrajectoryoftheoperatingpointofQN asCisdischarged.Hereweareinterestedin
1130 Chapter 14
CMOS Digital Logic Circuits
(a)
resulting in
IavtPHL =C[VDD−(VDD/2)]
tPHL = CVDD (14.46) 2Iav
(c)
(d)
Figure 14.30 Dynamic operation of a capacitively loaded CMOS inverter: (a) circuit; (b) input and output waveforms; (c) equivalent circuit during the capacitor discharge; (d) trajectory of the operating point as the input goes high and C discharges through QN .
the interval tPHL during which vO reduces from VDD to VDD/2. Correspondingly, the operating pointofQN movesfromEtoM.Foraportionofthistime,correspondingtothesegmentEF of the trajectory, QN operates in saturation. Then at F, v O = VDD − Vt , and QN enters the triode region.
A simple approach for determining tPHL consists of first calculating the average value of the current supplied by QN over the segment EM. Then, we use this average value of the discharge current to determine tPHL by means of the charge balance equation
t PLH
The value of Iav can be found as follows:
Iav = 1[iDN(E)+iDN(M)]
2
1 W kn′
2Ln
(14.47)
(14.48)
(14.49)
(14.50)
(14.51)
14.4 Dynamic Operation of the CMOS Inverter 1131
where
and
iDN(E)=
(VDD −Vtn)2
W
Ln 222
V 1V 2 iDN(M)=kn′ (VDD −Vtn) DD − DD
Note that we have assumed λn = 0. Combining Eqs. (14.46) to (14.49) provides tPHL = αnC
kn′ (W/L)nVDD
where αn is a factor determined by the relative values of Vt and VDD;
2 αn = 2 7 − 3Vtn + Vtn
4 VDD VDD
The value of αn typically falls in the range of 1 to 2.
An expression for the low-to-high inverter delay, tPLH , can be written by analogy to the
tPHL expression in Eq. (14.50),
where
tPLH = αp
kp′ (W/L)pVDD
2 α =2 7−3Vtp +Vtp
(14.52)
(14.53)
p 4 VDD VDD
Finally, the propagation delay tP can be found as the average of tPHL and tPLH ,
tP = 1(tPHL +tPLH) 2
Examination of the formulas in Eqs. (14.50) to (14.53) enables us to make a number of useful observations:
1. As expected, the two components of tP can be equalized by selecting the (W/L) ratios to equalize kn and kp, that is, by matching QN and QP. This assumes that αn = αp, which obtains when Vtn = −Vtp.
1132 Chapter 14
CMOS Digital Logic Circuits
2. Since tP is proportional to C, the designer should strive to reduce C. This is achieved by using the minimum possible channel length and by minimizing wiring and other parasitic capacitances. Careful layout of the chip can result in significant reduction in such capacitances.
3. Using a process technology with larger transconductance parameter k′ can result in shorter propagation delays. Keep in mind, however, that for such processes Cox is increased, and thus the value of C increases at the same time (more on this later).
4. Using larger W/L ratios can result in a reduction in tP. Care, however, should be exercised here also, since increasing the size of the devices increases the value of C, and thus the expected reduction in tP might not materialize. Reducing tP by increasing W/L, however, is an effective strategy when C is dominated by components not directly related to the size of the driving device (such as wiring or fan-out devices).
5. A larger supply voltage VDD results in a lower tP. However, VDD is determined by the process technology and thus is often not under the control of the designer. Furthermore, modern process technologies in which device sizes are reduced require lower VDD (see Appendix K). A motivating factor for lowering VDD is the need to keep the dynamic power dissipation at acceptable levels, especially in very-high-density chips. We will have more to say on this point in Section 14.6.
These observations clearly illustrate the conflicting requirements and the trade-offs available in the design of a CMOS digital integrated circuit (and indeed in any engineering design problem).
AnAlternativeApproach TheformulasderivedabovefortPHL andtPLH underestimatethe delay values for inverters implemented in deep-submicron technologies. This arises because of the velocity-saturation effect, which we shall discuss briefly in Section 15.1. There we will see that velocity saturation results in lower MOSFET currents in the saturation region, and hence in increased delay times. To deal with this problem, we present a very simple alternative approach to estimating the inverter propagation delay.
Figure 14.31 illustrates the alternative approach. During the discharge delay tPHL , QN is replaced by an equivalent resistance RN . Similarly, during the charging delay tPLH , QP is replaced by an equivalent resistance RP . It is easy to show that
and
tPHL =0.69RNC
(14.54)
(14.55)
(14.56) (14.57)
tPLH =0.69RPC EmpiricalvalueshavebeenfoundforRN andRP,
RN = 12.5 k (W/L)n
RP = 30 k (W/L)p
14.4
Dynamic Operation of the CMOS Inverter 1133
VDD
0
VDD
vO
vO
iDN
VDD
vI QP
N2
VDD QNC R CVDD
(a)
vI 0
t
0 tPHL t
VDD vO VDD
VDD
RP
v
O2
C00tPLH t
00t C
Figure 14.31 Equivalent circuits for determining the propagation delays (a) tPHL and (b) tPLH of the inverter.
(b)
Furthermore, it has been found that these values apply for a number of CMOS fabrication processes including 0.25 μm, 0.18 μm, and 0.13 μm (see Hodges et al., 2004).
As a final point, we note that the delay expressions in Eqs. (14.54) and (14.55) are obtained by assuming that the inverter is driven by a step-input voltage. In the more practical case of a ramp-input voltage, it has been shown that the 0.69 factor approaches unity, thus
tPHL ≃ RnC (14.54′)
and
tPLH ≃ RpC (14.55′) Example 14.6 Determining the Propagation Delay of the CMOS Inverter
Forthe0.25-μmprocesscharacterizedbyVDD =2.5V,Vtn =−Vtp =0.5V,kn′ =3.5kp′ =110μA/V2,find tPLH , tPHL , and tP for an inverter for which (W/L)n = 1.5 and (W/L)p = 3, and for C = 10 fF. Use both the approach based on average currents and that based on equivalent resistances, and compare the results obtained. If to save on power dissipation, the inverter is operated at VDD = 2.0 V, by what factor does tP change?
1134
Chapter 14 CMOS Digital Logic Circuits
Example 14.6 continued
Solution
(a) Using the average current approach, we determine from Eq. (14.51),
and using Eq. (14.50),
SinceV =V , tp tn
αn= 2 2=1.7 7−3×0.5+ 0.5
4 2.5 2.5
1.7×10×10−15
tPHL = 110×10−6 ×1.5×2.5 =41.2 ps
αp =αn =1.7 andwecandeterminetPLH fromEq.(14.52)as
1.7×10×10−15
tPLH =(110/3.5)×10−6×3×2.5=72.1ps
The propagation delay can now be found as
t=1t +t
P 2 PHL PLH
= 1 (41.2 + 72.1) = 56.7 ps
2 (b)Usingtheequivalent-resistanceapproach,wefirstfindRN fromEq.(14.56)as
RN =12.5=8.33k 1.5
and then use Eq. (14.54) to determine tPHL ,
tPHL =0.69×8.33×103 ×10×10−15 =57.5 ps
Similarly we use Eq. (14.57) to determine RP ,
RP = 30 = 10 k 3
and Eq. (14.55) to determine tPLH ,
tPLH =0.69×10×103 ×10×10−15 =69 ps
Thus,whilethevalueobtainedfortPHL ishigherthanthatfoundusingaveragecurrents,thevaluefortPLH is about the same. Finally, tP can be found as
tP = 1(57.5+69)=63.2 ps 2
which is a little higher than the value found using average currents.
To find the change in propagation delays obtained when the inverter is operated at VDD = 2.0 V, we
have to use the method of average currents. (The dependence on the power-supply voltage is absorbed in theempiricalvaluesofRN andRP.)UsingEq.(14.51),wewrite
αn= 2 2=1.9 7−3×0.5+ 0.5
422 ThevalueoftPHL cannowbefoundbyusingEq.(14.50):
1.9×10×10−15
tPHL = 110×10−6 ×1.5×2 =57.6 ps
14.4 Dynamic Operation of the CMOS Inverter 1135
Similarly, the value of αp = αn = 1.9 can be substituted in Eq. (14.52) to obtain, 1.9×10×10−15
and tP can be calculated as
tPLH =(110/3.5)×10−6×3×2=100.8ps tP = 1(57.6+100.8)=79.8 ps
2
Thus, as expected, reducing VDD has resulted in increased propagation delay.
Before leaving the subject of propagation delay, we should emphasize that hand analysis using the simple formulas above should not be expected to yield precise results. Rather, its value is in obtaining design insight. Precise results can always be obtained using SPICE and Multisim simulations (see examples in Appendix B and the extensive material on the website). However, it is never a good idea to use simulation if one does not know beforehand approximate values of the expected results.
1136 Chapter 14 CMOS Digital Logic Circuits
EXERCISES
14.11 For a CMOS inverter fabricated in a 0.18-μm process with VDD = 1.8 V, Vtn = −Vtp = 0.5 V, kn′ = 4kp′ = 300 μA/V2 , and having (W/L)n = 1.5 and (W/L)p = 3, find tPHL , tPLH , and tP when the
equivalent load capacitance C = 10 fF. Use the method of average currents.
Ans. 24.8 ps; 49.6 ps; 37.2 ps
D14.12 ForaCMOSinverterfabricatedina0.13-μmprocess,usetheequivalent-resistancesapproachto
determine (W/L)n and (W/L)p so that tPLH = tPHL = 50 ps when the effective load capacitance C = 20 fF.
Ans. 3.5; 8.3
14.4.3 Determining the Equivalent Load Capacitance C
Having determined the propagation delay of the CMOS inverter in terms of the equivalent load capacitance C, it now remains to determine the value of C. For this purpose, a thorough understanding of the various capacitances in a MOS transistor is essential, and we urge the reader to review the material in Section 10.2.1.
Figure 14.32 shows the circuit for determining the propagation delay of the CMOS inverter formed by Q1 and Q2. Note that we are showing the inverter driving a similar inverter formed by transistors Q3 and Q4. This reflects a practical situation and will help us explain how to determine the contribution of a driven inverter to the equivalent capacitance C at the output of the inverter under study (that formed by Q1 and Q2).
Indicated in Fig. 14.32 are the various transistor capacitances that connect to the output node of the Q1−Q2 inverter. Also shown is the wiring capacitance Cw, which represents
VDD
VDD
Cg4
Q2
Q4
Cdb2
Cgd2
vO
VDD
0tvI CwQ3
Q1
Cg3
Figure 14.32 Circuit for analyzing the propagation delay of the inverter formed by Q1 and Q2, which is driving a similar inverter formed by Q3 and Q4.
Cdb1
Cgd1
Cgd1
14.4 Dynamic Operation of the CMOS Inverter 1137
V
V 2Cgd1 2 Cgd1
Figure 14.33 The Miller multiplication of the feedback capacitance Cgd1.
the capacitance of the wire or interconnect that connects the output of the Q1−Q2 inverter to the input of the Q3−Q4 inverter. Interconnect capacitances have become increasingly dominant as the technology has scaled down. In fact, some digital IC designers hold the view that interconnect poses a greater limitation on the speed of operation than the transistors themselves. We will discuss this topic briefly in Section 15.1.
A glance at the circuit in Fig. 14.32 should be sufficient to indicate that a pencil-and-paper analysis is virtually impossible. That, of course, is the reason we opted for the simplification of replacing all these capacitances with an equivalent capacitance C. Before we consider the determination of C, it is useful to observe that during tPLH or tPHL, the output of the first inverter changes from 0 to VDD/2 or from VDD to VDD/2, respectively. Assuming that the switching threshold of the second inverter is VDD /2, it follows that the second inverter remains in the same state during each of our analysis intervals. This observation will have an important bearing on our estimation of the equivalent input capacitance of the second inverter. Let’s now consider the contribution of each of the capacitances in Fig. 14.32 to the value of the equivalent load capacitance C:
1. The gate–drain overlap capacitance of Q1 , Cgd 1 , can be replaced by an equivalent capacitance between the output node and ground of 2Cgd1. The factor 2 arises because of the Miller effect (Section 10.3.3). Specifically, refer to Fig. 14.33 and note that as vI goes high and vO goes low by the same amount, the change in voltage across Cgd1 is twice that amount. Thus the output node sees in effect twice the value of Cgd1. The same applies for the gate–drain overlap capacitance of Q2, Cgd 2 , which can be replaced by a capacitance 2Cgd 2 between the output node and ground.
2. Each of the drain–body capacitances Cdb1 and Cdb2 has a terminal at a constant voltage. Thus for the purpose of our analysis here, Cdb1 and Cdb2 can be replaced with equal capacitances between the output node and ground. Note, however, that the formulas given in Section 10.2.1 for calculating Cdb1 and Cdb2 are small-signal relationships, whereas the analysis here is obviously a large-signal one. A technique has been developed for finding equivalent large-signal values for Cdb1 and Cdb2 (see Hodges et al., 2004 and Rabaey et al., 2003).
3. Since the second inverter does not switch states, we will assume that the input capacitances of Q and Q remain approximately constant and equal to the total
3 4
gate capacitance WLCox + Cgsov + Cgdov . That is, the input capacitance of the load
inverter will be
Cg3 +Cg4 =(WL)3Cox +(WL)4Cox +Cgsov3 +Cgdov3 +Cgsov4 +Cgdov4 (14.58)
V
V
1138 Chapter 14 CMOS Digital Logic Circuits
4. The last component of C is the wiring capacitance Cw, which simply adds to the
value of C.
Thus, the total value of C is given by
C=2Cgd1 +2Cgd2 +Cdb1 +Cdb2 +Cg3 +Cg4 +Cw (14.59)
Example 14.7 Determining the Effective Load Capacitance C and the Propagation Delay
Consider a CMOS inverter fabricated in a 0.25-μm process for which Cox = 6 fF/μm2 , μn Cox =110 μA/V2 , μpCox =30 μA/V2, Vtn =–Vtp =0.5 V, and VDD =2.5 V. The W/L ratio of QN is 0.375 μm/0.25 μm, and that for QP is 1.125 μm/0.25 μm. The gate–source and gate–drain overlap capacitances are specified to be 0.3 fF/μm of gate width. Further, the effective (large-signal) values of drain–body capacitances are Cdbn = 1 fF and Cdbp = 1 fF. The wiring capacitance Cw =0.2 fF. Find tPHL, tPLH, and tP when the inverter is driving an identical inverter.
Solution
First, we determine the value of the equivalent capacitance C using Eqs. (14.58) and (14.59), C=2Cgd1 +2Cgd2 +Cdb1 +Cdb2 +Cg3 +Cg4 +Cw
where
Thus,
Cgd1 =0.3×Wn =0.3×0.375=0.1125fF Cgd2 =0.3×Wp =0.3×1.125=0.3375fF Cdb1 =1fF
Cdb2 =1fF
Cg3 =0.375×0.25×6+2×0.3×0.375=0.7875fF Cg4 =1.125×0.25×6+2×0.3×1.125=2.3625fF
Cw =0.2fF
C = 2 × 0.1125 + 2 × 0.3375 + 1 + 1 + 0.7875 + 2.3625 + 0.2 = 6.25 fF
Next we use Eqs. (14.51) and (14.52) to determine tPHL ,
αn= 2 2=1.7
7−3×0.5+ 0.5 4 2.5 2.5 1.7 × 6.25 × 10−15
tPHL = 110 × 10−6 × (0.375/0.25) × 2.5 = 25.8 ps
Similarly, we use Eqs. (14.53) and (14.54) to determine tPLH , αp =1.7
Finally, we determine tP as
EXERCISES
1.7 × 6.25 × 10−15
tPLH = 30 × 10−6 × (1.125/0.25) × 2.5 = 31.5 ps
tP = 1(25.8+31.5)=28.7 ps 2
14.5 Transistor Sizing 1139
14.13 ConsidertheinverterspecifiedinExample14.7whenloadedwithanadditional0.1-pFcapacitance. What will the propagation delay become?
Ans. 488 ps
14.14 In an attempt to decrease the area of the inverter in Example 14.7, (W/L)p is made equal to (W/L)n. What is the percentage reduction in area achieved? Find the new values of C, tPHL, tPLH, and tP. Assume that Cdbp does not change significantly.
Ans. 50%; 4.225 fF; 17.4 ps; 63.8 ps; 40.6 ps
14.15 FortheinverterofExample14.7,findthetheoreticalmaximumfrequencyatwhichitcanbeoperated. Ans. 17.4 GHz
14.5 Transistor Sizing
In this section we address the extremely important design question of selecting appropriate sizes (i.e., L and W/L values) for all transistors in a CMOS logic circuit. We begin with the CMOS inverter and then consider general logic gates.
14.5.1 Inverter Sizing
In this section we are concerned with the selection of appropriate values for the channel length L and the (W/L) ratios for the two transistors QN and QP in an inverter. Our reasoning can be summarized as follows.
1. To minimize area, the length of all channels is usually made equal to the minimum length permitted by the given technology.
1140 Chapter 14
CMOS Digital Logic Circuits
2. In a given inverter, if our interest is strictly to minimize area, (W/L)n is usually selected in the range 1 to 1.5. The selection of (W/L)p relative to (W/L)n has influence on the noisemarginsandtPLH.BothareoptimizedbymatchingQP andQN.This,however,is usually wasteful of area and, equally important, can increase the effective capacitance C,sothatalthoughtPLH ismadeequaltotPHL,thevalueofbothcanbehigherthanin the case without matching (see Problem 14.55). Thus, selecting (W/L)p = (W/L)n is a possibility, and (W/L)p = 2(W/L)n is a frequently used compromise.
3. Having settled on an appropriate ratio of (W/L)p to (W/L)n, we still have to select (W/L)n to reduce tP and thus allow higher speeds of operation. Any increase in (W/L)n and proportionally in (W/L)p will of course increase area, and hence the inverter contribution to the value of the equivalent capacitance C. To be more precise we express C as the sum of an intrinsic component Cint contributed by QN and QP of the inverter, and an extrinsic component Cext resulting from the wiring and the input capacitance of the driven gates,
C = Cint + Cext (14.60) Increasing (W/L)n and (W/L)p of the inverter by a factor S relative to that of a
minimum-size inverter for which Cint = Cint0 results in
C = SCint0 + Cext (14.61)
Now, if we use the equivalent-resistances approach to compute tP and define an equivalent inverter resistance Req as
Req = 1(RN +RP) (14.62) 2
then,
tP =0.69ReqC (14.63) Further, if for the minimum-size inverter Req is Req0, increasing (W/L)n and (W/L)p
by the factor S reduces Req by the same factor: Req =Req0/S
Combining Eqs. (14.63), (14.64), and (14.61), we obtain
R
tP =0.69 eq0 (SCint0 +Cext)
S
1 tP = 0.69 Req0 Cint0 + S Req0 Cext
(14.64)
(14.65)
We thus see that scaling the W/L ratios does not change the component of tP caused by the capacitances of QN and QP. It does, however, reduce the component of tP that results from capacitances external to the inverter itself. It follows that one can use Eq. (14.65) to decide on a suitable scaling factor S that keeps tP below a specified maximum value, keeping in mind of course the effect of increasing S on silicon area.
14.5 Transistor Sizing 1141
EXERCISE
14.16 FortheinverteranalyzedinExample14.7:
(a) Find the intrinsic and extrinsic components of C.
(b) By what factor must (W/L)n and (W/L)p be increased to reduce the extrinsic part of tP by a
factor of 2?
(c) EstimatetheresultingtP.
(d) By what factor is the inverter area increased?
Ans. (a) 2.9 fF, 3.35 fF; (b) 2; (c) 21 ps; (d) 2
FEDERICO FAGGIN—A PIONEER IN MICROPROCESSOR ELECTRONICS:
Holder of a degree in physics from the University of Padua, Federico Faggin first worked for SGS-Fairchild in Italy. In 1968 he relocated to California, joining Fairchild in Palo Alto, where he developed the silicon-gate MOS device that has dominated MOS production ever since. In 1970 he joined Intel, where he led the design and production of the Intel 4004, the world’s first commercial single-chip microcomputer, introduced in 1971. This design was based on a four-chip version with separated memory that Ted Hoff had designed in 1969 in response to the request by a Japanese calculator company for a twelve-chip flexible design. The 4004, a 4-bit processor, included 2300 PMOS logic circuits (a long-obsolete logic-circuit form) on a 3 mm × 4 mm die, using a random-logic process created by Faggin. Subsequently, Faggin was responsible for the 8008 at Intel, and the Z80 8-bit microprocessor at Zilog (which he founded in 1974). Later, he went on to cofound several other companies, including Synaptics (in 1986 with Carver Mead and others), which provided touch-sensitive pad and screen designs for the mobile and PC products of many manufacturers.
14.5.2 Transistor Sizing in CMOS Logic Gates
Once a CMOS gate circuit has been generated, the only significant step remaining in the
design is to decide on W/L ratios for all devices. These ratios usually are selected to provide
the gate with current-driving capability in both directions equal to that of the basic inverter.
Forthebasicinverterdesign,denote(W/L) =nand(W/L) =p,wherenisusually1to1.5
np
and, for a matched design, p = μn /μp n; it should be noted, however, that often p = 2n and
for minimum area p = n. Thus, we wish to select individual W/L ratios for all transistors in a logic gate so that the PDN should be able to provide a capacitor discharge current at least equal to that of an NMOS transistor with W/L = n, and the PUN should be able to provide a charging current at least equal to that of a PMOS transistor with W/L = p. This will guarantee a worst-case gate delay equal to that of the basic inverter.4
4 This statement assumes that the total effective capacitance C of the logic gate is the same as that of the inverter. In actual practice, the value of C will be larger for a gate, especially as the fan-in is increased.
1142 Chapter 14
CMOS Digital Logic Circuits
In the preceding description, the idea of “worst case” should be emphasized. It means that in deciding on device sizing, we should find the input combinations that result in the lowest output current and then choose sizes that will make this current equal to that of the basic inverter. Before we consider examples, we need to address the issue of determining the current-driving capability of a circuit consisting of a number of MOS devices. In other words, we need to find the equivalent W/L ratio of a network of MOS transistors. Toward that end, we consider the parallel and series connection of MOSFETs and find the equivalent W/L ratios.
The derivation of the equivalent W/L ratio is based on the fact that the on-resistance of a MOSFET is inversely proportional to W/L (see Eqs. 14.56 and 14.57). Thus, if a number of MOSFETs having ratios of (W/L)1, (W/L)2, . . ., are connected in series, the equivalent series resistance obtained by adding the on-resistances will be
Rseries =RN1 +RN2 +...
= constant + constant +...
(W/L)1 (W/L)2
11 (W/L) + (W/L) + . . .
(W/L)eq
resulting in the following expression for (W/L)eq for transistors connected in series:
= constant = constant
12
(W/L)eq = 1 (14.66) 1 + 1 +...
(W/L)1 (W/L)2
Similarly, we can show that the parallel connection of transistors with W/L ratios of (W/L)1,
(W/L)2,..., results in an equivalent W/L of
(W/L)eq =(W/L)1 +(W/L)2 +... (14.67)
As an example, two identical MOS transistors with individual W/L ratios of 4 result in an equivalent W/L of 2 when connected in series and of 8 when connected in parallel.5
As an example of proper sizing, consider the four-input NOR in Fig. 14.34. Here, the worst case (the lowest current) for the PDN is obtained when only one of the NMOS transistors is conducting. We therefore select the W/L of each NMOS transistor to be equal to that of the NMOS transistor of the basic inverter, namely, n. For the PUN, however, the worst-case situation (and indeed the only case) occurs when all inputs are low and the four series PMOS transistors are conducting. Since the equivalent W/L will be one-quarter of that of each PMOS device, we should select the W/L ratio of each PMOS transistor to be four times that of QP of the basic inverter, that is, 4p.
5Another way of thinking about this is as follows: Connecting MOS transistors in series is equivalent to adding the lengths of their channels while the width does not change; connecting MOS transistors in parallel does not change the channel length but increases the width to the sum of the W ’s.
14.5 Transistor Sizing 1143
VDD
A 4p B 4p C 4p D 4p
YABCD
Annnn BCD
Figure14.34 Propertransistorsizingforafour-inputNORgate.NotethatnandpdenotetheW/Lratiosof QN andQP,respectively,ofthebasicinverter.
VDD
pppp
BCD
Y ABCD
A 4n B 4n C 4n D 4n
Figure 14.35 Proper transistor sizing for a four-input NAND gate. Note that n and p denote the W/L ratios ofQN andQP,respectively,ofthebasicinverter.
As another example, we show in Fig. 14.35 the proper sizing for a four-input NAND gate. Comparison of the NAND and NOR gates in Figs. 14.34 and 14.35 indicates that because p is usually two to three times n, the NOR gate will require much greater area than the NAND gate. For this reason, NAND gates are generally preferred for implementing combinational-logic functions in CMOS.
A
1144 Chapter 14 CMOS Digital Logic Circuits
Example 14.8 Transistor Sizing of a CMOS Gate
Provide transistor W/L ratios for the logic circuit shown in Fig. 14.36. Assume that for the basic inverter
n = 1.5 and p = 5 and that the channel length is 0.25 μm.
B
VDD
D QPD (3.75/0.25) QPB
(1.875/0.25)
C
QPC (3.75/0.25)
A
QPA (3.75/0.25)
B
A
QNA (0.375/0.25) C
Y
QNB (0.75/0.25)
QNC QND (0.75/0.25) (0.75/0.25)
Figure 14.36 Circuit for Example 14.8.
Solution
Refer to Fig. 14.36, and consider the PDN first. We note that the worst case occurs when QNB is on and either QNC or QND is on. That is, in the worst case, we have two transistors in series. Therefore, we select each of QNB, QNC, and QND to have twice the width of the n-channel device in the basic inverter, thus
QNB: W/L = 2n = 3 = 0.75/0.25 QNC: W/L = 2n = 3 = 0.75/0.25 QND: W/L = 2n = 3 = 0.75/0.25
For transistor QNA, select W/L to be equal to that of the n-channel device in the basic inverter: QNA: W/L = n = 1.5 = 0.375/0.25
Next, consider the PUN. Here, we see that in the worst case, we have three transistors in series: QPA, QPC, and QPD. Therefore, we select the W/L ratio of each of these to be three times that of QP in the basic inverter, that is, 3p, thus
QPA: W/L = 3p = 15 = 3.75/0.25 QPC: W/L = 3p = 15 = 3.75/0.25 QPD: W/L = 3p = 15 = 3.75/0.25
Finally, the W/L ratio for QPB should be selected so that the equivalent W/L of the series connection of QPB and QPA should be equal to p. It follows that for QPB the ratio should be 1.5p,
QPB : W/L = 1.5p = 7.5 = 1.875/0.25 Figure 14.36 shows the circuit with the transistor sizes indicated.
14.5.3 Effects of Fan-In and Fan-Out on Propagation Delay
Each additional input to a CMOS gate requires two additional transistors, one NMOS and one PMOS. This is in contrast to other forms of MOS logic, where each additional input requires only one additional transistor, such as in the pseudo-NMOS logic, whose basic inverter was considered in Example 14.3 and which will be studied in some detail in the next chapter. The additional transistor in CMOS not only increases the chip area but also increases the total effective capacitance per gate and in turn increases the propagation delay. The size-scaling method described earlier compensates for some (but not all) of the increase in tP . Specifically, by increasing device size, we are able to preserve the current-driving capability. However, the capacitance C increases because of both the increased number of inputs and the increase in device size. Thus tP will still increase with fan-in, a fact that imposes a practical limit on the fan-in of, say, the NAND gate to about 4. If a higher number of inputs is required, then “clever” logic design should be adopted to realize the given Boolean function with gates of no more than four inputs. This would usually mean an increase in the number of cascaded stages and thus an increase in delay. However, such an increase in delay can be less than the increase due to the large fan-in (see Problem 14.59).
An increase in a gate’s fan-out adds directly to its load capacitance and, thus, increases its propagation delay.
Thus although CMOS has many advantages, it does suffer from increased circuit complexity when the fan-in and fan-out are increased, and from the corresponding effects of this complexity on both chip area and propagation delay. In Chapter 15, we shall study some simplified forms of CMOS logic that attempt to reduce this complexity, although at the expense of forgoing some of the advantages of basic CMOS.
14.5 Transistor Sizing 1145
1146 Chapter 14 CMOS Digital Logic Circuits
EXERCISES
14.17 ForaprocesstechnologywithL=0.18μm,n=1.5,p=3,givethesizesofalltransistorsin(a)a four-input NOR and (b) a four-input NAND. Also, give the relative areas of the two gates.
Ans.
(a) NMOS devices: W/L = 0.27/0.18, PMOS devices: 2.16/0.18;
(b) NMOS devices: W/L = 1.08/0.18, PMOS devices: 0.54 /0.18; NOR area/NAND area = 1.5
14.18 For the scaled NAND gate in Exercise 14.17, find the ratio of the maximum to minimum current available to (a) charge a load capacitance and (b) discharge a load capacitance.
Ans. (a) 4; (b) 1
14.5.4 Driving a Large Capacitance
In many cases in digital CMOS design, a logic gate must drive a large load capacitance. This might, for example, be due to a long wire on a chip, or to a requirement to drive an off-chip printed-circuit board trace, where the load capacitance can be several hundred times larger than the parasitic capacitances of the driving gate.
Let’s investigate how to drive such a large load capacitance without causing the propagation delay to be unacceptably large. Figure 14.37(a) shows the large capacitive load CL driven by a standard inverter. Note that we have simplified the model of the inverter by assuming that all its capacitances can be lumped into a capacitance C between its input and ground and that it has an effective output resistance R. Connecting CL directly to the inverter output results in a propagation delay, assuming a ramp input, equal to the time constant τ ,
tP =τ=CLR (14.68)
This propagation delay can be very large.
In an attempt to reduce the propagation delay, we can make the driver inverter large. Such
a case is shown in Fig. 14.37(b), where an inverter m times larger than the standard inverter is used. Its output resistance will be R/m, that is, m times lower than that of the standard inverter. As a result, the propagation delay in this case will be
τ = CL(R/m) = 1 CLR (14.69) m
which as desired has been reduced by a factor m. However, all is not well. Observe that the input capacitance of the large inverter is mC, which can be very large, requiring a large driving inverter to ensure that it does not contribute significantly to lengthening the overall propagation delay. Thus, it appears that we have not solved the problem, but rather shifted the burden to another inverter to drive the input of our large inverter.
The above reasoning leads to the idea of a chain of inverters connected in cascade, as shown in Fig. 14.37(c). Here we have n inverters of progressively larger sizes. In fact, it has been found that the optimum (i.e., lowest overall propagation delay) is obtained when each inverter in the chain is larger than the preceding inverter by the same factor x. Thus if inverter 1 has a unit
R R/m 1m
14.5 Transistor Sizing 1147
C CL mC CL τ= C R τ= 1C R
LmL (a) (b)
R R/x R/x2
1 x x2 x3 xn–1
1234n
R/x3
R/xn–1
C xC
τ1 = xCR
x2C x3C
τ2 = xCR τ3 = xCR
τtotal = nxCR
(c)
xn–1C CL
τn = CLR/xn–1 = xCR
for xn = CL/C
Figure14.37 DrivingalargeloadcapacitanceCL:(a)directly;(b)byutilizingalargeinverter;(c)byusing a chain of progressively larger inverters.
size, inverter 2 has a size x, inverter 3 has a size x2, and so on. Figure 14.37(c) shows the effect of inverter size scaling on its input capacitance and its equivalent output resistance. Observe that the delay time associated with the interface between each two succeeding inverters is τ = xCR; that is, each interface contributes equally to the overall delay. This, of course, is a result of the geometric size scaling of the inverters in this chain. It has been shown that minimum delay is obtained if this equality of time constants extends to the output node, that is, by making
R τn ≡CL xn−1
equal to xCR, which can be achieved if
xn = CL C
in which case the overall delay becomes
tP = τtotal = nxCR
(14.70)
(14.71)
1148 Chapter 14
CMOS Digital Logic Circuits
The question of selecting values for x and n remains. First, observe that there is already one condition on their values, namely, that in Eq. (14.70). It can be shown mathematically that the second condition that leads to minimum propagation delay (see Problem 14.62) is
x = e = 2.718 (14.72) In practice, it has been found that values for x between 2.5 and 4 lead to optimum performance
(see Hodges et al., 2004).
Example 14.9 Design of an Inverter Chain to Drive a Large Load Capacitance
An inverter whose input capacitance C = 10 fF and whose equivalent output resistance R = 1 k must
ultimately drive a load capacitance CL = 1 pF.
(a) What is the time delay that results if the inverter is connected directly to CL ?
(b) IfadriverchainsuchasthatinFig.14.37(c)isused,howmanyinvertersnandwhatsizeratioxshould
you use to minimize the total delay? What is the total path delay achieved?
Solution
(a) tP = τ = CL R = 10−12 × 103 = 1 ns.
(b) The delay is minimized by selecting
and
which yields
x = e = 2.718 n CL 10−12
x = C =10×10−15 =100
n= ln100 = ln100 =4.6 lnx lne
Since we must use an integral number of inverters, we select n=5
and obtain x from which yields
The total path delay will be
xn=x5=CL =100 C
x = (100)1/5 = 2.51
tP =nxCR
=5×2.51×10×10−15 ×103 =125.5ps
which is a reduction in delay by a factor of about 8!
14.6 Power Dissipation
Many of today’s integrated circuits are battery powered. Some even rely on “scavenged” energy, therefore severely limiting the supply of power. Other high-performance circuits, such as those found at computer server farms, have heat-dissipation limitations. Also, the desire to pack an ever-increasing number of gates on an IC chip (many millions at present) while keeping the power dissipated in the chip to an acceptable limit, has made attending to the power dissipated in a logic-gate circuit of paramount importance. Indeed, at the present time, minimizing power dissipation in digital ICs is perhaps the most important design challenge.
In this section, we look at sources of power consumption in digital CMOS circuits and present some metrics that are used in power optimization.
14.6.1 Sources of Power Dissipation
LetusreturntotheinverterofFig.14.17,whichdissipatesnopowerwhenvI islowandthe switch is open. In the other state, however, the power dissipation is approximately V 2 /R and
DD
can be substantial, as we saw in Examples 14.2 and 14.3. This power dissipation occurs even if the inverter is not switching and is thus known as static power dissipation.
Another inverter we studied earlier (see Fig. 14.18), which is the basis for the CMOS inverter, exhibits no static power dissipation, a definite advantage. Unfortunately, however, another component of power dissipation arises when a capacitance exists between the output node of the inverter and ground. As we have already seen, this is always the case, for the devices that implement the switches have internal capacitances, the wires that connect the inverter output to other circuits have capacitance, and, of course, there is the input capacitance of whatever circuit the inverter is driving. Now, as the inverter is switched from one state to another, current must flow through the switch(es) to charge (and discharge) the load capacitance. These currents give rise to power dissipation in the switches, called dynamic power dissipation.
An expression for the dynamic power dissipation of the inverter of Fig. 14.18 can be derived as follows. Consider first the situation when vI goes low. The pull-down switch PD turnsoffandthepull-upswitchPU turnson.Inthisstate,theinvertercanberepresentedbythe equivalent circuit shown in Fig. 14.38(a). Capacitor C will charge through the on-resistance of the pull-up switch, and the voltage across C will increase from 0 to VDD. Denoting by iD(t) the charging current supplied by VDD, we can write for the instantaneous power drawn from
VDD RPU
CRPD C
14.6 Power Dissipation 1149
Figure 14.38 Equivalent circuits for calculating the
dynamic power dissipation of the inverter in Figure 14.18: (a) (b) (a)whenvI islow;(b)whenvI ishigh.
1150 Chapter 14
CMOS Digital Logic Circuits
VDD the expression
pDD(t)=VDDiD(t)
The energy delivered by the power supply to charge the capacitor can be determined by
integrating pDD(t) over the charging interval Tc, Tc
0
=VDDQ
where Q is the charge delivered to the capacitor during the charging interval. Since the initial
charge on C was zero,
Thus,
Q=CVDD
E = CV 2 DD DD
Since at the end of the charging process the energy stored on the capacitor is E = 1CV2
(14.73)
(14.74)
(14.75)
EDD =
=VDD iD(t)dt
0
VDDiD(t)dt Tc
stored 2 DD
we can find the energy dissipated in the pull-up switch as
E =E −E = 1CV2 dissipated DD stored 2 DD
Thisenergyisdissipatedintheon-resistanceofswitchPU andisconvertedtoheat.
Next consider the situation when vI goes high. The pull-up switch PU turns off and the pull-down switch PD turns on. The equivalent circuit in this case is that shown in Fig. 14.38(b). Capacitor C is discharged through the on-resistance of the pull-down switch, and its voltage changes from VDD to 0. At the end of the discharge interval, there will be no energy left on the
capacitor. Thus all of the energy initially stored on the capacitor, 1 CV 2
2 DD
in the pull-down switch,
E = 1CV2 dissipated 2 DD
This amount of energy is dissipated in the on-resistance of switch PD and is converted to heat.
, will be dissipated
(14.76)
14.6 Power Dissipation 1151 Thus in each cycle of inverter switching, an amount of energy of 1 CV 2 is dissipated in
the pull-up switch and 1 CV 2
2 DD
cycle of
2 DD
is dissipated in the pull-down switch, for a total energy loss per
E /cycle = CV 2 (14.77) dissipated DD
If the inverter is switched at a frequency of f Hz, the dynamic power dissipation of the inverter will be
P = fCV 2 (14.78) dyn DD
This is a general expression that does not depend on the inverter circuit details or the values of the on-resistance of the switches.
The expression in Eq. (14.78) indicates that to minimize the dynamic power dissipation, one must strive to reduce the value of C. However, in many cases C is largely determined by the transistors of the inverter itself and cannot be substantially reduced. Another important factor in determining the dynamic power dissipation is the power-supply voltage VDD. Reducing VDD reduces Pdyn significantly. This has been a major motivating factor behind the reduction of VDD with every technology generation (see Appendix K). Thus, while the 0.5-μm CMOS process utilized a 5-V power supply, the power-supply voltage used with the 0.13-μm process is only 1.2 V.
Finally, since Pdyn is proportional to the operating frequency f, one may be tempted to reduce Pdyn by reducing f. However, this is not a viable proposition in light of the desire to operate digital systems at increasingly higher speeds. These newer chips, however, pack much more circuitry on the chip (as many as 2.75 billion transistors) and operate at higher frequencies (microprocessor clock frequencies above 5 GHz are now available). The dynamic power dissipation of such high-density chips can be over 100 W.
In addition to the dynamic power dissipation that results from the periodic charging and discharging of the inverter load capacitance, there is another component of power dissipation in the CMOS inverter that results from the current that flows through QP and QN during every switching event. Figure 14.39 shows this inverter current as a function of the input voltage
Figure 14.39 The current in the CMOS inverter versus the input voltage.
1152 Chapter 14
CMOS Digital Logic Circuits
vI for a matched inverter. We note that the current peaks at VM = VDD/2. Since at this voltage both QN and QP operate in saturation, the peak current is given by
1 WV 2
I =μC DD−V (14.79)
peak 2 n ox L n 2 tn
ThewidthofthecurrentpulsewilldependontherateofchangeofvI withtime;theslower the rising edge of the input waveform, the wider the current pulse and the greater the energy drawn from the supply. In general, however, this power component is usually much smaller than Pdyn.
EXERCISES
14.19 Find the dynamic power dissipation of the inverter analyzed in Example 14.7 when operated at a 1-GHz frequency. Recall that C = 6.25 fF and VDD = 2.5 V.
Ans. 39 μW.
14.20 Find the dynamic power dissipation of a CMOS inverter operated from a 1.8-V supply and having a load capacitance of 100 fF. Let the inverter be switched at 100 MHz.
Ans. 32.4 μW
14.21 Aparticularinvertercircuitinitiallydesignedina0.5-μmprocessisfabricatedina0.13-μmprocess. Assuming that the capacitance C will scale down in proportion to the minimum feature size (more on this in the next chapter) and that the power supply will be reduced from 5 V to 1.2 V, by what factor do you expect the dynamic power dissipation to decrease? Assume that the switching frequency f remains unchanged.
Ans. 66.8
14.6.2 Power–Delay and Energy–Delay Products
One is usually interested in high-speed operation (low tP) combined with low power dissipation. Unfortunately, these two requirements are often in conflict: Generally, if the designer of an inverter attempts to reduce power dissipation by, say, decreasing the supply voltage VDD, or the supply current, or both, the current-driving capability of the inverter decreases. This in turn results in longer times to charge and discharge the load and parasitic capacitances, and thus the propagation delay increases. It follows that a figure of merit for comparing logic-circuit technologies is the power–delay product (PDP) of the basic inverter of the given technology, defined as
PDP ≡ PD tP (14.80)
where PD is the power dissipation of the inverter. Note that the PDP is an energy quantity and has the units of joules. The lower the PDP, the more effective the inverter and the logic circuits based on the inverter are.
14.6 Power Dissipation 1153 For CMOS logic circuits, the static power dissipation of the inverter is zero,6 and thus PD
is equal to Pdyn and given by Eq. (14.78),
P =fCV2
Thus for the CMOS inverter,
D DD
PDP = fCV 2 t (14.81) DD P
If the inverter is operated at its theoretical maximum switching speed given by Eq. (14.43), then
PDP = 1 CV 2 (14.82) 2 DD
From our earlier discussion of dynamic power dissipation we know that 1 CV 2
2 DD
is the amount of energy dissipated during each charging or discharging event of the capacitor, that is, for each output transition of the inverter. Thus, the PDP has an interesting physical
interpretation: It is the energy consumed by the inverter for each output transition. Although the PDP is a valuable metric for comparing different technologies for implementing inverters, it is not useful as a design parameter for optimizing a given inverter circuit. To appreciate this point, observe that the expression in Eq. (14.82) indicates that the PDP can be minimized by reducing VDD as much as possible while, of course, maintaining proper circuit operation. This, however, would not necessarily result in optimal performance, for tP will increase as VDD is reduced. The problem is that the PDP expression in Eq. (14.82) does not in fact have information about tP. It follows that a better metric can be obtained by multiplying the energy per transition by the propagation delay. We can thus define the
energy–delay product EDP as
EDP ≡ Energy per transition × tP
= 1CV2 t (14.83) 2 DDP
We will utilize the EDP in later sections.
EXERCISE
14.22 For the CMOS inverter analyzed in Example 14.7, it was found that C = 6.25 fF, VDD = 2.5 V, and tP = 28.7 ps. Find the power–delay product when the inverter is operated at its theoretical maximum possible operating frequency. Also find EDP.
Ans. 19.5fJ;5.6×10−25 J·s.
6The exception to this statement is the power dissipation due to leakage currents and subthreshold conduction in the MOSFETs, discussed in Section 15.1.4.
1154 Chapter 14 CMOS Digital Logic Circuits Summary
A CMOS logic gate consists of an NMOS pull-down
network (PDN) and a PMOS pull-up network (PUN). The
PDN conducts for every input combination that requires a
low output. Since an NMOS transistor conducts when its
and capacitance. For minimum area, Wp = Wn. Also, a frequently used compromise is Wp = 2Wn .
For minimum area, (W/L)n is selected equal to 1. However, to reduce tP especially when a major part of C is extrinsic to the inverter, (W/L)n and correspondingly (W/L)p can be increased.
CMOS logic circuits are usually designed to provide equal current-driving capability in both directions. Furthermore, the worst-case values of the pull-up and pull-down currents are made equal to those of the basic inverter. Transistor sizing is based on this principle and makes use of the equivalent W/L ratios of series and parallel devices (Eqs. 14.66 and 14.67).
An important performance parameter of the inverter is the amount of power it dissipates. There are two components of power dissipation: static and dynamic. The first is the result of current flow in either the 0 or 1 state or both. The second occurs when the inverter is switched and has a capacitor load C. Dynamic power dissipation P =fCV2 .
dissipation is the power–delay product, PDP = PDtP.
The lower the PDP, the more effective the logic-circuit
family is. If dynamic power is dominant, such as in
CMOS, the delay-power product for an inverter operated
at its theoretical maximum switching frequency is PDP =
1 CV 2 , which is the energy drawn from the supply for a 2 DD
0-to-1 and a 1-to-0 transition.
Besides speed of operation and power dissipation, the silicon area required for an inverter is the third significant metric in digital IC design.
Predominantly because of its low power dissipation and because of its scalability, CMOS is by far the most dominant technology for digital IC design. This situation is expected to continue for many years to come.
Table 14.2 provides a summary of the important charac- teristics of the CMOS inverter.
input is high, the PDN is most directly synthesized from
the expression for the low output Y as a function of
the uncomplemented inputs. In a complementary fashion, the PUN conducts for every input combination that corresponds to a high output. Since a PMOS conducts when its input is low, the PUN is most directly synthesized from the expression for a high output (Y) as a function of the complemented inputs.
The digital logic inverter is the basic building block of digital circuits, just as the amplifier is the basic building block of analog circuits.
The static operation of a logic inverter is described by its voltage-transfer characteristic (VTC). The VTC determines the inverter noise margins; refer to Fig. 14.13, Fig. 14.15, and to Table 14.1 for the definitions of important VTC points and the noise margins. In particular, notethatNMH =VOH −VIH andNML =VIL −VOL,andrefer to the ideal VTC in Fig. 14.16.
The inverter is implemented using transistors operating as voltage-controlled switches. There are three possible arrangements, shown in Figs. 14.17, 14.18, and 14.19. The arrangement in Fig. 14.18 results in a high-performance inverter and is the basis for the CMOS inverter studied in Section 14.3.
The speed of operation of the inverter is characterized
delay, tP . Refer to Fig. 14.29 for
dyn DD
A metric that combines speed of operation and power
by its propagation the definitions of t
and t , and note that t = PHL P
PLH
1t+t. 2 PLH PHL
Digital ICs usually utilize the minimum channel length of the technology available. Thus for the CMOS inverter, QN and QP have L = Lmin . If matching is desired, Wp /Wn is selected equal to μn /μp at the expense of increased area
()
Summary 1155
PROBLEMS
Computer Simulation Problems
Problems identified by the Multisim/PSpice icon are intended to demonstrate the value of using SPICE simulation to verify hand analysis and design, and to investigate important issues such as gate noise margins and propagation delays. Instructions to assist in setting up PSpice and Multisim simulations for all the indicated problems can be found in the corresponding files on the website. Note that if a particular parameter value is not specified in the problem statement, you are to make a reasonable assumption.
Section 14.1: CMOS Logic-Gate Circuits
D 14.1 Consider MOS transistors fabricated in a 65-nm processforwhichμnCox =470μA/V2,μpCox =190μA/V2, Vtn =−Vtp =0.35V,andVDD =1V.
(a) Find Ron of an NMOS transistor with W/L = 1.5.
(b) Find Ron of a PMOS transistor with W/L = 1.5.
(c) If Ron of the PMOS device is to be equal to that of the
NMOS device in (a), what must (W/L)p be?
D 14.2 The CMOS inverter of Fig. 14.2(b) is implemented in a 0.13-μm process for which μn Cox = 500 μA/V2 , μp Cox = 125μA/V2,Vtn =−Vtp =0.4V,andVDD =1.2V.TheNMOS transistor has (W/L)n = 1.5.
(a) What must (W/L)p be if QN and QP are to have equal Ron resistances?
(b) Find the value of Ron.
D 14.3 Give the CMOS circuit that realizes a three-input
NOR gate.
D 14.4 GivetheCMOScircuitforathree-inputNANDgate.
D 14.5 Find the PUN that corresponds to the PDN shown in Fig. P14.5, and hence the complete CMOS logic circuit. What is the Boolean function realized?
D 14.6 Find the PUN that corresponds to the PDN shown in Fig. P14.6, and hence the complete CMOS logic circuit. What is the Boolean function realized?
Y
A
BC
Figure P14.6
D 14.7 Find the PDN that corresponds to the PUN shown in Fig. P14.7, and hence the complete CMOS logic circuit. What is the Boolean function realized?
VDD
A
BCD
Figure P14.7
Y
Y
A
Figure P14.5
B C
D 14.8 Give the CMOS realization for the Boolean function Y =(A+B)(C+D)
D 14.9 Find the PDN that is the dual of the PUN in Fig. 14.10(a) and hence give a CMOS realization of the exclusive-OR (XOR) function.
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
CHAPTER 14 PROBLEMS
D 14.10 Provide a CMOS logic gate circuit that realizes the function
Y =ABC+ABC+ABC
How many transistors are required? Explore the possibility of
reducing the number of the transistors required.
D 14.11 Sketch a CMOS logic circuit that realizes the function Y = AB + A B. This is called the equivalence or coincidence function.
D 14.12 Sketch a CMOS logic circuit that realizes the function Y = ABC + A B C.
D 14.13 It is required to design a CMOS logic circuit that realizes a three-input, even-parity checker. Specifically, the output Y is to be low when an even number (0 or 2) of the inputs A, B, and C are high.
(a) Give the Boolean function Y.
(b) Sketch a PDN directly from the expression for Y. Note
that it requires 12 transistors in addition to those in the
inverters.
(c) From inspection of the PDN circuit, reduce the number
of transistors to 10 (not counting those in the inverters).
(d) Find the PUN as a dual of the PDN in (c), and hence the
complete realization.
D 14.14 GiveaCMOSlogiccircuitthatrealizesthefunction of a three-input, odd-parity checker. Specifically, the output is to be high when an odd number (1 or 3) of the inputs are high. Attempt a design with 10 transistors (not counting those in the inverters) in each of the PUN and the PDN.
D 14.15 Design a CMOS full-adder circuit with inputs A, B,andC,andtwooutputsSandC0 suchthatSis1ifoneor three inputs are 1, and C0 is 1 if two or more inputs are 1.
Section 14.2: Digital Logic Inverters
14.16 A particular logic inverter is specified to have VIL =0.9 V, VIH =1.2 V, VOL =0.2 V, and VOH =1.8 V. Find thehighandlownoisemargins,NMH andNML.
14.17 Thevoltage-transfercharacteristicofaparticularlogic inverter is modeled by three straight-line segments in the manner shown in Fig. 14.13. If VIL = 1.2 V, VIH = 1.3 V, VOL =0.4V,andVOH =1.8V,find:
(a) the noise margins
(b) the value of VM
(c) the voltage gain in the transition region
14.18 For a particular inverter design using a power supply VDD, VOL =0.1VDD, VOH =0.8VDD, VIL = 0.4VDD, and VIH =0.6VDD.Whatarethenoisemargins?Whatisthewidth of the transition region? For a minimum noise margin of 0.4 V, what value of VDD is required?
14.19 A logic-circuit family that used to be very popular is transistor–transistor logic (TTL). The TTL logic gates and other building blocks are available commercially in small-scale-integrated (SSI) and medium-scale-integrated (MSI) packages. Such packages can be assembled on printed-circuit boards to implement a digital system. The device data sheets provide the following specifications of the basic TTL inverter (of the SN7400 type):
Logic-1 input level required to ensure a logic-0 level at the output: MIN (minimum) 2 V
Logic-0 input level required to ensure a logic-1 level at the output: MAX (maximum) 0.8 V
Logic-1 output voltage: MIN 2.4 V, TYP (typical) 3.3 V Logic-0 output voltage: TYP 0.22 V, MAX 0.4 V Logic-0-level supply current: TYP 3 mA, MAX 5 mA Logic-1-level supply current: TYP 1 mA, MAX 2 mA
(a) Find the worst-case values of the noise margins.
(b) Assuming that the inverter is in the logic-1 state 50% of the time and in the logic-0 state 50% of the time, find the average power dissipation in a typical circuit.
The power supply is 5 V.
14.20 Consider an inverter implemented as in Fig. 14.17(a). Let VDD =2.5 V, R=2k, Ron =100, VIL =0.8 V, and VIH =1V.
(a) Find VOL, VOH, NMH, and NML.
(b) TheinverterisdrivingNidenticalinverters.Eachofthese
load inverters, or fan-out inverters as they are usually called, is specified to require an input current of 0.2 mA when the input voltage (of the fan-out inverter) is high and zero current when the input voltage is low. Noting that the input currents of the fan-out inverters will have to be supplied through R of the driving inverter, find the resulting value of VOH and of NMH as a function of the number of fan-out inverters N. Hence find the maximum value N can have while the inverter is still providing an NMH valueapproximatelyequaltoitsNML.
Problems 1157
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
1158 Chapter 14 CMOS Digital Logic Circuits
(c) Find the power dissipation in the inverter in the two cases: (i) the output is low, and (ii) the output is high and driving the maximum fan-out found in (b).
14.21 For an inverter employing a 2-V supply, suggest an idealsetofvaluesforVM,VIL,VIH,VOL,VOH,NML,NMH.Also, sketch the VTC. What value of voltage gain in the transition region does your ideal specification imply?
14.22 For a particular inverter, the basic technology used provides an inherent limit to the small-signal, low-frequency voltage gain of 50 V/V. If, with a 2-V supply, the values of VOL and VOH are ideal, but VM = 0.4VDD, what are the best possiblevaluesofVIL andVIH thatcanbeexpected?Whatare the best possible noise margins you could expect? Find the large-signal voltage gain, where the gain is defined by (VOH − VOL )/(VIL − VIH ). (Hint: Use straight-line approximations for the VTC.)
*14.23 A logic-circuit type intended for use in a
digital-signal-processing application in a newly developed
hearing aid can operate down to single-cell supply voltages
of 1.2 V. If for its inverter, the output signals swing between
0 and VDD, the “gain-of-one” points are separated by less
than 1 V , and the noise margins are within 30% of one 3 DD
another, what ranges of values of VIL , VIH , VOL , VOH , NML , and NMH can you expect for the lowest possible battery supply?
D 14.24 Design the inverter circuit in Fig. 14.12(a) to provide VOH = 1.2 V, VOL = 50 mV, and so that the current drawn from the supply in the low-output state is 30 μA. The transistor has Vt = 0.4 V, μnCox = 500 μA/V2, and λ = 0. Specify the required values of VDD, RD, and W/L. How much power is drawn from the supply when the output is high? When the output is low?
14.25 For the current-steering circuit in Fig. 14.19, VCC = 2 V, IEE = 0.5 mA, find the values of RC1 and RC2 to obtain a voltage swing of 0.5 V at each output. What are the values realizedforVOH andVOL?
D 14.26 Refer to the analysis of the resistive-load MOS inverter in Example 14.2 and utilize the expressions derived there for the various inverter parameters. Design the cir- cuit to satisfy the following requirements: VOH = 1.2 V,
VOL = 50 mV, and the power dissipation in the low-output state = 60 μW. The transistor available has Vt = 0.4 V, μn Cox = 500 μA/V2 , and λ = 0. Specify the required values ofVDD,RD,andW/L.WhatarethevaluesobtainedforVIL,VM, VIH, NML, and NMH?
D 14.27 Refer to the analysis of the resistive-load MOS inverter in Example 14.2 and utilize the expressions derived there for the various inverter parameters. For a technology for which Vt = 0.3VDD, it is required to design the inverter to obtain VM = VDD /2. In terms of VDD , what is the required value of the design parameter Vx ? What values are obtained for VOH, VOL, VIL, VIH, NMH, and NML, in terms of VDD? Give numerical values for the case VDD = 1.2V. Now, express the power dissipated in the inverter in its low-output state in terms of the transistor’s W/L ratio. Let kn′ = 500 μA/V2. If the power dissipation is to be limited to approximately 100 μW, what W/L ratio is needed and what value of RD corresponds?
14.28 Anearlierformoflogiccircuits,nowobsolete,utilized
NMOS transistors only and was appropriately called NMOS
logic. The basic inverter, shown in Fig. P14.28, utilizes an
NMOS driver transistor Q and another NMOS transistor 1
CHAPTER 14 PROBLEMS
Q2, connected as a diode, forms the load of the inverter. Observe that Q operates in saturation at all times. Assume
2
V =V =V,λ =λ =0,anddenote k /k byk .Also
t1 t2 t 1 2 n1 n2 r neglect the body effect in Q2 (note that the body of Q2, not
shown, is connected to ground).
VDD
Q2
Q1
Figure P14.28
vI
i
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
CHAPTER 14 PROBLEMS
(a) Sketch i–v for Q2 and hence show that for vI low (i.e., vI < Vtn ), the output voltage will be VOH = VDD − Vt . (Hint: Although Q2 will be conducting zero current, it will have a voltage drop of Vt .)
(b) Taking VIL as the value of vI at which Q1 begins to conduct and vO begins to fall, find VIL .
(c) Find the relationship between vO and vI in the transition region. This is the region for which vI > Vt and both Q1 and Q2 are operating in saturation. Show that the relationship is linear and find its slope.
(d) If VOL ≃ 0 V, find the current IDD drawn from VDD and hence the average power dissipation in the inverter, assuming that it spends half the time in each of its two states.
(e) Find numerical values for all the parameters asked for
aboveforthecaseVDD =1.8V,Vt =0.5V,(W/L)1 =5,
(W/L) = 1,andμ C =300μA/V2. 25 nox
14.29 For the pseudo-NMOS inverter analyzed in Exam- ple 14.3 and in Exercise 14.5, what is the value of r that results inVM =VDD/2=0.9V?
14.30 Repeat Example 14.3 for a pseudo-NMOS inverter
fabricated in a 0.13-μm CMOS technology for which VDD =
and QP have L = 0.25μm and (W/L)n = 1.5. Investigate the variation of VM with the ratio Wp /Wn . Specifically, calculate VM for (a) Wp = 3.5W n (the matched case), (b) Wp = Wn (the minimum-size case); and (c) Wp = 2W n (a compromise case). For cases (b) and (c), estimate the approximate reduction in NML and silicon area relative to the matched case (a).
14.33 For a technology in which Vtn = 0.3VDD, show
that the maximum current that the inverter can sink
while its low-output level does not exceed 0.1 VDD is
0.065 k′ (W/L) V2 . For V = 1.3V, k′ = 500 μA/V2, find n nDD DD n
(W/L)n that permits this maximum current to be 0.1 mA.
14.34 A CMOS inverter for which kn = 5kp = 200 μA/V2 and Vt = 0.5 V is connected as shown in Fig. P14.34 to a sinusoidal signal source having a The ́venin equivalent voltage of 0.1-V peak amplitude and resistance of 100k. What signal voltage appears at node A with vI = +1.5 V? With vI=–1.5V?
Q
Problems 1159
1.2V,|V|=0.4V,k /k =5,andk =500μA/V2.FindV ,
t n p n OH 100 k
P
N
VOL , IDD , and the average power dissipation Pav . Also, use the vI
expression given in Exercise 14.5 to evaluate VM . Q
Section 14.3: The CMOS Inverter
14.31 Consider a CMOS inverter fabricated in a 65-nm
CMOS process for which VDD = 1 V, Vtn = −Vtp = 0.35 V, Figure P14.34 andμnCox =2.5μpCox =470μA/V2.Inaddition,QN andQP haveL=65nmand(W/L)n =1.5.
A 100-mV signal
(a) Find Wp that results in VM = VDD/2. What is the silicon area utilized by the inverter in this case?
(b) For the matched case in (a), find the values of VOH , VOL , VIH, VIL, NML, and NMH.
(c) For the matched case in (a), find the output resistance of the inverter in each of its two states.
14.32 Consider a CMOS inverter fabricated in a
0.25-μmCMOSprocessforwhichVDD=2.5V,Vtn=−Vtp= 0.5 V, and μnCox = 3.5 μpCox = 115μA/V2. In addition, QN
D 14.35 There are situations in which QN and QP of the CMOS inverter are deliberately mismatched to realize a certain desired value for VM . Show that the value required of the parameter r of Eq. (14.40) is given by
VM −Vtn r=V −V−V
For a 0.13-μm process characterized by Vtn = −Vtp = 0.4 V, VDD=1.3V,andμn=4μp,findtheratioWp/Wn requiredto obtain VM = 0.6VDD .
DD tp M
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
1160 Chapter 14 CMOS Digital Logic Circuits
14.36 ConsidertheCMOSinverterofFig.14.22withQN and QP matched and with the input vI rising slowly from 0 to VDD. AtwhatvalueofvI doesthecurrentflowingthroughQN and QP reach its peak? Give an expression for the peak current, neglecting λn and λp. For kn′ = 500 μA/V2, (W/L)n = 1.5, VDD = 1.3 V, and Vtn = 0.4V, find the value of the peak current.
14.37 Repeat Example 14.4 for a CMOS inverter fabricated in a 0.13-μm process for which VDD = 1.3 V, Vtn =| Vtp | =
S
CR
Figure P14.39
14.40 For the inverter circuit in Fig. P14.40, let vI go from VDD to0Vatt=0.Att=0+,vO =VOL.Findexpressionsfor VOH , vO(t), and tPLH . If R = 10 k, what is the largest value ofCthatensuresthattPLH isatmost100ps?
VDD
R
0.4 V, μ =4μ , and μ C =500μA/V2. In addition, Q n p nox
N
andQ haveL=0.13μmand(W/L) =1.5.Forpart(a)use Pn
V =V /2=0.65V. M DD
Section 14.4: Dynamic Operation of the CMOS Inverter
14.38 ForthecircuitshowninFig.P14.38,letswitchSopen at t = 0.
(a) Give the expression for vO(t).
(b) ForI=1mAandC=10pF,findthetimeatwhichvO
reaches 1 V.
I
CS
Figure P14.38
vI
Figure P14.40
C
CHAPTER 14 PROBLEMS
14.39 For the circuit in Fig. P14.39, let C be charged to 10 V and switch S closes at t = 0.
(a) Give the expression for vO(t).
(b) ForC=100pFandR=1k,findtPHL andtf.
14.41 For the inverter of Fig. 14.18(a) with a capacitance C connected between the output and ground, let the on-resistance of PU be 2 k and that of PD be 1 k. If the capacitance C = 50 fF, find tPLH , tPHL , and tP .
14.42 Alogicinverterisimplementedusingthearrangement of Fig. 14.18 with switches having Ron = 2 k, VDD = 1.8 V, andVIL=VIH=VDD/2.
(a) Find VOL, VOH, NML, and NMH.
(b) If vI rises instantaneously from 0 V to +1.8 V and
assuming the switches operate instantaneously—that is, at t = 0, PU opens and PD closes—find an expression for v O (t), assuming that a capacitance C is connected between the output node and ground. Hence find the high-to-low
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
CHAPTER 14 PROBLEMS
propagation delay (tPHL ) for C = 0.1 pF. Also find tTHL
(see Fig. 14.29).
(c) Repeat (b) for vI falling instantaneously from +1.8 V
to 0 V. Again assume that PD opens and PU closes instantaneously. Find an expression for v O (t), and hence find tPLH and tTLH .
14.43 Inaparticularlogicfamily,thestandardinverter,when loaded by a similar circuit, has a propagation delay specified to be 0.9 ns:
(a) If the current available to charge a load capacitance is half as large as that available to discharge the capacitance, whatdoyouexpecttPLH andtPHL tobe?
(b) If when an external capacitive load of 0.5 pF is added at the inverter output, its propagation delays increase by 50%, what do you estimate the normal combined capacitance of inverter output and input to be?
(c) If without the additional 0.5-pF load connected, the load inverter is removed and the propagation delays were observed to decrease by 40%, estimate the two components of the capacitance found in (b): that is, the component due to the inverter output and other associated parasitics, and the component due to the input of the load inverter.
*14.44 Consider an inverter for which tPLH, tPHL, tTLH, and tTHL are20ns,10ns,30ns,and15ns,respectively.Therising and falling edges of the inverter output can be approximated bylinearramps.Also,forsimplicity,wedefinetTLH tobe0% to 100% (rather than 10% to 90%) rise time, and similarly for tTHL . Two such inverters are connected in tandem and driven by an ideal input having zero rise and fall times. Calculate the time taken for the output voltage to complete its excursion for (a) a rising input and (b) a falling input. What is the propagation delay for the inverter?
14.45 For a CMOS inverter fabricated in a 0.13-μm process with VDD = 1.2V, Vtn = −Vtp = 0.4 V, kn′ = 4kp′ = 430 μA/V2, and having (W/L)n = 1.5 and (W/L)p = 3, find tPHL , tPLH , and tP when the equivalent load capacitance C = 10 fF. Use the method of average currents.
D 14.46 Consider a matched CMOS inverter fabricated in the 0.13-μm process specified in Problem 14.45. If C = 30 fF,
Problems 1161 use the method of average currents to determine the required
(W/L) ratios so that tP ≤ 80 ps.
14.47 For the CMOS inverter in Exercise 14.11 use the method of equivalent resistance to determine tPHL , tPLH , andtP.
14.48 Use the method of equivalent resistance to determine the propagation delay of a minimum-size inverter, that is, one for which (W/L)n = (W/L)p = 1, designed in a 0.13-μm technology. The equivalent load capacitance C = 20 fF.
D 14.49 Use the method of equivalent resistance to design an inverter to be fabricated in a 0.13-μm technology. It is required that for C = 10 fF, tPLH = tPHL, and tP ≤ 50 ps.
14.50 The method of average currents yields smaller values for tPHL and tPLH than those obtained by the method of equivalent resistances. Most of this discrepancy is due to the fact that the formula we derived for Iav does not take into account velocity saturation. As will be seen in Section 15.1.2, velocity saturation reduces the current significantly. Using the results in Example 14.6, by what factor do you estimate the current reduction to be in the NMOS transistor? Since tPLH does not change, what do you conclude about the effect of velocity saturation on the PMOS transistor in this technology?
14.51 Use the method of average currents to estimate tPHL , tPLH , and tP of a CMOS inverter fabricated in a 65-nm process for which Vtn = |Vtp| = 0.35 V, VDD = 1 V, μnCox = 470 μA/V2, and μpCox = 190 μA/V2. The inverter has (W/L)n = 1.5 and (W/L)p = 3, and the total capacitance at the inverter output node is 10 fF. Also, find the theoretical maximum frequency at which this inverter can be operated.
14.52 Find the propagation delay for a minimum-size inverter for which kn′ = 4kp′ = 380μA/V2 and (W/L)n = (W/L)p = 0.27 μm/0.18 μm, VDD = 1.8 V, Vtn = –Vtp = 0.5 V, and the capacitance is roughly 4 fF/μm of device width plus 2 f F/device. There is an additional load capacitance of 5 fF. What does tP become if the design is changed to a matched one? Use the method of average current.
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
1162 Chapter 14 CMOS Digital Logic Circuits
14.53 A matched CMOS inverter fabricated in a process for
whichCox =3.7fF/μm2,μnCox =180μA/V2,μpCox =45μA/V2,
Vtn =–Vtp =0.7V,andVDD =3.3V,usesWn =0.75μmand
L = L = 0.5 μm. The overlap capacitance and the effective np
drain–body capacitance per micrometer of gate width are 0.4 f F and 1.0 f F, respectively. The wiring capacitance is Cw = 2 f F. If the inverter is driving another identical inverter, find tPLH , tPHL , and tP . For how much additional capacitance load does the propagation delay increase by 50%?
Section 14.5: Transistor Sizing
14.54 An inverter whose equivalent load capacitance C is composed of 15 fF contributed by the inverter transistors, and 45 fF contributed by the wiring and other external circuitry, has been found to have a propagation delay of 80 ps. By what factor must (W/L)n and (W/L)p be increased so as to reduce tP to 40 ps? By what factor is the inverter area increased?
D *14.55 In this problem we investigate the effect of the selection of the ratio Wp/Wn on the propagation delay of an inverter driving an identical inverter, as in Fig. 14.32. Assume all transistors have the same L.
(a) Noting that except for Cw each of the capacitances in Eqs. (14.58) and (14.59) is proportional to the width of the relevant transistor, show that C can be expressed as
W C=Cn 1+ p +Cw
Wn
where Cn is determined by the NMOS transistors.
(b) UsingtheequivalentresistancesRN andRP,showthatfor
(W/L)n = 1,
(c) Use the results of (a) and (b) to determine tP in the case Wp =Wn, in terms of Cn and Cw.
(d) Use the results of (a) and (b) to determine tP in the matched case: that is, when Wp/Wn is selected to yield tPHL = tPLH .
(e) Compare the tP values in (c) and (d) for the two extreme cases:
(i)Cw =0 (ii)Cw ≫Cn
What do you conclude about the selection of Wp/Wn?
D 14.56 Consider the CMOS gate shown in Fig. 14.9. Specify W/L ratios for all transistors in terms of the ratios n and p of the basic inverter, such that the worst-case tPHL and tPLH of the gate are equal to those of the basic inverter.
D 14.57 Find appropriate sizes for the transistors used in
the exclusive-OR circuit of Fig. 14.10(b). Assume that the
basicinverterhas(W/L) =0.20μm/0.13μmand(W/L) = np
0.40 μm/0.13 μm. What is the total area, including that of the required inverters?
14.58 Consider a four-input CMOS NAND gate for which the transient response is dominated by a fixed-size capacitance between the output node and ground. Compare the values of tPLH and tPHL, obtained when the devices are sized as in Fig. 14.35, to the values obtained when all n-channel devices have W/L = n and all p-channel devices have W/L=p.
14.59 Figure P14.59 shows two approaches to realizing the OR function of six input variables. The circuit in Fig. P14.59(b), though it uses additional transistors, has in fact less total area and lower propagation delay because it uses NOR gates with lower fan-in. Assuming that the transistors in both circuits are properly sized to provide each gate with a current-driving capability equal to that of the basic matched inverter, find the number of transistors and the total area of each circuit. Assume the basic inverter to have a (W/L)n ratio of 0.20 μm/0.13 μm and a (W/L)p ratio of 0.40 μm/0.13 μm.
*14.60 Consider the two-input CMOS NOR gate of Fig. 14.7 whose transistors are properly sized so that the current-driving
CHAPTER 14 PROBLEMS
tPHL =8.625×103C 20.7 × 103
tPLH= W/W C pn
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
A1 A6
A1 A2 A3
A4 A5 A6
Figure P14.59
Y A1 A2 … A6
Problems 1163
CHAPTER 14 PROBLEMS
…
(a)
Y A1 A2 … A6
capability in each direction is equal to that of a matched
(b)
(c)
(d)
Differentiate the expression for t in (a) relative to x P
and set the derivative to zero. Thus show that the first condition for optimality is
C xn= L C
Differentiate the expression for tP in (a) relative to n and set the derivative to zero. Thus show that the second condition for optimality is
xn C =lnx CL
Combine the expressions in (b) and (c) to show that the value of x for minimum overall delay is
inverter. For Vt = 1 V and VDD = 5 V, find the gate threshold in the cases for which (a) input terminal A is connected to ground and (b) the two input terminals are tied together. Neglect the body effect in QPB.
L
C is the input capacitance of the standard inverter (which is
the first in the chain).
(a) Without increasing the number of inverters in the chain,
find the optimum value of x that results in minimizing the overalldelaytP andfindtheresultingvalueoftP interms of the time constant CR, where R is the output resistance of the standard inverter.
(b) If you are allowed to increase the number of inverters in the chain, what is the number of inverters and the value of x that result in minimizing the total path delay tP ? What is the value of tP achieved?
14.62 The purpose of this problem is to find the values of n and x that result in minimum path delay tP for the inverter chain in Fig. 14.37(c).
(a) Show that
t =τ =(n−1)xRC+ 1 RC P total xn−1 L
x=e Section 14.6: Power Dissipation
14.63 AnICinverterfabricatedina0.18-μmCMOSprocess is found to have a load capacitance of 10 fF. If the inverter is operated from a 1.8-V power supply, find the energy needed to charge and discharge the load capacitance. If the IC chip has 2 million of these inverters operating at an average switching frequency of 1 GHz, what is the power dissipated in the chip? What is the average current drawn from the power supply?
(b)
14.61 A chain of four inverters whose sizes are scaled by a factorxisusedtodrivealoadcapacitanceC =1200C,where
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
1164 Chapter 14 CMOS Digital Logic Circuits
14.64 Consider a logic inverter of the type shown in Fig. 14.18. Let VDD = 1 V, and let a 5-fF capacitance be connected between the output node and ground. If the inverter is switched at the rate of 2 GHz, determine the dynamic power dissipation. What is the average current drawn from the dc power supply?
14.65 Inaparticularlogic-circuittechnology,operatingwith a 3.3-V supply, the basic inverter draws (from the supply) a current of 60 μA in one state and 0 μA in the other. When the inverter is switched at the rate of 100 MHz, the average supply current becomes 150 μA. Estimate the equivalent capacitance at the output node of the inverter.
14.66 A collection of logic gates for which the static power dissipation is zero, and the dynamic power dissipation is 10 mW is operating at 50 MHz with a 5-V supply. By what fraction could the power dissipation be reduced if operation at 3.3 V were possible? If the frequency of operation is reduced by the same factor as the supply voltage (i.e., 3.3/5), what additional power can be saved?
14.67 A particular logic gate has tPLH and tPHL of 30 ns and 50 ns, respectively, and dissipates 1 mW with output low and 0.6 mW with output high. Calculate the corresponding delay–power product (under the assumption of a 50% duty-cycle signal and neglecting dynamic power dissipation).
D *14.68 We wish to investigate the design of the inverter shown in Fig. 14.17(a). In particular, we wish to determine the value for R. Selection of a suitable value for R is determined by two considerations: propagation delay and power dissipation.
(a) Show that if vI changes instantaneously from high to low and assuming that the switch opens instantaneously, the output voltage obtained across a load capacitance C will be
v (t)=V −V −V e−t/τ1 O OH OH OL
(b)
Following a steady state, if vI goes high and assuming that the switch closes immediately and has the equivalent circuit in Fig.14.17(c), show that the output falls exponentially according to
v(t)=V +V −V e−t/τ2 O OL OH OL
where τ2 = C R∥Ron ≃ CRon for Ron ≪ R. Hence show that the time for vO(t) to reach the 50% point is
tPHL =0.69CRon
Use the results of (a) and (b) to obtain the inverter
propagation delay, defined as the average of tPLH and tPHL as
CHAPTER 14 PROBLEMS
(c)
(d)
(e)
tP ≃ 0.35CR
for Ron ≪ R
Show that for an inverter that spends half the time in the logic-0 state and half the time in the logic-1 state, the average static power dissipation is
1 V2 P= DD
2R
Now that the trade-offs in selecting R should be clear, show that, for VDD =5 V and C = 10 pF, to obtain a propagation delay no greater than 5 ns and a power dissipation no greater than 15 mW, R should be in a specific range. Find that range and select an appropriate value for R. Then determine the resulting values of tP and P.
where τ = CR. Hence show that the time required for
D 14.69 A logic-circuit family with zero static power
dissipation normally operates at VDD = 2.5 V. To reduce its
dynamic power dissipation, operation at 1.8 V is considered.
It is found, however, that the currents available to charge and
discharge load capacitances also decrease. If current is (a)
proportional to V or (b) proportional to V 2 , what reductions DD DD
in maximum operating frequency do you expect in each case? What fractional change in delay–power product do you expect in each case?
1
v (t)toreachthe50%point, 1 V +V ,is
O 2 OH OL tPLH =0.69CR
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
14.70 InthisproblemweestimatetheCMOSinverterpower dissipation resulting from the current pulse that flows in QN andQP whentheinputpulsehasfiniteriseandfalltimes.Refer to Fig.14.39 and let Vtn =−Vtp =0.5 V, VDD =1.8 V, and kn =kp =450μA/V2.Lettheinputrisingandfallingedgesbe linear ramps with the 0-to-VDD and VDD -to-0 transitions taking
1 ns each. Find Ipeak . To determine the energy drawn from the supply per transition, assume that the current pulse can be approximated by a triangle with a base corresponding to the time for the rising or falling edge to go from Vt to VDD − Vt , and the height equal to Ipeak . Also, determine the power dissipation that results when the inverter is switched at 100 MHz.
Problems 1165
CHAPTER 14 PROBLEMS
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
CHAPTER 15
Advanced Topics in Digital Integrated- Circuit Design
Introduction 1167
15.1 Implications of Technology Scaling: IssuesinDeep-SubmicronDesign 1168
15.2 Digital IC Technologies, Logic-Circuit Families, and Design
Methodologies 1179
15.3 Pseudo-NMOS Logic Circuits 1183
15.4 Pass-Transistor Logic Circuits 1192
15.5 Dynamic MOS Logic Circuits 1208
15.6 Bipolar and BiCMOS Logic Circuits 1217
Summary 1226 Problems 1227
IN THIS CHAPTER YOU WILL LEARN
1. The implications of technology scaling (Moore’s law) over more than 40 years and continuing, and some of the current challenges in the design of deep-submicron (L < 0.25 μm) circuits.
2. How and why CMOS has become the dominant technology for digital IC design.
3. That by replacing the pull-up network (PUN) of a CMOS logic gate by a single PMOS transistor that is permanently on, considerable savings in transistor count and silicon area can be achieved in gates with high fan-in.The resulting circuits are known as pseudo-NMOS.
4. That a useful and conceptually simple form of MOS logic circuit, known as pass-transistor logic (PTL), utilizes MOS transistors as series switches in the signal path from input to output.
5. That a very effective switch for both analog and digital applications, known as transmission gate, is formed by connecting an NMOS and a PMOS transistor in parallel.
6. That eliminating the pull-up network and placing two complementary switches, operated by a clock signal, in series with the pull-down network of a CMOS gate results in an interesting and useful class of circuits known as dynamic logic.
7. How the BJT differential-pair configuration is used as a current switch to realize the fastest commercially available logic-circuit family: emitter-coupled logic (ECL).
8. How the MOSFET and the BJT are combined in BiCMOS circuits in ways that take advantage of the best attributes of each device.
Introduction
In this chapter we study a number of advanced topics in digital logic-circuit design. We begin by taking a closer look at the implications of Moore’s law. Specifically, over the past 45 years or so, the MOSFET dimensions have been reduced by a factor of 2 about every five years. This scaling has been accompanied by reductions in VDD and Vt . The opportunities provided and challenges posed by scaling are studied in Section 15.1. We then survey the field of digital IC technologies in order to place CMOS in proper perspective.
Standard CMOS logic, which we studied in Chapter14, excels in almost every performance category: It is easy to design, has the maximum possible voltage swing, is
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Advanced Topics in Digital Integrated-Circuit Design
robust from a noise-immunity standpoint, dissipates no static power, and can be designed to provide equal high-to-low and low-to-high propagation delays. Its main disadvantage is the requirement of two transistors for each additional gate input, which for gates with high fan-in can make the chip area large and increase the total capacitance and, correspondingly, the propagation delay and the dynamic power dissipation. For this reason designers of digital integrated circuits have been searching for forms of CMOS logic circuits that can be used to supplement standard CMOS. This chapter presents three such forms that reduce the required number of transistors but incur other costs. These forms are not intended to replace standard CMOS, but are rather to be used in special applications for special purposes.
Pseudo-NMOS logic, studied in Section 15.3, replaces the pull-up network (PUN) in a CMOS logic gate by a single permanently “on” PMOS transistor. The reduction in transistor count and silicon area comes at the expense of static power dissipation. As well, the output low-level VOL becomes dependent on the transistors’ W/L ratios.
Pass-transistor logic (PTL), studied in Section 15.4, utilizes MOS transistors as switches in the series path from input to output. Though simple and attractive for special applications, PTL does not restore the signal level and thus requires the occasional use of standard CMOS inverters to avoid signal-level degradation, especially in long chains of switches.
The dynamic logic circuits studied in Section 15.5 dispense with the PUN and place two complementary switches in series with the PDN. The switches are operated by a clock, and the gate output is stored on the load capacitance. Here the reduction in transistor count is achieved at the expense of a more complex design that is less robust than static CMOS.
Although CMOS accounts for the vast majority of digital integrated circuits, there is a bipolar logic-circuit family that is still of some interest. This is emitter-coupled logic (ECL), which we study briefly in Section 15.6.1. Finally, in Section 15.6.2 we show how the MOSFET and the BJT can be combined in ways that take advantage of the best properties of each, resulting in what are known as BiCMOS circuits.
The sections of this chapter are almost independent modules, thus selected ones can be studied as they come up, and others may be deferred to a later time.
15.1 Implications of Technology Scaling: Issues in Deep-Submicron Design
As mentioned in Chapter 5, and in a number of locations throughout the book, the minimum MOSFET channel length has been continually reduced over the past 50 years or so. In fact, a new CMOS fabrication technology has been introduced every 2 or 3 years, with the minimum allowable channel length reduced by about 30%, that is, to 0.7 the value in the preceding generation. Thus, with every new technology generation, the device area has been reduced by a factor of 1/(0.7 × 0.7) or approximately 2, allowing the fabrication of twice as many devices on a chip of the same area. This astounding phenomenon, predicted nearly 50 years ago by Gordon Moore, has become known as Moore’s law. It is this ability to pack an exponentially increasing number of transistors on an IC chip that has resulted in the continuing reduction in the cost per logic function.
Figure 15.1 shows the exponential reduction in MOSFET channel length (by a factor of 2 every 5 years) over a 40-year period, with the dots indicating some of the prominent technology generations, or nodes. Thus, we see the 10-μm process of the early 1970s, the
15.1 Implications of Technology Scaling: Issues in Deep-Submicron Design 1169
Lmin 10 m 1.0 m 0.1 m
phenomenon, known as Moore’s law, is continuing.
submicron (L < 1 μm) processes of the early 1990s, and the deep-submicron (L < 0.25 μm) processes of the last decade, including the current 22-nm process. A microprocessor chip fabricated in a 22-nm CMOS process, clocked at 3.8 GHz and having 4.31 billion transistors, was announced in 2014. Deep-submicron (DSM) processes present the circuit designer with a host of new opportunities and challenges. It is our purpose in this section to briefly consider some of these.
15.1.1 Silicon Area
We begin this section with a brief discussion of silicon area. In addition to minimizing power dissipation and propagation delay, an important objective in the design of digital VLSI circuits is the minimization of silicon area per logic gate. The smaller area requirement enables the fabrication of a larger number of gates per chip, which has economic and space advantages from a system-design standpoint. Area reduction occurs in three different ways: through advances in processing technology that enable the reduction of the minimum device size, through advances in circuit-design techniques, and through careful chip layout. In this book, our interest lies in circuit design, and we shall make frequent comments on the relationship between the design of a circuit and its silicon area. As a general rule, the simpler the circuit, the smaller the area required. As we have seen in Section 14.5, the circuit designer has to decide on device sizes. Choosing smaller devices has the obvious advantage of requiring smaller silicon area and at the same time reducing parasitic capacitances and thus increasing speed. Smaller devices, however, have lower current-driving capability, which tends to increase delay. Thus, as in all engineering design problems, there is a trade-off to be quantified and exercised in a manner that optimizes whatever aspect of the design is thought to be critical for the application at hand.
15.1.2 Scaling Implications
Table 15.1 provides a summary of the implications of scaling the device dimensions by a factor 1/S, where S > 1. As well, we assume that VDD and Vt are scaled by the same factor.
10 nm
1970 1980 1990
2000 2010 Year
Figure 15.1 The MOSFET channel length has been reduced by a factor of 2 about every 5 years. This
1170 Chapter 15
Advanced Topics in Digital Integrated-Circuit Design
Table 15.1
1
2 3 4 5 6 7 8
9 10
Implications of Device and Voltage Scaling
Parameter
W, L, tox VDD,Vt
Area/Device
Cox kn′ , kp′
Cgate
tP (intrinsic)
Energy/Switching cycle (intrinsic)
Pdyn
Power density
Relationship
Scaling Factor
1/S
Although the scaling of VDD has occurred for a number of technology nodes (e.g., from 5 V for the 0.5-μm process down to 1.2 V for the 0.13-μm process and 1 V for the 65-nm process), Vt has been reduced but not by the same factor. Thus the assumption in row 2 of Table 15.1 is not entirely correct. Nevertheless, our interest here is to gain a general appreciation for the effects of scaling.
Table 15.1 provides the relationships for the various transistor and inverter parameters in order to show how the resulting scale factors are obtained. We thus see that the device area scales by 1/S2; the oxide capacitance Cox, and the transconductance parameters kn′ and kp′ scalebyS;andtheMOSFETgatecapacitancescalesby1/S.Itisimportanttonote that the component of the inverter propagation delay due to the transistor capacitances (i.e., excluding the wiring capacitance) scales by 1/S; this very useful result of scaling implies that the circuit can be operated at S times the frequency; that is, the speed of operation increases by a factor S. Equally important, the dynamic power dissipation scales by 1/S2. This, of course, is a major motivating factor behind the scaling of VDD. Another motivating factor is the need to keep the electric fields in the MOSFETs within acceptable bounds.
Although the dynamic power dissipation is scaled by 1/S2, the power per unit area remains unchanged. Nevertheless, for a number of reasons, as the size and complexity of digital IC chips continue to increase, so does their power dissipation. Indeed power dissipation has now become the number-one issue in IC design. The problem is further exacerbated by the static power dissipation, arising from both subthreshold conduction and diode leakage currents, that plagues deep-submicron CMOS devices. We will discuss this issue shortly.
1/S WL 1/S2
εox /tox S μnCox,μpCox S
WLC ox
αC/k′VDD
CV2 DD
1/S 1/S 1/S3
CV2
DD 1/S2
fmaxCV2 DD
=
2tP
Pdyn/Device area 1
15.1 Implications of Technology Scaling: Issues in Deep-Submicron Design 1171
EXERCISES
15.1 By what factor does the power–delay product PDP change if an inverter is fabricated in a 0.13-μm technology rather than a 0.25-μm technology? Assume S ≃ 2.
Ans. PDP decreases by a factor of 8.
15.2 If VDD and Vt are kept constant, which entries in Table 15.1 change and to what value?
Ans. tP now scales by 1/S2; the energy/switching cycle now scales by 1/S only; Pdyn now scales by S; and the power density now scales by S3 (a major problem).
15.1.3 Velocity Saturation
The short channels of MOSFETs fabricated in deep-submicron processes give rise to physical phenomena not present in long-channel devices, and thus to changes in the MOSFET i−v characteristics. The most important of these short-channel effects is velocity saturation. Here we refer to the drift velocity of electrons in the channel of an NMOS transistor (holes in PMOS) under the influence of the longitudinal electric field established by vDS. In our derivation of the MOSFET i−v characteristics in Section 5.1, we assumed that the velocity vn of the electrons in an n-channel device is given by
where E is the electric field given by
vn =μnE (15.1) E = vDS (15.2)
L
The relationship in Eq. (15.1) applies as long as E is below a critical value Ecr that fallsintherange1V/μmto5V/μm.ForE>Ecr,thedriftvelocitysaturatesatavalueνsat of approximately 107 cm/s. Figure 15.2 shows a sketch of νn versus E. Although the change from
vn
vsat
0 Ecr E
Figure15.2 ThevelocityofelectronsinthechannelofanNMOStransistorreachesaconstantvalueνsat≃107 cm/s when the electric field E reaches a critical value Ecr . A similar situation occurs for p-channel devices.
Slope n
1172 Chapter 15
Advanced Topics in Digital Integrated-Circuit Design
a linear to a constant ν is gradual, we shall assume for simplicity that ν saturates abruptly at E = Ecr .
The electric field E in a short-channel MOSFET can easily exceed Ecr even though VDD is low. If we denote the value of vDS at which velocity saturation occurs by VDSsat, then from Eq. (15.2),
Ecr = VDSsat L
which when substituted in Eq. (15.1) provides
(15.3)
(15.4)
(15.5)
or alternatively,
Thus, VDSsat is a device parameter.
V v =μ DSsat
sat n L L
VDSsat = μ vsat n
EXERCISE
15.3 Find VDSsat for an NMOS transistor fabricated in a 0.25-μm CMOS process with μn = 400 cm2 /V · s. Let L = 0.25 μm and assume vsat = 107 cm/s.
Ans. 0.63 V
The iD−vDS Characteristics The iD−vDS equations of the MOSFET can be modified to include velocity saturation as follows. Consider a long-channel NMOS transistor operating in the triode region with vGS set to a constant value VGS. The drain current will be
W 1
iD=μnCox L vDS (VGS−Vt)−2vDS (15.6)
where we have for the time being neglected channel-length modulation. We know from our study in Section 5.1 that iD will saturate at
vDS =VOV =VGS −Vt (15.7)
and the saturation current will be
iD = 2μnCox L (VGS −Vt)2 (15.8)
1 W
iD
1 μ C WV2 2 n ox L OV
IDsat
vGS Vt VOV
15.1 Implications of Technology Scaling: Issues in Deep-Submicron Design 1173
vDS results in a current IDsat that is lower than the value for a long-channel device.
This will also be the case in a short-channel device as long as the value of vDS in Eq. (15.7) is lower than VDSsat. That is, as long as
VOV
then velocity saturation kicks in at vDS = VDSsat and iD saturates at a value IDsat , as shown in
VDSsat VOV
Figure 15.3 Velocity saturation causes the iD−vDS characteristic to saturate at VDSsat. This early saturation
Fig. 15.3. The value of IDsat can be obtained by substituting vDS = VDSsat in Eq. (15.6), W 1
IDsat =μnCox L VDSsat VGS −Vt − 2VDSsat This expression can be simplified by utilizing Eq. (15.5) to obtain
1 IDsat = WCox νsat VGS − Vt − 2 VDSsat
(15.9)
(15.10)
ReplacingVGS inEq.(15.9)withvGS,andincorporatingthechannel-lengthmodulationfactor (1+λvDS), we obtain a general expression for the drain current of an NMOS transistor operating in velocity saturation,
W 1
iD =μnCox L VDSsat vGS −Vt −2VDSsat (1+λvDS) (15.11)
1174 Chapter 15
Advanced Topics in Digital Integrated-Circuit Design
iD
0
Triode
Velocity saturation
Saturation
vGS Vt VDSsat
vGS Vt VDSsat
vGS Vt VDSsat vGS Vt VDSsat
vDS
VDSsat
Figure 15.4 The iD−vDS characteristics of a short-channel MOSFET. Note the three different regions of
operation: triode, saturation, and velocity saturation.
iD
0
Linear
Quadratic
Vt (Vt VDSsat) vGS
Figure 15.5 TheiD−vGS characteristicofashort-channelNMOStransistoroperatingatvDS >VDSsat.Observe the quadratic and the linear portions of the characteristic. Also note that in the absence of velocity saturation, the quadratic curve would continue as shown with the broken line.
which applies for
vGS −Vt ≥VDSsat and vDS ≥VDSsat (15.12)
Figure 15.4 shows a set of iD−vDS characteristic curves and clearly delineates the three regions of operation: triode, saturation, and velocity saturation.
Equation (15.11) indicates that in the velocity-saturation region, iD is linearly related to vGS. This is a major change from the quadratic relationship that characterizes operation in the saturation region. Figure 15.5 makes this point clearer by presenting a graph for iD versus vGS of a short-channel device operating at vDS > VDSsat . Observe that for 0 < vGS − Vt ≤ VDSsat , the MOSFET operates in the saturation region and iD is related to vGS by the familiar quadratic equation(Eq.15.8).ForvGS −Vt ≥VDSsat,thetransistorentersthevelocity-saturationregion and iD varies linearly with vGS (Eq. 15.11).
15.1 Implications of Technology Scaling: Issues in Deep-Submicron Design
1175
Short-channel PMOS transistors undergo velocity saturation at the same value of νsat (approximately 107cm/s), but the effects on the device characteristics are less pronounced than in the NMOS case. This is due to the lower values of μp and the correspondingly higher valuesofEcr andVDSsat.
Example 15.1
Consider MOS transistors fabricated in a 0.25-μm CMOS process for which V = 2.5 V, V = −V
=
n p DSsat
0.5 V, μnCox = 115 μA/V2, μpCox = 30 μA/V2, λn = 0.06 V−1, and λp = 0.1 V−1. Let L = 0.25 μm
and(W/L) =(W/L) =1.5.MeasurementsindicatethatfortheNMOStransistor,V =0.63V,andfor
the PMOS device, V = 1 V. Calculate the drain current obtained in each of the NMOS and PMOS DSsat
transistors for VGS = VDS = VDD . Compare with the values that would have been obtained in the absence
of velocity saturation. Also give the range of vDS for which iD is saturated, with and without velocity saturation.
Solution
For the NMOS transistor, VGS = 2.5 V results in VGS − Vtn = 2.5 − 0.5 = 2 V, which is greater than VDSsat . Also, VDS = 2.5 V is greater than VDSsat ; thus both conditions in Eq. (15.12) are satisfied, and the NMOS transistor will be operating in the velocity-saturation region, and thus iD is given by Eq. (15.11):
iD =115×10−6 ×1.5×0.63× 2.5−0.5−1×0.63 ×(1+0.06×2.5)=210.6μA
2 If velocity saturation were absent, the current would be
i =1μC Wv −V21+λv D 2 n ox L GS tn DS
n
= 1 ×115×10−6 ×1.5×(2.5−0.5)2 ×(1+0.06×2.5) 2
= 396.8 μA
Thus, velocity saturation reduces the current level by nearly 50%! The saturation current, however, is obtained over a larger range of v DS ; specifically, for v DS = 0.63 V to 2.5 V. (Of course, the current does not remain constant over this range because of channel-length modulation.) In the absence of velocity saturation, the current saturates at VOV = VGS − Vt = 2 V, and thus the saturation current is obtained over therangevDS =2Vto2.5V.
For the PMOS transistor, we see that since V − V =2 V and V =2.5 V are both larger than GSt DS
VDSsat = 1 V the device will be operating in velocity saturation, and iD can be obtained by adapting Eq. (15.11) as follows:
W 1 iD = μpCox VDSsat VGS−Vtp− VDSsat 1+λpVDS
Lp2
=30×10−6 ×1.5×1× 2.5−0.5− 1 ×1 (1+0.1×2.5) 2
= 84.4 μA
DD tn tp
1176
Chapter 15 Advanced Topics in Digital Integrated-Circuit Design
Example 15.1 continued
Without velocity saturation, we have
i = 1μ C W V −V 21+λ V D2poxLGStp pDS
p
= 1 ×30×10−6 ×1.5×(2.5−0.5)2(1+0.1×2.5) 2
= 112.5 μA
Thus velocity saturation reduces the current by 25% (which is less than in the case of the NMOS transistor),
and the saturated current is obtained over the range V = 1 V to 2.5 V. In the absence of velocity DS
saturation,thesaturatediD wouldhavebeenobtainedforVDS=2Vto2.5V.
EXERCISE
15.4 RepeattheprobleminExample15.1fortransistorsfabricatedina0.13-μmCMOSprocessforwhich V =1.2V,V =−V =0.4V,μ C =430μA/V2,μ C =110μA/V2,λ =λ =0.1V−1.Let
DD tn tp nox pox n p
L = 0.13 μm, (W/L)n = (W/L)p = 1.5, VDSsat (NMOS) = 0.34 V, and VDSsat (PMOS) = 0.6 V.
Ans. NMOS: ID = 154.7 μA, compared to 231.2 μA without velocity saturation; saturation is obtained over the range v =0.34 V to 1.2V, compared to v =0.8 V to 1.2V in the absence of velocity
DS DS
saturation. PMOS: ID = 55.4 μA compared to 59.1 μA, and vDS = 0.6 V to 1.2 V compared to 0.8 V
to 1.2 V.
Effect on the Inverter Characteristics The VTC of the CMOS inverter can be derived using the modified iD−vDS characteristics of the MOSFETs. The results, however, indicate relatively small changes from the VTC derived in Section 14.3 using the long-channel equations (see Rabaey et al., 2003, and Hodges et al., 2004), and we shall not pursue this subject here. The dynamic characteristics of the inverter, however, are significantly impacted by velocity saturation. This is because the current available to charge and discharge the equivalent load capacitance C is substantially reduced.
A Remark on the MOSFET Model The model derived above for short-channel MOSFETs is an approximate one, intended to enable the circuit designer to perform hand analysis to gain insight into circuit operation. Also, the model parameter values are usually obtained from measured data by means of a numerical curve-fitting process. As a result, the model applies only over a restricted range of terminal voltages.
Modeling short-channel MOSFETs is an advanced topic that is beyond the scope of this book. Suffice it to say that sophisticated models have been developed and are utilized by circuit simulation programs such as SPICE (see Appendix B). Circuit simulation is an essential step
15.1 Implications of Technology Scaling: Issues in Deep-Submicron Design 1177 in the design of integrated circuits. However, it is not a substitute for initial hand analysis
and design.
15.1.4 Subthreshold Conduction
In our study of the NMOS transistor in Section 5.1, we assumed that current conduction between drain and source occurs only when vGS exceeds Vt. That is, we assumed that for vGS
s – 0 T(s) = –a1—- s + 0
Vi
Vi
Vo
0 0 90
CR Flat gain (a1)
1/0 0.5
CR Flat gain (a1)
1/0 1
180
Vo Vi
1
20 log a1
R1
φ()
–2 tan–1 (ωCR)
C
17.4.2 Second-Order Filter Functions
The general second-order (or biquadratic) filter transfer function is usually expressed in the standard form
T(s)= a2s2 +a1s+a0 s2 +(ω0/Q)s+ω20
where ω0 and Q determine the natural modes (poles) according to
ω p1,p2 =− 0 ±jω0 1− 1/4Q2
(17.27)
(17.28)
17.4 First-Order and Second-Order Filter Functions 1311
2Q
We are usually interested in the case of complex-conjugate natural modes, obtained for
Q > 0.5. Figure 17.15 shows the location of the pair of complex-conjugate poles in the s plane. Observe that the radial distance of the natural modes (from the origin) is equal to ω0, which is known as the pole frequency. The parameter Q determines the distance of the poles from the jω axis: the higher the value of Q, the closer the poles are to the jω axis, and the more selective the filter response becomes. An infinite value for Q locates the poles on the jω axis and can yield sustained oscillations in the circuit realization. A negative value of Q implies that the poles are in the right half of the s plane, which certainly produces oscillations. The parameter Q is called the pole quality factor, or simply pole Q.
The transmission zeros of the second-order filter are determined by the numerator coefficients, a0, a1, and a2. It follows that the numerator coefficients determine the type of second-order filter function (i.e., LP, HP, etc.). Seven special cases of interest are illustrated in Fig. 17.16. For each case we give the transfer function, the s-plane locations of the transfer function singularities, and the magnitude response. Circuit realizations for the various second-order filter functions will be given in subsequent sections.
All seven special second-order filters have a pair of complex-conjugate natural modes characterized by a frequency ω0 and a quality factor Q.
In the low-pass (LP) case, shown in Fig. 17.16(a), the two transmission zeros are at s = ∞. The magnitude response can exhibit a peak with the details indicated. It can be shown that
√√
the peak occurs only for Q > 1/ 2. The response obtained for Q = 1/ 2 is the Butterworth,
or maximally flat, response.
The high-pass (HP) function shown in Fig. 17.16(b) has both transmission zeros at s = 0
(dc). The magnitude response shows a peak for Q > 1/ 2, with the details of the response as indicated. Observe the duality between the LP and HP responses.
Next consider the bandpass (BP) filter function shown in Fig.17.16(c). Here, one transmission zero is at s = 0 (dc), and the other is at s = ∞. The magnitude response peaks at ω = ω0 . Thus the center frequency of the bandpass filter is equal to the pole frequency ω0 . The
Figure 17.15 Definition of the parameters ω0 and Q of a pair of complex-conjugate poles.
√
1312 Chapter 17
Filters and Tuned Amplifiers
selectivity of the second-order bandpass filter is usually measured by its 3-dB bandwidth. This is the difference between the two frequencies ω1 and ω2 at which the magnitude response is 3 dB below its maximum value (at ω0). It can be shown that
Thus,
2 ω0
ω1,ω2 =ω0 1+ 1/4Q ±2Q (17.29)
BW ≡ω2 −ω1 =ω0/Q (17.30)
Observe that as Q increases, the bandwidth decreases and the bandpass filter becomes more selective.
If the transmission zeros are located on the jω axis, at the complex-conjugate locations ±jωn, then the magnitude response exhibits zero transmission at ω = ωn. Thus a notch in the magnitude response occurs at ω = ωn, and ωn is known as the notch frequency. Three cases of the second-order notch filter are possible: the regular notch, obtained when ωn = ω0 [Fig. 17.16(d)]; the low-pass notch, obtained when ωn > ω0 [Fig. 17.16(e)]; and the high-pass notch, obtained when ωn < ω0 [Fig. 17.16(f)]. The reader is urged to verify the response details given in these figures (a rather tedious task, though!). Observe that in all notch cases, the transmission at dc and at s = ∞ is finite. This is so because there are no transmission zeros at either s = 0 or s = ∞.
The last special case of interest is the all-pass (AP) filter whose characteristics are illustrated in Fig. 17.16(g). Here the two transmission zeros are in the right half of the s plane, at the mirror-image locations of the poles. (This is the case for all-pass functions of any order.) The magnitude response of the all-pass function is constant over all frequencies; the flat gain, as it is called, is in our case equal to |a2|. The frequency selectivity of the all-pass function is in its phase response.
EXERCISES
√
17.13 For a maximally flat second-order low-pass filter (Q = 1/ 2), show that at ω = ω0 the magnitude
response is 3 dB below the value at dc.
17.14 Give the transfer function of a second-order bandpass filter with a center frequency of 105 rad/s, a
center-frequency gain of 10, and a 3-dB bandwidth of 103 rad/s. Ans. T(s)= 104s
s2 +103s+1010
17.15 (a) For the second-order notch function with ωn = ω0 , show that for the attenuation to be greater
than A dB over a frequency band BWa, the value of Q is given by Q≤ √ω0
10A/10 −1
(Hint:First,showthatanytwofrequencies,ω1 andω2,atwhich|T|isthesamearerelatedbyω1ω2 = ω20 .)
(b) Use the result of (a) to show that the 3-dB bandwidth is ω0 /Q, as indicated in Fig. 17.16(d).
17.16 Consider a low-pass notch with ω0 = 1 rad/s, Q = 10, ωn = 1.2 rad/s, and a dc gain of unity. Find the frequency and magnitude of the transmission peak. Also find the high-frequency transmission. Ans. 0.986 rad/s; 3.17; 0.69
BW
a
1313
Filter Type and T(s) (a) Low pass (LP)
s-Plane Singularities j
|T|
a 0
T(s) = -----------------------------
a 0 / 20
max
0
1 2Q
a0 DC gain = -- - 2 0
0 2Q
2 0 2 s +s--+0 Q
0
(b) High pass (HP)
aQ 1 1
a2 s2 T(s) = -----------
j
0 a2
2 0 2 s +s--+0 Q
0
High-frequency gain = a2
0 2Q
1 max 0 1 2Q2
(c) Bandpass (BP)
j T O at
a 1 s
T(s) = ------
1, 2
a
202 s +s--+0 Q
1
2
a1Q Center-frequencygain =--
1 2
Figure 17.16 Second-order filtering functions.
0 0 2Q
0
0
0.707 Tmax
(a1Q/ b
20) ab0
OO at
T
a0 Q
2 1 1
0 10
0
4Q2 2Q
0
0 max Tmax
(a1Q/ 0)
0
max 0
T 24Q2
0
0 1 2 20
(0 /Q)
0
4Q2
1 2
1314
Filter Type and T(s) (d) Notch
s-Plan e Sing ular ities |T|
s 2 + 20 T(s) = a ---
2n DC gain = a2 -- 20
2 2 120
202 s +s--+0 Q
DC gain = High-frequency gain = a2
(e) Low-pass notch (LPN)
s 2 + 2n T(s) = a2----------------------------
2 0 2 s +s--+0 Q
High-frequency gain = a2
n 0
(f) High-pass notch (HPN)
T(s) = a2-------------------------
2n DC gain = a2 - 20
22
a
s +n
a
2 0 2 s +s--+0 Q
High-frequency gain = a2
Figure17.16 continued
n 0
1
2
1315
(g) Allpass(AP)
T
Flat gain = a2
0 0 2Q 2Q
2 0 2 s –s--+0 Q
0 0 0
T(s) = a2--------------------
202 s +s-- +0 Q
0
Figure17.16 continued
j
O
a2
O
0
0
2
1316 Chapter 17
Filters and Tuned Amplifiers
and
CL
ω20 =1/LC ω0 /Q = 1/CR
00
xL
17.5 The Second-Order LCR Resonator
In this section we shall study the second-order LCR resonator shown in Fig. 17.17(a). The use of this resonator to derive circuit realizations for the various second-order filter functions will be demonstrated. It will be shown in the next section that replacing the inductor L by a simulated inductance obtained using an op amp–RC circuit results in an op amp–RC resonator. The latter forms the basis of an important class of active-RC filters to be studied in Section 17.6.
17.5.1 The Resonator Natural Modes
The natural modes or poles of the parallel resonance circuit of Fig. 17.17(a) can be determined by applying an excitation that does not change the natural structure of the circuit. Two possible ways of exciting the circuit are shown in Fig. 17.17(b) and (c). In Fig. 17.17(b) the resonator is excited with a current source I connected in parallel. Since, as far as the natural response of a circuit is concerned, an independent ideal current source is equivalent to an open circuit, the excitation of Fig. 17.17(b) does not alter the natural structure of the resonator. Thus the circuit in Fig. 17.17(b) can be used to determine the natural modes of the resonator by simply finding the poles of any response function. We can for instance take the voltage Vo across the resonator as the response and thus obtain the response function Vo/I = Z, where Z is the impedance of the parallel resonance circuit. However, because of the parallel structure of the circuit it is more convenient to work in terms of the admittance Y; thus,
Vo = 1 = I Y
1
(1/sL) + sC + (1/R)
(17.31)
(17.32)
(17.33)
s/C
s2 +s(1/CR)+(1/LC)
=
Equating the denominator to the standard form s2 + s(ω /Q) + ω2 leads to
R
I CLVoViRCVo
R
zyx
(a) (b) (c)
Figure 17.17 (a) The second-order parallel LCR resonator. (b, c) Two ways of exciting the resonator of (a) without changing its natural structure; resonator poles are those poles of Vo/I and Vo/Vi.
Thus,
√ ω0=1/ LC
Q = ω0 CR
(17.34) (17.35)
17.5
The Second-Order LCR Resonator 1317
These expressions should be familiar to the reader from studies of parallel resonance circuits in introductory courses on circuit theory.
An alternative way of exciting the parallel LCR resonator for the purpose of determining its natural modes is shown in Fig. 17.17(c). Here, node x of inductor L has been disconnected from ground and connected to an ideal voltage source Vi. Now, since as far as the natural response of a circuit is concerned, an ideal independent voltage source is equivalent to a short circuit, the excitation of Fig. 17.17(c) does not alter the natural structure of the resonator. Thus we can use the circuit in Fig. 17.17(c) to determine the natural modes of the resonator. These are the poles of any response function. For instance, we can select Vo as the response variable and find the transfer function Vo/Vi. The reader can easily verify that this will lead to the natural modes determined earlier.
In a design problem, we will be given ω0 and Q and will be asked to determine L, C, and R. Equations (17.34) and (17.35) are two equations in the three unknowns. The one available degree of freedom can be utilized to set the impedance level of the circuit to a value that results in practical component values.
17.5.2 Realization of Transmission Zeros
Having selected the component values of the LCR resonator to realize a given pair of complex-conjugate natural modes, we now consider the use of the resonator to realize a desired filter type (e.g., LP, HP, etc.). Specifically, we wish to find out where to inject the input voltage signal Vi so that the transfer function Vo/Vi is the desired one. Toward that end, note that in the resonator circuit in Fig. 17.17(a), any of the nodes labeled x, y, or z can be disconnected from ground and connected to Vi without altering the circuit’s natural modes. When this is done, the circuit takes the form of a voltage divider, as shown in Fig. 17.18(a). Thus the transfer function realized is
T(s)= Vo(s) = Z2(s) Vi(s) Z1(s)+Z2(s)
(17.36)
We observe that the transmission zeros are the values of s at which Z2(s) is zero, provided Z1(s) is not simultaneously zero, and the values of s at which Z1(s) is infinite, provided Z2(s) is not simultaneously infinite. This statement makes physical sense: The output will be zero either when Z2(s) behaves as a short circuit or when Z1(s) behaves as an open circuit. If there is a value of s at which both Z1 and Z2 are zero, then Vo/Vi will be finite and no transmission zero is obtained. Similarly, if there is a value of s at which both Z1 and Z2 are infinite, then Vo/Vi will be finite and no transmission zero is realized.
17.5.3 Realization of the Low-Pass Function
Using the scheme just outlined, we see that to realize a low-pass function, node x is disconnected from ground and connected to Vi , as shown in Fig. 17.18(b). The transmission zeros of this circuit will be at the value of s for which the series impedance becomes
Z1 xL
Vi Z2 Vo Vi RC Vo
(a) General structure (b) LP yC zR
Vi R L Vo Vi C L Vo
(c) HP x L
(d) BP x L1
C1
C
y
yC2
Vi RVoVi L2 RVo
(e) Notch at0 L
C1 y
(f) General notch
x
C1
Vi C2 R Vo Vi C2 Vo
(g) LPN (n 0)
(h) LPN as s L1
C
x
y
Vi L2RVo
(i) HPN (n 0)
Figure17.18 Realizationofvarioussecond-orderfilterfunctionsusingtheLCRresonatorofFig.17.17(b):
(a) general structure, (b) LP, (c) HP, (d) BP, (e) notch at ω , (f) general notch, (g) LPN ω ≥ ω , (h) LPN
ass→∞,(i)HPN ωn <ω0 .
0n0
infinite (sL becomes infinite at s = ∞) and the value of s at which the shunt impedance becomes zero (1/[sC + (1/R)] becomes zero at s = ∞). Thus this circuit has two transmission zeros at s = ∞, as a second-order LP is supposed to. The transfer function can be written either by inspection or by using the voltage divider rule. Following the latter approach, we obtain
T(s)≡Vo=Z2=Y1= 1/sL
Vi Z1 +Z2 Y1 +Y2 (1/sL)+sC+(1/R)
= 1/LC
s2 +s(1/CR)+(1/LC)
17.5.4 Realization of the High-Pass Function
(17.37)
17.5 The Second-Order LCR Resonator 1319
To realize the second-order high-pass function, node y is disconnected from ground and connected to Vi , as shown in Fig. 17.18(c). Here the series capacitor introduces a transmission zero at s = 0 (dc), and the shunt inductor introduces another transmission zero at s = 0 (dc). Thus, by inspection, the transfer function may be written as
Vo a2s2
T(s)≡ V = s2 +s(ω /Q)+ω2 (17.38)
i00
where ω0 and Q are the natural mode parameters given by Eqs. (17.34) and (17.35) and a2 is the high-frequency transmission. The value of a2 can be determined from the circuit by observing that as s approaches ∞, the capacitor approaches a short circuit and Vo approaches Vi , resulting in a2 = 1.
17.5.5 Realization of the Bandpass Function
The bandpass function is realized by disconnecting node z from ground and connecting it to Vi, as shown in Fig.17.18(d). Here the series impedance is resistive and thus does not introduce any transmission zeros. These are obtained as follows: One zero at s = 0 is realized by the shunt inductor, and one zero at s = ∞ is realized by the shunt capacitor. At the center frequency ω0, the parallel LC-tuned circuit exhibits an infinite impedance, and thus no current flows in the circuit. It follows that at ω = ω0, Vo = Vi. In other words, the center-frequency gain of the bandpass filter is unity. Its transfer function can be obtained as follows:
T(s)= YR = 1/R
YR +YL +YC (1/R)+(1/sL)+sC
= s(1/CR)
s2 +s(1/CR)+(1/LC)
17.5.6 Realization of the Notch Functions
(17.39)
To obtain a pair of transmission zeros on the jω axis, we use a parallel resonance circuit in the
series arm, as shown in Fig. 17.18(e). Observe that this circuit is obtained by disconnecting
i
both nodes x and y from ground and connecting them together to V . The impedance of the LC
√
circuit becomes infinite at ω = ω0 = 1/ LC, thus causing zero transmission at this frequency.
The shunt impedance is resistive and thus does not introduce transmission zeros. It follows
1320 Chapter 17
Filters and Tuned Amplifiers
that the circuit in Fig. 17.18(e) will realize the notch transfer function
T(s)=a s2 +ω20 (17.40)
The value of the high-frequency gain a2 can be found from the circuit to be unity.
To obtain a notch-filter realization in which the notch frequency ωn is arbitrarily placed relative to ω0, we adopt a variation on the scheme above. We still use a parallel LC circuit in
the series branch, as shown in Fig. 17.18(f), where L1 and C1 are selected so that
L1C1 = 1/ω2n (17.41)
Thus the L1C1 tank circuit will introduce a pair of transmission zeros at ±jωn, provided the L2C2 tank is not resonant at ωn. Apart from this restriction, the values of L2 and C2 must be selected to ensure that the natural modes have not been altered; thus,
C1 + C2 = C (17.42)
L1∥L2 =L (17.43)
In other words, when Vi is replaced by a short circuit, the circuit should reduce to the original LCR resonator. Another way of thinking about the circuit of Fig. 17.18(f) is that it is obtained from the original LCR resonator by lifting part of L and part of C off ground and connecting them to Vi.
It should be noted that in the circuit of Fig. 17.18(f), L2 does not introduce a zero at s = 0 because at s = 0, the L1C1 circuit also has a zero. In fact, at s = 0 the circuit reduces to an inductive voltage divider with the dc transmission being L2/(L1 +L2). Similar comments can be made about C2 and the fact that it does not introduce a zero at s = ∞ and that the transmission at s = ∞ is C1 /(C1 + C2 ).
The LPN and HPN filter realizations are special cases of the general notch circuit of Fig. 17.18(f). Specifically, for the LPN,
ωn >ω0
and thus
L1C1 < (L1 ∥L2)(C1 + C2)
This condition can be satisfied with L2 eliminated (i.e., L2 = ∞ and L1 = L), resulting in the
2 s2 +s(ω0/Q)+ω20
LPN circuit in Fig. 17.18(g). The transfer function can be written by inspection as T(s)≡Vo =a s2+ω2n
(17.44) whereω2n =1/LC1,ω20 =1/L(C1 +C2),ω0/Q=1/CR,anda2 isthehigh-frequencygain.From
V 2 s2 +s(ω /Q)+ω2 i00
the circuit we see that as s → ∞, the circuit reduces to that in Fig. 17.18(h), for which
Vo= C1
Vi C1 +C2
Thus,
(17.45) To obtain an HPN realization we start with the circuit of Fig. 17.18(f) and use the fact that
ωn < ω0 to obtain
L1C1 >(L1∥L2)(C1 +C2)
which can be satisfied while selecting C2 = 0 (i.e., C1 = C). Thus we obtain the reduced circuit shown in Fig. 17.18(i). Observe that as s → ∞, Vo approaches Vi and thus the high-frequency gain is unity. Thus, the transfer function can be expressed as
T(s)≡ Vo = s2 +(1/L1C)
Vi s2 +s(1/CR)+[1/(L1∥L2)C]
17.5.7 Realization of the All-Pass Function
(17.46)
(17.47)
(17.48)
a2 = C1 C1 +C2
17.5 The Second-Order LCR Resonator 1321
The all-pass transfer function
can be written as
T(s)= s2 −s(ω0/Q)+ω20 s2 +s(ω0/Q)+ω20
T (s) = 1 − s2(ω0 /Q)
s2 +s(ω0/Q)+ω20
The second term on the right-hand side is a bandpass function with a center-frequency gain of 2. We already have a bandpass circuit (Fig. 17.18d), but with a center-frequency gain of unity. We shall therefore attempt an all-pass realization with a flat gain of 0.5, that is,
T(s)=0.5− s(ω0/Q)
s2 +s(ω0/Q)+ω20
This function can be realized using a voltage divider with a transmission ratio of 0.5 together with the bandpass circuit of Fig. 17.18(d). To effect the subtraction, the output of the all-pass circuit is taken between the output terminal of the voltage divider and that of the bandpass filter, as shown in Fig. 17.19. Unfortunately this circuit has the disadvantage of lacking a common ground terminal between the input and the output. An op amp–RC realization of the all-pass function will be presented in the next section.
R1 R
Vi
Vo
CL
R1
Figure17.19 Realizationofthesecond-orderall-pass transfer function using a voltage divider and an LCR resonator.
1322 Chapter 17 Filters and Tuned Amplifiers
EXERCISES
17.17 Use the circuit of Fig. 17.18(b) to realize a second-order low-pass function of the maximally flat type with a 3-dB frequency of 100 kHz.
Ans. SelectingR=1k,weobtainC=1125pFandL=2.25mH.
17.18 Use the circuit of Fig. 17.18(e) to design a notch filter to eliminate a bothersome power-supply hum at a 60-Hz frequency. The filter is to have a 3-dB bandwidth of 10 Hz (i.e., the attenuation is greater than 3 dB over a 10-Hz band around the 60-Hz center frequency; see Exercise 17.15 and Fig. 17.16d). Use R = 10 k.
Ans. C = 1.6 μF and L = 4.42 H (Note the large inductor required. This is why passive filters are not practical in low-frequency applications.)
17.6 Second-Order Active Filters Based on Inductor Replacement
In this section, we study a family of op amp–RC circuits that realize the various second-order filter functions. The circuits are based on an op amp–RC resonator obtained by replacing the inductor L in the LCR resonator with an op amp–RC circuit that has an inductive input impedance.
17.6.1 The Antoniou Inductance-Simulation Circuit
Over the years, many op amp–RC circuits have been proposed for simulating the operation of an inductor. Of these, one circuit invented by A. Antoniou6 (see Antoniou, 1969) has proved to be the “best.” By “best” we mean that the operation of the circuit is very tolerant of the nonideal properties of the op amps, in particular their finite gain and bandwidth. Figure 17.20(a) shows the Antoniou inductance-simulation circuit. If the circuit is fed at its input (node 1) with a voltage source V1 and the input current is denoted I1, then for ideal op amps the input impedance can be shown to be
Zin ≡ V1/I1 = sC4R1R3R5/R2 (17.49) which is that of an inductance L given by
L = C4R1R3R5/R2 (17.50)
Figure 17.20(b) shows the analysis of the circuit assuming that the op amps are ideal and thus that a virtual short circuit appears between the two input terminals of each op amp, and assuming also that the input currents of the op amps are zero. The analysis begins at node 1, which is assumed to be fed by a voltage source V1 , and proceeds step by step, with the order of the steps indicated by the circled numbers. The result of the analysis is the expression shown for the input current I1 from which Zin is found.
6Andreas Antoniou is a Canadian academic, currently (2014) a professor emeritus of electrical and computer engineering at the University of Victoria, Victoria, British Columbia.
17.6 Second-Order Active Filters Based on Inductor Replacement 1323
(a)
(b)
Figure 17.20 (a) The Antoniou inductance-simulation circuit. (b) Analysis of the circuit assuming ideal op amps. The order of the analysis steps is indicated by the circled numbers.
The design of this circuit is usually based on selecting R1 = R2 = R3 = R5 = R and C4 = C, which leads to L = CR2 . Convenient values are then selected for C and R to yield the desired inductance value L. More details on this circuit and the effect of the nonidealities of the op amps on its performance can be found in Sedra and Brackett (1978).
17.6.2 The Op Amp–RC Resonator
Figure 17.21(a) shows the LCR resonator we studied in detail in Section 17.5. Replacing the inductor L with a simulated inductance realized by the Antoniou circuit of Fig. 17.20(a) results in the op amp–RC resonator of Fig. 17.21(b). (Ignore for the moment the additional amplifier
1324 Chapter 17
Filters and Tuned Amplifiers
Vr
R6 C6 L zyx
(a)
K
Vo
A1
C4
R1 R2 R3
Vr
R5 zyA2 x
R6 C6
L C4R1R3R5/R2 (b)
r2
r2 K1r
r1
K
1 (c)
Figure 17.21 (a) An LCR resonator. (b) An op amp–RC resonator obtained by replacing the inductor L in the LCR resonator of (a) with a simulated inductance realized by the Antoniou circuit of Fig. 17.20(a). (c) Implementation of the buffer amplifier K.
drawn with broken lines.) The circuit of Fig. 17.21(b) is a second-order resonator having a pole frequency
ω0 = 1/ LC6 = 1/ C4C6R1R3R5/R2 (17.51)
where we have used the expression for L given in Eq. (17.50). The pole Q factor can be obtainedusingtheexpressioninEq.(17.35)withC=C6 andR=R6;thus,Q=ω0 C6 R6.
17.6 Second-Order Active Filters Based on Inductor Replacement 1325 Replacing ω0 by the expression in Eq. (17.51) gives
Q=ωCR=R C6 R2 066 6C4R1R3R5
Usually one selects C4 =C6 =C and R1 =R2 =R3 =R5 =R, which results in ω0 = 1/CR
Q = R6/R
(17.52)
(17.53) (17.54)
Thus, if we select a practically convenient value for C, we can use Eq. (17.53) to determine the value of R to realize a given ω0 , and then use Eq. (17.54) to determine the value of R6 to realize a given Q.
17.6.3 Realization of the Various Filter Types
The op amp–RC resonator of Fig. 17.21(b) can be used to generate circuit realizations for the various second-order filter functions by following the approach described in detail in Section 17.5 in connection with the LCR resonator. Thus to obtain a bandpass function, we disconnect node z from ground and connect it to the signal source Vi . A high-pass function is obtained by injecting Vi to node y. To realize a low-pass function using the LCR resonator, the inductor terminal x is disconnected from ground and connected to Vi. The corresponding node in the active resonator is the node at which R5 is connected to ground,7 labeled as node x in Fig. 17.21(b). A regular notch function (ωn = ω0 ) is obtained by feeding Vi to nodes x and y. In all cases the output can be taken as the voltage across the resonance circuit, Vr. However, this is not a convenient node to use as the filter output terminal because connecting a load there would change the filter characteristics. The problem can be solved easily by utilizing a buffer amplifier. This is the amplifier of gain K, drawn with broken lines in Fig. 17.21(b). Figure 17.21(c) shows how this amplifier can be simply implemented using an op amp connected in the noninverting configuration. Note that not only does the amplifier K buffer the output of the filter, but it also allows the designer to set the filter gain to any desired value by appropriately selecting the value of K.
Figure 17.22 shows the various second-order filter circuits obtained from the resonator of Fig. 17.21(b). The transfer functions and design equations for these circuits are given in Table 17.1. Note that the transfer functions can be written by analogy to those of the LCR resonator. We have already commented on the LP, HP, BP, and regular-notch circuits given in Fig. 17.22(a) to (d). The LPN and HPN circuits in Fig. 17.22(e) and (f) are obtained by direct analogy to their LCR counterparts in Fig. 17.18(g) and (i), respectively. The all-pass circuit in Fig. 17.22(g), however, deserves some explanation.
17.6.4 The All-Pass Circuit
From Eq. (17.48) we see that an all-pass function with a flat gain of unity can be written as
AP = 1 − (BP with a center-frequency gain of 2) (17.55)
Two circuits whose transfer functions are related in this fashion (i.e., the transfer function of one is equal to unity minus the transfer function of the other) are said to be
7This point might not be obvious! The reader, however, can show by direct analysis that when Vi is fed tothisnode,thefunctionVr/Vi isindeedlowpass.
1326 Chapter 17
Filters and Tuned Amplifiers
K
R6 C6
R1
Vo
A2
Vo
A1
(a) LP
R2
R3
C4 R5 x
Vi
K
yC6 R1 R2 R3 C4
A1
ViR6 R5 A2
K
(b) HP
Vo
A1
zR6 R1 R2 R3 C4
ViC6 R5 A2
(c) BP
Figure 17.22 Realizations for the various second-order filter functions using the op amp–RC resonator of Fig. 17.21(b): (a) LP, (b) HP, (c) BP. The circuits are based on the LCR circuit in Fig. 17.18. Design considerations are given in Table 17.1.
17.6 Second-Order Active Filters Based on Inductor Replacement 1327
Vo
K
yC6 R1 R2 R3 C4
Vx R6
i A2 R5
(d) Notch at0
Vo
K
yC61 RRRC
A1
A1
1 1234
x C62R6
Vi y2 R
(e)LPN,n 0 Vo
K
yC6 R1 R2 R3 C4
x1 R6 R51 R52 Vi x
(f)HPN,n 0
Figure 17.22 continued (d) Notch at ω0 ; (e) LPN, ωn ≥ ω0 ; (f) HPN, ωn ≤ ω0 .
A2 5
A1
A2 2
1328 Chapter 17
Filters and Tuned Amplifiers
r1
C6
r2
Vo
A1
Vi
R6
R R R C4 123
A2
(g) All-pass
R5
Figure17.22 continued(g)Allpass.
Table 17.1
Circuit
Resonator
Fig. 17.21(b)
Low-pass (LP)
Fig. 17.22(a)
High-pass (HP)
Fig. 17.22(b)
Bandpass (BP)
Fig. 17.22(c)
Regular notch (N)
Fig. 17.22(d)
Design Data for the Circuits of Fig. 17.22
Transfer Function and Other Parameters
ω0 = 1/C4C6R1R3R5/R2
Design Equations
Q=R6
T(s)=
T(s)=
T(s)=
T(s)=
C6 R2 C4 R1R3R5
KR2/C4C6R1R3R5 s2+s1+ R2
C6R6 C4C6R1R3R5 Ks2
1R s2+s + 2
C6R6 C4C6R1R3R5 Ks/C6 R6
s2+s1+ R2 C6R6 C4C6R1R3R5
2 K s + R2/C4C6R1R3R5
1R s2 + s + 2
C4 = C6 = C (practical value) R1 =R2 =R3 =R5 =1/ω0C
R6=Q/ω0C K=DCgain
K = High-frequency gain
K = Center-frequency gain
C6R6
C4C6R1R3R5
K = Low- and high-frequency gain
s2+s + 2 C6R6 C4C6R1R3
ωn = 1/ C4C6R1R3R51/R2
R51
+
R52
17.6 Second-Order Active Filters Based on Inductor Replacement 1329
Low-pass notch (LPN) Fig. 17.22(e)
T(s)=K C61 C61 + C62
×
s2+R/CC RRR 2 4 61 1 3 5
s2+s 1+ R2
C61 + C62 R6 C4 C61 + C62 R1R3R5
K = DC gain
C61 +C62 =C6 =C 2
C61 =C ω0/ωn C62 =C−C61
K = High-frequency gain
1 + 1 = 1 =ω0C R51 R52 R5
2 R51=R5 ω0/ωn
ωn = 1/ C4C61R1R3R5/R2
ω0 =1/ C4 C61 +C62 R1R3R5/R2
Q = R 6
C61 + C62 R2
C4
T(s)=K 1 R 1 1
R1R3R5 s2+R/CCRRR
High-pass notch (HPN) Fig. 17.22(f)
2 4 6 1 3 51
R11 ω0=2 +
R52 =R5
2 1− ωn/ω0
C4 C6 R1 R3
R51 R52
Q=R C6 R2 1+1
6
T(s)=
C4 R1R3 s2−s1r2+ R2
R51 R52
All-pass (AP) Fig. 17.22(g)
C6R6 r1 C4C6R1R3R5 s2+s1+ R2
r1 = r2 = r (arbitrary) Adjustr2 tomakeQz =Q
C6R6 C4C6R1R3R5
ω =ω Q =Qr /r Flatgain=1
z0z12
complementary.8 Thus the all-pass circuit with unity flat gain is the complement of the bandpass circuit with a center-frequency gain of 2. A simple procedure exists for obtaining the complement of a given linear circuit: Disconnect all the circuit nodes that are connected to ground and connect them to Vi, and disconnect all the nodes that are connected to Vi and connect them to ground. That is, interchanging input and ground in a linear circuit generates a circuit whose transfer function is the complement of that of the original circuit.
Returning to the problem at hand, we first use the circuit of Fig. 17.22(c) to realize a BP with a gain of 2 by simply selecting K = 2 and implementing the buffer amplifier with the circuit of Fig. 17.21(c) with r1 = r2 . We then interchange input and ground and thus obtain the all-pass circuit of Fig. 17.22(g).
Finally, in addition to being simple to design, the circuits in Fig. 17.22 exhibit excellent performance. They can be used on their own to realize second-order filter functions, or they can be cascaded to implement high-order filters.
8 More about complementary circuits will be presented later in conjunction with Fig. 17.31.
1330 Chapter 17 Filters and Tuned Amplifiers
EXERCISES
D17.19 Use the circuit of Fig. 17.22(c) to design a second-order bandpass filter with a center frequency of 10 kHz, a 3-dB bandwidth of 500 Hz, and a center-frequency gain of 10. Use C = 1.2 nF. Ans. R1 =R2 =R3 =R5 =13.26 k; R6 =265 k; C4 =C6 =1.2 nF; K =10, r1 =10 k, r2 = 90 k
D17.20 Realize the Chebyshev filter of Example 17.2, whose transfer function is given in Eq. (17.25), as the cascade connection of three circuits: two of the type shown in Fig. 17.22(a) and one first-order op amp–RC circuit of the type shown in Fig. 17.13(a). Note that you can make the dc gain of all sections equal to unity. Do so. Use as many 10-k resistors as possible.
Ans. First-order section: R1 = R2 = 10 k, C = 5.5 nF; second-order section with ω0 = 4.117 × 104 rad/sandQ=1.4:R1 =R2 =R3 =R5 =10k,R6 =14k,C4 =C6 =2.43nF,r1 =∞,r2 =0; second-order section with ω0 =6.246 × 104 rad/s and Q=5.56: R1 =R2 =R3 =R5 =10 k, R6 =55.6 k, C4 =C6 =1.6 nF, r1 =∞, r2 =0
17.7 Second-Order Active Filters Based on the Two-Integrator-Loop Topology
In this section, we study another family of op amp–RC circuits that realize second-order filter functions. The circuits are based on the use of two integrators connected in cascade in an overall feedback loop and are thus known as two-integrator-loop circuits.
17.7.1 Derivation of the Two-Integrator-Loop Biquad
To derive the two-integrator-loop biquadratic circuit, or biquad as it is commonly known,9 consider the second-order high-pass transfer function
Vhp Ks2
V = s2 +s(ω /Q)+ω2 (17.56)
where K is the high-frequency gain. Cross-multiplying Eq. (17.56) and dividing both sides of the resulting equation by s2 (to get all the terms involving s in the form 1/s, which is the transfer function of an integrator) gives
2
Vhp+1 ω0Vhp + ω0Vhp =KVi (17.57)
Qs s2
In this equation we observe that the signal (ω0 /s)Vhp can be obtained by passing Vhp through an
integrator with a time constant equal to 1/ω0 . Furthermore, passing the resulting signal through
9The name biquad stems from the fact that this circuit in its most general form is capable of realizing a biquadratic transfer function, that is, one that is the ratio of two quadratic polynomials.
i00
17.7 Second-Order Active Filters Based on the Two-Integrator-Loop Topology 1331
another identical integrator results in the third signal involving Vhp in Eq. (17.57)—namely, (ω20 /s2 )Vhp . Figure 17.23(a) shows a block diagram for such a two-integrator arrangement. Note
that in anticipation of the use of the inverting op-amp Miller integrator circuit (Section 2.5.2) to implement each integrator, the integrator blocks in Fig. 17.23(a) have been assigned negative signs.
The problem still remains, however, of how to form Vhp, the input signal feeding the two cascaded integrators. Toward that end, we rearrange Eq. (17.57), expressing Vhp in terms of its single- and double-integrated versions and of Vi as
Vhp = KVi − 1 ω0 Vhp − ω20 V hp (17.58) Qs s2
which suggests that Vhp can be obtained by using the weighted summer of Fig. 17.23(b). Now it should be easy to see that a complete block diagram realization can be obtained by combining the integrator blocks of Fig. 17.23(a) with the summer block of Fig. 17.23(b), as shown in Fig. 17.23(c).
In the realization of Fig. 17.23(c), Vhp , obtained at the output of the summer, realizes the high-pass transfer function Thp ≡ Vhp /Vi of Eq. (17.56). The signal at the output of the first integrator is –(ω0/s)Vhp, which is a bandpass function,
(−ω0/s)Vhp =− Kω0s =Tbp(s) (17.59)
Vi
s2 +s(ω0/Q)+ω20
(a)
(b)
Figure 17.23 Derivation of a block diagram realization of the two-integrator-loop biquad.
(c)
1332 Chapter 17
Filters and Tuned Amplifiers
Therefore the signal at the output of the first integrator is labeled Vbp. Note that the center-frequency gain of the bandpass filter realized is equal to –KQ.
In a similar fashion, we can show that the transfer function realized at the output of the second integrator is the low-pass function,
ω20/s2Vhp = Kω20 =Tlp(s) (17.60) Vi s2 +s(ω0/Q)+ω20
Thus the output of the second integrator is labeled Vlp. Note that the dc gain of the low-pass filter realized is equal to K.
We conclude that the two-integrator-loop biquad shown in block diagram form in Fig. 17.23(c) realizes the three basic second-order filtering functions, LP, BP, and HP, simultaneously. This versatility has made the circuit very popular and has given it the name universal active filter.
17.7.2 Circuit Implementation
To obtain an op-amp circuit implementation of the two-integrator-loop biquad of Fig. 17.23(c), we replace each integrator with a Miller integrator circuit having CR = 1/ω0, and we replace the summer block with an op-amp summing circuit that is capable of assigning both positive and negative weights to its inputs. The resulting circuit, known as the Kerwin–Huelsman–Newcomb or KHN biquad, after its inventors, is shown in Fig. 17.24(a). Given values for ω0, Q, and K, the design of the circuit is straightforward: We select suitably practical values for the components C and R of the integrators so that CR = 1/ω0 . To determine the values of the resistors associated with the summer, we first use superposition to express the output of the summer Vhp in terms of its inputs, Vi, Vbp, and Vlp as
(17.61)
(17.62)
RRRRR
V=V31+f+V21+f−Vf
hp iR +R R bpR +R R lpR 2312311
Substituting V = −(ω /s)V and V = ω 2 /s2 V gives bp 0 hp lp 0 hp
2 Vhp = R3 1+ Rf Vi + R2 1+ Rf −ω0 Vhp − Rf ω0 Vhp
R2 +R3 R1 R2 +R3 R1 s R1 s2 Equating the last right-hand-side terms of Eqs. (17.61) and (17.58) gives
Rf /R1 = 1
which implies that we can select arbitrary but practically convenient equal values for R1 and Rf . Then, equating the second-to-last terms on the right-hand side of Eqs. (17.61) and (17.58) and setting R1 = Rf yields the ratio R3 /R2 required to realize a given Q as
R3/R2 =2Q−1 (17.63)
Thus an arbitrary but convenient value can be selected for either R2 or R3, and the value of the other resistance can be determined using Eq. (17.63). Finally, equating the coefficients of Vi inEqs.(17.61)and(17.58)andsubstitutingRf =R1 andforR3/R2 fromEq.(17.63)resultsin
K = 2 − (1/Q) (17.64)
17.7 Second-Order Active Filters Based on the Two-Integrator-Loop Topology 1333 R1
Rf C
R2 R R
C
Vlp
Vi
Vhp
R3
(a)
RH
Vhp
RB
RF
Vbp
Vo
Vbp Vlp
RL
(b)
Figure 17.24 (a) The KHN biquad circuit, obtained as a direct implementation of the block diagram of Fig. 17.23(c). The three basic filtering functions, HP, BP, and LP, are simultaneously realized. (b) To obtain notch and all-pass functions, the three outputs are summed with appropriate weights using this op-amp summer.
Thus the gain parameter K is fixed to this value.
The KHN biquad can be used to realize notch and all-pass functions by summing
weighted versions of the three outputs, LP, BP, and HP. Such an op-amp summer is shown in Fig. 17.24(b); for this summer we can write
RRR Vo=− FVhp+ FVbp+ FVlp
(17.65)
HBL
SubstitutingforThp,Tbp,andTlp fromEqs.(17.56),(17.59),and(17.60),respectively,gives
the overall transfer function
Vo =−K(RF/RH)s2 −s(RF/RB)ω0 +(RF/RL)ω20 (17.66)
Vi s2 +s(ω0/Q)+ω20
from which we can see that different transmission zeros can be obtained by the appropriate selection of the values of the summing resistors. For instance, a notch is obtained by selecting RB =∞and
R ω2
H= n (17.67) RL ω0
RH RB RL RRR
=−V FT+FT+FT
i R hp R bp R lp
1334 Chapter 17
Filters and Tuned Amplifiers
17.7.3 An Alternative Two-Integrator-Loop Biquad Circuit
An alternative two-integrator-loop biquad circuit in which all three op amps are used in a single-ended mode can be developed as follows: Rather than using the input summer to add signals with positive and negative coefficients, we can introduce an additional inverter, as shown in Fig. 17.25(a). Now all the coefficients of the summer have the same sign, and we can dispense with the summing amplifier altogether and perform the summation at the virtual-ground input of the first integrator. Observe that the summing weights of 1, 1/Q, and K are realized by using resistances of R, QR, and R/K, respectively. The resulting circuit is shown in Fig. 17.25(b), from which we observe that the high-pass function is no longer available! This is the price paid for obtaining a circuit that utilizes all op amps in a single-ended mode. The circuit of Fig. 17.25(b) is known as the Tow–Thomas biquad, after its originators.
Rather than using a fourth op amp to realize the finite transmission zeros required for the notch and all-pass functions, as was done with the KHN biquad, an economical feedforward scheme can be employed with the Tow–Thomas circuit. Specifically, the virtual ground available at the input of each of the three op amps in the Tow–Thomas circuit permits the input signal to be fed to all three op amps, as shown in Fig. 17.26. If Vo is taken at the output of the damped integrator, straightforward analysis yields the filter transfer function
C 11 r 1 s2 1 +s − +
Vo=−CCR1RR3 C2RR2 Vi s2+s 1 + 1
(17.68)
QCR C2R2 which can be used to obtain the design data given in Table 17.2.
1
Vi K Vhp Vbp (a)
R
Rd QR
Vlp
Vlp
1
Q
0 s
0 s
1
CC VKRr
r
Rg R i
Vlp
Vbp
(b)
Vlp
Figure17.25 (a)Derivationofanalternativetwo-integrator-loopbiquadinwhichallopampsareusedina single-ended fashion. (b) The resulting circuit, known as the Tow–Thomas biquad.
17.7 Second-Order Active Filters Based on the Two-Integrator-Loop Topology 1335
Figure 17.26 The Tow–Thomas biquad with feedforward. The transfer function of Eq. (17.68) is realized by feeding the input signal through appropriate components to the inputs of the three op amps. This circuit can realize all special second-order functions. The design equations are given in Table 17.2.
Table 17.2
All cases
LP
Positive BP
Negative BP
HP
Notch
(all types)
AP
17.7.4 Final Remarks
Two-integrator-loop biquads are extremely versatile and easy to design. However, their performance is adversely affected by the finite bandwidth of the op amps. Special techniques exist for compensating the circuit for such effects (see the SPICE simulation example on the website, and Sedra and Brackett, 1978).
EXERCISES
D17.21 Design the KHN circuit to realize a high-pass function with f0 = 10 kHz and Q = 2. Choose C = 1 nF. What is the value of high-frequency gain obtained? What is the center-frequency gain of the bandpass function that is simultaneously available at the output of the first integrator? Ans. R=15.9k;R1 =Rf =R2 =10k(arbitrary);R3 =30k;1.5;3
Design Data for the Circuit in Fig. 17.26
C = arbitrary, R = 1/ω0C, r = arbitrary
C1 =0, R1 =∞, R2 =R/dc gain, R3 =∞
C1 = 0, R1 = ∞, R2 = ∞, R3 = Qr/center-frequency gain
C1 = 0, R1 = QR/center-frequency gain, R2 = ∞, R3 = ∞
C1 =C× high-frequency gain, R1 =∞, R2 =∞, R3 =∞
C1 = C × high-frequency gain, R1 = ∞,
R =Rω/ω2/high-frequencygain,R =∞
20n3
C1 =C× flat gain, R1 =∞, R2 =R/gain, R3 =Qr/gain
1336
Chapter 17 Filters and Tuned Amplifiers
D17.22 Use the KHN circuit together with an output summing amplifier to design a low-pass notch filter withf0 =5kHz,fn =8kHz,Q=5,andadcgainof3.SelectC=1nFandRL =10k.
Ans. R=31.83k;R1 =Rf =R2 =10k(arbitrary);R3 =90k;RH =25.6k;RF =16.7k; RB =∞
D17.23 Use the Tow–Thomas biquad [Fig. 17.25(b)] to design a second-order bandpass filter with f0 = 10 kHz, Q = 20, and unity center-frequency gain. If R = 10 k, give the values of C, Rd , and Rg . Ans. 1.59 nF; 200 k; 200 k
D17.24 Use the data of Table 17.2 to design the biquad circuit of Fig. 17.26 to realize an all-pass filter withω0 =104 rad/s,Q=5,andflatgain=1.UseC=10nFandr=10k.
Ans. R=10k;Q-determiningresistor=50k;C1 =10nF;R1 =∞;R2 =10k;R3 =50k
17.8 Single-Amplifier Biquadratic Active Filters
The op amp–RC biquadratic circuits studied in the two preceding sections provide good performance, are versatile, and are easy to design and to adjust (tune) after final assembly. Unfortunately, however, they are not economic in their use of op amps, requiring three or four amplifiers per second-order section. This can be a problem, especially in applications that call for conservation of power-supply current: for instance, in a battery-operated instrument. In this section we shall study a class of second-order filter circuits that requires only one op amp per biquad. These minimal realizations, however, suffer a greater dependence on the limited gain and bandwidth of the op amp and can also be more sensitive to the unavoidable tolerances in the values of resistors and capacitors than the multiple-op-amp biquads of the preceding sections. The single-amplifier biquads (SABs) are therefore limited to the less stringent filter specifications—for example, pole Q factors less than about 10.
The synthesis of SAB circuits is based on the use of feedback to move the poles of an RC circuit from the negative real axis, where they naturally lie, to the complex-conjugate locations required to provide selective filter response. The synthesis of SABs follows a two-step process:
1. Synthesis of a feedback loop that realizes a pair of complex-conjugate poles characterized by a frequency ω0 and a Q factor Q.
2. Injecting the input signal in a way that realizes the desired transmission zeros. 17.8.1 Synthesis of the Feedback Loop
Consider the circuit shown in Fig. 17.27(a), which consists of a two-port RC network n placed in the negative-feedback path of an op amp. We shall assume that, except for having a finite gain A, the op amp is ideal. We shall denote by t(s) the open-circuit voltage-transfer function of the RC network n, where the definition of t(s) is illustrated in Fig. 17.27(b). The transfer function t(s) can in general be written as the ratio of two polynomials N(s) and D(s):
t(s)= N(s) D(s)
A
(a) (b)
Figure17.27 (a)Feedbackloopobtainedbyplacingatwo-portRCnetworkninthefeedbackpathofanop amp. (b) Definition of the open-circuit transfer function t(s) of the RC network.
The roots of N(s) are the transmission zeros of the RC network, and the roots of D(s) are its poles. Study of circuit theory shows that while the poles of an RC network are restricted to lie on the negative real axis, the zeros can in general lie anywhere in the s plane.
The loop gain L(s) of the feedback circuit in Fig. 17.27(a) can be determined using the method of Section 11.3.3. It is simply the product of the op-amp gain A and the transfer function t(s),
L(s) = At(s) = AN(s) D(s)
Substituting for L(s) into the characteristic equation 1 + L(s) = 0
results in the poles sP of the closed-loop circuit obtained as solutions to the equation t(sP ) = − 1
A
In the ideal case, A = ∞ and the poles are obtained from
N (sP ) = 0
(17.69)
(17.70)
(17.71)
(17.72)
ω1111
s 2 + s 0 + ω 20 = s 2 + s + Q C1
C2 R3
+
C1C2R3R4
17.8 Single-Amplifier Biquadratic Active Filters 1337
That is, the filter poles are identical to the zeros of the RC network.
Since our objective is to realize a pair of complex-conjugate poles, we should select an RC
network that can have complex-conjugate transmission zeros. The simplest such networks are the bridged-T networks shown in Fig. 17.28 together with their transfer functions t(s) from b to a, with a open-circuited. As an example, consider the circuit generated by placing the bridged-T network of Fig. 17.28(a) in the negative-feedback path of an op amp, as shown in Fig. 17.29. The pole polynomial of the active-filter circuit will be equal to the numerator polynomial of the bridged-T network; thus,
1338 Chapter 17
Filters and Tuned Amplifiers
ab
(a)
ab
(b)
Figure17.28 TwoRCnetworks(calledbridged-Tnetworks)thatcanhavecomplextransmissionzeros.The transfer functions given are from b to a, with a open-circuited.
which enables us to obtain ω0 and Q as
ω0 = √ 1
C1C2R3R4 √C C R R 1
Figure 17.29 An active-filter feedback loop generated using the bridged-T network of Fig. 17.28(a).
(17.73)
(17.74)
If we are designing this circuit, ω0 and Q are given and Eqs. (17.73) and (17.74) can be used to determine C1, C2, R3, and R4. It follows that there are two degrees of freedom. Let us
1 −1
Q=1234 +
R3 C1C2
17.8 Single-Amplifier Biquadratic Active Filters 1339 exhaust one of these by selecting C1 =C2 =C. Let us also denote R3 =R and R4 =R/m. By
substituting in Eqs. (17.73) and (17.74), and with some manipulation, we obtain
m = 4Q2 (17.75)
CR = 2Q (17.76) ω0
Thus if we are given the value of Q, Eq. (17.75) can be used to determine the ratio of the two resistances R3 and R4. Then the given values of ω0 and Q can be substituted in Eq. (17.76) to determine the time constant CR. There remains one degree of freedom—the value of C or R can be arbitrarily chosen. In an actual design, this value, which sets the impedance level of the circuit, should be chosen so that the resulting component values are practical.
EXERCISES
D17.25 Design the circuit of Fig. 17.29 to realize a pair of poles with ω0 = 104 rad/s and Q = 1. Select C1 =C2 =1nF.
Ans. R3 =200 k; R4 =50 k
17.26 For the circuit designed in Exercise 17.25, find the location of the poles of the RC network in the
feedback loop.
Ans. −0.382×104 and−2.618×104 rad/s
17.8.2 Injecting the Input Signal
Having synthesized a feedback loop that realizes a given pair of poles, we now consider connecting the input signal source to the circuit. We wish to do this, of course, without altering the poles.
Since, for the purpose of finding the poles of a circuit, an ideal voltage source is equivalent to a short circuit, it follows that any circuit node that is connected to ground can instead be connected to the input voltage source without causing the poles to change. Thus the method of injecting the input voltage signal into the feedback loop is simply to disconnect a component (or several components) that is (are) connected to ground and connect it (them) to the input source. Depending on the component(s) through which the input signal is injected, different transmission zeros are obtained. This is, of course, the same method we used in Section 17.5 with the LCR resonator and in Section 17.6 with the biquads based on the LCR resonator.
As an example, consider the feedback loop of Fig. 17.29. Here we have two grounded nodes (one terminal of R4 and the positive input terminal of the op amp) that can serve for injecting the input signal. Figure 17.30(a) shows the circuit with the input signal injected through part of the resistance R4. Note that the two resistances R4/α and R4/(1−α) have a parallel equivalent of R4.
Analysis of the circuit to determine its voltage-transfer function T(s) ≡ Vo(s)/Vi(s) is illustrated in Fig. 17.30(b). Note that we have assumed the op amp to be ideal and have
1340 Chapter 17
Filters and Tuned Amplifiers
(a)
2 Vo/R3
4 (Vo/R3)C2
(R4/)
3 0A
7 1 0V
(b)
R3
Vx
X
C1
5 Vx Vo sC2R3
sC1(Vo Vx)
Node equation at X
R4/(1) 8 Vx/(R4 (
6 9
ViVx Vi R4/
1
Vo
Figure17.30 (a)ThefeedbackloopofFig.17.29withtheinputsignalinjectedthroughpartofresistanceR4. This circuit realizes the bandpass function. (b) Analysis of the circuit in (a) to determine its voltage transfer function T(s) with the order of the analysis steps indicated by the circled numbers.
indicated the order of the analysis steps by the circled numbers. The final step, number 9, consists of writing a node equation at X and substituting for Vx by the value determined in step 5. The result is the transfer function
Vo −s(α/C1R4)
V=1111 i s2+s + +
C1 C2 R3 C1C2R3R4
We recognize this as a bandpass function whose center-frequency gain can be controlled by the value of α. As expected, the denominator polynomial is identical to the numerator polynomial of t(s) given in Fig. 17.28(a).
17.8 Single-Amplifier Biquadratic Active Filters 1341
EXERCISE
17.27 Use the component values obtained in Exercise 17.25 to design the bandpass circuit of Fig. 17.30(a). Determine the values of (R4/α) and R4/(1−α) to obtain a center-frequency gain of unity.
Ans. 100 k; 100 k
17.8.3 Generation of Equivalent Feedback Loops
The complementary transformation of feedback loops is based on the property of linear networks illustrated in Fig. 17.31 for the two-port (three-terminal) network n. In Fig. 17.31(a), terminal c is grounded and a signal Vb is applied to terminal b. The transfer function from b to a with c grounded is denoted t. Then, in Fig. 17.31(b), terminal b is grounded and the input signal is applied to terminal c. The transfer function from c to a with b grounded can be shown to be the complement of t—that is, 1 − t. (Recall that we used this property in generating a circuit realization for the all-pass function in Section 17.6.)
Application of the complementary transformation to a feedback loop to generate an equivalent feedback loop is a two-step process:
1. Nodes of the feedback network and any of the op-amp inputs that are connected to ground should be disconnected from ground and connected to the op-amp output. Conversely, those nodes that were connected to the op-amp output should be now connected to ground. That is, we simply interchange the op-amp output terminal with ground.
2. The two input terminals of the op amp should be interchanged.
The feedback loop generated by this transformation has the same characteristic equation, and
hence the same poles, as the original loop.
c
(a)
(b)
Figure 17.31 Interchanging input and ground results in the complement of the transfer function.
1342 Chapter 17
Filters and Tuned Amplifiers
t(s)
Network n
A
Network n
A
1 t(s)
Figure 17.32 Application of the complementary transformation to the feedback loop in (a) results in the equivalent loop (same poles) shown in (b).
To illustrate, we show in Fig. 17.32(a) the feedback loop formed by connecting a two-port RC network in the negative-feedback path of an op amp. Application of the complementary transformation to this loop results in the feedback loop of Fig. 17.32(b). Note that in the latter loop the op amp is used in the unity-gain follower configuration. We shall now show that the two loops of Fig. 17.32 are equivalent.
If the op amp has an open-loop gain A, the follower in the circuit of Fig. 17.32(b) will have a gain of A/(A + 1). This, together with the fact that the transfer function of network n from c to a is 1 – t (see Fig. 17.31), enables us to write for the circuit in Fig. 17.32(b) the characteristic equation
1− A (1−t)=0 A+1
This equation can be manipulated to the form
1 + At = 0
which is the characteristic equation of the loop in Fig. 17.32(a). As an example, consider the application of the complementary transformation to the feedback loop of Fig. 17.29: The feedback loop of Fig. 17.33(a) results. Injecting the input signal through C1 results in the circuit in Fig. 17.33(b), which can be shown (by direct analysis) to realize a second-order high-pass function. This circuit is one of a family of SABs known as the Sallen-and-Key circuits, after their originators. The design of the circuit in Fig. 17.33(b) is based on Eqs. (17.73) through (17.76): namely, R3 =R, R4 =R/4Q2, C1 =C2 =C, CR=2Q/ω0, and the value of C is arbitrarily chosen to be practically convenient.
As another example, Fig. 17.34(a) shows the feedback loop generated by placing the two-port RC network of Fig. 17.28(b) in the negative-feedback path of an op amp. For an ideal op amp, this feedback loop realizes a pair of complex-conjugate natural modes having
Figure 17.33 (a) Feedback loop obtained by applying the complementary transformation to the loop in Fig. 17.29. (b) Injecting the input signal through C1 realizes the high-pass function. This is one of the Sallen-and-Key family of circuits.
17.8 Single-Amplifier Biquadratic Active Filters 1343
(a) (b)
V
C3
R2
R1
C4
R2
C4
C3
R1
(a)
C3
(b)
R2
Vi
(c)
C4
Vo
R1
Figure 17.34 (a) Feedback loop obtained by placing the bridged-T network of Fig. 17.28(b) in the negative-feedback path of an op amp. (b) Equivalent feedback loop generated by applying the complementary transformation to the loop in (a). (c) A low-pass filter obtained by injecting Vi through R1 into the loop in (b).
1344 Chapter 17
Filters and Tuned Amplifiers
the same location as the zeros of t(s) of the RC network. Thus, using the expression for t(s)
given in Fig. 17.28(b), we can write for the active-filter poles
ω0 = 1/ C3C4R1R2 C C R R 1
(17.77) (17.78)
Normally the design of this circuit is based on selecting R1 = R2 = R, C4 = C, and C3 = C/m. When substituted in Eqs. (17.77) and (17.78), these yield
m = 4Q2 (17.79) CR = 2Q/ω0 (17.80)
with the remaining degree of freedom (the value of C or R) left to the designer to choose. Injecting the input signal to the C4 terminal that is connected to ground can be shown to result in a bandpass realization. If, however, we apply the complementary transformation to the feedback loop in Fig. 17.34(a), we obtain the equivalent loop in Fig. 17.34(b). The loop equivalence means that the circuit of Fig. 17.34(b) has the same poles and thus the same ω0 and Q and the same design equations (Eqs. 17.77 through 17.80). The new loop in Fig. 17.34(b) can be used to realize a low-pass function by injecting the input signal as shown
in Fig. 17.34(c).
In conclusion, we note that complementary transformation is a powerful tool that enables
us to obtain new filter circuits from ones we already have, thus increasing our repertoire of filter realizations.
Q= 3412 + C4 R1R2
1 −1
EXERCISES
17.28 Analyze the circuit in Fig. 17.34(c) to determine its transfer function Vo (s)/Vi (s) and thus show that ω0 and Q are indeed those in Eqs. (17.77) and (17.78). Also show that the dc gain is unity.
√ D17.29 Design the circuit in Fig. 17.34(c) to realize a low-pass filter with f0 = 4 kHz and Q = 1/ 2. Use
10-k resistors.
Ans. R1 =R2 =10 k; C3 =2.81 nF; C4 =5.63 nF
17.9 Sensitivity
Because of the tolerances in component values and because of the finite op-amp gain, the response of the actual assembled filter will deviate from the ideal response. As a means for predicting such deviations, the filter designer employs the concept of sensitivity. Specifically, for second-order filters one is usually interested in finding how sensitive their poles are relative to variations (both initial tolerances and future drifts) in RC component values and amplifier gain. These sensitivities can be quantified using the classical sensitivity function Sxy, defined as
Sy ≡ Lim y/y (17.81) x x→0 x/x
Thus,
S xy = ∂ y x ( 1 7 . 8 2 ) ∂x y
17.9 Sensitivity 1345
Here, x denotes the value of a component (a resistor, a capacitor, or an amplifier gain) and y denotes a circuit parameter of interest (say, ω0 or Q). For small changes
Sxy ≃ y/y (17.83) x/x
Thus we can use the value of Sxy to determine the per-unit change in y due to a given per-unit change in x. For instance, if the sensitivity of Q relative to a particular resistance R1 is 5, then a 1% increase in R1 results in a 5% increase in the value of Q.
Example 17.3
ForthefeedbackloopofFig.17.29,findthesensitivitiesofω0 andQrelativetoallthepassivecomponents and the op-amp gain. Evaluate these sensitivities for the design considered in the preceding section for whichC1 =C2.
Solution
To find the sensitivities with respect to the passive components, called passive sensitivities, we assume that the op-amp gain is infinite. In this case, ω0 and Q are given by Eqs. (17.73) and (17.74). Thus for ω0 we have
ω0= 1 C1C2R3R4
which can be used together with the sensitivity definition of Eq. (17.82) to obtain Sω0 =Sω0 =Sω0 =Sω0 =−1
For Q we have
2
1 1 1 −1
Q=
C1C2R3R4
C +C R 123
C1 C2 R3 R4
to which we apply the sensitivity definition to obtain
−1
SCQ=1 C2−C1 C2+C1 1 2 C1 C2 C1 C2
For the design with C1 = C2 we see that SCQ = 0. Similarly, we can show that 1
SCQ =0, SRQ = 1, SRQ =−1 23242
It is important to remember that the sensitivity expression should be derived before values corresponding to a particular design are substituted.
1346
Chapter 17 Filters and Tuned Amplifiers
Example 17.3 continued
Next we consider the sensitivities relative to the amplifier gain. If we assume the op amp to have a
finite gain A, the characteristic equation for the loop becomes
1 + At(s) = 0 (17.84)
where t(s) is given in Fig. 17.28(a). To simplify matters we can substitute for the passive components by their design values. This causes no errors in evaluating sensitivities, since we are now finding the sensitivity with respect to the amplifier gain. Using the design values obtained earlier—namely, C1 = C2 = C, R3 = R, R4 = R/4Q2, and CR = 2Q/ω0—we get
s2 +sω0/Q+ω20
t(s) = s2 + sω /Q(2Q2 + 1) + ω2 (17.85)
00
where ω0 and Q denote the nominal or design values of the pole frequency and Q factor. The actual values are obtained by substituting for t(s) in Eq. (17.84):
ωω s 2 + s 0 2 Q 2 + 1 + ω 20 + A s 2 + s 0 + ω 20
QQ
Assuming the gain A to be real and dividing both sides by A + 1, we get
Q A+1
From this equation we see that the actual pole frequency, ω0a, and the pole Q, Qa, are
ω 2Q2
s2+s 0 1+ +ω20=0
(17.86)
(17.87) (17.88)
= 0
Qa =
ω0a =ω0 Q
1+2Q2/(A+1) Sω0a =0
A
Thus
2Q2/(A+1)
A A+1 1+2Q2/(A+1)
SQa = A
SQa ≃ 2Q2
For A≫2Q2 and A≫1 we obtain
It is usual to drop the subscript a in this expression and write
SA ≃ A
Note that if Q is high (Q ≥ 5), its sensitivity relative to the amplifier gain can be quite high.10
(17.89)
AA Q 2Q2
10Because the open-loop gain A of op amps usually has wide tolerance, it is important to keep Sω0 and SQ very AA
small.
The results of Example17.3 indicate a serious disadvantage of single-amplifier biquads—the sensitivity of Q relative to the amplifier gain is quite high. Although a technique exists for reducing SAQ in SABs (see Sedra et al., 1980), this is done at the expense of increased passive sensitivities. Nevertheless, the resulting SABs are used extensively in many applications. However, for filters with Q factors greater than about 10, one usually opts for one of the multiamplifier biquads studied in Sections 17.6 and 17.7. For these circuits SAQ is proportional to Q, rather than to Q2 as in the SAB case (Eq. 17.89).
EXERCISE
17.30 In a particular filter utilizing the feedback loop of Fig. 17.29, with C1 = C2 , use the results of Example 17.3 to find the expected percentage change in ω0 and Q under the conditions that (a) R3 is 2% high, (b) R4 is 2% high, (c) both R3 and R4 are 2% high, and (d) both capacitors are 2% low and both resistors are 2% high.
Ans. (a) –1%, +1%; (b) –1%, –1%; (c) –2%, 0%; (d) 0%, 0%
17.10 Transconductance-C Filters
The op amp–RC circuits studied in Sections 17.4 and 17.6 through 17.8 are ideally suited for implementing audio-frequency filters using discrete op amps, resistors, and capacitors, assembled on printed-circuit boards. Such circuits have also been implemented in hybrid thin- or thick-film forms where the op amps are used in chip form (i.e., without their packages).
The limitation of op amp–RC filters to low-frequency applications is a result of the relatively low bandwidth of general-purpose op amps. The lack of suitability of these filter circuits for implementation in IC form stems from:
1. The need for large-valued capacitors, which would require impractically large chip areas;
2. The need for very precise values of RC time constants. This is impossible to achieve on an IC without resorting to expensive trimming and tuning techniques; and
3. The need for op amps that can drive resistive and large capacitive loads. As we have seen, CMOS op amps are usually capable of driving only small capacitances.
17.10.1 Methods for IC Filter Implementation
We now introduce the three approaches currently in use for implementing filters in monolithic form.
Transconductance-C Filters These utilize transconductance amplifiers or simply trans- conductors together with capacitors and are hence called Gm–C filters. Because high-quality and high-frequency transconductors can be easily realized in CMOS technology, where small-valued capacitors are plentiful, this filter-design method is very popular at this time. It
17.10 Transconductance-C Filters 1347
1348 Chapter 17
Filters and Tuned Amplifiers
has been used at medium and high frequencies approaching the hundreds of megahertz range. We shall study this method briefly in this section.
MOSFET-C Filters These utilize the two-integrator-loop circuits of Section 17.8 but with the resistors replaced with MOSFETs operating in the triode region. Clever techniques have been evolved to obtain linear operation with large input signals. Because of space limitations, we shall not study this design method here and refer the reader to Tsividis and Voorman (1992).
Switched-Capacitor Filters These are based on the ingenious technique of obtaining a large resistance by switching a capacitor at a relatively high frequency. Because of the switching action, the resulting filters are discrete-time circuits, as opposed to the continuous-time filters studied thus far. The switched-capacitor approach is ideally suited for implementing low-frequency filters in IC form using CMOS technology. We shall study switched-capacitor filters in Section 17.11.
EARLY FILTER PIONEERS—CAUER AND DARLINGTON:
While on a fellowship with Vannevar Bush at MIT and Harvard, the German mathematician Wilhelm Cauer (1900–1945) used the Chebyshev polynomials in a way that unified the field of filter transfer function design. The elliptical filters now known as Cauer filters have equiripple performance in both the passband and the stopband(s). Cauer continued to make contributions to LC filter synthesis until his mysterious disappearance and presumed death in Berlin on the last day of the Second World War.
Sidney Darlington (1906–1997) developed a complete design theory for LC filters while working at the Bell Telephone Laboratories in the 1940s. Ironically, in later years he became better known for his invention of a particular transistor circuit, the Darlington pair.
17.10.2 Transconductors
Figure 17.35(a) shows the circuit symbol for a transconductor, and Fig. 17.35(b) shows its equivalent circuit. Here we are assuming the transconductor to be ideal, with infinite input and output impedances. Actual transconductors will obviously deviate from this ideal model. We shall investigate the effects of nonidealities in some of the end-of-chapter problems. Otherwise, we shall assume that for the purpose of this introductory study, the transconductors are ideal.
The transconductor of Fig. 17.35(a) has a positive output; that is, the output current Io = Gm Vi flows out of the output terminal. Transconductors with a negative output are, of course, also possible and one is shown in Fig. 17.35(c), with its ideal model in Fig. 17.35(d).
The transconductors of Fig. 17.35(a) and (c) are both of the single-ended type. As mentioned in Chapter 9, differential amplification is preferred over the single-ended variety for a number of reasons, including lower susceptibility to noise and interference. This preference for fully differential operation extends to other signal-processing functions including filtering where it can be shown that distortion, an important issue in filter design, is reduced in fully differential configurations. As a result, at the present time, most IC analog filters utilize fully differential circuits. For this purpose, we show in Fig. 17.35(e) a differential-input–differential-output transconductor.
+ Io = GmVi V Gm+
17.10 Transconductance-C Filters 1349 Io
GmVi
Io
i–
Rin =
Vi
Rout =
(a)
(b)
+ Io=GmVi GV Gm– Vi mi
Vi–
(c)
Io
(d)
Io I I I 22o
–+
Vi/2 + + +Vi
Gm– 2 Q1 Q2 2
–Vi
–Vi/2 – Io Io = GmVi
(e)
I
Figure17.35 (a)Apositivetransconductor;(b)equivalentcircuitofthetransconductorin(a);(c)anegative transconductor and its equivalent circuit (d); (e) a fully differential transconductor; (f) a simple circuit implementation of the fully differential transconductor.
We have already encountered circuits for implementing transconductors. As an example of a simple implementation, we show the circuit in Fig. 17.35(f), which is simply a differential amplifier loaded with two current sources. The linearity of this circuit is of course limited by the iD−vGS characteristic of the MOSFET, necessitating the use of small input signals. Many elaborate transconductor circuits have been proposed and utilized in the design of Gm –C filters (see Chan Carusone, Johns, and Martin, 2012).
17.10.3 Basic Building Blocks
In this section we present the basic building blocks of Gm –C filters. Figure 17.36(a) shows how a negative transconductor can be used to realize a resistance. An integrator is obtained by feeding the output current of a transconductor, Gm Vi , to a grounded capacitor, as shown in
(f)
1350 Chapter 17
Filters and Tuned Amplifiers
I GmVi GV i+mi
+ Gm+ 0Gm– Vi–
Vi – GmVi CVo –
R Vi = Vi = 1
GmVi Vo Gm
in Ii (a)
+
GmVi
Gm
Vo= sC (b)
V = sC i
Gm1Vi
Gm2Vo
Vo
Gm2 –
Vo
Gm1 –
Vi – XC – +
+
(c)
Gm2Vo
Gm1Vi
++ +++
Vi Gm1–CVoGm2– –––
–
+
Vo –
+
Vo –
Gm1Vi
2C Gm1Vi
Gm2Vo (d)
Gm2Vo
+++++ Vi Gm1– Vo Gm2–
– –– Gm1Vi
2C
Gm2Vo (e)
Figure 17.36 Realization of (a) a resistance using a negative transconductor; (b) an ideal noninverting integrator; (c) a first-order low-pass filter (a damped integrator); and (d) a fully differential first-order low-pass filter. (e) Alternative realization of the fully differential first-order low-pass filter.
Fig. 17.36(b). The transfer function obtained is
Vo = Gm Vi sC
(17.90)
17.10 Transconductance-C Filters 1351
which is ideal because we have assumed the transconductor to be ideal (see Problem 17.86). To obtain a damped integrator, or a first-order low-pass filter, we connect a resistance of the type in Fig. 17.36(a) in parallel with the capacitor C in the integrator of Fig. 17.36(b). The resulting circuit is shown in Fig. 17.36(c). The transfer function can be obtained by writing a
node equation at X. The result is
Vo =− Gm1 (17.91) Vi sC + Gm2
Thus, the pole frequency is (Gm2/C) and the dc gain is (−Gm1/Gm2).
The circuit in Figure 17.36(c) can be easily converted to the fully differential form shown in
Fig. 17.36(d). An alternative implementation of the fully differential first-order low-pass filter is shown in Fig. 17.36(e). Note that the latter circuit requires four times the capacitance value of the circuit in Fig. 17.36(d). Nevertheless, the circuit of Fig. 17.36(e) has some advantages (see Chan Carusone et al., 2012).
17.10.4 Second-Order Gm–C Filter
To obtain a second-order Gm–C filter, we use the two-integrator-loop topology of Fig. 17.25(a). Absorbing the (1/Q) branch within the first integrator, and lumping the second integrator together with the inverter into a single noninverting integrator block, we obtain the block diagram in Fig. 17.37(a). This block diagram can be easily implemented by Gm –C circuits, resulting in the circuit of Fig. 17.37(b). Note that
1. The inverting integrator is realized by the inverting transconductor Gm1, capacitor C1, and the resistance implemented by transconductor Gm3.
2. The noninverting integrator is realized by the noninverting transconductor Gm2 and capacitor C2.
3. The input summer is implemented by transconductor Gm4, which feeds an output current Gm4Vi to the integrator capacitor C1, and transconductor Gm1, which feeds an output current Gm1V2 to C1.
To derive the transfer functions (V1 /Vi ) and (V2 /Vi ) we first note that V2 related by
V2 = Gm2 V1 sC2
and V1 are (17.92)
Next, we write a node equation at X and use the relationship above to eliminate V2. After some simple algebraic manipulations we obtain
V1 =− s(Gm4/C1)
Vi s2+sGm3 +Gm1Gm2
C1 C1C2
Now, using Eq. (17.92) to replace V1 in Eq. (17.93) results in
V2 =− Gm2Gm4/C1C2
Vi s2+sGm3 +Gm1Gm2
(17.93)
(17.94)
C1 C1C2
1352 Chapter 17
Filters and Tuned Amplifiers
Thus, the circuit in Fig. 17.37(b) is capable of realizing simultaneously a bandpass function (V1/Vi) and a low-pass function (V2/Vi). For both
1
Vi K
V2
ω0 =
Gm1Gm2 C1 C2
(17.95)
– ω0
s+ω0 Q
+ ω0 s
V1 (a)
+
Gm1V2
X
+
Gm2V1
Gm2 +
C1V1 C2V2
+
Gm1 – ––
+G
m3 –
Gm4 –
Gm3V1
Vi
–
Gm4Vi
–
Gm3V1
(b)
++ ++
Gm1 C1V1Gm2V2
– – – – C2 –
+++
G+ Gm3 Vim4– – ––
(c)
Figure 17.37 (a) Block diagram of the two-integrator-loop biquad. This is a somewhat modified version of Fig. 17.25. (b) Gm –C implementation of the block diagram in (a). (c) Fully differential Gm –C implementation of the block diagram in (a). In all parts, V1/Vi is a bandpass function and V2/Vi is a low-pass function.
and
and for the low-pass function,
Gm1Gm2 Gm3
17.10
Transconductance-C Filters 1353
Q =
C1 C2
(17.96)
(17.97)
(17.98)
For the bandpass function,
Center-frequency gain = − Gm4
DC gain = − Gm4 Gm1
Gm3
There are a variety of possible designs. The most common is to make the time constants of the integrators equal [which is the case in the block diagram of Fig. 17.37(a)]. Doing this and selecting Gm1 = Gm2 = Gm and C1 = C2 = C results in the following design equation
Gm =ω0 C
Gm3 = Gm Q
For the BP: Gm4 = Gm |Gain| Q
For the LP: Gm4 = Gm |Gain|
(17.99)
(17.100)
(17.101) (17.102)
Example 17.4
Design the Gm –C circuit of Fig. 17.37(b) to realize a bandpass filter with a center frequency of 10 MHz, a 3-dB bandwidth of 1 MHz, and a center-frequency gain of 10. Use equal capacitors of 5 pF.
Solution
Using the equal-integrator-time-constants design, Eq. (17.99) yields
Gm =ω0C=2π×10×106 ×5×10−12 =0.314mA/V
Thus,
To obtain Gm3 , we first note that Q = f0 /BW = 10/1 = 10, and then use Eq. (17.100) to obtain
or
Finally, Gm4 can be found by using Eq. (17.101) as
Gm1 = Gm2 = 0.314 mA/V
Gm3 = Gm = 0.314 = 0.0314 mA/V
Q 10
Gm3 = 31.4 μA/V
Gm4 = Gm ×10=0.314mA/V 10
1354 Chapter 17
Filters and Tuned Amplifiers
We note that the feedforward approach utilized in Section 17.7.3 to realize different transmission zeros (as required for high-pass, notch, and all-pass functions) can be adapted to the Gm –C circuit in Fig. 17.37(b). Some of these possibilities are explored in the end-of-chapter problems. Finally, the circuit in Fig. 17.37(b) can be easily converted to the fully differential form shown in Fig. 17.37(c).
EXERCISE
D17.31 Design the circuit of Fig. 17.37(b) to realize a maximally flat low-pass filter with f3dB = 20 MHz and a dc gain of unity. Design for equal integrator time constants, and use equal capacitors of 2 pF each.
Ans. Gm1 = Gm2 = Gm4 = 0.251 mA/V; Gm3 = 0.355 mA/V
This concludes our study of Gm–C filters. The interested reader can find considerably more material on this subject in Schaumann et al. (2010).
17.11 Switched-Capacitor Filters
In this section we study another approach to the design of analog filters for IC implementation. Switched-capacitor filters, which require only small capacitors, analog switches, and op amps that need to drive only small capacitive loads, are ideally suited for implementation in CMOS. Currently, the switched-capacitor approach is the preferred method for the design of integrated-circuit audio filters.
17.11.1 The Basic Principle
The switched-capacitor filter technique is based on the realization that a capacitor switched between two circuit nodes at a sufficiently high rate is equivalent to a resistor connecting these two nodes. To be specific, consider the active-RC integrator of Fig. 17.38(a). This is the familiar Miller integrator, which we used in the two-integrator-loop biquad in Section 17.7. In Fig. 17.38(b) we have replaced the input resistor R1 by a grounded capacitor C1 together with two MOS transistors acting as switches. In some circuits, more elaborate switch configurations are used, but such details are beyond our present need.
The two MOS switches in Fig. 17.38(b) are driven by a nonoverlapping two-phase clock. Figure 17.38(c) shows the clock waveforms. We shall assume in this introductory exposition that the clock frequency fc(fc = 1/Tc) is much higher than the frequency of the input signal vi. Thus the variations in the input signal are negligibly small during clock phase φ1, when C1 is connected across the input signal source vi. It follows that during φ1, capacitor C1 charges up to the voltage vi,
qC1 =C1vi
17.11 Switched-Capacitor Filters 1355
(a) (b)
(c)
(d)
Figure 17.38 Basic principle of the switched-capacitor filter technique. (a) Active-RC integrator. (b) Switched-capacitor integrator. (c) Two-phase clock (nonoverlapping). (d) During φ1, C1 charges up to the current value of vi and then, during φ2, discharges into C2.
Then, during clock phase φ2, capacitor C1 is connected to the virtual-ground input of the op amp, as indicated in Fig. 17.38(d). Capacitor C1 is thus forced to discharge, and its previous charge qC1 is transferred to C2, in the direction indicated in Fig. 17.38(d).
From the description above we see that during each clock period Tc an amount of charge qC1 = C1vi is extracted from the input source and supplied to the integrator capacitor C2. Thus the average current flowing between the input node (IN) and the virtual-ground node (VG) is
iav = C1vi Tc
If Tc is sufficiently short, one can think of this process as almost continuous and thus can define an equivalent resistance Req that is in effect present between nodes IN and VG:
Thus,
Req ≡vi/iav Req =Tc/C1
(17.103)
(17.104)
Thus the time constant that determines the frequency response of the filter is established by theclockperiodTc andthecapacitorratioC2/C1.Boththeseparameterscanbewellcontrolled
Using Req we obtain an equivalent time constant for the integrator: Time constant = C R = T C2
2eq cC1
1356 Chapter 17
Filters and Tuned Amplifiers
in an IC process. Specifically, note the dependence on capacitor ratios rather than on absolute values of capacitors. The accuracy of capacitor ratios in MOS technology can be controlled to within 0.1%.
Another point worth observing is that with a reasonable clocking frequency (such as 100 kHz) and not-too-large capacitor ratios (say, 10), one can obtain reasonably large time constants (such as 10−4 s) suitable for audio applications. Since capacitors typically occupy relatively large areas on the IC chip, one attempts to minimize their values. In this context, it is important to note that the ratio accuracies quoted earlier are obtainable with the smaller capacitor value as low as 0.1 pF.
17.11.2 Practical Circuits
The switched-capacitor (SC) circuit in Fig. 17.38(b) realizes an inverting integrator [note the direction of charge flow through C2 in Fig. 17.38(d)]. As we saw in Section 17.7, a two-integrator-loop active filter is composed of one inverting and one noninverting integrator.11 To realize a switched-capacitor biquad filter, we therefore need a pair of complementary switched-capacitor integrators. Figure 17.39(a) shows a noninverting, or positive, integrator circuit. The reader is urged to follow the operation of this circuit during the two clock phases and thus show that it operates in much the same way as the basic circuit of Fig. 17.38(b), except for a sign reversal.
In addition to realizing a noninverting integrator function, the circuit in Fig. 17.39(a) is insensitive to stray capacitances; however, we shall not explore this point any further. The interested reader is referred to Schaumann, Ghausi, and Laker (1990). By reversal of the clock phases on two of the switches, the circuit in Fig. 17.39(b) is obtained. This circuit realizes the inverting integrator function, like the circuit of Fig. 17.38(b), but is insensitive to stray capacitances [which the original circuit of Fig. 17.38(b) is not]. The complementary integrators of Fig. 17.39 have become the standard building blocks in the design of switched-capacitor filters.
Let us now consider the realization of a complete biquad circuit. Figure 17.40(a) shows the active-RC, two-integrator-loop circuit studied earlier. By considering the cascade of integrator 2 and the inverter as a positive integrator, and then simply replacing each resistor by its switched-capacitor equivalent, we obtain the circuit in Fig. 17.40(b). Ignore the damping around the first integrator (i.e., the switched capacitor C5) for the time being and note that the feedback loop indeed consists of one inverting and one noninverting integrator. Then note the phasing of the switched capacitor used for damping. Reversing the phases here would convert the feedback to positive and move the poles to the right half of the s plane. On the other hand, the phasing of the feed-in switched capacitor (C6) is not that important; a reversal of phases would result only in an inversion in the sign of the function realized.
Having identified the correspondences between the active-RC biquad and the switched- capacitor biquad, we can now derive design equations. Analysis of the circuit in Fig. 17.40(a) yields
ω0 = √ 1 (17.105) C1C2R3R4
Replacing R3 and R4 with their switched-capacitor equivalent values, that is, R3 =Tc/C3 and R4 =Tc/C4
11 In the two-integrator loop of Fig. 17.25(b), the noninverting integrator is realized by the cascade of a Miller integrator and an inverting amplifier.
17.11 Switched-Capacitor Filters 1357
(a)
(b)
Figure 17.39 A pair of complementary stray-insensitive, switched-capacitor integrators. (a) Noninverting switched-capacitor integrator. (b) Inverting switched-capacitor integrator.
gives ω0 of the switched-capacitor biquad as
Tc C2 = Tc C1 C3 C4
If, further, we select the two integrating capacitors C1 and C2 to be equal, C1 =C2 =C
C3 C4
C2 C1
It is usual to select the time constants of the two integrators to be equal; that is,
ω0 = 1 Tc
(17.106)
(17.107)
(17.108)
(17.109)
(17.110)
then
where from Eq. (17.106)
C3 =C4 =KC
K = ω0Tc
1358 Chapter 17 Filters and Tuned Amplifiers
Figure 17.40 (a) A two-integrator-loop, active-RC biquad and (b) its switched-capacitor counterpart.
(b)
For the case of equal time constants, the Q factor of the circuit in Fig. 17.40(a) is given by R5 /R4 . Thus the Q factor of the corresponding switched-capacitor circuit in Fig. 17.40(b) is given by
17.12 Tuned Amplifiers 1359
Thus C5 should be selected from
Q=Tc/C5 =C4 Tc /C4 C5
C = C4 = KC = ω T C 5QQ0cQ
(17.111)
(17.112)
(17.113)
Finally, the center-frequency gain of the bandpass function is given by Center-frequency gain = C6 = Q C6
C5 ω0TcC
EXERCISE
D17.32 Use C1 = C2 = 20 pF and design the circuit in Fig. 17.40(b) to realize a bandpass function with f0 = 10 kHz, Q = 20, and unity center-frequency gain. Use a clock frequency fc = 200 kHz. Find the values of C3, C4, C5, and C6.
Ans. 6.283 pF; 6.283 pF; 0.314 pF; 0.314 pF
17.11.3 Final Remarks
We have attempted to provide only an introduction to switched-capacitor filters. We have made many simplifying assumptions, the most important being the switched-capacitor–resistor equivalence (Eq. 17.103). This equivalence is correct only at fc = ∞ and is approximately correct for fc ≫ f . Switched-capacitor filters are, in fact, discrete-time circuits whose analysis and design can be carried out exactly using z-transform techniques. The interested reader is referred to the bibliography in Appendix I.
The switched-capacitor circuits presented above are of the single-ended variety. In most applications, fully differential versions of these circuits are employed.
17.12 Tuned Amplifiers
We conclude this chapter with the study of a special kind of frequency-selective network, the LC-tuned amplifier. Figure 17.41 shows the general shape of the frequency response of a tuned amplifier. The techniques discussed apply to amplifiers with center frequencies in the range of a few hundred kilohertz to a few hundred megahertz. Tuned amplifiers find application in the radio-frequency (RF) and intermediate-frequency (IF) sections of communications receivers and in a variety of other systems. It should be noted that the tuned-amplifier response of Fig. 17.41 is similar to that of the bandpass filter discussed in earlier sections.
1360 Chapter 17
Filters and Tuned Amplifiers
Figure 17.41 Frequency response of a tuned amplifier.
As indicated in Fig. 17.41, the response is characterized by the center frequency ω0 , the 3-dB bandwidth B, and the skirt selectivity, which is usually measured as the ratio of the 30-dB bandwidth to the 3-dB bandwidth. In many applications, the 3-dB bandwidth is less than 1% of ω0. This narrow-band property makes possible certain approximations that can simplify the design process.
The tuned amplifiers discussed in this section can be implemented in discrete-circuit form using transistors together with passive inductors and capacitors. Increasingly, however, they are implemented in IC form, where the inductors are specially fabricated by depositing thin metal films in a spiral shape. These IC inductors, however, are very small and hence are useful only in very-high-frequency applications. Also they usually have considerable losses or, equivalently, low Q factors. Various circuit techniques have been proposed to raise the realized Q factors. These usually involve an amplifier circuit that generates a negative resistance, which is connected to the inductor in a way that cancels part of its resistance and thus enhance its Q factor. The resulting tuned amplifiers are therefore referred to as active-LC filters (see Schaumann et al., 2010).
This section considers tuned amplifiers that are small-signal voltage amplifiers in which the transistors operate in the “class A” mode; that is, the transistors conduct at all times. Tuned power amplifiers such as those based on class C operation of the transistor, are not studied in this book. (For a discussion on the classification of amplifiers, refer to Section 12.1.)
17.12.1 The Basic Principle
The basic principle underlying the design of tuned amplifiers is the use of a parallel LCR circuit as the load, or at the input, of a BJT or an FET amplifier. This is illustrated in Fig. 17.42 with a MOSFET amplifier having a tuned-circuit load. For simplicity, the bias details are not included. Since this circuit uses a single tuned circuit, it is known as a single-tuned amplifier. The amplifier equivalent circuit is shown in Fig. 17.42(b). Here R denotes the parallel equivalent of RL and the output resistance ro of the FET, and C is the parallel equivalent ofCL andtheFEToutputcapacitance(usuallysmall).Fromtheequivalentcircuitwecanwrite
Vo=−gmVi = −gmVi
YL sC+1/R+1/sL
(b)
Thus the voltage gain can be expressed as
Vo =−gm s
Vi C s2 +s(1/CR)+1/LC
17.12 Tuned Amplifiers 1361
Figure 17.42 The basic prin- ciple of tuned amplifiers is illustrated using a MOSFET with a tuned-circuit load. Bias details are not shown.
(17.114) which is a second-order bandpass function. Thus the tuned amplifier has a center frequency of
a 3-dB bandwidth of
a Q factor of
and a center-frequency gain of
√ ω0=1/ LC
B= 1 CR
Q ≡ ω0/B = ω0CR
Vo(jω0) =−gmR Vi(jω0)
(17.115)
(17.116)
(17.117)
(17.118)
Note that the expression for the center-frequency gain could have been written by inspection; at resonance, the reactances of L and C cancel out and the impedance of the parallel LCR circuit reduces to R.
1362 Chapter 17 Filters and Tuned Amplifiers
Example 17.5
It is required to design a tuned amplifier of the type shown in Fig. 17.42, having f0 = 1 MHz, 3-dB bandwidth = 10 kHz, and center-frequency gain = –10 V/V. The FET available has at the bias point gm = 5 mA/V and ro = 10 k. The output capacitance is negligibly small. Determine the values of RL , CL , and L.
Solution
Center-frequency gain = –10 = –5R. Thus R = 2 k. Since R = RL ∥ro, then RL = 2.5 k. B=2π×104= 1
Thus
CR
= 7958 pF
= 3.18 μH
Since ω0 = 2π × 106 = 1/√LC, we obtain
L = 1
17.12.2 Inductor Losses
C = 1
2π ×104 ×2×103
4π2 ×1012 ×7958×10−12
The power loss in the inductor is usually represented by a series resistance rs as shown in Fig. 17.43(a). However, rather than specifying the value of rs , the usual practice is to specify the inductor Q factor at the frequency of interest,
Q0 ≡ ω0L (17.119) rs
Typically, Q0 is in the range of 50 to 200.
The analysis of a tuned amplifier is greatly simplified by representing the inductor loss
by a parallel resistance Rp , as shown in Fig. 17.43(b). The relationship between Rp and Q0 can be found by writing, for the admittance of the circuit in Fig. 17.43(a),
For Q0 ≫ 1,
Y(jω0)= 1
rs +jω0L
1 1 1 1+j(1/Q0) = jω0L 1 − j(1/Q0) = jω0L 1 + 1/Q02
11
Y(jω0)≃ jω L 1+jQ (17.120)
00
L
rs
L Rp
Equating this to the admittance of the circuit in Fig. 17.43(b) gives
Q0 = Rp (17.121)
Figure 17.43 Inductor equivalent circuits.
17.12 Tuned Amplifiers 1363
or, equivalently,
ω0L
Rp =ω0LQ0 (17.122)
Finally, it should be noted that the coil Q factor poses an upper limit on the value of Q achieved by the tuned circuit.
EXERCISE
17.33 If the inductor in Example 17.5 has Q0 = 150, find Rp and then find the value to which RL should be changed to keep the overall Q, and hence the bandwidth, unchanged.
Ans. 3 k; 15 k
17.12.3 Use of Transformers
In many cases it is found that the required value of inductance is not practical, in the sense that coils with the required inductance might not be available with the required high values of Q0 . A simple solution is to use a transformer to effect an impedance change. Alternatively, a tapped coil, known as an autotransformer, can be used, as shown in Fig. 17.44. Provided the two parts of the inductor are tightly coupled, which can be achieved by winding on a ferrite core, the transformation relationships shown hold. The result is that the tuned circuit seen between terminals 1 and 1′ is equivalent to that in Fig. 17.42(b). For example, if a turns ratio n = 3 is used in the amplifier of Example 17.5, then a coil with inductance L′ = 9 × 3.18 = 28.6 μH and a capacitance C′ = 7958/9 = 884 pF will be required. Both these values are more practical than the original ones.
In applications that involve coupling the output of a tuned amplifier to the input of another amplifier, the tapped coil can be used to raise the effective input resistance of the latter amplifier stage. In this way, one can avoid reduction of the overall Q. This point is illustrated in Fig. 17.45 and in the following exercises.
1364 Chapter 17
Filters and Tuned Amplifiers
Figure 17.44 A tapped induc-
tor is used as an impedance trans-
former to allow using a higher
′
inductance, L , and a ′
Ic
smaller
capacitance, C .
L I C1n
(a)
(b)
1
Rin Cin
R1
R1
C1
L n2Rin
I
Cin n2
Figure 17.45 (a) The output of a tuned amplifier is coupled to the input of another amplifier via a tapped coil. (b) An equivalent circuit. Note that the use of a tapped coil increases the effective input impedance of the second amplifier stage.
EXERCISES
D17.34 ConsiderthecircuitinFig.17.45(a),firstwithouttappingthecoil.LetL=5μHandassumethat R1 is fixed at 1 k. We wish to design a tuned amplifier with f0 = 455 kHz and a 3-dB bandwidth of 10 kHz [this is the intermediate frequency (IF) amplifier of an AM radio]. If the BJT has Rin = 1 k and Cin = 200 pF, find the actual bandwidth obtained and the required value of C1 . Ans. 13 kHz; 24.27 nF
D17.35 Since the bandwidth realized in Exercise 17.34 is greater than desired, find an alternative design utilizing a tapped coil as in Fig. 17.45(a). Find the value of n that allows the specifications to be just met. Also find the new required value of C1 and the current gain Ic/I at resonance. Assume that at the bias point the BJT has gm = 40 mA/V.
Ans. 1.36; 24.36 nF; 19.1 A/A
17.12.4 Amplifiers with Multiple Tuned Circuits
The selectivity achieved with the single tuned circuit of Fig. 17.42 is not sufficient in many applications—for instance, in the IF amplifier of a radio or a TV receiver. Greater selectivity is obtained by using additional tuned stages. Figure 17.46 shows a BJT with tuned circuits at both the input and the output.12 In this circuit the bias details are shown, from which we note that biasing is quite similar to the classical arrangement employed in low-frequency, discrete-circuit design. However, to avoid the loading effect of the bias resistors RB1 and RB2 on the input tuned circuit, a radio-frequency choke (RFC) is inserted in series with each resistor. Such chokes have low resistance but high impedances at the frequencies of interest. The use of RFCs in biasing tuned RF amplifiers is common practice.
The analysis and design of the double-tuned amplifier of Fig. 17.46 is complicated by the Miller effect13 due to capacitance Cμ. Since the load is not simply resistive, as was the case in the amplifiers studied in Section 10.3.3, the Miller impedance at the input will be complex. This reflected impedance will cause detuning of the input circuit as well as “skewing” of the response of the input circuit. Needless to say, the coupling introduced by Cμ makes tuning (or aligning) the amplifier quite difficult. Worse still, the capacitor Cμ can cause oscillations to occur (see Gray and Searle, 1969, and Problem 17.101).
Methods exist for neutralizing the effect of Cμ, using additional circuits arranged to feed back a current equal and opposite to that through Cμ. An alternative, and preferred, approach is to use circuit configurations that do not suffer from the Miller effect. These are discussed later. Before leaving this section, however, we wish to point out that circuits of the type shown in Fig. 17.46 are usually designed utilizing the y-parameter model of the BJT (see
Figure 17.46 A BJT amplifier with tuned circuits at the input and the output.
12Note that because the input circuit is a parallel resonant circuit, an input current source (rather than voltage source) signal is utilized.
13Here we use “Miller effect” to refer to the effect of the feedback capacitance Cμ in reflecting back an input impedance that is a function of the amplifier load impedance.
17.12 Tuned Amplifiers 1365
1366 Chapter 17
Filters and Tuned Amplifiers
Appendix C). This is done because here, in view of the fact that Cμ plays a significant role, the y-parameter model makes the analysis simpler (in comparison to that using the hybrid-π model). Also, the y parameters can easily be measured at the particular frequency of interest, ω0. For narrow-band amplifiers, the assumption is usually made that the y parameters remain approximately constant over the passband.
17.12.5 The Cascode and the CC–CB Cascade
From our study of amplifier frequency response in Chapter 10, we know that two amplifier configurations do not suffer from the Miller effect. These are the cascode configuration and the common-collector, common-base cascade. Figure 17.47 shows tuned amplifiers based on these two configurations. The CC–CB cascade is usually preferred in IC implementations because its differential structure makes it suitable for IC biasing techniques. (Note that the biasing details of the cascode circuit are not shown in Fig. 17.47(a). Biasing can be done using arrangements similar to those discussed in earlier chapters.)
(a)
(b)
Figure 17.47 Two tuned-amplifier configurations that do not suffer from the Miller effect: (a) cascode and (b) common-collector, common-base cascade. (Note that bias details of the cascode circuit are not shown.)
17.12.6 Synchronous Tuning and Stagger Tuning
In the design of a tuned amplifier with multiple tuned circuits, the question of the frequency to which each circuit should be tuned arises. The objective, of course, is for the overall response to exhibit high passband flatness and skirt selectivity. To investigate this question, we shall assume that the overall response is the product of the individual responses: in other words, that the stages do not interact. This can easily be achieved using circuits such as those in Fig. 17.47.
Consider first the case of N identical resonant circuits, known as the synchronously tuned case. Figure 17.48 shows the response of an individual stage and that of the cascade. Observe the bandwidth “shrinkage” of the overall response. The 3-dB bandwidth B of the overall amplifier is related to that of the individual tuned circuits, ω0 /Q, by (see Problem 17.102)
B = ω0 √21/N − 1 (17.123) Q
√
The factor 21/N − 1 is known as the bandwidth-shrinkage factor. Given B and N, we can
use Eq. (17.123) to determine the bandwidth required of the individual stages, ω0 /Q. EXERCISE
D17.36 Consider the design of an IF amplifier for an FM radio receiver. Using two synchronously tuned stages with f0 = 10.7 MHz, find the 3-dB bandwidth of each stage so that the overall bandwidth is 200 kHz. Using 3-μH inductors find C and R for each stage.
Ans. 310.8 kHz; 73.7 pF; 6.95 k
17.12 Tuned Amplifiers 1367
T (dB)
3 dB
Response of individual stages
Overall response
B
0 Q
0 0 Figure 17.48 Frequency response of a synchronously tuned amplifier.
1368 Chapter 17
Filters and Tuned Amplifiers
Figure17.49 Stagger-tuningtheindividualresonantcircuitscanresultinanoverallresponsewithapassband flatter than that obtained with synchronous tuning (Fig. 17.48).
A much better overall response is obtained by stagger-tuning the individual stages, as illustrated in Fig. 17.49. Stagger-tuned amplifiers are usually designed so that the overall response exhibits maximal flatness around the center frequency f0. Such a response can be obtained by transforming the response of a maximally flat (Butterworth) low-pass filter up the frequency axis to ω0. Appendix H shows how this can be done.
Summary
A filter is a linear two-port network with a transfer function T (s) = Vo (s)/Vi (s). For physical frequencies, the filter transmission is expressed as T(jω) = |T(jω)|ejφ(ω). The magnitude of transmission can be expressed in decibels using either the gain function G(ω) ≡ 20 log|T | or the attenuation function A(ω) ≡ − 20 log|T |.
The transmission characteristics of a filter are specified in terms of the edges of the passband(s) and the stopband(s); the maximum allowed variation in passband transmission, Amax (dB); and the minimum attenuation required in the stopband, Amin (dB). In some applications, the phase characteristics are also specified.
The filter transfer function can be expressed as the ratio of two polynomials in s; the degree of the denominator polynomial, N, is the filter order. The N roots of the denominator polynomial are the poles (natural modes).
To obtain a highly selective response, the poles are complex and occur in conjugate pairs (except for one real pole when N is odd). The zeros are placed on the jω axis in the stopband(s) including ω = 0 and ω = ∞.
The Butterworth filter approximation provides a low-pass response that is maximally flat at ω = 0. The transmission
decreases monotonically as ω increases, reaching 0 (infi- nite attenuation) at ω = ∞, where all N transmission zeros lie. Eq. (17.11) gives |T |, where ε is given by Eq. (17.14) and the order N is determined using Eq. (17.15). The poles are found using the graphical construction of Fig. 17.10, and the transfer function is given by Eq. (17.16).
The Chebyshev filter approximation provides a low-pass response that is equiripple in the passband with the transmission decreasing monotonically in the stopband. All the transmission zeros are at s = ∞. Eq. (17.18) gives |T | in the passband and Eq. (17.19) gives |T | in the stopband, where ε is given by Eq. (17.21). The order N can be determined using Eq. (17.22). The poles are given by Eq. (17.23) and the transfer function by Eq. (17.24).
Figures 17.13 and 17.14 provide a summary of first-order filter functions and their realizations.
Figure 17.16 provides the characteristics of seven special second-order filtering functions.
The second-order LCR resonator of Fig. 17.17(a) realizes √
a pair of complex-conjugate poles with ω0 = 1/ LC and Q = ω0CR. This resonator can be used to realize the
various special second-order filtering functions, as shown in Fig. 17.18.
By replacing the inductor of an LCR resonator with a simulated inductance obtained using the Antoniou circuit of Fig. 17.20(a), the op amp–RC resonator of Fig. 17.21(b) is obtained. This resonator can be used to realize the various second-order filter functions as shown in Fig. 17.22. The design equations for these circuits are given in Table 17.1.
Biquads based on the two-integrator-loop topology are the most versatile and popular second-order filter realizations. There are two varieties: the KHN circuit of Fig. 17.24(a), which realizes the LP, BP, and HP functions simulta- neously and can be combined with the output summing amplifier of Fig. 17.24(b) to realize the notch and all-pass functions; and the Tow–Thomas circuit of Fig. 17.25(b), which realizes the BP and LP functions simultaneously. Feedforward can be applied to the Tow–Thomas cir- cuit to obtain the circuit of Fig. 17.26, which can be designed to realize any of the second-order functions (see Table 17.2).
Single-amplifier biquads (SABs) are obtained by placing a bridged-T network in the negative-feedback path of an op amp. If the op amp is ideal, the poles realized are at the same locations as the zeros of the RC network. The complementary transformation can be applied to the feedback loop to obtain another feedback loop having identical poles. Different transmission zeros are realized by feeding the input signal to circuit nodes that are connected to ground. SABs are economic in their use of
Section 17.1: Filter Transmission, Types, and Specification
17.1 The transfer function of a first-order low-pass fil- ter (such as that realized by an RC circuit) can be
Problems 1369 op amps but are sensitive to the op-amp nonidealities and
are thus limited to low-Q applications (Q ≤ 10). The classical sensitivity function
∂y/y S xy = ∂ x / x
is a very useful tool in investigating how tolerant a filter circuit is to the unavoidable inaccuracies in component values and to the nonidealities of the op amps.
Transconductance-C circuits utilize transconductors and capacitors to realize medium- and high-frequency fil- ters (as high as hundreds of megahertz) that can be implemented in CMOS. The basic building block is the integrator, and the basic filter building block is based on the two-integrator-loop topology.
Switched-capacitor (SC) filters are based on the principle that a capacitor C, periodically switched between two circuit nodes at a high rate, fc , is equivalent to a resistance R = 1/Cfc connecting the two circuit nodes. SC filters can be fabricated in monolithic form using CMOS IC technology.
Tuned amplifiers utilize LC-tuned circuits as loads, or at the input, of transistor amplifiers. They are used in the design of the RF tuner and the IF amplifier of commu- nication receivers. The cascode and the CC–CB cascade configurations are frequently used in the design of tuned amplifiers. Stagger-tuning the individual tuned circuits results in a flatter passband response (in comparison to that obtained with all the resonant circuits synchronously tuned).
PROBLEMS
17.2 A sinusoid with 1-V peak amplitude is applied at the input of a filter having the transfer function
T(s)= 2π×104 s+2π ×104
Find the peak amplitude and the phase (relative to that of the input sinusoid) of the output sinusoid if the frequency of the input sinusoid is (a) 1 kHz, (b) 10 kHz, (c) 100 kHz, and (d) 1 MHz.
expressed as T (s) = ω0 / s + ω0 , where ω0 is the 3-dB frequency of the filter. Give in table form the values of |T|, φ, G, and A at ω = 0, 0.5ω0,ω0,2ω0,5ω0,10ω0, and 100ω0 .
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
1370 Chapter 17 Filters and Tuned Amplifiers
*17.3 A filter has the transfer function T (s) = 1/[(s + 1)(s2 +
complex-conjugate poles is at 18° angles from the jω axis, and the other pair is at 54° angles. Give the transfer function in each of the following cases.
(a) The transmission zeros are all at s = ∞ and the dc gain is unity.
(b) The transmission zeros are all at s = 0 and the high-frequency gain is unity.
What type of filter results in each case?
17.11 Athird-orderlow-passfilterhastransmissionzerosat ω = 2 rad/s and ω = ∞. Its natural modes are at s = −1 and s = −0.5 ± j0.8. The dc gain is unity. Find T(s).
17.12 A second-order low-pass filter has poles at −0.25 ± j and a transmission zero at ω = 2 rad/s. If the dc gain is unity, give the transfer function T(s). What is the gain at ω approaching infinity?
17.13 Find the order N and the form of T(s) of a bandpass filter having transmission zeros as follows: one at ω = 0, one at ω = 103 rad/s, one at 3×103 rad/s, one at 6×103 rad/s, and one at ω = ∞. If this filter has a monotonically decreasing passband transmission with a peak at the center frequency of 2×103 rad/s,andequirippleresponseinthestopbands,sketch the shape of its |T|.
*17.14 Analyze the RLC network of Fig. P17.14 to deter- mine its transfer function Vo(s)/Vi(s) and hence its poles and zeros. (Hint: Begin the analysis at the output and work your way back to the input.)
1 2 H
Vi(s) 1 F 1 F 1 Vo(s)
Figure P17.14
Section 17.3: Butterworth and Chebyshev Filters
D 17.15 Determine the order N of the Butterworth filter for which Amax = 0.5 dB, Amin ≥ 20 dB, and the selectivity ratio ωs /ωp = 1.7. What is the actual value of minimum stopband attenuation realized? If Amin is to be exactly 20 dB, to what value can Amax be reduced?
√
s+1)]. Show that |T|= 1+ω6 and find an expression for
its phase response φ(ω). Calculate the values of |T| and φ for ω = 0.1, 1, and 10 rad/s and then find the output corresponding to each of the following input signals:
(a) 10 sin 0.1t (volts) (b) 10 sin t (volts) (c) 10 sin 10t (volts)
17.4 Forthefilterwhosemagnituderesponseissketched(as the blue curve) in Fig.17.3, find |T| at ω=0, ω=ωp, and ω=ωs.Amax =0.2dB,andAmin =60dB.
D17.5 Alow-passfilterisrequiredtopassallsignalswithin its passband, extending from 0 to 4 kHz, with a transmission variation of at most 5% (i.e., the ratio of the maximum to minimum transmission in the passband should not exceed 1.05). The transmission in the stopband, which extends from 5 kHz to ∞, should not exceed 0.05% of the maximum passband transmission. What are the values of Amax , Amin , and the selectivity factor for this filter?
17.6 A low-pass filter is specified to have fp = 5 kHz and a selectivity factor of 10. The specifications are just met by a first-order transfer function
2π × 104
T (s) = s + 2π × 104
What must Amax and Amin be?
17.7 A low-pass filter is specified to have Amax = 2 dB and Amin = 12 dB. It is found that these specifications can be just met with a single-time-constant RC circuit having a time constant of 1 s and a dc transmission of unity. What must ωp and ωs of this filter be? What is the selectivity factor?
17.8 Sketchtransmissionspecificationsforahigh-passfilter having a passband defined by f ≥ 3 kHz and a stopband defined byf≤2kHz.Amax =0.4dB,andAmin =60dB.
17.9 Sketch transmission specifications for a bandstop filter that is required to pass signals over the bands 0 ≤ f ≤ 10 kHz and 20 kHz ≤ f ≤ ∞ with Amax of 0.5 dB. The stopband extends from f = 12 kHz to f = 18 kHz, with a minimum required attenuation of 50 dB.
Section 17.2: The Filter Transfer Function
17.10 Consider a fifth-order filter whose poles are all at a radial distance from the origin of 104 rad/s. One pair of
CHAPTER 17 PROBLEMS
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
CHAPTER 17 PROBLEMS
17.16 Show that the order N of a Butterworth filter can be obtained from the approximate expression
N ≥ Amin − 20 log ε 20 log(ωs/ωp)
Hint: Use Eq. (17.15) and neglect the unity term.
17.17 Calculate the value of attenuation obtained at a frequency 1.8 times the 3-dB frequency of a seventh-order Butterworth filter.
17.18 Find the natural modes of a Butterworth filter having a 0.5-dB bandwidth of 103 rad/s and N = 5.
D 17.19 Design a Butterworth filter that meets the following low-passspecifications:fp =10kHz,Amax =3dB,fs =20kHz, and Amin = 20 dB. Find N, the natural modes, and T(s). What is the attenuation provided at 30 kHz?
17.20 Sketch the transfer function magnitude for a low-pass Chebyshev filter of (a) sixth order and (b) seventh order.
17.21 On the same diagram, sketch the magnitude of the transfer function of a Butterworth and a Chebyshev low-pass filter of fifth order and having the same ωp and Amax. At the stopband edge, ωs , which filter gives greater attenuation?
*17.22 Sketch |T| for a seventh-order low-pass Chebyshev filter with ωp = 1 rad/s and Amax = 0.5 dB. Use Eq. (17.18) to determine the values of ω at which |T | = 1 and the values ofωatwhich|T|=1/√1+ε2.Indicatethesevaluesonyour sketch. Use Eq. (17.19) to determine |T | at ω = 2 rad/s, and indicate this point on your sketch. For large values of ω, at what rate (in dB/octave) does the transmission decrease?
17.23 Contrast the attenuation provided by a sixth-order Chebyshev filter at ωs = 2ωp to that provided by a Butterworth filter of equal order. For both, Amax = 1 dB. Sketch |T | for both filters on the same axes.
D *17.24 It is required to design a low-pass filter to meet the following specifications: fp = 3.4 kHz, Amax = 1 dB, fs =4 kHz, Amin =35 dB.
(a) Find the required order of Chebyshev filter. What is the excess (above 35 dB) stopband attenuation obtained?
(b) Find the poles and the transfer function. Section 17.4: First-Order and
Second-Order Filter Functions
D 17.25 Use the information displayed in Fig. 17.13 to design a first-order op amp–RC low-pass filter having a 3-dB
Problems 1371 frequency of 5 kHz, a dc gain magnitude of 10, and an input
resistance of 12 k.
D 17.26 Use the information given in Fig. 17.13 to design a first-order op amp–RC high-pass filter with a 3-dB frequency of 200 Hz, a high-frequency input resistance of 120 k, and a high-frequency gain magnitude of unity.
17.27 Derive an expression for the transfer function of the
op amp–RC circuit that is shown in Fig. 17.13(c). Give
expressions for the frequency of the transmission zero ω , the Z
frequency of the pole ωP , the dc gain, and the high-frequency gain.
D *17.28 Use the information given in Fig. 17.13 to design a first-order op amp–RC spectrum-shaping network with a transmission zero frequency of 100 Hz, a pole frequency of 10 kHz, and a dc gain magnitude of unity. The low-frequency input resistance is to be 10 k. What is the high-frequency gain that results? Sketch the magnitude of the transfer function versus frequency.
D *17.29 By cascading a first-order op amp–RC low-pass circuit with a first-order op amp–RC high-pass circuit, one can design a wideband bandpass filter. Provide such a design for the case in which the midband gain is 12 dB and the 3-dB bandwidth extends from 50 Hz to 50 kHz. Select appropriate component values under the constraints that no resistors higher than 100 k are to be used and that the input resistance is to be as high as possible.
D17.30 DeriveT(s)fortheopamp–RCcircuitinFig.17.14. Find |T (jω)| and φ (ω) We wish to use this circuit as a variable phase shifter by adjusting R. If the input signal frequency is 5×103 rad/s and if C = 10 nF, find the values of R required to obtain phase shifts of –30°, –60°, –90°, –120°, and –150°.
17.31 ShowthatbyinterchangingRandCintheopamp–RC circuit of Fig. 17.14, the resulting phase shift covers the range 0 to 180° (with 0° at high frequencies and 180° at low frequencies).
D *17.32 Use two first-order op amp–RC all-pass circuits in cascade to design a circuit that provides a set of three-phase 60-Hz voltages, each separated by 120° and equal in magnitude, as shown in the phasor diagram of Fig. P17.32. These voltages simulate those used in three-phase power transmission systems. Use 1-μF capacitors.
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
1372 Chapter 17
Filters and Tuned Amplifiers
Figure P17.32
17.33 Use the information in Fig. 17.16(a) to obtain the transfer function of a second-order low-pass filter with ω0 = 104 rad/s, Q = 2, and dc gain = 1. At what frequency does |T | peak? What is the peak transmission?
D *17.34 Use the information in Fig. 17.16(a) to obtain the transfer function of a second-order low-pass filter that just meets the specifications defined in Fig. 17.3 with ωp = 1 rad/s and Amax = 3 dB. Note that there are two possible solutions. For each, find ω0 and Q. Also, if ωs = 2 rad/s, find the value of Amin obtained in each case.
17.35 Findthetransferfunctionofasecond-orderhigh-pass filter with a maximally flat passband response, a 3-dB frequency at ω = 1 rad/s, and a high-frequency gain of unity. Give the location of the poles and zeros.
17.36 Use the information given in Fig. 17.16(b) to find the transfer function of a second-order high-pass filter with
a bothersome interference of 60-Hz frequency. Since the frequency of the interference is not stable, the filter should be designed to provide attenuation ≥20 dB over a 6-Hz band centered around 60 Hz. The dc transmission of the filter is to be unity.
17.40 Consider a second-order all-pass circuit in which errors in the component values result in the frequency of the zeros being slightly lower than that of the poles. Roughly sketch the expected |T |. Repeat for the case of the frequency of the zeros slightly higher than the frequency of the poles.
17.41 Considerasecond-orderall-passfilterinwhicherrors in the component values result in the Q factor of the zeros being greater than the Q factor of the poles. Roughly sketch the expected |T|. Repeat for the case of the Q factor of the zeros lower than the Q factor of the poles.
Section 17.5: The Second-Order LCR Resonator
17.42 Analyze the circuit in Fig. 17.17(c) to determine its transfer function T (s) ≡ Vo (s)/Vi (s), and hence show that its poles are characterized by ω0 and Q of Eqs. (17.34) and (17.35), respectively.
D17.43 DesigntheLCRresonatorofFig.17.17(a)toobtain naturalmodeswithω0 =105 rad/sandQ=5.UseR=10k.
17.44 For the LCR resonator of Fig. 17.17(a), find the change in ω0 that results from
(a) increasing L by 1% (b) increasing C by 1% (c) decreasing R by 1%
17.45 For each of the circuits in Fig. P17.45, find the transmission as ω approaches zero and as ω approaches ∞, and hence find the transmission zeros.
17.46 Derive an expression for Vo(s)/Vi(s) of the high-pass circuit in Fig. 17.18(c).
CHAPTER 17 PROBLEMS
natural modes at −0.5 ± j
of unity. What are ω0 and Q of the poles?
√
3/2 and a high-frequency gain
17.37 Find the transfer function of a second-order bandpass filter for which the center frequency f0 = 10 kHz, the 3-dB bandwidth is 500 Hz, and the center-frequency gain is 10. Also, give the locations of the poles and zeros.
D**17.38 (a) Show that |T| of a second-order bandpass
function is geometrically symmetrical around the center
frequency ω . That is, the members of each pair of frequencies 0
ω1 and ω2 for which T(jω1) = T(jω2) are related by ω 1 ω 2 = ω 20 .
(b) Find the transfer function of the second-order bandpass filter that meets specifications of the form in Fig. 17.4 where ωp1 = 8100 rad/s, ωp2 = 10,000 rad/s, and Amax = 3 dB. If ωs1 = 3000 rad/s find Amin and ωs2 .
D *17.39 Use the result of Exercise 17.15 to find the transfer function of a notch filter that is required to eliminate
D 17.47 Use the circuit of Fig. 17.18(b) to design a low-pass 6√
filter with ω0 = 10 rad/s and Q = 1/ 2. Utilize a 1-nF capacitor.
D 17.48 Modify the bandpass circuit of Fig. 17.18(d) to change its center-frequency gain from 1 to 0.5 without changing ω0 or Q.
17.49 Consider the LCR resonator of Fig. 17.17(a) with node x disconnected from ground and connected to an input signal
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
C1 C1
Vi C2VoVi C2Vo R
–––– (a) (b)
L1 L1R
Vi L2 Vo Vi L2 Vo ––––
Problems 1373
CHAPTER 17 PROBLEMS
Figure P17.45
(c)
(d)
source Vx, node y disconnected from ground and connected to another input signal source Vy, and node z disconnected from ground and connected to a third input signal source Vz . Use superposition to find the voltage that develops across the resonator, Vo, in terms of Vx, Vy, and Vz.
17.50 ConsiderthenotchcircuitshowninFig.17.18(g).For whatratioofC2 toC1 doesthenotchoccurat1.1ω0?Forthis case, what is the magnitude of the transmission at frequencies ≪ ω0 ? At frequencies ≫ ω0 ?
Section 17.6: Second-Order Active Filters Based on Inductor Replacement
D 17.51 Design the circuit of Fig. 17.20 (utilizing suitable component values) to realize an inductance of (a) 15 H, (b) 1.5 H, and (c) 0.15 H.
17.52 Figure P17.52 shows a generalized form of the Antoniou circuit of Fig. 17.20(a). Here, R5 is eliminated and the other four components are replaced by general impedances Z1, Z2, Z3, and Z4.
(a) With an impedance Z5 connected between node 2 and ground, show that the input impedance looking into port 1 (i.e., between node 1 and ground) is
ZZ Z11= 1 3 Z5
A1
Z1 Z2 Z3 Z4 12
A2
(b)
(c)
From the symmetry of the circuit, show that if an impedance Z6 is connected between terminal 1 and ground, the input impedance looking into port 2, which is between terminal 2 and ground, is given by
Z22= Z2Z4 Z6
Z1 Z3
From the expressions above, observe that the two-port
network in Fig. P17.52 acts as an “impedance trans-
former.” Since by the appropriate choice of Z1 , Z2 , Z3 ,
Figure P17.52
Z2Z4
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
and Z , the transformation ratio can be a general function 4
1374 Chapter 17 Filters and Tuned Amplifiers
of the complex frequency variable s, the circuit is known
as a generalized impedance converter, or GIC.
17.53 Consider the Antoniou circuit of Fig. 17.20(a) with R5 eliminated, a capacitor C6 connected between node 1 and ground, and a voltage source V2 connected to node 2. Show that the input impedance seen by V2 is R2/s2C4C6R1R3. How does this impedance behave for physical frequencies (s = jω)? (This impedance is known as a frequency-dependent negative resistance, or FDNR.)
*17.54 Starting from first principles and assuming ideal op amps, derive the transfer function of the circuit in Fig. 17.22(a).
D *17.55 It is required to design a fifth-order Butterworth filter having a 3-dB bandwidth of 105 rad/s and a unity dc gain. Use a cascade of two circuits of the type shown in Fig. 17.22(a) and a first-order op amp–RC circuit of the type shown in Fig. 17.13(a). Select appropriate component values.
D17.56 DesignthecircuitofFig.17.22(e)torealizeanLPN function with f0 =10 kHz, fn =12 kHz, Q=10, and a unity dc gain. Select C4 = 10 nF.
D 17.57 Design the all-pass circuit of Fig. 17.22(g) to provideaphaseshiftof180°atf =2kHzandtohaveQ=2. Use 1-nF capacitors.
D 17.58 Using the transfer function of the LPN filter, given in Table 17.1, derive the design equations also given.
D 17.59 Using the transfer function of the HPN filter, given in Table 17.1, derive the design equations also given.
D**17.60 Itisrequiredtodesignathird-orderlow-passfilter whose |T | is equiripple in both the passband and the stopband (in the manner shown in Fig. 17.3, except that the response shown is for N = 5). The filter passband extends from ω = 0 to ω = 1 rad/s, and the passband transmission varies between 1 and 0.9. The stopband edge is at ω = 1.2 rad/s. The following transfer function was obtained using filter-design tables:
0.4508 s2 +1.6996
T (s) = (s + 0.7294)(s2 + s0.2786 + 1.0504)
The actual filter realized is to have ωp = 105 rad/s.
(a) Obtain the transfer function of the actual filter by replacing s by s/105.
(b) Realize this filter as the cascade connection of a first-order LP op amp–RC circuit of the type shown in Fig. 17.13(a)
and a second-order LPN circuit of the type shown in Fig. 17.22(e). Each section is to have a dc gain of unity. Select appropriate component values. (Note: A filter with an equiripple response in both the passband and the stopband is known as an elliptic filter.)
Section 17.7: Second-Order Active
Filters Based on the Two-Integrator-Loop Topology
D 17.61 Design the KHN circuit of Fig. 17.24(a) to realize a bandpass filter with a center frequency of 2 kHz and a 3-dB bandwidth of 50 Hz. Use 10-nF capacitors. Give the complete circuit and specify all component values. What value of center-frequency gain is obtained?
D17.62 (a)UsingtheKHNbiquadwiththeoutputsumming amplifier of Fig. 17.24(b), show that an all-pass function is realized by selecting RL = RH = RB /Q. Also show that the flat gain obtained is KRF /RH .
(b) Design the all-pass circuit to obtain ω0 = 105 rad/s, Q = 4, and flat gain = 10. Select appropriate component values.
17.63 Consider the case of the KHN circuit used together with the summing amplifier in Fig. 17.24(b) to realize a notch filter with a notch frequency ωn and a high-frequency gain of G. Find expressions for the values required of the resistances associated with the summing amplifier.
D 17.64 Consider a notch filter with ωn = ω0 realized by using the KHN biquad with an output summing amplifier. If the summing resistors used have 1% tolerances, what is the worst-case percentage deviation between ωn and ω0 ?
D17.65 DesignthecircuitofFig.17.26torealizealow-pass notch filter with ω0 = 105 rad/s, Q = 10, dc gain = 1, and ωn =1.3×105 rad/s.UseC=10nFandr=20k.
D 17.66 In the all-pass realization using the circuit of Fig. 17.26, which component(s) does one need to trim to adjust(a)onlyωz and(b)onlyQz?
D **17.67 Repeat Problem 17.60 using the Tow–Thomas biquad of Fig. 17.26 to realize the second-order section in the cascade.
Section 17.8: Single-Amplifier Biquadratic Active Filters
D 17.68 Design the circuit of Fig. 17.29 to realize a pair of poleswithω0 =105 rad/sandQ=1/√2.UseC1 =C2 =1nF.
CHAPTER 17 PROBLEMS
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
CHAPTER 17 PROBLEMS
*17.69 Derive the transfer function t(s) of the bridged-T network in Fig. 17.28(a), and thus verify the expression given in the figure.
17.70 Consider the bridged-T network of Fig. 17.28(a) with R3 =R4 =R and C1 =C2 =C, and denote CR=τ. Find the zeros and poles of the bridged-T network. If the network is placed in the negative-feedback path of an ideal infinite-gain op amp, as in Fig. 17.29, find the poles of the closed-loop amplifier.
17.71 Consider the bridged-T network of Fig. 17.28(b) with R1 =R2 =R, C4 =C, and C3 =C/36. Let the network be placed in the negative-feedback path of an infinite-gain op amp and let C4 be disconnected from ground and connected to the input signal source Vi. Analyze the resulting circuit to determine its transfer function Vo (s)/Vi (s), where Vo (s) is the voltage at the op-amp output. Show that the circuit obtained is a bandpass filter and find its ω0 , Q, and the center-frequency gain.
D17.72 UsethecircuitinFig.17.30(b)withα=1torealize a bandpass filter with a center frequency of 10 kHz and a 3-dB bandwidth of 2 kHz. Give the values of all components and specify the center-frequency gain obtained.
D **17.73 Consider the bandpass circuit shown in Fig.17.30(a). Let C1 = C2 = C, R3 = R, R4 = R/4Q2, CR = 2Q/ω0, and α = 1. Disconnect the positive input terminal of the op amp from ground and apply Vi through a voltage divider R1 , R2 to the positive input terminal as well as through R4 /α as before. Analyze the circuit to find its transfer function Vo/Vi. Find the ratio R2/R1 so that the circuit realizes (a) an all-pass function and (b) a notch function. Assume the op amp to be ideal.
D *17.74 Derive the transfer function of the circuit in Fig. 17.33(b) assuming the op amp to be ideal. Thus show that the circuit realizes a high-pass function. What is the high-frequency gain of the circuit? Design the circuit for a maximally flat response with a 3-dB frequency of 104 rad/s.
D 17.76 The process of obtaining the complement of a transfer function by interchanging input and ground, as illustrated in Fig. 17.31, applies to any general network (not just RC networks as shown). Show that if the network n is a bandpass with a center-frequency gain of unity, then the complement obtained is a notch. Verify this by using the RLC circuits of Fig. 17.18(d) and (e).
Section 17.9: Sensitivity
17.77 Evaluate the sensitivities of ω0 and Q relative to R, L, and C of the low-pass circuit in Fig. 17.18(b).
*17.78 Verify the following sensitivity identities:
(a) Ify=uv,thenSxy =Sxu +Sxv. (b)Ify=u/v,thenSxy=Sxu−Sxv.
(c) If y = ku, where k is a constant, then Sxy = Sxu. (d) If y = un, where n is a constant, then Sxy = nSxu. (e) Ify=f1(u)andu=f2(x),thenSxy =Suy ·Sxu.
*17.79 For the high-pass filter of Fig. 17.33(b), what are the sensitivities of ω0 and Q to amplifier gain A?
*17.80 For the feedback loop of Fig. 17.34(a), use the expressions in Eqs. (17.77) and (17.78) to determine the sensitivities of ω0 and Q relative to all passive components for the design in which R1 = R2 .
17.81 For the op amp–RC resonator of Fig. 17.21(b), use the expressions for ω0 and Q given in the top row of Table 17.1 to determine the sensitivities of ω0 and Q to all resistors and capacitors.
Section 17.10: Transconductance-C Filters
17.82 For the fully differential transconductor of Fig.17.35(f), find an expression for Gm in terms of I and the MOSFET’s transconductance parameter kn. For kn = 0.5 mA/V, find the bias current I that results in Gm = 0.25 mA/V. If for tuning purposes it is required to adjust Gm in a ±5% range, what is the required range for adjusting I?
D 17.83 Using the circuit of Fig. 17.36(a) to realize a 1-k resistance, what Gm is needed? If the output resistance of the transconductor is 100 k, what is the resistance actually realized?
D 17.84 Using four transconductors, give the circuit for obtaining an output voltage Vo related to three input voltages
Use C = C = 10 nF. (Hint: For a maximally flat response, 12
√
Q=1/ 2andω3dB =ω0.)
Problems 1375
D *17.75 Design a fifth-order Butterworth low-pass filter that has a 3-dB bandwidth of 10 kHz and a dc gain of unity. Use the cascade connection of two Sallen-and-Key circuits [Fig. 17.34(c)] and a first-order section [Fig. 17.13(a)]. Use a 10-k value for all resistors.
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
1376 Chapter 17 Filters and Tuned Amplifiers
V1, V2, and V3 by Vo = V1 −2V2 +3V3. Give the values of the four transconductances as ratios of Gm of the transconductor that delivers the output voltage.
D17.85 FortheintegratorinFig.17.36(b),whatvalueofGm is needed to obtain an integrator with a unity-gain frequency of 10 MHz utilizing a 5-pF capacitor?
D 17.86 If the transconductor in the integrator of Fig.17.36(b) has an output resistance Ro and an output capacitance Co, what is the transfer function realized? If the error in the integrator time constant must be less than 1%, what is the smallest value of C that can be used? If the low-frequency pole introduced by Ro is to be at least two decades lower than the unity-gain frequency of the integrator, what is the smallest Gm that this transconductor must have?
D 17.87 Design the first-order low-pass filter in Fig. 17.36(c) to have a pole frequency of 20 MHz and a dc gain of 10. Use C = 2 pF.
D 17.88 If a capacitor C1 is connected between the input node and node X in the circuit of Fig. 17.36(c), what transfer function Vo/Vi is realized?
(c) Use a fourth inverting transconductor Gm4 with its input connected to an input voltage Vi and its output connected to node 1. Compare the circuit thus created to the two-integrator-loop Gm –C filter of Fig. 17.37(b).
(d) What filter function is (i) V1/Vi, (ii) V2/Vi?
D 17.90 Consider the Gm –C second-order bandpass filter of Fig. 17.37(b) and its associated expressions in Eqs. (17.95) and (17.96). Generate an alternative design based on selecting Gm1 =Gm2 =Gm3 =Gm and C2 =C. Find expressions for C1 andGm intermsofω0,Q,andC.
D 17.91 To enable the second-order Gm –C circuit in Fig. 17.37(b) to realize filter functions other than bandpass and lowpass, implement the following modifications:
(a) Connect a capacitor C3 between the positive input terminal and the output terminal of transconductor Gm4 and
(b) Add a fifth negative transconductor Gm5 with Vi applied to its input, and its output connected to the node at which V2 is taken.
Derive an expression for the transfer function V1 /Vi .
D 17.92 Design the circuit of Fig. 17.37(c) to realize a bandpass function having a center frequency of 25 MHz, Q = 5, and a center-frequency gain of 5. Select Gm1 = Gm2 and C1 =C2 =5 pF.
Section 17.11: Switched-Capacitor Filters
17.93 For the switched-capacitor input circuit of Fig. 17.38(b), in which a clock frequency of 200 kHz is used, what input resistances correspond to capacitance C1 valuesof1pF,5pF,and10pF?
17.94 For a dc voltage of 1 V applied to the input of the circuit of Fig. 17.38(b), in which C1 is 1 pF, what charge is transferred for each cycle of the two-phase clock? For a 100-kHz clock, what is the average current drawn from the input source? For a feedback capacitance of 10 pF, what change would you expect in the output for each cycle of the clock? For an amplifier that saturates at ±10 V and the feedback capacitor initially discharged, how many clock cycles would it take to saturate the amplifier? What is the average slope of the staircase output voltage produced?
D17.95 Repeat Exercise17.32 for a clock frequency of 500 kHz.
CHAPTER 17 PROBLEMS
D *17.89 For the circuit in Fig. P17.89:
– Gm1 I1
1+
Gm2 +
+ –
2
V1 – –C
Zin ≡ V1 I1
Figure P17.89
(a) ShowthattheinputimpedanceZin isthatofaninductance L and find an expression for L.
(b) Use the inductance generated at the input to form an LCR resonator. To realize the resistance R, use a third transconductor Gm3.
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
CHAPTER 17 PROBLEMS
D 17.96 Repeat Exercise 17.32 for Q = 50.
D 17.97 Design the circuit of Fig. 17.40(b) to realize, at the
output of the second (noninverting) integrator, a maximally
*17.102 (a) Substituting s = jω in the transfer function
T(s) of a second-order bandpass filter [see Fig. 17.16(c)],
find |T(jω)|. For ω in the vicinity of ω [i.e., ω = ω + 0 20
δω=ω 1+δω/ω , where δω/ω ≪1 so that ω ≃ 200 0
ω0 1+2δω/ω0 ],showthat,forQ≫1,
flat low-pass function with ω
= 10
3
rad/s and unity dc gain.
3dB
Use a clock frequency fc = 100 kHz and select C1 = C2 = 5 pF.
Give the values of C3 , C4 , C5 , and C6 . (Hint: For a maximally
flat response, Q = 1/√2 and ω = ω .)
T jω0
2
Problems 1377
3dB 0
|T(jω)|≃
1 + 4Q2 δω/ω
Section 17.12: Tuned Amplifiers
*17.98 A voltage signal source with a resistance Rs = 10 k is connected to the input of a common-emitter BJT amplifier. Between base and emitter is connected a tuned circuit with L=0.5μHandC=200pF.Thetransistorisbiasedat1mA andhasβ=200,Cπ =10pF,andCμ =0.5pF.Thetransistor load is a resistance of 5 k. Find ω0 , Q, the 3-dB bandwidth, and the center-frequency gain of this single-tuned amplifier.
17.99 A coil having an inductance of 10 μH is intended for applications around 1-MHz frequency. Its Q is specified to be 250. Find the equivalent parallel resistance Rp. What is the value of the capacitor required to produce resonance at 1 MHz? What additional parallel resistance is required to produce a 3-dB bandwidth of 12 kHz?
17.100 Aninductanceof36μHisresonatedwitha1000-pF capacitor. If the inductor is tapped at one-third of its turns and a 1-k resistor is connected across the one-third part, find f0 and Q of the resonator.
*17.101 Consider a common-emitter transistor amplifier loaded with an inductance L. Ignoring ro, show that for ωCμ ≪ 1/ωL, the amplifier input admittance is given by
0
(b) Use the result obtained in (a) to show that the 3-dB bandwidth B, of N synchronously tuned sections connected in cascade, is
B=ω0/Q√21/N −1
**17.103 (a) Using the fact that for Q ≫ 1 the second-order bandpass response in the neighborhood of ω0 is the same as the response of a first-order low-pass with 3-dB frequency of (ω0 /2Q), show that the bandpass response at ω = ω0 + δω, for δω ≪ ω0, is given by
|T(jω)|≃
1 + 4Q2 δω/ω0
Tjω 0
2
1 Y ≃ −ω2C Lg +jω C +C
(b) Use the relationship derived in (a) together with Eq. (17.123) to show that a bandpass amplifier with a 3-dB bandwidth B, designed using N synchronously tuned stages, has an overall transfer function given by
T j ω
T(jω) = 0 overall
overall 1 + 4(21/N − 1)(δω/B)2 N /2
(c) Use the relationship derived in (b) to find the attenuation
(in decibels) obtained at a bandwidth 2B for N = 1 to 5. Also find the ratio of the 30-dB bandwidth to the 3-dB bandwidth for N = 1 to 5.
inrμm πμ π
(Note: The real part of the input admittance can be negative. This can lead to oscillations.)
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
CHAPTER 18
Signal Generators and Waveform- Shaping Circuits
Introduction 1379
18.1 Basic Principles of Sinusoidal Oscillators 1380
18.6 Generation of a Standardized Pulse: TheMonostableMultivibrator 1417
18.7 Integrated-Circuit Timers 1419 18.8 Nonlinear Waveform-Shaping
Circuits 1424 Summary 1428 Problems 1428
18.2 Op Amp–RC Oscillator Circuits
18.3 LC and Crystal Oscillators 1396
18.4 Bistable Multivibrators 1404
18.5 Generation of Square and Triangular Waveforms Using Astable
Multivibrators 1412
1388
IN THIS CHAPTER YOU WILL LEARN
1. That an oscillator circuit that generates sine waves can be implemented by connecting a frequency-selective network in the positive-feedback path of an amplifier.
2. The conditions under which sustained oscillations are obtained and the frequency of the oscillations.
3. How to design nonlinear circuits to control the amplitude of the sine wave obtained in a linear oscillator.
4. A variety of circuits for implementing a linear sine-wave oscillator.
5. How op amps can be combined with resistors and capacitors to implement precision
multivibrator circuits.
6. How a bistable circuit can be connected in a feedback loop with an op-amp integrator to implement a generator of square and triangular waveforms.
7. The application of one of the most popular IC chips of all time, the 555 timer, in the design of generators of pulse and square waveforms.
8. How a triangular waveform can be shaped by a nonlinear circuit to provide a sine waveform.
Introduction
In the design of electronic systems, the need frequently arises for signals having prescribed standard waveforms, for example, sinusoidal, square, triangular, or pulse. Systems in which standard signals are required include computer and control systems where clock pulses are needed for, among other things, timing; communication systems where signals of a variety of waveforms are utilized as information carriers; and test and measurement systems where signals, again of a variety of waveforms, are employed for testing and characterizing electronic devices and circuits. In this chapter we study signal-generator circuits.
The signal-generator or oscillator circuits studied in this chapter are collectively capable of providing signals with frequencies in the range of hertz to hundreds of gigahertz. While some can be fabricated on chip, others utilize discrete components. Examples of commonly encountered oscillators include the microprocessor clock generator (fabricated on chip utilizing the ring oscillator studied in Section16.4.4 with frequencies in the several-gigahertz range); the carrier-waveform generator in wireless transceivers (on chip, up to the hundreds-of-gigahertz range); the oscillator in an electronic watch (utilizing a quartz
1379
1380 Chapter 18
Signal Generators and Waveform-Shaping Circuits
crystal with a frequency of 215 Hz); and the variable-frequency function generator in the electronics lab (utilizing a discrete circuit with frequency in the hertz to megahertz range).
There are two distinctly different approaches for the generation of sinusoids, perhaps the most commonly used of the standard waveforms. The first approach, studied in Sections 18.1 to 18.3, employs a positive-feedback loop consisting of an amplifier and an RC or LC frequency-selective network. While the frequency of the generated sine wave is determined by the frequency-selective network, the amplitude is set using a nonlinear mechanism, implemented either with a separate circuit or using the nonlinearities of the amplifying device itself. In spite of this, these circuits, which generate sine waves utilizing resonance phenomena, are known as linear oscillators. The name clearly distinguishes them from the circuits that generate sinusoids by way of the second approach. In these circuits, a sine wave is obtained by appropriately shaping a triangular waveform. We study waveform-shaping circuits in Section 18.8, following the study of triangular-waveform generators.
Circuits that generate square, triangular, pulse (etc.) waveforms, called nonlinear oscillators or function generators, employ circuit building blocks known as multivibrators. There are three types of multivibrator: the bistable (Section 18.4), the astable (Section 18.5), and the monostable (Section 18.6). The multivibrator circuits presented in this chapter employ op amps and are intended for precision analog applications. Bistable and monostable multivibrator circuits using digital logic gates were studied in Chapter 16.
A general and versatile scheme for the generation of square and triangular waveforms is obtained by connecting a bistable multivibrator and an op-amp integrator in a feedback loop (Section 18.5). Similar results can be obtained using a commercially available versatile IC chip, the 555 timer (Section 18.7).
18.1 Basic Principles of Sinusoidal Oscillators
In this section, we study the basic principles of the design of linear sine-wave oscillators. In spite of the name linear oscillator, some form of nonlinearity has to be employed to provide control of the amplitude of the output sine wave. In fact, all oscillators are essentially nonlinear circuits. This complicates the task of analysis and design of oscillators: No longer is one able to apply transform (s-plane) methods directly. Nevertheless, techniques have been developed by which the design of sinusoidal oscillators can be performed in two steps: The first step is a linear one, and frequency-domain methods of feedback circuit analysis can be readily employed. Subsequently, in step 2, a nonlinear mechanism for amplitude control can be provided.
18.1.1 The Oscillator Feedback Loop
The basic structure of a sinusoidal oscillator consists of an amplifier and a frequency-selective network connected in a positive-feedback loop, such as that shown in block diagram form in Fig. 18.1. Although no input signal will be present in an actual oscillator circuit, we include an input signal here to help explain the principle of operation. It is important to note that unlike thenegative-feedbackloopofFig.11.1,herethefeedbacksignalxf issummedwithapositive sign. Thus the gain-with-feedback is given by
Af (s) = A(s) (18.1) 1 − A(s)β(s)
where we note the negative sign in the denominator. The loop gain L(s) is given by
L(s) ≡ A(s)β(s) (18.2)
18.1 Basic Principles of Sinusoidal Oscillators 1381
Figure18.1 Thebasicstructureofasinusoidaloscillator.Apositive-feedbackloopisformedbyanamplifier and a frequency-selective network. In an actual oscillator circuit, no input signal will be present; here an input signal xs is employed to help explain the principle of operation.
and the characteristic equation is
1 − L(s) = 0 (18.3) 18.1.2 The Oscillation Criterion
If at a specific frequency f0 the loop gain Aβ is equal to unity, it follows from Eq. (18.1) that Af will be infinite. That is, at this frequency the circuit will have a finite output for zero input signal. Such a circuit is by definition an oscillator. Thus the condition for the feedback loop of Fig. 18.1 to provide sinusoidal oscillations of frequency ω0 is
L(jω0) ≡ A(jω0)β(jω0) = 1 (18.4)
That is, at ω0 the phase of the loop gain should be zero and the magnitude of the loop gain should be unity. This is known as the Barkhausen criterion. Note that for the circuit to oscillate at one frequency, the oscillation criterion should be satisfied only at one frequency (i.e., ω0); otherwise the resulting waveform will not be a simple sinusoid.
An intuitive feeling for the Barkhausen criterion can be gained by considering once more the feedback loop of Fig. 18.1. For this loop to produce and sustain an output xo with no input applied (xs = 0), the feedback signal xf ,
xf =βxo
should be sufficiently large that when multiplied by A it produces xo, that is,
that is,
which results in
Axf =xo
Aβxo =xo
Aβ = 1
Amplifier A
It should be noted that the frequency of oscillation ω0 is determined solely by the phase characteristics of the feedback loop; the loop oscillates at the frequency for which the phase is zero (or, equivalently, 360°). It follows that the stability of the frequency of oscillation will be determined by the manner in which the phase φ(ω) of the feedback loop varies with frequency. A “steep” function φ(ω) will result in a more stable frequency. This can be seen if one imagines a change in phase φ due to a change in one of the circuit components. If dφ/dω is large, the resulting change in ω0 will be small, as illustrated in Fig. 18.2.
1382 Chapter 18
Signal Generators and Waveform-Shaping Circuits
Figure 18.2 Dependence of the oscillator-frequency stability on the slope of the phase response. A steep phase response (i.e., large dφ/dω) results in a small ω0 for a given change in phase φ [resulting from a change (due, for example, to temperature) in a circuit component].
An alternative approach to the study of oscillator circuits consists of examining the circuit poles, which are the roots of the characteristic equation (Eq. 18.3). For the circuit to produce sustained oscillations at a frequency ω0 the characteristic equation has to have roots at s= ±jω0. Thus 1−A(s)β(s) should have a factor of the form s2 +ω02.
EXERCISE
18.1 Considerasinusoidaloscillatorformedbyconnectinganamplifierwithagainof2andasecond-order bandpass filter in a feedback loop. Find the pole frequency and the center-frequency gain of the filter needed to produce sustained oscillations at 1 kHz.
Ans. 1 kHz; 0.5
18.1.3 Analysis of Oscillator Circuits
Analysis of a given oscillator circuit to determine the frequency of oscillation and the condition for the oscillations to start proceeds in three steps:
1. Break the feedback loop to determine the loop gain A(s)β(s). This step is similar to that utilized in Section 11.2 in the analysis of negative-feedback amplifiers.
2. The oscillation frequency ω0 is found as the frequency for which the phase angle of A(jω) β(jω) is zero or, equivalently, 360◦.
3. The condition for the oscillations to start is found from |A(jω0)β(jω0)|≥1
Note that making the magnitude of the loop gain slightly greater than unity ensures that oscillations will start.
18.1 Basic Principles of Sinusoidal Oscillators 1383
Example 18.1
Figure 18.3(a) shows a sinusoidal oscillator formed by placing a second-order LCR bandpass filter [see Fig. 17.18(d)] in the feedback path of a positive-gain amplifier. Find the frequency of oscillation ω0 , and the condition for oscillations to start. Assume an ideal op amp.
Solution
To obtain the loop gain, we break the positive-feedback loop at the positive input terminal of the op amp where the input impedance is infinite, apply an input voltage Vi, and find the returned voltage Vr. This results in the circuit in Fig. 18.3(b). Since the op amp is ideal, we can find its output voltage Vo and hence A(s) as
A(s)≡Vo =1+r2 Vi r1
The transfer function of the frequency-selective network β(s) ≡ Vr /Vo can be found utilizing Eq. (17.39) as
1
Vs β(s)≡ r = CR
Vo s2 +s 1 + 1 CR LC
While we have found it easy to determine A(s) and β(s) separately, our interest is in fact in their
product, the loop gain A(s) β(s),
s1 1+r2 CR r1
s2 +s 1 + 1
r2
r2
A(s)β(s) =
CR
LC
r1
r1 –Vo –
++
R
L
Vr C
(a)
Figure18.3 (a)Anoscillatorformedbyconnectingapositive-gainamplifierinafeedbackloopwithabandpassRLC circuit. (b) Breaking the feedback loop at the input of the op amp to determine A(s) ≡ Vo (s)/Vi (s) and β (s) ≡ Vr (s)/Vo (s), and hence the loop gain A(s)β(s).
Vi +–
Vo
C
R
L
(b)
1384
Chapter 18 Signal Generators and Waveform-Shaping Circuits
Example 18.1 continued Substituting s = jω,
CR
From this expression we see that the phase angle of A(jω) β(jω) will be zero at the value of ω that
makes the real part of the denominator zero, thus
√ ω0=1/ LC
At this frequency, the magnitude of the loop gain is given by |A(jω0)β(jω0)| =1+ r2
Thus oscillation will start for
r1 r2/r1 ≥0
A(jω)β(jω)= 1 ω
ω r j1+2 CR r1
−ω2 + +j LC
While r2 = 0 is theoretically sufficient for sustained oscillations, it is usual to design for r2 /r1 > 0 to ensure that oscillations start. This point will be explained in greater detail in the next section.
Before leaving this example, we observe that the results could have been obtained by inspection of the
circuit in Fig. 18.3(a). Since the phase angle of the amplifier gain is zero, we examine the LCR bandpass
circuit to determine the frequency at which its phase is zero. This in turn is the frequency at which the
√
LC tank has an infinite impedance, which is the resonance frequency ω0 = 1/ LC. At this frequency the
transmission of the bandpass LCR circuit is unity. Thus for oscillation to start, the amplifier gain must be greater than or equal to unity.
An Alternative Analysis Approach There is a simple alternative approach for the analysis of oscillator circuits that does not involve breaking the feedback loop. The method proceeds as follows: We assume that the circuit is oscillating and thus has voltage and current signals at the oscillation frequency ω0 . We analyze the circuit in the usual manner and reduce the equations to a single equation in terms of a single voltage or current variable. Since the voltage or current quantity is not zero (because the circuit is assumed to be oscillating), we can divide by the variable and thus eliminate it. The equation can then be manipulated to the form
D(s)=0
where D(s) is a polynomial in s. Substituting s = jω, we then equate the real and imaginary parts of D(jω) to zero. One of the resulting equations yields ω0 and the other provides the condition for sustained oscillation. This method will be utilized on numerous occasions in the next sections.
18.1 Basic Principles of Sinusoidal Oscillators 1385
EXERCISE
18.2 ApplythealternativeanalysismethodtothecircuitofFig.18.3(a)andthusdetermineD(s),Re[D(jω)], Im[D(jω)], ω0, and the condition for sustained oscillation.
Ans.D(s)=s2−s1 r2+1;−ω2+1;−ωr2;1√LC;r2=0 CR r1 LC LC CR r1
18.1.4 Nonlinear Amplitude Control
The oscillation condition, the Barkhausen criterion, discussed in Section 18.1.2, guarantees sustained oscillations in a mathematical sense. It is well known, however, that the parameters of any physical system cannot be maintained constant for any length of time. In other words, supposeweworkhardtomake|Aβ| =1atω=ω0,andthenthetemperaturechangesand|Aβ| becomes slightly less than unity. Obviously, oscillations will cease in this case. Conversely, if |Aβ| exceeds unity, oscillations will grow in amplitude. We therefore need a mechanism for forcing |Aβ| to remain equal to unity at the desired value of output amplitude. This task is accomplished by providing a nonlinear circuit for gain control.
Basically, the function of the gain-control mechanism is as follows: First, to ensure that oscillations will start, one designs the circuit such that |Aβ| is slightly greater than unity. This corresponds to designing the circuit so that the poles are in the right half of the s plane. Thus as the power supply is turned on, oscillations will grow in amplitude. When the amplitude reaches the desired level, the nonlinear network comes into action and causes the loop gain to be reduced to exactly unity. In other words, the poles will be “pulled back” to the jω axis. This action will cause the circuit to sustain oscillations at this desired amplitude. If, for some reason, the loop gain is reduced below unity, the amplitude of the sine wave will diminish. This will be detected by the nonlinear network, which will cause the loop gain to increase to exactly unity.
As will be seen, there are two basic approaches to the implementation of the nonlinear amplitude-stabilization mechanism. The first approach makes use of a limiter circuit (see Section 4.6). Oscillations are allowed to grow until the amplitude reaches the level to which the limiter is set. When the limiter comes into operation, the amplitude remains constant. Obviously, the limiter should be “soft” to minimize nonlinear distortion. Such distortion, however, is reduced by the filtering action of the frequency-selective network in the feedback loop. In fact, in one of the oscillator circuits studied in Section 18.2, the sine waves are hard limited, and the resulting square waves are applied to a bandpass filter present in the feedback loop. The “purity” of the output sine waves will be a function of the selectivity of this filter. That is, the higher the Q of the filter, the less the harmonic content of the sine-wave output.
The other mechanism for amplitude control utilizes an element whose resistance can be controlled by the amplitude of the output sinusoid. By placing this element in the feedback circuit so that its resistance determines the loop gain, the circuit can be designed to ensure that the loop gain reaches unity at the desired output amplitude. Diodes, or JFETs operated in the triode region,1 are commonly employed to implement the controlled-resistance element.
1We have not studied JFETs in this book. However, the book website includes material on JFETs and JFET circuits.
1386 Chapter 18 Signal Generators and Waveform-Shaping Circuits
EXERCISE
18.3 Assume that the oscillator of Fig. 18.3(a) is designed for a loop-gain magnitude greater than unity so that the amplitude of oscillations grows to the point that the op-amp output saturates. Assume that the saturation levels of the op amp are ±2 V and that the signal at the output of the op amp is nearly a square wave. If the bandpass LCR circuit is of sufficiently high selectivity, what is the amplitude of the sine wave across the LC circuit? (Hint: The fundamental frequency component in the Fourier series expansion of a square wave of amplitude V has an amplitude 4V/π.)
Ans. 2.55 V
18.1.5 A Popular Limiter Circuit for Amplitude Control
We conclude this section by presenting a limiter circuit that is frequently employed for the amplitude control of op-amp oscillators, as well as in a variety of other applications. The circuit is more precise and versatile than those presented in Chapter 4.
The limiter circuit is shown in Fig. 18.4(a), and its transfer characteristic is depicted in Fig. 18.4(b). To see how the transfer characteristic is obtained, consider first the case of a small (close to zero) input signal v I and a small output voltage v O , so that v A is positive and vB is negative. It can be easily seen that both diodes D1 and D2 will be off. Thus all of the input current vI /R1 flows through the feedback resistance Rf , and the output voltage is given by
vO = − Rf /R1 vI (18.5) This is the linear portion of the limiter transfer characteristic in Fig. 18.4(b). We now can use
superposition to find the voltages at nodes A and B in terms of ±V and vO as
v=V R3 +v R2 (18.6)
v =−V R4 +v R5 (18.7) B R+R OR+R
As vI goes positive, vO goes negative (Eq. 18.5), and we see from Eq. (18.7) that vB will become more negative, thus keeping D2 off. Equation (18.6) shows, however, that vA becomes less positive. Then, if we continue to increase vI , a negative value of vO will be reached at which vA becomes −0.7 V or so and diode D1 conducts. If we use the constant-voltage-drop model for D1 and denote the voltage drop VD, the value of vO at which D1 conducts can be found from Eq. (18.6). This is the negative limiting level, which we denote L−,
RR
L−=−V3−VD 1+3 (18.8)
R2 R2
The corresponding value of vI can be found by dividing L− by the limiter gain −Rf /R1. If vI is increasedbeyondthisvalue,morecurrentisinjectedintoD1,andvA remainsatapproximately
A R+R OR+R 2323
4545
V
R2 D1
A
Slope
vO
L
0 vI Slope Rf
18.1 Basic Principles of Sinusoidal Oscillators 1387
R RRR
(Rf //R4) 131
f
vI
D2
vO
R4 B
R5
L
R1
Slope (Rf //R3) R1
(b)
V (a)
vO
L
Slope R4 R1
L (c)
0 vI Slope R3
Figure 18.4 (a) A popular limiter circuit. (b) Transfer characteristic of the limiter circuit; L− and L+ are givenbyEqs.(18.8)and(18.9),respectively.(c)WhenRf isremoved,thelimiterturnsintoacomparatorwith the characteristic shown.
−VD. Thus the current through R2 remains constant, and the additional diode current flows through R3. Thus R3 appears in effect in parallel with Rf , and the incremental gain (ignoring the diode resistance) is −(Rf ∥R3)/R1. To make the slope of the transfer characteristic small in the limiting region, a low value should be selected for R3.
ThetransfercharacteristicfornegativevI canbefoundinamanneridenticaltothatjust employed. It can be easily seen that for negative vI , diode D2 plays an identical role to that
R1
1388 Chapter 18
Signal Generators and Waveform-Shaping Circuits
played by diode D1 for positive vI . We can use Eq. (18.7) to find the positive limiting level L+ RR
L+=V4+VD 1+4 (18.9) R5 R5
and the slope of the transfer characteristic in the positive limiting region is −(Rf ∥R4)/R1. We thus see that the circuit of Fig. 18.4(a) functions as a soft limiter, with the limiting levels L+ and L− , and the limiting gains independently adjustable by the selection of appropriate resistor values.
Finally, we note that increasing Rf results in a higher gain in the linear region while keeping L+ and L− unchanged. In the limit, removing Rf altogether results in the transfer characteristic of Fig. 18.4(c), which is that of a comparator. That is, the circuit compares vI with the comparator reference value of 0 V: vI > 0 results in vO ≃L−, and vI <0 yields vO ≃L+.
EXERCISE
18.4 For the circuit of Fig. 18.4(a) with V =15 V, R1 =30 k, Rf =60 k, R2 =R5 =9 k, and R3 = R4 = 3 k, find the limiting levels and the value of vI at which the limiting levels are reached. Also determine the limiter gain and the slope of the transfer characteristic in the positive and negative limiting regions. Assume that VD = 0.7 V.
Ans. ±5.93 V; ±2.97 V; –2; –0.095
18.2 Op Amp–RC Oscillator Circuits
In this section we shall study some practical oscillator circuits utilizing op amps and RC networks. These circuits are usually assembled on printed-circuit boards; their frequency of operation extends from very low frequencies to at most 1 MHz.
18.2.1 The Wien-Bridge Oscillator
One of the simplest oscillator circuits is based on the Wien bridge. Figure 18.5 shows a Wien-bridge oscillator without the nonlinear gain-control network. The circuit consists of an op amp connected in the noninverting configuration, with a closed-loop gain of 1+R2/R1. In the feedback path of this positive-gain amplifier, an RC network is connected. The loop gain can be easily obtained by multiplying the transfer function Va(s)/Vo(s) of the feedback network by the amplifier gain,
RZ L(s)= 1+ 2 p
= 1+R2/R1 1+ZsYp
R1 Zp +Zs
Thus,
Substituting s = jω results in
L(s) = 1 + R2 /R1 3+sCR+1/sCR
ω0CR= 1 ω0 CR
(18.10)
18.2
Op Amp–RC Oscillator Circuits 1389
Figure 18.5 A Wien-bridge oscillator without amplitude stabilization.
1 + R2 /R1
3 + j(ωCR − 1/ωCR)
L(jω) =
The loop gain will be a real number (i.e., the phase will be zero) at one frequency given by
That is,
ω0 = 1/CR (18.12) Oscillations will start at this frequency if the loop gain is at least unity. This can be achieved
by selecting
R2/R1 = 2 (18.13)
To ensure that oscillations will start, one chooses R2 /R1 slightly greater than 2. The reader can easily verify that if R2/R1 = 2 + δ, where δ is a small number, the roots of the characteristic equation 1 − L(s) = 0 will be in the right half of the s plane.
The amplitude of oscillation can be determined and stabilized by using a nonlinear control
network. Two different implementations of the amplitude-controlling function are shown in
Figs. 18.6 and 18.7. The circuit in Fig. 18.6 employs a symmetrical feedback limiter of the
typestudiedinSection18.1.4.ItisformedbydiodesD1 andD2 togetherwithresistorsR3,R4,
R5, and R6. The limiter operates in the following manner: At the positive peak of the output
voltage vO, the voltage at node b will exceed the voltage v1 (which is about 1 vO), and diode D2 3
conducts. This will clamp the positive peak to a value determined by R5, R6, and the negative power supply. To be specific, the value of the positive output peak can be calculated by setting vb =v1 +VD2 and writing a node equation at node b while neglecting the current through D2. Similarly, the negative peak of the output sine wave will be clamped to the value that causes diodeD1 toconduct.Thevalueofthenegativepeakcanbedeterminedbysettingva =v1 −VD1
(18.11)
1390 Chapter 18
Signal Generators and Waveform-Shaping Circuits
R1
D21
R2
Cs
Rs
Rp
Cp
16 nF
THE WIEN-BRIDGE OSCILLATOR:
EXERCISE
Figure 18.6 A Wien-bridge oscillator with a limiter used for amplitude control.
The Wien bridge consisting of four resistors and two capacitors was invented in 1891 by Max Wien, a Prussian physicist, for inductance measurement. Much later, William Hewlett (cofounder in 1939 of Hewlett-Packard), while working toward his master’s degree at Stanford University, realized the importance of placing part of the Wien bridge in a positive-feedback loop to form what was called the Wien-bridge oscillator. The first product in 1939 of the new Hewlett-Packard Company was the HP200A, a flexible, precision sine-wave generator using vacuum tubes to implement the amplifier and a tungsten lamp to control the loop gain and thus the amplitude of the sine wave.
D2
18.5 For the circuit in Fig. 18.6: (a) Disregarding the limiter circuit, find the location of the closed-loop poles. (b) Find the frequency of oscillation. (c) With the limiter in place, find the amplitude of the output sine wave (assume that the diode drop is 0.7 V).
Ans. (a) (105/16)(0.015 ± j); (b) 1 kHz; (c) 21.36 V (peak-to-peak)
Cp
16 nF
18.2 Op Amp–RC Oscillator Circuits 1391
P
Cs Rp
D1
D2
Rs
Figure 18.7 A Wien-bridge oscillator with an alternative method for amplitude stabilization.
and writing an equation at node a while neglecting the current through D1. Finally, note that to obtain a symmetrical output waveform, R3 is chosen equal to R6, and R4 equal to R5.
The circuit of Fig. 18.7 employs an inexpensive implementation of the parameter-variation mechanism of amplitude control. Potentiometer P is adjusted until oscillations just start to grow. As the oscillations grow, the diodes start to conduct, causing the effective resistance between a and b to decrease. Equilibrium will be reached at the output amplitude that causes the loop gain to be exactly unity. The output amplitude can be varied by adjusting potentiometer P.
As indicated in Fig. 18.7, the output is taken at point b rather than at the op-amp output terminal because the signal at b has lower distortion than that at a. To appreciate this point, note that the voltage at b is proportional to the voltage at the op-amp input terminals and that the latter is a filtered (by the RC network) version of the voltage at node a. Node b, however, is a high-impedance node, and a buffer will be needed if a load is to be connected.
EXERCISE
18.6 ForthecircuitinFig.18.7,findthefollowing:(a)thesettingofpotentiometerPatwhichoscillations just start; (b) the frequency of oscillation.
Ans. (a) 20 k to ground; (b) 1 kHz
18.2.2 The Phase-Shift Oscillator
The basic structure of the phase-shift oscillator is shown in Fig. 18.8. It consists of a negative-gain amplifier (–K) with a three-section (third-order) RC ladder network in the feedback. The circuit will oscillate at the frequency for which the phase shift of the RC
1392 Chapter 18
Signal Generators and Waveform-Shaping Circuits
Figure 18.8 A phase-shift oscillator.
network is 180°. Only at this frequency will the total phase shift around the loop be 0° or 360°. Here we should note that the reason for using a three-section RC network is that three is the minimum number of sections (i.e., lowest order) that is capable of producing a 180° phase shift at a finite frequency.
For oscillations to be sustained, the value of K should be equal to the inverse of the magnitude of the RC network transfer function at the frequency of oscillation. However, to ensure that oscillations start, the value of K has to be chosen slightly higher than the value that satisfies the unity-loop-gain condition. Oscillations will then grow in magnitude until limited by some nonlinear control mechanism.
Figure 18.9 shows a practical phase-shift oscillator with a feedback limiter, consisting of diodes D1 and D2 and resistors R1, R2, R3, and R4 for amplitude stabilization. To start oscillations, Rf has to be made slightly greater than the minimum required value. Although the circuit stabilizes more rapidly and provides sine waves with more stable amplitude, if Rf is made much larger than this minimum, the price paid is an increased output distortion.
K
EXERCISES
18.7 Consider the circuit of Fig. 18.9 without the limiter. Break the feedback loop at X and find the loop gain Aβ≡Vo(j ω)/Vx(j ω) in symbolic form (i.e., do not substitute the numerical values given). To do this, it is easier to start at the output and work backward, finding the various currents and voltages, and eventually Vx in terms of Vo.
Ans. ω2C2RRf
4 + j(3ωCR − 1/ωCR)
18.8 Use the expression derived in Exercise 18.7 to find the frequency of oscillation f0 and the minimum
f
requiredvalueofR foroscillationstostartinthecircuitofFig.18.9.
√
Ans. ω0 = 1/ 3CR;Rf ≥ 12R;f0 = 574.3Hz;Rf = 120 k
18.2.3 The Quadrature Oscillator
The quadrature oscillator is based on the two-integrator loop studied in Section 17.7. As an active filter, the loop is damped to locate the poles in the left half of the s plane. Here, no such
madeequalto2R,andthus–R cancels2R,andattheinputweareleftwithacurrentsource
f
v /2RfeedingacapacitorC.Theresultisthatv=1 tvO1 dtandv =2v= 1 tv dt.That
18.2 Op Amp–RC Oscillator Circuits 1393
D1
D2
Figure 18.9 A practical phase-shift oscillator with a limiter for amplitude stabilization.
damping will be used, since we wish to locate the poles on the jω axis to provide sustained oscillations. In fact, to ensure that oscillations start, the poles are initially located in the right half-plane and then “pulled back” by the nonlinear gain control.
Figure 18.10(a) shows a practical quadrature oscillator. Amplifier 1 is connected as an
inverting Miller integrator with a limiter in the feedback for amplitude control. Amplifier
2 is connected as a noninverting integrator [thus replacing the cascade connection of the
Miller integrator and the inverter in the two-integrator loop of Fig. 17.25(b)]. To understand
the operation of this noninverting integrator, consider the equivalent circuit shown in
Fig. 18.10(b). Here, we have replaced the integrator input voltage vO1 and the series resistance
2R by the Norton equivalent composed of a current source vO1/2R and a parallel resistance 2R.
Now, since vO2 = 2v, where v is the voltage at the input of op amp 2, the current through Rf
willbe(2v−v)/Rf =v/Rf inthedirectionfromoutputtoinput.ThusRf givesrisetoanegative
input resistance, –Rf , as indicated in the equivalent circuit of Fig. 18.10(b). Nominally, Rf is
O1 C 0 2R O2 CR 0 O1
is, for Rf = 2R, the circuit functions as a perfect noninverting integrator. If, however, Rf is
made smaller than 2R, a net negative resistance appears in parallel with C.
Returning to the oscillator circuit in Fig. 18.10(a), we note that the resistance Rf in the positive-feedback path of op amp 2 is made variable, with a nominal value of 2R. Decreasing
1394 Chapter 18
Signal Generators and Waveform-Shaping Circuits
D1
D2
v vO2 2
vO1 2R
2R C Rf
(b)
2
v
(a)
Figure 18.10 (a) A quadrature-oscillator circuit. (b) Equivalent circuit at the input of op amp 2.
the value of Rf moves the poles to the right half-plane (Problem 18.21) and ensures that the oscillations start. Too much positive feedback, although it results in better amplitude stability, also results in higher output distortion (because the limiter has to operate “harder”). In this regard, note that the output vO2 will be “purer” than vO1 because of the filtering action provided by the second integrator on the peak-limited output of the first integrator.
If we disregard the limiter and break the loop at X, the loop gain can be obtained as
L(s) ≡ Vo2 = − 1 (18.14)
Vx s2C2R2 Thus the loop will oscillate at frequency ω0, given by
ω0 = 1 (18.15) CR
Finally, it should be pointed out that the name quadrature oscillator is used because the circuit provides two sinusoids with 90° phase difference. This is the case because vO2 is the integral of vO1. There are many applications for which quadrature sinusoids are required.
18.2.4 The Active-Filter-Tuned Oscillator
The last oscillator circuit that we shall discuss is quite simple both in principle and in design. Nevertheless, the approach is general and versatile and can result in high-quality (i.e., low-distortion) output sine waves. The basic principle is illustrated in Fig. 18.11. The
f0
v2 V
v1 V
Figure 18.11 Block diagram of the active-filter-tuned oscillator.
circuit consists of a high-Q bandpass filter connected in a positive-feedback loop with a hard limiter. To understand how this circuit works, assume that oscillations have already started. The output of the bandpass filter will be a sine wave whose frequency is equal to the center frequency of the filter, f0. The sine-wave signal v1 is fed to the limiter, which produces at its output a square wave whose levels are determined by the limiting levels and whose frequency is f0. The square wave in turn is fed to the bandpass filter, which filters out the harmonics and provides a sinusoidal output v1 at the fundamental frequency f0. Obviously, the purity of the output sine wave will be a direct function of the selectivity (or Q factor) of the bandpass filter.
The simplicity of this approach to oscillator design should be apparent. We have independent control of frequency and amplitude as well as of distortion of the output sinusoid. Any filter circuit with positive gain can be used to implement the bandpass filter. The frequency stability of the oscillator will be directly determined by the frequency stability of the bandpass-filter circuit. Also, a variety of limiter circuits (see Section 4.6) with different degrees of sophistication can be used to implement the limiter block.
Figure 18.12 shows one possible implementation of the active-filter-tuned oscillator. This circuit uses a variation on the bandpass circuit based on the Antoniou inductance-simulation circuit [see Fig. 17.22(c)]. Here resistor R2 and capacitor C4 are interchanged. This makes the output of the lower op amp directly proportional to (in fact, twice as large as) the voltage across the resonator, and we can therefore dispense with the buffer amplifier K. The limiter used is a very simple one consisting of a resistance R1 and two diodes.
EXERCISE
18.9 UsingC=16nF,findthevalueofRsuchthatthecircuitofFig.18.12produces1-kHzsinewaves.If the diode drop is 0.7 V, find the peak-to-peak amplitude of the output sine wave. (Hint: A square wave with peak-to-peak amplitude of V volts has a fundamental component with 4V /π volts peak-to-peak amplitude.)
Ans. 10 k; 3.6 V
18.2 Op Amp–RC Oscillator Circuits 1395
1396 Chapter 18
Signal Generators and Waveform-Shaping Circuits
D1 D2
Figure 18.12 A practical implementation of the active-filter-tuned oscillator.
18.2.5 A Final Remark
A1
A2
The op amp–RC oscillator circuits studied are useful for operation in the range 10 Hz to 100 kHz (or perhaps 1 MHz at most). Whereas the lower frequency limit is dictated by the size of passive components required, the upper limit is governed by the frequency-response and slew-rate limitations of op amps. For higher frequencies, circuits that employ transistors together with LC-tuned circuits or crystals are frequently used.2 These are discussed in Section 18.3.
18.3 LC and Crystal Oscillators
Oscillators utilizing transistors (FETs or BJTs), with LC circuits or crystals as the frequency-selective feedback elements, are used in the frequency range of 100 kHz to hundreds of gigahertz. They exhibit higher Q than the RC types. However, LC oscillators are difficult to tune over wide ranges, and crystal oscillators operate at a single frequency.
18.3.1 The Colpitts and Hartely Oscillators
Figure 18.13 shows two commonly used configurations of LC oscillators. They are known as the Colpitts oscillator and the Hartley oscillator. Both utilize a parallel LC circuit connected between collector and base (or between drain and gate if a FET is used) with a fraction of the tuned-circuit voltage fed to the emitter (the source in a FET). This feedback is achieved by
2Of course, transistors can be used in place of the op amps in the circuits just studied. At higher frequencies, however, better results are obtained with LC-tuned circuits and crystals.
Ic
Ic
L1
18.3 LC and Crystal Oscillators 1397
C1
L
Vcb
Vcb
Veb C2 Veb
C
L2
(a) (b)
Figure 18.13 Two commonly used configurations of LC-tuned oscillators: (a) Colpitts and (b) Hartley.
way of a capacitive divider in the Colpitts oscillator and by way of an inductive divider in the Hartley circuit. Observe that in both circuits the voltage Veb gives rise to a current Ic in the direction shown, which in turn results in a positive voltage across the LC circuit. Thus, we do have a positive-feedback loop.
If the frequency of operation is sufficiently low that we can neglect the transistor capacitances, the frequency of oscillation will be determined by the resonance frequency of the parallel-tuned circuit (also known as a tank circuit because it behaves as a reservoir for energy storage). Thus for the Colpitts oscillator we have
(18.16)
(18.17)
The ratio L1/L2 or C1/C2 determines the feedback factor and thus must be adjusted in conjunction with the transistor gain to ensure that oscillations will start. Depending on where the output voltage of the oscillator is to be taken, the appropriate terminal of the transistor can be connected to ground. In this regard, note that any of the three terminals can be grounded without changing the nature of the feedback loop. As an example, we show in Fig. 18.14(a) the Colpitts oscillator with the emitter connected to ground and the output taken at the collector. Although the bias arrangement is not shown, we have included a resistance R that models the combination of the output resistance of the transistor (ro), the inductor loss, and the input resistance of the circuit to which the oscillator output is connected.
To determine the oscillation condition for the Colpitts oscillator in Fig. 18.14(a), we replace the transistor with its equivalent circuit, as shown in Fig. 18.14(b). To simplify the analysis, we have neglected the transistor capacitance Cμ (Cgd for a FET). Capacitance Cπ (Cgs for a FET), although not shown, can be considered to be a part of C2 . The input resistance rπ (infiniteforaFET)hasalsobeenneglected,assumingthatatthefrequencyofoscillation rπ ≫(1/ωC2). Finally, as mentioned earlier, the resistance R includes ro of the transistor.
C C ω0 =1 L 1 2
and for the Hartley oscillator we have
ω0=1/ (L1+L2)C
C1 +C2
1398 Chapter 18
Signal Generators and Waveform-Shaping Circuits
C1 Vo
sC2 V
L Vc V(1s2LC2)
C
R
V L
sC2 V
C2C2 RC1
(a) (b)
Figure18.14 (a)AColpittsoscillatorinwhichtheemitterisgroundedandtheoutputistakenatthecollector. (b) Equivalent circuit of the Colpitts oscillator of (a). To simplify the analysis, Cμ and rπ are neglected. We can consider Cπ to be part of C2, and we can include ro in R.
Using the alternative analysis approach described in Section 18.1.3, we analyze the circuit as shown in Fig. 18.14(b). A node equation at the transistor collector (node C) yields
1 2 sC2Vπ+gmVπ+ R+sC1 1+sLC2 Vπ=0
SinceVπ ̸=0(oscillationshavestarted),itcanbeeliminated,andtheequationcanberearranged
V gm V
in the form
1 s3LC1C2 +s2(LC2/R)+s(C1 +C2)+ gm + R =0
Substituting s = j ω gives
g +1−ω2LC2 +jω(C +C)−ω3LCC=0 mRR1212
(18.18)
(18.19)
For oscillations to start, both the real and imaginary parts must be zero. Equating the imaginary part to zero gives the frequency of oscillation as
C C
ω0 =1 L 1 2 (18.20)
zero and using Eq. (18.20) gives
C2/C1 =gmR (18.21)
which has a simple physical interpretation: For sustained oscillations, the magnitude of the gain from base to collector (gm R) must be equal to the inverse of the voltage ratio provided by the capacitive divider, which from Fig. 18.14(a) can be seen to be Veb /Vce = C1 /C2 . Of course, for oscillations to start, the loop gain must be made greater than unity, a condition that can be
3If rπ is taken into account, the frequency of oscillation can be shown to shift slightly from the value given by Eq. (18.20).
C1 +C2
which is the resonance frequency of the tank circuit, as anticipated.3 Equating the real part to
stated in the equivalent form
gmR > C2/C1
(18.22)
As oscillations grow in amplitude, the transistor’s nonlinear characteristics reduce the effective valueofgm and,correspondingly,reducetheloopgaintounity,thussustainingtheoscillations. Analysis similar to the foregoing can be carried out for the Hartley circuit (see later: Exercise 18.10). At high frequencies, more accurate transistor models must be used. Alternatively, the y parameters of the transistor can be measured at the intended frequency ω0, and the analysis can then be carried out using the y-parameter model (see Appendix C). This is usually simpler and more accurate, especially at frequencies above about 30% of the
transistor fT .
As an example of a practical LC oscillator, we show in Fig. 18.15 a discrete-circuit
implementation of a Colpitts oscillator, complete with bias details. Here the radio-frequency choke (RFC) provides a high impedance at ω0 but a low dc resistance.
Finally, a few words are in order on the mechanism that determines the amplitude of oscillations in the LC oscillators discussed above. Unlike the op-amp oscillators that incorporate special amplitude-control circuitry, LC oscillators utilize the nonlinear iC−vBE characteristics of the BJT (the iD–vGS characteristics of the FET) for amplitude control. Thus these LC oscillators are known as self-limiting oscillators. Specifically, as the oscillations grow in amplitude, the effective gain of the transistor is reduced below its small-signal value. Eventually, an amplitude is reached at which the effective gain is reduced to the point that the Barkhausen criterion is satisfied exactly. The amplitude then remains constant at this value.
Reliance on the nonlinear characteristics of the BJT (or the FET) implies that the collector (drain) current waveform will be nonlinearly distorted. Nevertheless, the output voltage signal will still be a sinusoid of high purity because of the filtering action of the LC circuit. Detailed
Figure 18.15 Complete discrete-circuit implementation for a Colpitts oscillator.
18.3 LC and Crystal Oscillators 1399
1400 Chapter 18 Signal Generators and Waveform-Shaping Circuits
analysis of amplitude control, which makes use of nonlinear-circuit techniques, is beyond the
scope of this book.
EXERCISES
18.10 Show that for the Hartley oscillator of Fig. 18.13(b), the frequency of oscillation is given by
Eq. (18.17) and that for oscillations to start gmR > L1/L2 .
D18.11 Using a BJT biased at IC = 1 mA, design a Colpitts oscillator to operate at ω0 = 106 rad/s. Use C1 = 0.01 μF and assume that the coil available has a Q of 100 (this can be represented by a resistance in parallel with C1 given by Q/ω0C1). Also assume that there is a load resistance at the collector of 2 k and that for the BJT, ro = 100 k. Find C2 and L.
Ans. 0.66 μF; 100 μH (a somewhat smaller C2 would be used to allow oscillations to grow in amplitude)
OSCILLATOR PIONEERS:
Heinrich Georg Barkhausen was a German physicist who taught at the Technical University of Dresden. In 1911, at age 29, he became what has since been described as the world’s first chaired professor of electrical engineering. Among his many interests were high-frequency oscillators, and he created the enduring Barkhausen stability criterion.
Nevada-born Ralph Hartley was a Rhodes Scholar who began work at Western Electric in 1915. He led a transatlantic-radio project for which he invented his tapped-inductor oscillator. As well, he is renowned for having developed a neutralizing scheme to prevent the triode “singing” (self-oscillation) produced by internal input/output capacitance coupling (analogous to that produced by Cμ in a BJT or Cgd in a FET).
Edwin Henry Colpitts was a school principal in Newfoundland. He later obtained advanced education in math and physics at Harvard and in 1907 joined Western Electric, where he ultimately led a group in radio telephony. Later, he improved upon the Hartley tapped-inductor oscillator by introducing a more flexible capacitance voltage divider. The circuit now known as the Colpitts oscillator was patented in 1920 as the “oscillation generator.” Though invented in the context of vacuum tubes, the Colpitts oscillator is extremely versatile and has marked significance in BJT and MOS designs.
18.3.2 The Cross-Coupled LC Oscillator
A currently popular LC oscillator circuit suitable for fabrication in IC form and capable of operating at frequencies approaching hundreds of gigahertz (for use in wireless transceivers) is shown in Fig. 18.16(a). It consists of a pair of MOSFETs connected in the differential amplifier configuration, each with a parallel LC-tuned circuit load, and with the drain of each connected to the gate of the other. The latter connection gives rise to the “cross-coupled” part of the name.
To see how the cross-coupled LC oscillator works, we first note that, as in a differential amplifier, from a signal point of view each of Q1 and Q2 operates in the grounded-source configuration. Next we observe that if we think of Q1 and Q2 together with their loads as common-source amplifiers, we see that the cross coupling simply means that the output of each
VDD
RP LC RPLC
Vo
Q1 Q2
I
(a)
Q1RPL Q2RPL CC
(b)
Figure18.16 (a)Thecross-coupledLCoscillator.(b)Signalequivalentcircuitofthecross-coupledoscillator in (a).
amplifier drives the input of the other, resulting in the feedback loop shown in Fig. 18.16(b).
Here we have eliminated all dc bias sources to concentrate on the signal operation of the circuit.
18.3 LC and Crystal Oscillators 1401
Examination of the feedback loop in Fig. 18.16(b) reveals that at the resonance frequency
√
of each of the two tank circuits (i.e., at ω=ω0 =1 LC), the load of each of Q1 and Q2
reduces to a resistance Rp = ω0LQ, where Q is the quality factor of the inductance. Taking into consideration the output resistance ro of each of Q1 and Q2, we can write for the gain of each of the two stages at ω = ω0,
A1 =A2 =−gm(Rp ∥ro)
Thus each stage exhibits a 180◦ phase shift, for a total phase shift around the loop of 360◦.
Thus the circuit will provide sustained oscillations at
provided
√
ω0=1 LC (18.23)
|A1A2| =[gm(Rp ∥ro)]2 =1
1402 Chapter 18
Signal Generators and Waveform-Shaping Circuits
which reduces to
gm(Rp ∥ ro) = 1 (18.24)
The condition in Eq. (18.24) can be used to determine the minimum required value of gm at which each of Q1 and Q2 is operated for oscillations to be sustained. As usual, to ensure that oscillations start, a somewhat higher value of gm is used. Amplitude stabilization is provided by the nonlinear MOSFET characteristics.
For applications at very high frequency, the inductor is fabricated on chip by depositing a thin metal film in a spiral shape. Such IC inductors have small values (in the nanohenry range) and, unfortunately, small Q factors as well.
EXERCISE
D18.12 Design the cross-coupled oscillator to operate at ω0 = 10 Grad/s. The IC inductors available have L = 10 nH and Q = 10. If the transistor ro = 10 k, find the required value of C and the minimum required value of gm at which Q1 and Q2 are to be operated.
Ans. 1 pF; 1.1 mA/V
18.3.3 Crystal Oscillators
A piezoelectric crystal, such as quartz, exhibits electromechanical-resonance characteristics that are very stable (with time and temperature) and highly selective (having very high Q factors). The circuit symbol of a crystal is shown in Fig. 18.17(a), and its equivalent-circuit model is given in Fig. 18.17(b). The resonance properties are characterized by a large inductance L (as high as hundreds of henrys), a very small series capacitance Cs (as small as 0.0005 pF), a series resistance r representing a Q factor ω0L/r that can be as high as a few hundred thousand, and a parallel capacitance Cp (a few picofarads). Capacitor Cp represents the electrostatic capacitance between the two parallel plates of the crystal. Note that Cp ≫ Cs .
Since the Q factor is very high, we may neglect the resistance r and express the crystal
impedance as
1 Z(s) = 1 sCp + sL + 1/sCs
which can be manipulated to the form
1 s2 +(1/LCs)
Z(s)= sC s2 +C +C /LC C ppssp
(18.25)
From Eq. (18.25) and from Fig. 18.17(b), we see that the crystal has two resonance frequencies:
a series resonance at ωs
ωs =1/ LCs (18.26)
(a) (b) (c)
Figure18.17 Apiezoelectriccrystal.(a)Circuitsymbol.(b)Equivalentcircuit.(c)Crystalreactanceversus
frequency [note that, neglecting the small resistance r, Zcrystal = jX(ω)].
and a parallel resonance at ωp
Thus for s = jω we can write
CC
18.3 LC and Crystal Oscillators 1403
ωp =1
Z(jω)=−j
L
1
ω C p
s p Cs +Cp
ω2 −ω2s ω 2 − ω 2p
(18.27)
(18.28)
From Eqs.(18.26) and(18.27) we note that ωp>ωs. However, since Cp≫Cs, the two resonance frequencies are very close. Expressing Z(jω) = jX(ω), the crystal reactance X(ω) will have the shape shown in Fig. 18.17(c). We observe that the crystal reactance is inductive over the very narrow frequency band between ωs and ωp. For a given crystal, this frequency band is well defined. Thus we may use the crystal to replace the inductor of the Colpitts oscillator [Fig. 18.13(a)]. The resulting circuit will oscillate at the resonance frequency of the crystal inductance L with the series equivalent of Cs and (Cp +C1C2/(C1 +C2)). Since Cs is
much smaller than the three other capacitances, it will be dominant and
ω0 ≃ 1/ LCs = ωs (18.29)
In addition to the basic Colpitts oscillator, a variety of configurations exist for crystal oscillators. Figure 18.18 shows a popular configuration (called the Pierce oscillator) utilizing a CMOS inverter (see Section 14.3) as an amplifier. Resistor Rf determines a dc operating point in the high-gain region of the VTC of the CMOS inverter. Resistor R1 together with capacitor C1 provides a low-pass filter that discourages the circuit from oscillating at a higher harmonic of the crystal frequency. Note that this circuit also is based on the Colpitts configuration.
1404 Chapter 18
Signal Generators and Waveform-Shaping Circuits
Figure 18.18 A Pierce crystal oscillator utilizing a CMOS inverter as an amplifier.
The extremely stable resonance characteristics and the very high Q factors of quartz crystals result in oscillators with very accurate and stable frequencies. Crystals are available with resonance frequencies in the range of a few kilohertz to hundreds of megahertz. Temperature coefficients of ω0 of 1 or 2 parts per million (ppm) per degree Celsius are achievable. Unfortunately, however, crystal oscillators, being mechanical resonators, are fixed-frequency circuits.
EXERCISE
18.13 A 2-MHz quartz crystal is specified to have L = 0.52 H, Cs = 0.012 pF, Cp = 4 pF, and r = 120 . Find fs, fp, and Q.
Ans. 2.015 MHz; 2.018 MHz; 55,000
18.4 Bistable Multivibrators
In this section we begin the study of waveform-generating circuits of the other type—nonlinear oscillators or function generators. These devices make use of a special class of circuits known as multivibrators. As mentioned earlier, there are three types of multivibrator: bistable, monostable, and astable. This section is concerned with the first, the bistable multivibrator.4
As its name indicates, the bistable multivibrator has two stable states. The circuit can remain in either stable state indefinitely and moves to the other stable state only when appropriately triggered.
4 Digital implementations of multivibrators were presented in Chapter 16. Here, we are interested in implementations utilizing op amps.
18.4.1 The Feedback Loop
Bistability can be obtained by connecting a dc amplifier in a positive-feedback loop having a loop gain greater than unity. Such a feedback loop is shown in Fig. 18.19; it consists of an op amp and a resistive voltage divider in the positive-feedback path. To see how bistability is obtained, consider operation with the positive input terminal of the op amp near ground potential. This is a reasonable starting point, since the circuit has no external excitation. Assume that the electrical noise that is inevitably present in every electronic circuit causes a small positive increment in the voltage v+. This incremental signal will be amplified by the large open-loop gain A of the op amp, with the result that a much greater signal will appear in the op amp’s output voltage vO. The voltage divider (R1, R2) will feed a fraction β ≡ R1 /(R1 + R2 ) of the output signal back to the positive input terminal of the op amp. If Aβ is greater than unity, as is usually the case, the fed-back signal will be greater than the original increment in v+. This regenerative process continues until eventually the op amp saturates with its output voltage at the positive saturation level, L+. When this happens, the voltage at the positive input terminal, v + , becomes L+ R1 /(R1 + R2 ), which is positive and thus keeps the op amp in positive saturation. This is one of the two stable states of the circuit.
In the description above we assumed that when v+ was near zero volts, a positive increment occurred in v+. Had we assumed the equally probable situation of a negative increment, the op amp would have ended up saturated in the negative direction with vO =L− and v+ =L−R1/(R1 +R2). This is the other stable state.
We thus conclude that the circuit of Fig. 18.19 has two stable states, one with the op amp in positive saturation and the other with the op amp in negative saturation. The circuit can exist in either of these two states indefinitely. We also note that the circuit cannot exist in the state for which v + = 0 and v O = 0 for any length of time. This is a state of unstable equilibrium (also known as a metastable state); any disturbance, such as that caused by electrical noise, causes the bistable circuit to switch to one of its two stable states. This is in sharp contrast to the case when the feedback is negative, causing a virtual short circuit to appear between the op amp’s input terminals and maintaining this virtual short circuit in the face of disturbances. A physical analogy for the operation of the bistable circuit is depicted in Fig. 18.20.
18.4 Bistable Multivibrators 1405
Figure18.19 Apositive-feedbackloopcapableof bistable operation.
Figure 18.20 A physical analogy for the operation of the bistable circuit. The ball cannot remain at the top of the hill for any length of time (a state of unstable equilibrium or metastability); the inevitably present disturbance will cause the ball to fall to one side or the other, where it can remain indefinitely (the two stable states).
1406 Chapter 18
Signal Generators and Waveform-Shaping Circuits
18.4.2 Transfer Characteristic of the Bistable Circuit
The question naturally arises as to how we can make the bistable circuit of Fig. 18.19 change state. To help answer this crucial question, we derive the transfer characteristic of the bistable circuit. Reference to Fig. 18.19 indicates that either of the two nodes that are connected to ground can serve as an input terminal. We investigate both possibilities.
Figure18.21(a)showsthebistablecircuitwithavoltagevI appliedtotheinvertinginput terminal of the op amp. To derive the transfer characteristic vO–vI , assume that vO is at one of its two possible levels, say L+, and thus v+ =βL+. Now as vI is increased from 0 V, we can see from the circuit that nothing happens until vI reaches a value equal to v+ (i.e., βL+). As
R1R2 vO
v1
vI12
1 2
(a)
vO
L1
0 VTH vI
vO L1
L2
(b)
vO
0 VTH
(d)
L1
0
VTL
L2
vI
VTL
vI
L2
(c)
Figure 18.21 (a) The bistable circuit of Fig. 18.19 with the negative input terminal of the op amp disconnected from ground and connected to an input signal vI . (b) The transfer characteristic of the circuit in (a) for increasing vI . (c) The transfer characteristic for decreasing vI . (d) The complete transfer characteristics.
vI beginstoexceedthisvalue,anetnegativevoltagedevelopsbetweentheinputterminalsof the op amp. This voltage is amplified by the open-loop gain of the op amp, and thus vO goes negative. The voltage divider in turn causes v+ to go negative, thus increasing the net negative input to the op amp and keeping the regenerative process going. This process culminates in the op amp saturating in the negative direction: that is, with vO = L− and, correspondingly, v+ = βL−. It is easy to see that increasing vI further has no effect on the acquired state of the bistable circuit. Figure 18.21(b) shows the transfer characteristic for increasing vI . Observe that the characteristic is that of a comparator with a threshold voltage denoted VTH , where VTH =βL+.
Next consider what happens as v I is decreased. Since now v + = β L− , we see that the circuitremainsinthenegative-saturationstateuntilvI goesnegativetothepointthatitequals βL−. As vI goes below this value, a net positive voltage appears between the op amp’s input terminals. This voltage is amplified by the op-amp gain and thus gives rise to a positive voltage at the op amp’s output. The regenerative action of the positive-feedback loop then sets in and causes the circuit eventually to go to its positive saturation state, in which v O = L+ and v + = β L+ . The transfer characteristic for decreasing v I is shown in Fig. 18.21(c). Here again we observe that the characteristic is that of a comparator, but with a threshold voltage VTL =βL−.
The complete transfer characteristics, vO−vI , of the circuit in Fig. 18.21(a) can be obtained by combining the characteristic in Fig. 18.21(b) and (c), as shown in Fig. 18.21(d). As indicated, the circuit changes state at different values of v I , depending on whether v I is increasing or decreasing. Thus the circuit is said to exhibit hysteresis; the width of the hysteresis is the difference between the high threshold VTH and the low threshold VTL. Also note that the bistable circuit is in effect a comparator with hysteresis. As will be shown shortly, adding hysteresis to a comparator’s characteristics can be very beneficial in certain applications. Finally, observe that because the bistable circuit of Fig. 18.21 switches from the positive state (v O = L+ ) to the negative state (v O = L− ) as v I is increased past the positive threshold VTH , the circuit is said to be inverting. A bistable circuit with a noninverting transfer characteristic will be presented shortly.
18.4.3 Triggering the Bistable Circuit
Returning now to the question of how to make the bistable circuit change state, we observe from the transfer characteristics of Fig. 18.21(d) that if the circuit is in the L+ state it can be switched to the L− state by applying an input vI of value greater than VTH ≡ βL+. Such an input causes a net negative voltage to appear between the input terminals of the op amp, which initiates the regenerative cycle that culminates in the circuit switching to the L− stable state. HereitisimportanttonotethattheinputvI merelyinitiatesortriggersregeneration.Thuswe canremovevI withnoeffectontheregenerationprocess.Inotherwords,vI canbesimplya pulseofshortduration.TheinputsignalvI isthusreferredtoasatriggersignal,orsimplya trigger.
The characteristics of Fig. 18.21(d) indicate also that the bistable circuit can be switched to the positive state (vO =L+) by applying a negative trigger signal vI of magnitude greater than that of the negative threshold VTL .
18.4.4 The Bistable Circuit as a Memory Element
We observe from Fig. 18.21(d) that for input voltages in the range VTL < vI < VTH , the output can be either L+ or L−, depending on the state that the circuit is already in. Thus, for this input
18.4 Bistable Multivibrators 1407
1408 Chapter 18
Signal Generators and Waveform-Shaping Circuits
range, the output is determined by the previous value of the trigger signal (the trigger signal that caused the circuit to be in its current state). Thus the circuit exhibits memory. Indeed, the bistable multivibrator is the basic memory element of digital systems, as we have seen in Chapter 16. Finally, note that in analog-circuit applications, such as the ones of concern to us in this chapter, the bistable circuit is also known as a Schmitt trigger.
18.4.5 A Bistable Circuit with Noninverting Transfer Characteristic
The basic bistable feedback loop of Fig. 18.19 can be used to derive a circuit with noninverting transfer characteristic by applying the input signal vI (the trigger signal) to the terminal of R1 that is connected to ground. The resulting circuit is shown in Fig. 18.22(a). To obtain the transfer characteristic we first employ superposition to the linear circuit formed by R1 and R2, thus expressing v+ in terms of vI and vO as
v =v R2 +v R1 (18.30) + IR+R OR+R
From this equation we see that if the circuit is in the positive stable state with vO =L+, positive values for vI will have no effect. To trigger the circuit into the L− state, vI must be made negative and of such a value as to make v+ decrease below zero. Thus the low-threshold VTL can be found by substituting in Eq. (18.30) vO =L+, v+ =0, and vI =VTL. The result is
VTL =−L+(R1/R2) (18.31)
Similarly, Eq. (18.30) indicates that when the circuit is in the negative-output state (vO = L−), negative values of vI will make v+ more negative with no effect on operation. To initiate the regeneration process that causes the circuit to switch to the positive state, v+ must be made to
1212
vO
VTL 0 VTH vI
L
(b)
Figure 18.22 (a) A bistable circuit derived from the positive-feedback loop of Fig. 18.19 by applying vI through R1. (b) The transfer characteristic of the circuit in (a) is noninverting. [Compare it to the inverting characteristic in Fig. 18.21(d).]
L
R1
R2
vI
v
vO
(a)
18.4 Bistable Multivibrators 1409 go slightly positive. The value of vI that causes this to happen is the high-threshold voltage
VTH , which can be found by substituting in Eq. (18.30) vO = L− and v+ = 0. The result is VTH =−L−(R1/R2) (18.32)
The complete transfer characteristic of the circuit of Fig. 18.22(a) is displayed in Fig. 18.22(b). Observe that a positive triggering signal vI (of value greater than VTH ) causes the circuit to switch to the positive state (vO goes from L− to L+). Thus the transfer characteristic of this circuit is noninverting.
18.4.6 Application of the Bistable Circuit as a Comparator
The comparator is an analog-circuit building block that is used in a variety of applications ranging from detecting the level of an input signal relative to a preset threshold value to the design of analog-to-digital (A/D) converters. Although one normally thinks of the comparator as having a single threshold value [see Fig. 18.23(a)], it is useful in many applications to add hysteresis to the comparator characteristic. If this is done, the comparator
(a)
Figure 18.23 (a) Block diagram representation and transfer characteristic for a comparator having a reference, or threshold, voltage VR . (b) Comparator characteristic with hysteresis.
1410 Chapter 18
Signal Generators and Waveform-Shaping Circuits
VTH
VR 0 VTL
t
Signal corrupted with interference
Multiple zero crossings
Figure 18.24 Illustrating the use of hysteresis in the comparator characteristic as a means of rejecting interference.
exhibitstwothresholdvalues,VTL andVTH,symmetricallyplacedaboutthedesiredreference level, as indicated in Fig. 18.23(b). Usually VTH and VTL are separated by a small amount, say 100 mV.
To demonstrate the need for hysteresis, we consider a common application of comparators. It is required to design a circuit that detects and counts the zero crossings of an arbitrary waveform. Such a function can be implemented using a comparator whose threshold is set to 0 V. The comparator provides a step change at its output every time a zero crossing occurs. Each step change can be used to generate a pulse, and the pulses are fed to a counter circuit.
Imagine now what happens if the signal being processed has—as it usually does have—interference superimposed on it, say of a frequency much higher than that of the signal. It follows that the signal might cross the zero axis a number of times around each of the zero-crossing points we are trying to detect, as shown in Fig. 18.24. The comparator would thus change state a number of times at each of the zero crossings, and our count would obviously be in error. However, if we have an idea of the expected peak-to-peak amplitude of the interference, the problem can be solved by introducing hysteresis of appropriate width in the comparator characteristics. Then, if the input signal is increasing in magnitude, the comparator with hysteresis will remain in the low state until the input level exceeds the high threshold VTH . Subsequently the comparator will remain in the high state even if, owing to interference, the signal decreases below VTH . The comparator will switch to the low state only if the input signal is decreased below the low threshold VTL . The situation is illustrated
18.4 Bistable Multivibrators 1411 R2
R2
R1
vI R
R1
vI R
vO
D13 D1 Z
D12 D14
vO Z1
Z2
(a)
(b)
Figure 18.25 Limiter circuits are used to obtain more precise output levels for the bistable circuit. In both circuits the value of R should be chosen to yield the current required for the proper operation of the zener diodes. (a) For this circuit L+ = VZ1 + VD and L− = −(VZ2 + VD ), where VD is the forward diode drop. (b) For this circuit L+ =VZ +VD1 +VD2 and L− =−(VZ +VD3 +VD4).
in Fig. 18.24, from which we see that including hysteresis in the comparator characteristic provides an effective means for rejecting interference (thus providing another form of filtering).
18.4.7 Making the Output Levels More Precise
The output levels of the bistable circuit can be made more precise than the saturation voltages of the op amp are by cascading the op amp with a limiter circuit (see Section 4.6 for a discussion of limiter circuits). Two such arrangements are shown in Fig. 18.25.
EXERCISES
D18.14 TheopampinthebistablecircuitofFig.18.21(a)hasoutputsaturationvoltagesof±13V.Design the circuit to obtain threshold voltages of ±5 V. For R1 = 10 k, find the value required for R2 . Ans. 16 k
D18.15 IftheopampinthecircuitofFig.18.22(a)has±10-Voutputsaturationlevels,designthecircuit to obtain ±5-V thresholds. Give suitable component values.
Ans. Possible choice: R1 = 10 k and R2 = 20 k
18.16 Consider a bistable circuit with a noninverting transfer characteristic and let L+ = −L− = 10 V and VTH = −VTL = 5 V. If vI is a triangular wave with a 0-V average, a 10-V peak amplitude, and a 1-ms period, sketch the waveform of vO. Find the time interval between the zero crossings of vI and vO.
Ans. vO is a square wave with 0-V average, 10-V amplitude, and 1-ms period and is delayed by 125 μs relative to vI
1412 Chapter 18 Signal Generators and Waveform-Shaping Circuits
18.17 Consider an op amp having saturation levels of ±12 V used without feedback, with the inverting input terminal connected to +3 V and the noninverting input terminal connected to vI . Characterize its operation as a comparator. What are L+, L−, and VR, as defined in Fig. 18.23(a)?
Ans. +12 V; –12 V; +3 V
18.18 In the circuit of Fig. 18.22(a), let L+ =−L− =10 V and R1 =1 k. Find a value for R2 that gives a hysteresis of 100-mV width.
Ans. 200 k
VTL 0
v2
L
v1 VTH
L
C
R
VTH L VTL L
18.5 Generation of Square and Triangular Waveforms Using Astable Multivibrators
A square waveform can be generated by arranging for a bistable multivibrator to switch states periodically. This can be done by connecting the bistable multivibrator with an RC circuit in a feedback loop, as shown in Fig. 18.26(a). Observe that the bistable multivibrator has an inverting transfer characteristic and can thus be realized using the circuit of Fig. 18.21(a). This results in the circuit of Fig. 18.26(b). We shall show shortly that this circuit has no stable states and thus is appropriately named an astable multivibrator.
At this point we wish to remind the reader of an important relationship, which we shall employ on many occasions in the following few sections: A capacitor C that is charging or
v1 v2
L
tt L
(a)
Figure 18.26 (a) Connecting a bistable multivibrator with inverting transfer characteristics in a feedback loop with an RC circuit results in a square-wave generator.
18.5 Generation of Square and Triangular Waveforms Using Astable Multivibrators 1413
(b)
(c)
Figure 18.26 continued (b) The circuit obtained when the bistable multivibrator is implemented with the circuit of Fig. 18.21(a). (c) Waveforms at various nodes of the circuit in (b). This circuit is called an astable multivibrator.
discharging through a resistance R toward a final voltage V∞ has a voltage v(t), v(t)=V −V −V e−t/τ
∞ ∞ 0+
where V0+ is the voltage at t = 0+ and τ = CR is the time constant.
18.5.1 Operation of the Astable Multivibrator
To see how the astable multivibrator operates, refer to Fig. 18.26(b) and let the output of the bistable multivibrator be at one of its two possible levels, say L+. Capacitor C will charge toward this level through resistor R. Thus the voltage across C, which is applied to the negative input terminal of the op amp and thus is denoted v−, will rise exponentially toward L+ with a time constant τ = CR. Meanwhile, the voltage at the positive input terminal
1414 Chapter 18
Signal Generators and Waveform-Shaping Circuits
of the op amp is v+ =βL+. This situation will continue until the capacitor voltage reaches the positive threshold VTH = βL+, at which point the bistable multivibrator will switch to the other stable state, in which vO = L− and v+ = βL−. The capacitor will then start discharging, and its voltage, v−, will decrease exponentially toward L−. This new state will prevail until v − reaches the negative threshold VTL = β L− , at which time the bistable multivibrator switches to the positive-output state, the capacitor begins to charge, and the cycle repeats itself.
From the preceding description we see that the astable circuit oscillates and produces a square waveform at the output of the op amp. This waveform, and the waveforms at the two input terminals of the op amp, are displayed in Fig. 18.26(c). The period T of the square wave can be found as follows: During the charging interval T1 the voltage v− across the capacitor at any time t, with t = 0 at the beginning of T1, is given by (see Appendix E)
v =L −L −βL e−t/τ −++−
where τ = CR. Substituting v− = βL+ at t = T1 gives
v =L −L −βL e−t/τ −−−+
T1 =τln1−β L−/L+ 1−β
(18.33) Similarly, during the discharge interval T2 the voltage v− at any time t, with t = 0 at the
beginning of T2, is given by
Substituting v− = βL− at t = T2 gives
T2 =τln1−β L+/L−
(18.34) Equations (18.33) and (18.34) can be combined to obtain the period T = T1 + T2 . Normally,
1−β
L+ = −L− , resulting in symmetrical square waves of period T given by
T =2τln1+β (18.35) 1−β
Note that this square-wave generator can be made to have variable frequency by switching different capacitors C (usually in decades) and by continuously adjusting R (to obtain continuous frequency control within each decade of frequency). Also, the waveform across C can be made almost triangular by using a small value for the parameter β. However, triangular waveforms of superior linearity can be easily generated using the scheme discussed next.
Before leaving this section, however, note that although the astable circuit has no stable states, it has two quasi-stable states and remains in each for a time interval determined by the time constant of the RC network and the thresholds of the bistable multivibrator.
18.5 Generation of Square and Triangular Waveforms Using Astable Multivibrators 1415
EXERCISES
18.19
18.20
For the circuit in Fig. 18.26(b), let the op-amp saturation voltages be ±10 V, R1 = 100 k, R2 = R = 1 M, and C = 0.01 μF. Find the frequency of oscillation.
Ans. 274 Hz
Consider a modification of the circuit of Fig. 18.26(b) in which R1 is replaced by a pair of diodes connected in parallel in opposite directions. For L+ = −L− = 12 V, R2 = R = 10 k, C = 0.1 μF, and the diode voltage as a constant denoted VD, find an expression for frequency as a function of VD . If VD = 0.70 V at 25°C with a TC of –2 mV/°C, find the frequency at 0°C, 25°C, 50°C, and 100°C. Note that the output of this circuit can be sent to a remotely connected frequency meter to provide a digital readout of temperature.
Ans. f = 500/ln[(12 + VD )/(12 − VD )] Hz; 3995 Hz, 4281 Hz, 4611 Hz, 5451 Hz
18.5.2 Generation of Triangular Waveforms
The exponential waveforms generated in the astable circuit of Fig. 18.24 can be changed to triangular by replacing the low-pass RC circuit with an integrator. (The integrator is, after all, a low-pass circuit with a corner frequency at dc.) The integrator causes linear charging and discharging of the capacitor, thus providing a triangular waveform. The resulting circuit is shown in Fig. 18.27(a). Observe that because the integrator is inverting, it is necessary to invert the characteristics of the bistable circuit. Thus the bistable circuit required here is of the noninverting type and can be implemented using the circuit of Fig. 18.22(a).
We now proceed to show how the feedback loop of Fig. 18.27(a) oscillates and generates
a triangular waveform v1 at the output of the integrator and a square waveform v2 at the output
of the bistable circuit: Let the output of the bistable circuit be at L+. A current equal to L+/R
will flow into the resistor R and through capacitor C, causing the output of the integrator to
linearly decrease with a slope of −L+/CR, as shown in Fig. 18.27(c). This will continue until
the integrator output reaches the lower threshold VTL of the bistable circuit, at which point
the bistable circuit will switch states, its output becoming negative and equal to L−. At this
moment the current through R and C will reverse direction, and its value will become equal to
L /R. It follows that the integrator output will start to increase linearly with a positive slope −
equal to L− /CR. This will continue until the integrator output voltage reaches the positive threshold of the bistable circuit, VTH . At this point the bistable circuit switches, its output becomes positive (L+), the current into the integrator reverses direction, and the output of the integrator starts to decrease linearly, beginning a new cycle.
From the discussion above, it is relatively easy to derive an expression for the period T of the square and triangular waveforms. During the interval T1 we have, from Fig. 18.27(c),
from which we obtain
VTH −VTL = L+ T1 CR
T1 =CRVTH −VTL (18.36) L+
1416 Chapter 18
Signal Generators and Waveform-Shaping Circuits
v1
C
v1 v2
v2
VTL
v1 L
v2
L
(a)
(b)
(c)
Figure 18.27 A general scheme for generating triangular and square waveforms.
Similarly, during T2 we have
from which we obtain
(18.37) Thus to obtain symmetrical square waves we design the bistable circuit to have L+ = −L− .
VTH−VTL =−L− T2 CR
VTH
T2 =CRVTH −VTL −L−
EXERCISE
D18.21 ConsiderthecircuitofFig.18.27(a)withthebistablecircuitrealizedbythecircuitinFig.18.22(a). If the op amps have saturation voltages of ±10 V, and if a capacitor C = 0.01 μF and a resistor R1 = 10 k are used, find the values of R and R2 (note that R1 and R2 are associated with the bistable circuit of Fig. 18.22a) such that the frequency of oscillation is 1 kHz and the triangular waveform has a 10-V peak-to-peak amplitude.
Ans. 50 k; 20 k
18.6 Generation of a Standardized Pulse: The Monostable Multivibrator 1417 18.6 Generation of a Standardized
Pulse: The Monostable Multivibrator
In some applications the need arises for a pulse of known height and width generated in response to a trigger signal. Because the width of the pulse is predictable, its trailing edge can be used for timing purposes—that is, to initiate a particular task at a specified time. Such a standardized pulse can be generated by the third type of multivibrator, the monostable multivibrator.
The monostable multivibrator has one stable state in which it can remain indefinitely. It also has a quasi-stable state to which it can be triggered and in which it stays for a predetermined interval equal to the desired width of the output pulse. When this interval expires, the monostable multivibrator returns to its stable state and remains there, awaiting another triggering signal. The action of the monostable multivibrator has given rise to its alternative name, the one-shot.
Figure 18.28(a) shows an op-amp monostable circuit. We observe that this circuit is an augmented form of the astable circuit of Fig. 18.26(b). Specifically, a clamping diode D1 is added across the capacitor C1, and a trigger circuit composed of capacitor C2, resistor R4, and diode D2 is connected to the noninverting input terminal of the op amp. The circuit operates as follows: In the stable state, which prevails in the absence of the triggering signal, the output of the op amp is at L+ and diode D1 is conducting through R3 and thus clamping the voltage vB to one diode drop above ground. We select R4 much larger than R1, so that diode D2 will beconductingaverysmallcurrentandthevoltagevC willbeverycloselydeterminedbythe
vE (L VD2)
D12
C B
(a)
A
Dt 1
Figure 18.28 (a) An op-amp monostable circuit. (b) Signal waveforms in the circuit of (a).
(b)
1418 Chapter 18
Signal Generators and Waveform-Shaping Circuits
voltagedividerR1,R2.ThusvC =βL+,whereβ=R1/(R1 +R2).Thestablestateismaintained because βL+ is greater than VD1.
Now consider the application of a negative-going step at the trigger input and refer to the signal waveforms shown in Fig. 18.28(b). The negative triggering edge is coupled to the cathode of diode D2 via capacitor C2, and thus D2 conducts heavily and pulls node C down. If the trigger signal is of sufficient height to cause vC to go below vB, the op amp will see a net negative input voltage and its output will switch to L−. This in turn will cause vC to go negative to βL−, keeping the op amp in its newly acquired state. Note that D2 will then cut off, thus isolating the circuit from any further changes at the trigger input terminal.
The negative voltage at A causes D1 to cut off, and C1 begins to discharge exponentially toward L− with a time constant C1R3. The monostable multivibrator is now in its quasi-stable state, which will prevail until the declining vB goes below the voltage at node C, which is βL−. At this instant the op-amp output switches back to L+ and the voltage at node C goes back to βL+. Capacitor C1 then charges toward L+ until diode D1 turns on and the circuit returns to its stable state.
From Fig. 18.28(b), we observe that a negative pulse is generated at the output during the quasi-stable state. The duration T of the output pulse is determined from the exponential waveform of vB,
by substituting vB(T) = βL−, which yields
v (t)=L −L −V e−t/C1R3 B − − D1
βL =L −L −V e−T/C1R3 − − − D1
V−L T=C1R3 ln D1 − βL− −L−
For V ≪ L , this equation can be approximated by D1 −
1 T≃C1R3 ln 1−β
(18.38)
(18.39)
Finally, note that the monostable circuit should not be triggered again until capacitor C1 has been recharged to VD1; otherwise the resulting output pulse will be shorter than normal. This recharging time is known as the recovery period. Circuit techniques exist for shortening the recovery period.
EXERCISE
18.22 For the monostable circuit of Fig. 18.28(a), find the value of R3 that will result in a 100-μs output pulseforC1 =0.1μF,β=0.1,VD =0.7V,andL+ =−L− =12V.
Ans. 6171
18.7 Integrated-Circuit Timers
Commercially available integrated-circuit packages exist that contain the bulk of the circuitry needed to implement monostable and astable multivibrators with precise characteristics. In this section we discuss the most popular of such ICs, the 555 timer. Introduced in 1972 by the Signetics Corporation as a bipolar integrated circuit, the 555 is also available in CMOS technology and from a number of manufacturers.5
18.7.1 The 555 Circuit
Figure 18.29 shows a block diagram representation of the 555 timer circuit (for the actual
circuit, refer to Grebene, 1984). The circuit consists of two comparators, an SR flip-flop, and
a transistor Q1 that operates as a switch. One power supply (VCC ) is required for operation,
with the supply voltage typically 5 V. A resistive voltage divider, consisting of the three
equal-valued resistors labeled R1, is connected across VCC and establishes the reference
(threshold) voltages for the two comparators. These are VTH = 2 VCC for comparator 1 and
VTL = 1 VCC for comparator 2. 3
3
18.7 Integrated-Circuit Timers 1419
We studied SR flip-flops in Chapter 16. For our purposes here we note that an SR flip-flop is a bistable circuit having complementary outputs, denoted Q and Q. In the set state, the output at Q is “high” (approximately equal to VCC ) and that at Q is “low” (approximately equal to 0 V). In the other stable state, termed the reset state, the output at Q is low and that at Q is
VCC
R1
R1
Comparator 2
R1
Comparator 1
VTH
VTL
100 Q1
RQ
Flip-flop
SQ
Threshold
Trigger
Discharge
Out
Ground
Figure 18.29 A block diagram representation of the internal circuit of the 555 integrated-circuit timer.
5In a recent article in IEEE Spectrum (May 2009), the 555 was selected as one of the “25 Microchips That Shook the World.”
1420 Chapter 18
Signal Generators and Waveform-Shaping Circuits
high. The flip-flop is set by applying a high level (VCC ) to its set input terminal, labeled S. To reset the flip-flop, a high level is applied to the reset input terminal, labeled R. Note that the reset and set input terminals of the flip-flop in the 555 circuit are connected to the outputs of comparator 1 and comparator 2, respectively.
The positive-input terminal of comparator 1 is brought out to an external terminal of the 555 package, labeled Threshold. Similarly, the negative-input terminal of comparator 2 is connected to an external terminal labeled Trigger, and the collector of transistor Q1 is connected to a terminal labeled Discharge. Finally, the Q output of the flip-flop is connected to the output terminal of the timer package, labeled Out.
18.7.2 Implementing a Monostable Multivibrator Using the 555 IC
Figure 18.30(a) shows a monostable multivibrator implemented using the 555 IC together with an external resistor R and an external capacitor C. In the stable state the flip-flop will be in the reset state, and thus its Q output will be high, turning on transistor Q1. Transistor Q1 will be saturated, and thus vC will be close to 0 V, resulting in a low level at the output of comparator 1. The voltage at the trigger input terminal, labeled vtrigger, is kept high (greater than VTL), and thus the output of comparator 2 also will be low. Finally, note that since the flip-flop is in the reset state, Q will be low and thus vO will be close to 0 V.
To trigger the monostable multivibrator, a negative input pulse is applied to the trigger inputterminal.Asvtrigger goesbelowVTL,theoutputofcomparator2goestothehighlevel,thus setting the flip-flop. Output Q of the flip-flop goes high, and thus vO goes high, and output Q goes low, turning off transistor Q1. Capacitor C now begins to charge up through resistor R, anditsvoltagevC risesexponentiallytowardVCC,asshowninFig.18.30(b).Themonostable multivibrator is now in its quasi-stable state. This state prevails until vC reaches and begins to exceed the threshold of comparator 1, VTH , at which time the output of comparator 1 goes high, resetting the flip-flop. Output Q of the flip-flop now goes high and turns on transistor Q1. In turn, transistor Q1 rapidly discharges capacitor C, causing vC to go to 0 V. Also, when the flip-flop is reset, its Q output goes low, and thus vO goes back to 0 V. The monostable multivibrator is now back in its stable state and is ready to receive a new triggering pulse.
From the description above we see that the monostable multivibrator produces an output pulse vO as indicated in Fig. 18.30(b). The width of the pulse, T, is the time interval that the monostable multivibrator spends in the quasi-stable state; it can be determined by reference to the waveforms in Fig. 18.30(b) as follows: Denoting the instant at which the trigger pulse isappliedast=0,theexponentialwaveformofvC canbeexpressedas
v =V 1−e−t/CR C CC
Substituting vC = VTH = 2 VCC at t = T gives 3
T = CR ln 3 ≃ 1.1CR
Thus the pulse width is determined by the external components C and R, which can be selected
to have values as precise as desired.
18.7.3 An Astable Multivibrator Using the 555 IC
Figure 18.31(a) shows the circuit of an astable multivibrator employing a 555 IC, two external resistors, RA and RB, and an external capacitor C. To see how the circuit operates, refer to the
(18.40)
(18.41)
VCC
18.7 Integrated-Circuit Timers 1421
R
vC
C
vO
R1
R1
Comparator 2
R1
Comparator 1
VTH VTL
100 Q1
RQ
Flip-flop
SQ
vtrigger
0
0
vO
0
vtrigger
VTL
to VCC VTH
VCC
(a)
vC
t
t
t
T
T
(b)
Figure 18.30 (a) The 555 timer connected to implement a monostable multivibrator. (b) Waveforms of the circuit in (a).
1422 Chapter 18
Signal Generators and Waveform-Shaping Circuits
VCC
RA
RB vC
C
vO
R1
R1
Comparator 2
R1
Comparator 1
VTH VTL
100 Q1
RQ
Flip-flop
SQ
vC
vO VCC
VCC
VTH
VTL
t
t
(a)
TH
TL
(b)
Figure 18.31 (a) The 555 timer connected to implement an astable multivibrator. (b) Waveforms of the circuit in (a).
waveforms depicted in Fig. 18.31(b). Assume that initially C is discharged and the flip-flop is set. Thus vO is high and Q1 is off. Capacitor C will charge up through the series combination of RA and RB, and the voltage across it, vC, will rise exponentially toward VCC. As vC crosses the level equal to VTL, the output of comparator 2 goes low. This, however, has no effect on the circuit operation, and the flip-flop remains set. Indeed, this state continues until vC reaches and begins to exceed the threshold of comparator 1, VTH . At this instant of time, the output of comparator 1 goes high and resets the flip-flop. Thus vO goes low, Q goes high, and transistor Q1 is turned on. The saturated transistor Q1 causes a voltage of approximately zero volts to appear at the common node of RA and RB. Thus C begins to discharge through RB and the collector of Q1. The voltage vC decreases exponentially with a time constant CRB toward0V.WhenvC reachesthethresholdofcomparator2,VTL,theoutputofcomparator2, goes high and sets the flip-flop. The output vO then goes high, and Q goes low, turning off Q1. Capacitor C begins to charge through the series equivalent of RA and RB, and its voltage rises exponentially toward VCC with a time constant C(RA +RB). This rise continues until vC reaches VTH , at which time the output of comparator 1 goes high, resetting the flip-flop, and the cycle continues.
From the description above we see that the circuit of Fig. 18.31(a) oscillates and produces a square waveform at the output. The frequency of oscillation can be determined as follows. Reference to Fig. 18.31(b) indicates that the output will be high during the interval TH , in whichvC risesfromVTL toVTH.TheexponentialriseofvC canbedescribedby
vC =VCC −(VCC −VTL)e−t/C(RA+RB) (18.42) where t = 0 is the instant at which the interval TH begins. Substituting vC = VTH = 2 VCC at
18.7 Integrated-Circuit Timers 1423
t=TH andVTL = 1VCC resultsin 3
3
TH =C(RA +RB)ln2≃0.69C(RA +RB) (18.43) We also note from Fig. 18.31(b) that vO will be low during the interval TL, in which vC falls
towardzero,fromVTH toVTL.TheexponentialfallofvC canbedescribedby
vC =VTHe−t/CRB (18.44)
where we have taken t = 0 as the beginning of the interval TL. Substituting vC = VTL = 1 VCC
att=TL andVTH = 2VCC resultsin 3
3
TL = CRB ln 2 ≃ 0.69 CRB (18.45) Equations (18.43) and (18.45) can be combined to obtain the period T of the output square
wave as
T =TH +TL =0.69C(RA +2RB) (18.46) Also, the duty cycle of the output square wave can be found from Eqs. (18.43) and (18.45):
Dutycycle≡ TH = RA+RB (18.47) TH +TL RA +2RB
Notethatthedutycyclewillalwaysbegreaterthan0.5(50%);itapproaches0.5ifRA isselected to be much smaller than RB (unfortunately, at the expense of increased supply current).
1424 Chapter 18 Signal Generators and Waveform-Shaping Circuits
EXERCISES
D18.23 Using a 10-nF capacitor C, find the value of R that yields an output pulse of 100 μs in the monostable circuit of Fig. 18.30(a).
Ans. 9.1 k
D18.24 For the circuit in Fig. 18.31(a), with a 1-nF capacitor, find the values of RA and RB that result in
an oscillation frequency of 100 kHz and a duty cycle of 75%. Ans. 7.2 k, 3.6 k
18.8 Nonlinear Waveform-Shaping Circuits
Diodes or transistors can be combined with resistors to synthesize two-port networks having arbitrary nonlinear transfer characteristics. Such two-port networks can be employed in waveform shaping—that is, changing the waveform of an input signal in a prescribed manner to produce a waveform of a desired shape at the output. In this section we illustrate this application by a concrete example: the sine-wave shaper. This is a circuit whose purpose is to change the waveform of an input triangular-wave signal to a sine wave. Though simple, the sine-wave shaper is a practical building block used extensively in function generators. This method of generating sine waves should be contrasted to that using linear oscillators (Sections 18.1–18.3). Although linear oscillators produce sine waves of high purity, they are not convenient at very low frequencies. Also, linear oscillators are in general more difficult to tune over wide frequency ranges. In the following we discuss two distinctly different techniques for designing sine-wave shapers.
18.8.1 The Breakpoint Method
In the breakpoint method the desired nonlinear transfer characteristic (in our case the sine function shown in Fig. 18.32) is implemented as a piecewise linear curve. Diodes are utilized as switches that turn on at the various breakpoints of the transfer characteristic, thus switching into the circuit additional resistors that cause the transfer characteristic to change slope.
Consider the circuit shown in Fig. 18.33(a). It consists of a chain of resistors connected across the entire symmetrical voltage supply +V, −V. The purpose of this voltage divider is to generate reference voltages that will serve to determine the breakpoints in the transfer characteristic. In our example these reference voltages are denoted +V2 , +V1 , −V1 , −V2 . Note that the entire circuit is symmetrical, driven by a symmetrical triangular wave and generating a symmetrical sine-wave output. The circuit approximates each quarter-cycle of the sine wave by three straight-line segments; the breakpoints between these segments are determined by the reference voltages V1 and V2.
The circuit works as follows: Let the input be the triangular wave shown in Fig. 18.33(b), and consider first the quarter-cycle defined by the two points labeled 0 and 1. When the input signal is less in magnitude than V1, none of the diodes conducts. Thus zero current flows through R4, and the output voltage at B will be equal to the input voltage. But as the input
vO
18.8 Nonlinear Waveform-Shaping Circuits 1425
vI 0 T T 2
t
Figure 18.32 Using a nonlinear (sinusoidal) transfer characteristic to shape a triangular waveform into a sinusoid.
D1 D12
D13 D14
(a)
(b)
0
Figure 18.33 (a) A three-segment sine-wave shaper. (b) The input triangular waveform and the output approximately sinusoidal waveform.
0TT 2
t
1426 Chapter 18
Signal Generators and Waveform-Shaping Circuits
rises to V1 and above, D2 (assumed ideal) begins to conduct. Assuming that the conducting D2 behaves as a short circuit, we see that, for vI > V1,
vO=V1+(vI−V1) R5 R4 +R5
This implies that as the input continues to rise above V1 , the output follows, but with a reduced slope. This gives rise to the second segment in the output waveform, as shown in Fig. 18.33(b). Note that in developing the equation above we have assumed that the resistances in the voltage divider are low enough in value to cause the voltages V1 and V2 to be constant independent of the current coming from the input.
Next consider what happens as the voltage at point B reaches the second breakpoint determined by V2. At this point, D1 conducts, thus limiting the output vO to V2 (plus, of course, the voltage drop across D1 if it is not assumed to be ideal). This gives rise to the third segment, which is flat, in the output waveform. The overall result is to “bend” the waveform and shape it into an approximation of the first quarter-cycle of a sine wave. Then, beyond the peak of the input triangular wave, as the input voltage decreases, the process unfolds, the output becoming progressively more like the input. Finally, when the input goes sufficiently negative, the process begins to repeat at –V1 and –V2 for the negative half-cycle.
Although the circuit is relatively simple, its performance is surprisingly good. A measure of goodness usually taken is to quantify the purity of the output sine wave by specifying the percentage total harmonic distortion (THD). This is the percentage ratio of the rms voltage of all harmonic components above the fundamental frequency (which is the frequency of the triangular wave) to the rms voltage of the fundamental (see also Chapter 12). Interestingly, one reason for the good performance of the diode shaper is the beneficial effects produced by the nonideal i–v characteristics of the diodes—that is, the exponential knee of the junction diode as it goes into forward conduction. The consequence is a relatively smooth transition from one line segment to the next.
Practical implementations of the breakpoint sine-wave shaper employ six to eight segments (compared with the three used in the example above). Also, transistors are usually employed to provide more versatility in the design, with the goal being increased precision and lower THD (see Grebene, 1984, pages 592–595).
18.8.2 The Nonlinear-Amplification Method
The other method we discuss for the conversion of a triangular wave into a sine wave is based on feeding the triangular wave to the input of an amplifier having a nonlinear transfer characteristic that approximates the sine function. One such amplifier circuit consists of a differential pair with a resistance connected between the two emitters, as shown in Fig. 18.34. With appropriate choice of the values of the bias current I and the resistance R, the differential amplifier can be made to have a transfer characteristic that closely approximates that shown inFig.18.32.ObservethatforsmallvI thetransfercharacteristicofthecircuitofFig.18.34is almostlinear,asasinewaveformisnearitszerocrossings.AtlargevaluesofvI thenonlinear characteristics of the BJTs reduce the gain of the amplifier and cause the transfer characteristic to bend, approximating the sine wave as it approaches its peak. (More details on this circuit can be found in Grebene, 1984, pages 595–597.)
18.8 Nonlinear Waveform-Shaping Circuits 1427
Figure 18.34 A differential pair with an emitter-degeneration resistance used to imple- ment a triangular-wave to sine-wave converter. Operation of the circuit can be graphically described by Fig. 18.32.
EXERCISES
D18.25 The circuit in Fig. E18.25 is required to provide a three-segment approximation to the nonlinear i–v characteristic, i = 0.1v2, where v is the voltage in volts and i is the current in milliamperes. Find the values of R1, R2, and R3 such that the approximation is perfect at v = 2 V, 4 V, and 8 V. Calculate the error in current value at v = 3 V, 5 V, 7 V, and 10 V. Assume ideal diodes.
i
R2 R3
v R1
3V 7V Figure E18.25
Ans. 5 k, 1.25 k, 1.25 k; −0.3 mA, +0.1 mA, −0.3 mA, 0
18.26 A detailed analysis of the circuit in Fig. 18.34 shows that its optimum performance occurs when
the values of I and R are selected so that RI = 2.5VT , where VT is the thermal voltage. For this design, the peak amplitude of the input triangular wave should be 6.6VT , and the corresponding sine wave across R has a peak value of 2.42VT. For I =0.25mA and RC =10 k, find the peak amplitude of the sine-wave output vO. Assume α ≃ 1.
Ans. 4.84 V
1428 Chapter 18 Signal Generators and Waveform-Shaping Circuits Summary
There are two distinctly different types of signal gener- ator: the linear oscillator, which utilizes some form of resonance, and the nonlinear oscillator or function gener- ator, which employs a switching mechanism implemented with a multivibrator circuit.
A linear oscillator can be realized by placing a frequency-selective network in the feedback path of an amplifier (an op amp or a transistor). The circuit will oscil- late at the frequency at which the total phase shift around the loop is zero or 360°, provided the magnitude of loop gain at this frequency is equal to, or greater than, unity.
If in an oscillator the magnitude of loop gain is greater than unity, the amplitude will increase until a nonlinear amplitude-control mechanism is activated.
The Wien-bridge oscillator, the phase-shift oscillator, the quadrature oscillator, and the active-filter-tuned oscillator are popular configurations for frequencies up to about 1 MHz. These circuits employ RC networks together with op amps or transistors. For higher frequencies, LC-tuned or crystal-tuned oscillators are utilized. Popular configurations include the Colpitts circuit for discrete-circuit implementation and the cross-coupled circuit for IC implementation at frequencies as high as hundreds of gigahertz.
Crystal oscillators provide the highest possible frequency accuracy and stability.
There are three types of multivibrator: bistable, monostable, and astable. Op-amp circuit implementations
PROBLEMS
Section 18.1: Basic Principles of Sinusoidal Oscillators
18.1 Consider a sinusoidal oscillator consisting of an ampli- fier having a frequency-independent gain A (where A is posi- tive) and a second-order bandpass filter with a pole frequency ω0, a pole Q denoted Q, and a positive center-frequency gain K. Find the frequency of oscillation, and the condition that A and K must satisfy for sustained oscillation.
18.2 For the oscillator circuit described in Problem 18.1: (a) Derive an expression for dφ/dω, evaluated at ω = ω0.
of multivibrators are useful in analog-circuit applications that require high precision.
The bistable multivibrator has two stable states and can remain in either state indefinitely. It changes state when triggered. A comparator with hysteresis is bistable.
A monostable multivibrator, also known as a one-shot, has one stable state, in which it can remain indefinitely. When triggered, it goes into a quasi-stable state in which it remains for a predetermined interval, thus generating, at its output, a pulse of known width.
An astable multivibrator has no stable state. It oscillates between two quasi-stable states, remaining in each for a predetermined interval. It thus generates a periodic waveform at the output.
A feedback loop consisting of an integrator and a bistable multivibrator can be used to generate triangular and square waveforms.
The 555 timer, a commercially available IC, can be used with external resistors and a capacitor to implement high-quality monostable and astable multivibrators.
A sine waveform can be generated by feeding a triangular waveform to a sine-wave shaper. A sine-wave shaper can be implemented either by using diodes (or transistors) and resistors, or by using an amplifier having a nonlinear transfer characteristic that approximates the sine function.
(b) Use the result of (a) to find an expression for the per-unit change in frequency of oscillation resulting from a phase-angle change of φ, in the amplifier transfer function.
d−1 1dy Hint:dx tan y =1+y2 dx
18.3 FortheoscillatordescribedinProblem18.1,showthat, independent of the value of A and K, the poles of the circuit
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
Problems 1429
CHAPTER 18 PROBLEMS
lie at a radial distance of ω0. Find the value of AK that results in poles appearing (a) on the jω axis, and (b) in the right half of the s plane, at a horizontal distance from the jω axis of ω0 /(2Q).
D 18.4 For the oscillator circuit in Fig. 18.3(a) find the percentage change in the oscillation frequency resulting from a change of +1% in the value of (a) L, (b) C, and (c) R.
18.5 An oscillator is formed by loading a transconductance amplifier having a positive gain with a parallel RLC circuit and connecting the output directly to the input (thus applying positive feedback with a factor β = 1). Let the transconduc- tance amplifier have an input resistance of 5 k and an output resistance of 5 k. The LC resonator has L = 1 μH, C = 100 pF, and Q = 50. For what value of transconductance Gm will the circuit oscillate? At what frequency?
18.6 In a particular oscillator characterized by the structure of Fig. 18.1, the frequency-selective network exhibits a loss of 12 dB and a phase shift of 180° at ω0. Give the phase shift and the minimum gain that the amplifier must have for oscillation to begin.
18.7 An oscillator is designed by connecting in a loop three identical common-source amplifier stages of the type shown in Fig. P18.7. Note that the bias circuits are not shown, and assume that R and C include the transistor output resistance and capacitance, respectively. For the circuit to oscillate at a frequency ω0, what must the phase angle provided by each amplifier stage be? Give an expression for ω0. For sustained oscillations, what is the minimum gm required of each transistor?
(a)
C
R
Figure P18.7
D 18.8 Consider the circuit of Fig. 18.4(a) with Rf removed to realize the comparator function. Find suitable values for all resistors so that the comparator output levels are ±3 V and the slope of the limiting characteristic is 0.05. Use power-supply voltages of ±5 V and assume the voltage drop of a conducting diode to be 0.7 V.
D 18.9 Consider the circuit of Fig. 18.4(a) with Rf removed
to realize the comparator function. Sketch the transfer
characteristic. Show that by connecting a dc source VB to
the virtual ground of the op amp through a resistor RB, the
transfer characteristic is shifted along the vI axis to the point
v =−R /R V . Utilizing available ±5-V dc supplies for I 1BB
±V and for VB, find suitable component values so that the limiting levels are ±3 V and the comparator threshold is at vI = +2 V. Neglect the diode voltage drop (i.e., assume that VD = 0). The input resistance of the comparator is to be 100 k, and the slope in the limiting regions is to be ≤ 0.05 V/V. Use standard 5% resistors (see Appendix J).
18.10 DenotingthezenervoltagesofZ1 andZ2 byVZ1 andVZ2 and assuming that in the forward direction the voltage drop
Figure P18.10
(b)
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
1430 Chapter 18 Signal Generators and Waveform-Shaping Circuits
is approximately 0.7 V, sketch and clearly label the transfer characteristics vO–vI of the circuits in Fig. P18.10. Assume the op amps to be ideal.
Section 18.2: Op Amp–RC Oscillator Circuits
18.11 For the Wien-bridge oscillator circuit in Fig. 18.5, show that the transfer function of the feedback network
18.16 Repeat Problem 18.15 for the circuit in Fig. P18.16.
Figure P18.16
*18.17 Consider the circuit of Fig. 18.7 with the 50-k potentiometer replaced by two fixed resistors: 10 k between the op amp’s negative input and ground, and 15 k. Modeling each diode as a 0.65-V battery in series with a 100- resistance, find the peak-to-peak amplitude of the output sinusoid.
D **18.18 Design the circuit of Fig. 18.7 for operation at10kHzusingR=10k.Ifat10kHztheop amp provides an excess phase shift (lag) of 5.7°, what will be the frequency of oscillation? (Assume that the phase shift introduced by the op amp remains constant for frequencies around 10 kHz.) To restore operation to 10 kHz, what change must be made in the shunt resistor of the Wien bridge? Also, to what value must R2/R1 be changed?
*18.19 For the circuit of Fig. 18.9, connect an additional resistor (R=10 k) in series with the rightmost capaci- tor C. For this modification (and ignoring the amplitude stabilization circuitry), find the loop gain Aβ by breaking the circuit at node X. Find Rf for oscillation to begin, and find f0.
D 18.20 ForthecircuitinFig.P18.19,breaktheloopatnode X and find the loop gain (working backward for simplicity to
Va(s)/Vo(s) is that of a bandpass filter. Find ω0 and Q of the poles, and find the center-frequency gain.
18.12 For the Wien-bridge oscillator of Fig. 18.5, let the closed-loop amplifier (formed by the op amp and the resistors R1 and R2) exhibit a phase shift of −3° in the neighborhood of ω=1/CR. Find the frequency at which oscillations can occur in this case in terms of CR. (Hint: Use Eq. 18.11.)
18.13 For the Wien-bridge oscillator of Fig. 18.5, use the expression for loop gain in Eq. (18.10) to find the poles of the closed-loop system. Give the expression for the pole Q, and use it to show that to locate the poles in the right half of the s plane, R2/R1 must be selected to be greater than 2.
D 18.14 Reconsider Exercise 18.5 with R3 and R6 increased to reduce the output voltage. What values are required for a peak-to-peak output of 8 V? What results if R3 and R6 are open-circuited?
18.15 For the circuit in Fig. P18.15, find L(s), L(jω), the frequency for zero loop phase, and R2/R1 for oscillation. Assume the op amp to be ideal.
CHAPTER 18 PROBLEMS
R1
R2
CR
R
C
Figure P18.15
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
Problems 1431
CHAPTER 18 PROBLEMS
Figure P18.20
findVx intermsofVo).ForR=10k,findCandRf toobtain sinusoidal oscillations at 15 kHz.
*18.21 Consider the quadrature-oscillator circuit of Fig. 18.10 without the limiter. Let the resistance Rf be equal to 2R/(1+), where ≪ 1. Show that the poles of the characteristic equation are in the right-half s plane and given by s ≃ (1/CR)[(/4) ± j].
D 18.22 Using C = 1.6 nF, find the value of R such that the circuit of Fig. 18.12 produces 10-kHz sine waves. If the diode drop is 0.7 V, find the peak-to-peak amplitude of the output sine wave. How do you modify the circuit to double the output amplitude? (Hint: A square wave with peak-to-peak amplitude of V volts has a fundamental component with 4V /π volts peak-to-peak amplitude.)
*18.23 Assuming that the diode-clipped waveform in Exer- cise 18.9 is nearly an ideal square wave and that the resonator Q is 20, provide an estimate of the distortion in the output sine wave by calculating the magnitude (relative to the fundamental) of
(a) the second harmonic
(b) the third harmonic
(c) the fifth harmonic
(d) the rms of harmonics to the tenth
Note that a square wave of amplitude V and frequency ω is represented by the series
4V sinωt + 1sin3ωt + 1sin5ωt + 1sin7ωt + … π357
Section 18.3: LC and Crystal Oscillators
18.24 For the Colpitts oscillator circuit in Fig. P18.24, derive an equation governing circuit operation and hence find the frequency of oscillation and the condition on the gain gmRL that ensures that oscillations will start. Assume that RL includes ro of Q1. Simplify your final expressions by assuming rπ is large. Observe that this circuit is based on the configuration in Fig. 18.13(a) except that here the biasing circuit is included and the collector is placed at signal ground.
L
C1
Figure P18.24
Q1
C2
I RL
18.25 FortheColpittsoscillatorcircuitinFig.P18.25,derive an equation governing circuit operation and hence find the frequency of oscillation and the condition the gain gm RL must
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
1432 Chapter 18 Signal Generators and Waveform-Shaping Circuits
satisfy for oscillations to start. Assume that RL includes the MOSFET’s ro.
L
C1
Figure P18.25
of the BJT is included in RL and neglect Rf (i.e., assume Rf ≫ ω0 L). Simplify your final expressions by assuming rπ is large. Observe that this circuit is similar to that in Fig. 18.15 except for utilizing a different biasing scheme.
Q1 C2
I RL
I
CHAPTER 18 PROBLEMS
Rf
C2
L
C1
18.26 FortheColpittsoscillatorcircuitinFig.P18.26,derive an equation governing circuit operation and hence find the frequency of oscillation and the condition the gain gm RL must satisfy to ensure that oscillations will start. Neglect ro of the BJT. Simplify your final expressions by assuming that rπ is large. Note that this circuit is based on the configuration of Fig. 18.13(a) but with the bias circuit included and the base grounded.
Q1
RL
Figure P18.27
L
Q1
I
C1
C2
RL
*18.28 The LC oscillator in Fig. P18.28 is based on connecting a positive-gain amplifier (formed by Q1, Q2, and RC ) with a bandpass RLC circuit in a feedback loop.
Figure P18.28
18.27 FortheColpittsoscillatorcircuitinFig.P18.27,derive an equation governing circuit operation and hence find the frequencyofoscillationandtheconditionthegaingmRL must satisfy to ensure that oscillations will start. Assume that ro
Figure P18.26
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
CHAPTER 18 PROBLEMS
(a) Replace the BJTs with their small-signal models while neglecting rπ and ro (to simplify matters).
(b) By inspection of the circuit found in (a), find the frequency of oscillation and the condition required for oscillations to start. Express the latter as the minimum required value of (IRC ).
(c) If IRC is selected equal to 1 V, show that oscillations will start. If oscillations grow to the point that Vo is large enough to turn the BJTs on and off, show that the signal at the collector of Q2 will be a square wave of 1 V peak-to-peak. Estimate the peak-to-peak amplitude of the output sine wave Vo.
D 18.29 Design the cross-coupled LC oscillator of Fig. 18.16(a) to operate at ω0 = 20 Grad/s. The IC inductors available have L = 5 nH and Q = 10. If the transistor ro = 5 k, find the required value of C and the minimum required value of gm at which Q1 and Q2 are to be operated.
18.30 Consider the Pierce crystal oscillator of Fig. 18.18 with the crystal as specified in Exercise 18.13. Let C1 be variable in the range 1 pF to 10 pF, and let C2 be fixed at 10 pF. Find the range over which the oscillation frequency can be tuned. (Hint: Use the result in the statement leading to the expression in Eq. 18.29.)
Section 18.4: Bistable Multivibrators
D 18.31 DesignthebistablecircuitinFig.18.21(a)toobtain a hysteresis of 2-V width. The op amp saturates at ±5 V. Select R1 = 10 k and determine R2 .
18.32 Consider the bistable circuit of Fig. 18.21(a) with the op amp’s positive input terminal connected to a positive-voltage source V through a resistor R3.
(a) Derive expressions for the threshold voltages VTL and VTH in terms of the op amp’s saturation levels L+ and L−, R1, R2, R3, and V.
(b) LetL+=−L−=10V,V=15V,andR1 =10k.Find the values of R2 and R3 that result in VTL = +4.9 V and
VTH = +5.1 V.
18.33 Consider the bistable circuit of Fig. 18.22(a) with the op amp’s negative-input terminal disconnected from ground and connected to a reference voltage VR.
(a) Derive expressions for the threshold voltages VTL and VTH in terms of the op amp’s saturation levels L+ and L−, R1, R2, and VR.
Problems 1433 (b) Let L+ =−L− =V and R1 =10 k. Find R2 and VR that
result in threshold voltages of 0 and V/10.
18.34 For the circuit in Fig. P18.34, sketch and label the transfer characteristic v O−v I . The diodes are assumed to have a constant 0.7-V drop when conducting, and the op amp saturates at ±12 V. What is the maximum diode current?
Figure P18.34
18.35 Consider the circuit of Fig. P18.34 with R1 eliminated and R2 short-circuited. Sketch and label the transfer char- acteristic vO−vI. Assume that the diodes have a constant 0.7-V drop when conducting and that the op amp saturates at ±12 V.
*18.36 Consider a bistable circuit having a noninverting transfer characteristic with L = −L = 12 V, V = −1 V,
andVTH=+1V.
(a) For a 0.5-V-amplitude sine-wave input having zero average, what is the output?
(b) Describe the output if a sinusoid of frequency f and amplitude of 1.1 V is applied at the input. By how much can the average of this sinusoidal input shift before the output becomes a constant value?
D 18.37 Design the circuit of Fig. 18.25(a) to realize a transfer characteristic with ±7.5-V output levels and ±7.5-V threshold values. Design so that when vI = 0 V a current of 0.5mA flows in the feedback resistor and a current of 1 mA flows through the zener diodes. Assume that the output saturation levels of the op amp are ±10 V. Specify the voltages of the zener diodes and give the values of all resistors.
+ − TL
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1434 Chapter 18
Signal Generators and Waveform-Shaping Circuits
R4
R6
R3
R2
R1
Figure P18.41
R7
R5
Z1 Z2
C
CHAPTER 18 PROBLEMS
Section 18.5: Generation of Square and Triangular Waveforms Using Astable Multivibrators
noninverting integrator. Using equal values for all resistors except R7 and a 0.5-nF capacitor, design the circuit to obtain a square wave at the output of the bistable multivibrator of 15-V peak-to-peak amplitude and 10-kHz frequency. Sketch and label the waveform at the integrator output. Assuming ±13-V op-amp saturation levels, design for a minimum zener current of 1 mA. Specify the zener voltage required, and give the values of all resistors.
Section 18.6: Generation of a Standardized Pulse—The Monostable Multivibrator
D 18.42 For the monostable circuit considered in Exer- cise 18.22, calculate the recovery time.
*18.43 Figure P18.43 shows a monostable multivibrator circuit. In the stable state, vO = L+, vA = 0, and vB = −Vref . The circuit can be triggered by applying a positive input pulse of height greater than Vref . For normal operation, C1 R1 ≪ CR. Show the resulting waveforms of vO and vA. Also, show that the pulse generated at the output will have a width T given by
18.38 Find the frequency of oscillation of the circuit in Fig.18.26(b)forthecaseR1 =10k,R2 =16k,C=5nF, and R=62 k.
D 18.39 Augment the astable multivibrator circuit of Fig. 18.26(b) with an output limiter of the type shown in Fig. 18.25(b). Design the circuit to obtain an output square wave with 5-V amplitude and 1-kHz frequency using a 10-nF capacitor C. Use β = 0.462, and design for a current in the resistive divider approximately equal to the average current in the RC network over a half-cycle. Assuming ±13-V op-amp saturation voltages, arrange for the zener to operate at a minimum current of 1 mA. Specify the values of all resistors and the zenor voltage.
D 18.40 UsingtheschemeofFig.18.27,designacircuitthat provides square waves of 10 V peak to peak and triangular waves of 10 V peak to peak. The frequency is to be 1 kHz. Implement the bistable circuit with the circuit of Fig. 18.25(b). Use a 0.01-μF capacitor and specify the values of all resistors and the required zener voltage. Design for a minimum zener current of 1 mA and for a maximum current in the resistive divider of 0.2 mA. Assume that the output saturation levels of the op amps are ±12 V.
D *18.41 The circuit of Fig. P18.41 consists of an invert- ing bistable multivibrator with an output limiter and a
T = CR ln
L−L + −
Vref
Note that this circuit has the interesting property that the pulse
width can be controlled by changing Vref .
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
Figure P18.43
D *18.44 Using the circuit of Fig. 18.28, with a nearly ideal op amp for which the saturation levels are ±13 V, design a monostable multivibrator to provide a negative output pulse of 100-μs duration. Use capacitors of 0.1 nF and 1 nF. Wherever possible, choose resistors of 100 k in your design. Diodes have a drop of 0.7 V. What is the minimum input step size that will ensure triggering? How long does the circuit take to recover to a state in which retriggering is possible with a normal output?
Section 18.7: Integrated-Circuit Timers
18.45 Consider the 555 circuit of Fig. 18.29 when the Threshold and the Trigger input terminals are joined together and connected to an input voltage vI . Verify that the transfer characteristic v O –v I is that of an inverting bistable circuit
sionsforTH andTL,expressingthemintermsofVTH and VTL.
(b) For the case C=1 nF, RA =7.2 k, RB =3.6 k, and VCC = 5 V, find the frequency of oscillation and the duty cycle of the resulting square wave when no external voltage is applied to the terminal VTH .
(c) For the design in (b), let a sine-wave signal of a much
lower frequency than that found in (b) and of 1-V
peak amplitude be capacitively coupled to the circuit
node VTH . This signal will cause VTH to change around
its quiescent value of 2 V , and thus T will change 3CC H
correspondingly—a modulation process. Find TH, and find the frequency of oscillation and the duty cycle at the two extreme values of VTH .
Section 18.8: Nonlinear Waveform-Shaping Circuits
D *18.49 The two-diode circuit shown in Fig. P18.49 can
provide a crude approximation to a sine-wave output when
driven by a triangular waveform. To obtain a good approxi-
mation, we select the peak of the triangular waveform, V, so
that the slope of the desired sine wave at the zero crossings
is equal to that of the triangular wave. Also, the value of R
is selected so that when v is at its peak, the output voltage I
is equal to the desired peak of the sine wave. If the diodes exhibit a voltage drop of 0.7 V at 1-mA current, changing at the rate of 0.1 V per decade, find the values of V and R that will yield an approximation to a sine waveform of 0.7-V peak amplitude. Then find the angles θ (where θ = 90° when vI is at its peak) at which the output of the circuit, in volts, is 0.7, 0.65, 0.6, 0.55, 0.5, 0.4, 0.3, 0.2, 0.1, and 0. Use the
Figure P18.49
Problems 1435 connected to an external terminal. This allows the user to
change V externally (i.e., V no longer remains at 2 V ). TH TH 3 CC
CHAPTER 18 PROBLEMS
Note, however, that whatever the value of VTH becomes, VTL always remains 1 V .
2 TH
(a) For the astable circuit of Fig. 18.31, rederive the expres-
with thresholds V = 1 V TL 3 CC
of 0 and VCC.
and V = 2 V TH 3 CC
and output levels
D 18.46 (a) Using a 0.5-nF capacitor C in the circuit of
Fig. 18.30(a), find the value of R that results in an output
pulse of 10-μs duration.
(b) If the 555 timer used in (a) is powered with VCC = 12 V,
and assuming that VTH can be varied externally (i.e., it need
not remain equal to 2 V ), find its required value so that the 3 CC
pulse width is increased to 20 μs, with other conditions the same as in (a).
D 18.47 Usinga680-pFcapacitor,designtheastablecircuit of Fig. 18.31(a) to obtain a square wave with a 20-kHz frequency and an 80% duty cycle. Specify the values of RA and RB.
*18.48 Thenodeinthe555timeratwhichthevoltageisVTH (i.e., the inverting input terminal of comparator 1) is usually
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1436 Chapter 18 Signal Generators and Waveform-Shaping Circuits
angle values obtained to determine the values of the exact sine wave (i.e., 0.7 sin θ ), and thus find the percentage error of this circuit as a sine shaper. Provide your results in tabular form.
D 18.50 Design a two-segment sine-wave shaper using a 6.8-k-input resistor, two diodes, and two clamping voltages. The circuit, fed by an 8-V peak-to-peak triangular wave, should limit the amplitude of the output signal via a 0.7-V diode to a value corresponding to that of a sine wave whose zero-crossing slope matches that of the triangle. What are the clamping voltages you have chosen?
18.51 Show that the output voltage of the circuit in Fig. P18.51 is given by
where IS is the saturation current of the diode and VT is the thermal voltage. Since the output voltage is proportional to the logarithm of the input voltage, the circuit is known as a logarithmic amplifier. Such amplifiers find application in situations where it is desired to compress the signal range.
18.52 Verify that the circuit in Fig. P18.52 implements the transfer characteristic vO = −v1v2 for v1, v2 > 0. Such a cir- cuit is known as an analog multiplier. Check the circuit’s per- formance for various combinations of input voltage of values, say, 0.5 V, 1 V, 2 V, and 3 V. Assume all diodes to be identical, with 700-mV drop at 1-mA current. Note that a squarer can easily be produced using a single input (e.g., v1) connected via a 0.5-k resistor (rather than the 1-k resistor shown).
**18.53 Detailed analysis of the circuit in Fig. 18.34 shows that optimum performance (as a sine shaper) occurs when the values of I and R are selected so that RI = 2.5VT , where VT is the thermal voltage, and the peak amplitude of the input triangular wave is 6.6VT . If the output is taken across R (i.e., between the two emitters), find vI corresponding to vO =0.25VT, 0.5VT, VT, 1.5VT, 2VT, 2.4VT, and 2.42VT. Plot vO–vI and compare to the ideal curve given by
CHAPTER 18 PROBLEMS
v vO=−VTln I ,vI>0
ISR
Figure P18.51
vO =2.42VT sin
v I ×90°
6.6VT
D1
A
D2
D4
BD D3
Figure P18.52
C
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
APPENDICES ON COMPANION WEBSITE
For your convenience, ten additional chapters on important reference topics are included on the Companion Website. In PDF format, the Appendices are fully searchable and can be bookmarked.
Appendix A: VLSI Fabrication Technology This article is a concise explanation of the technology that goes into fabricating integrated circuits. The different processes used are described and compared, and the characteristics of the resulting devices presented. Design considerations that restrict IC designers are explored.
Appendix B: SPICE Device Models and Design and Simulation Examples Using PSpice® and MultisimTM This three-part appendix could stand as a book on its own. Part 1 describes the models SPICE programs use to represent op amps, diodes, MOSFETs, and BJTs in integrated circuits. A thorough understanding of these models is critical for designers trying to extract meaningful information from an analysis. Part 2 describes and discusses all the PSpice® simulations, while Part 3 does the same for the MultisimTM simulations. This is a rich resource to help analyze, experiment with, and design circuits that relate to the topics studied in Microelectronic Circuits.
Appendix C: Two-Port Network Parameters Throughout the text, we use different possible ways to characterize linear two-port networks. This appendix summarizes the y, z, h, and g parameters and provides their equivalent-circuit representations.
Appendix D: Some Useful Network Theorems This article reviews Thévenin’s theo- rem, Norton’s theorem, and the source-absorption theorem, all of which are useful in simplifying the analysis of electronic circuits.
Appendix E: Single-Time-Constant Circuits STC circuits are composed of, or can be reduced to, one reactive component (inductance or capacitance) and one resistance. This is important to the design and analysis of linear and digital circuits. Analyzing an ampli- fier circuit can usually be reduced to the analysis of one or more STC circuits.
Appendix F: s-Domain Analysis: Poles, Zeroes, and Bode Plots Most of the work in analyzing the frequency response of an amplifier involves finding the amplifier volt- age gain as a function of the complex frequency s. The tools to do this are summarized in this appendix.
Appendix G: Comparison of the MOSFET and the BJT Provides a comprehensive compilation and comparison of the properties of the MOSFET and the BJT. The com- parison is aided by the inclusion of typical parameter values of devices fabricated with modern process technologies.
Appendix H: Design of Stagger-Tuned Amplifiers Provides a systematic procedure for the design of this type of tuned amplifier (Section 17.12.6).
Appendix I: Bibliography An excellent resource for students beginning research proj- ects, this bibliography outlines key reference works on electronic circuits, circuit and system analysis, devices and IC fabrication, op amps, analog and digital circuits, filters and tuned amplifiers, and SPICE.
Appendix L: Answers to Selected Problems.
APPENDIX G
COMPARISON OF THE MOSFET AND THE BJT
The full text of Appendix G is on the book’s website. Here, we show only Table G.3, which provides a summary comparison of the MOSFET and the BJT.
Table G.3 Comparison of the MOSFET and the BJT NMOS
Circuit Symbol
To Operate in
the Active Mode, Two Conditions Have to Be Satisfied
Current–Voltage Characteristics in the Active Region
iD iG vGD
vDS
npn
iC iB vBC
vCE
vGS
(1) Induce a channel:
vGS ≥ Vt, Vt = 0.3–0.5V Let vGS =Vt +vOV
(2) Pinch-off channel at drain:
vGD