计算机代考 ECE 391 Computer Systems

ECE 391 Computer Systems
Engineering

University of Illinois

Copyright By PowCoder代写 加微信 powcoder

Portions taken from ECE 391 Lecture Notes by , , , Wikipedia, the free
encyclopedia, ’ x86 Assembly Guide, ’s Programming from the Ground Up, and the X86
Assembly Wikibook

Lecture 2: x86 instruction set architecture: introduction and instructions.

Administrivia

– In TAs office hours by 09/01
– you can hand in anytime during office hours

At the end of this sequence you should
be able to:
• Understand ISAs and their role in computer

• Recognize the specifics of x86 ISA instructions

and GNU notation
• Demonstrate a working familiarity with x86

assembly by building simple x86 programs
• Follow x86 assembly function calling

conventions
• Communicate with devices in x86 assembly

What is an ISA?

RISC v CISC

Instruction Sets
• ARMv[1-8]
• IBM System{3,7}
• IBM PowerPC
• Intel i860
• Motorola 68000 family
• MIPS [i-v]
• Sun SPARC

Opteron courtesy , Wikipedia

X86 Characteristics

• variable-length instruction encoding (in bytes)
• small register set: 8 mostly general-purpose
• 32-bit, byte-addressable address space
• complex addressing modes
• many data types supported by hardware

EAX accumulator EIP instruction pointer
EBX base (of array) EFLAGS flags/condition codes
ECX count (for loops)
EDX data (2nd operand)
ESI source index (string copy)
EDI destination index
EBP base pointer (base of stack frame)
ESP stack pointer

extended, i.e., 32-bit

31 16 15 0

for 8-bit registers, change “X” to “H” or “L”
(only for A, B, C, and D)

31 16 15 0

for 16-bit registers, drop “E”

use % as a prefix for registers in assembly

other registers: floating-point, MMX, etc. (not discussed in this class)

data types — many supported!

– 8-, 16-, 32-bit unsigned and 2’s complement
– IEEE single- and double-precision floating point
– Intel “extended” f.p. (80-bit); pre-IEEE standard
– ASCII strings
– binary-coded decimal

• Microprocessor addresses a maximum of 2n
different memory locations, where n is a number
of bits on the address bus

– x86 supports byte addressable memory
– byte (8 bits) is a basic memory unit
– e.g., when you specify address 24 in memory, you get

the entire eight bits
– when the microprocessors address a 16-bit word of

memory, two consecutive bytes are accessed

How are bytes stored to memory?

big-endian
(big end first)

little-endian
(little end first)

x86 uses this approach

Operations

Operations—lots of them!

arithmetic logical shift
ADD AND SHL
SUB OR SAR
NEG NOT SHR
INC XOR ROL

ORL %ECX, %EBX # EBX ¬ EBX OR ECX

operation data type (technically optional)
L = long (32b)
W = word (16b)
B = byte (8b)

destination and first sourcesecond source

comment marker

typically 2-operand instructions (destination
and one source are the same)

immediate values

$0x____ hex
$0_____ octal
$53 decimal

immediate value marker

how big can they get?

• usually up to 32 bits
• larger constants ⇒ longer instructions
• length of operand must be encoded, too, of

what does the following
instruction do?

ANDL 0, %EAX

what does the following
instruction do?

ANDL 0, %EAX

answer is NOT

EAX ¬ EAX AND M[0]

(usually crashes)

Data Movement: memory addressing

displacement(SR1,SR2,scale)
address is: displacement + SR1 + SR2 * scale

defaults to 0 any but ESP

1,2,4,8 (defaults to 1)

Data movement: instructions

MOV src, dst reg. or mem. ref.
LEA src, dst reg. only

immediate, reg., or mem. ref

mem. ref. only—address stored in dst

(can’t both be memory references)

MOVW %DX, 0x10(%EBP) # M[EBP + 0x10] ¬ DX

MOVB (%EBX,%ESI,4), %CL # CL ¬ M[EBX + ESI * 4]

EAX ¬ M[0x10000 + ECX]
M[LABEL] ¬ DI
ESI ¬ LABEL + 4 (two ways!)

ESI ¬ LABEL + EAX + 4

EAX ¬ M[0x10000 + ECX] MOVL 0x10000(%ECX), %EAX
M[LABEL] ¬ DI MOVW %DI, LABEL
ESI ¬ LABEL + 4 (two ways!) MOVL $LABEL + 4, %ESI

LEAL LABEL + 4, %ESI
ESI ¬ LABEL + EAX + 4 LEAL LABEL + 4(%EAX), %ESI

what instructions set flags (i.e., condition
– not all instructions set flags
– some instructions set some flags!
– use CMP or TEST to set flags:

CMPL %EAX, %EBX # flags ¬ (EBX – EAX)
TESTL %EAX, %EBX # flags ¬ (EBX AND EAX)

– note that EBX does not change in either case
– Not exclusive as in LC-3

Condition Codes (in EFLAGS)

SF — sign flag: result is negative when viewed as
2’s complement data type

ZF — zero flag: result is exactly zero
CF — carry flag: unsigned carry or borrow occurred
OF — overflow flag: 2’s complement overflow
PF — parity flag: even parity in result (even # of 1 bits)

(and other instruction-dependent meanings)

Control Flow Instructions

• branches based on combinations of condition

• think about
– CMPL %ESI, %EDX (sets flags based on (EDX –

– what combination of flags needed for

unsigned/signed relationship comparisons (EDX < ESI, for example)? test yourself #1 #2 #3 #4 #5 #6 A 010 010 010 110 110 110 B -000 -110 -111 -000 -011 -111 C 010 100 011 110 011 111 CF 0 1 1 0 0 1 OF 0 1 0 0 1 0 SF 0 1 0 1 0 1 unsigned A
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