CS计算机代考程序代写 x86 mips assembly Welcome to Computer Organization and Assembly!

Welcome to Computer Organization and Assembly!

The Control
CS/COE 0447
Jarrett Billingsley

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Class announcements
proj1 is graded!
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The Control
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Braindead
last time, we looked at this thing:
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Register File
imm field

ALU
MemWrite

ALUSrc
ALUOp
rd
RegWrite

RegDataSrc
rs
rt

Data Memory
Data
Address
it can do the work that instructions do, but it can’t run them.
for that, we need something to set all those blue control signals.

– it’s like a weird, awkward calculator at this point. you can use it to do calculations, but you have to do it all manually.
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Data Memory
Feeling nervous
the control is what sets the write enables and selects to the appropriate values to make each instruction happen.
it’s like the CPU’s brain and nervous system.
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Control
c’mon you lazy bums
Register File

ALU
awwwww we don’t wannaaaa
it does this by reading the instructions.
sub v0, t0, t1
Register file, read t0 and t1, and write to v0. ALU, do subtraction. Interconnect, route the data from the two registers into the ALU and from the ALU into the register file. Data memory, you get to take a break.
yissssss
👀

Instruction Execution
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Phases of instruction execution
Fetch (IF or F)
use PC to get the next instruction from memory
Decode (ID or D)
look at the fetched instruction and set control signals
Execute (EX or X)
wait for data to flow through the datapath
Memory Access (MEM or M)
if it’s a load or store, do that
Write-back (WB or W)
if there’s a destination register, write the result to it
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F
D
X
M
W
often we can do multiple phases “at the same time.”

– every instruction will have a fetch and decode phase.
– almost all instructions have an execute phase (except for a no-op).
– only loads and stores have a memory phase.
– only instructions with destination registers have a write-back phase.
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Which parts do what

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Instruction Memory
PC
Control
Register File

ALU
Data Memory

F

D

W

X

M

Single-cycle machine control
we’ll be talking about a single-cycle machine and building one for the project
this means each instruction takes one clock cycle to execute
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add t0, t1, t2

sb t0, 4(s0)

do F, D, X…
W: store sum in t0
M: store value in memory

do F, D, X…
each instruction ends on the rising edge of the clock.
(that’s when the registers/memory store the computed values.)

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That’s fine for Harvard architectures…
but what about von Neumann architectures, with 1 memory?
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Memory
PC
Control
Register File

ALU
so, the control and the rest of the CPU have to take turns.
the memory is now used for both the F and M phases.
which means each instruction takes multiple steps…

– remember, 1 memory = von Neumann, 2 memories = Harvard
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Multi-cycle machine control
the simplest multi-cycle machine takes two cycles per instruction:
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sb t0, 4(s0)
use memory for M: store value

use memory for F…

D, X…
save the fetched instruction into the control!
now the control has to remember which state it’s in as well as what the fetched instruction was.
so a multi-cycle control unit is an FSM.

– the register in the control that saves the fetched instruction is a microarchitectural register
– it’s hidden from view, but needed to implement the ISA
– it’s often called IR for “instruction register”, which makes sense
– of course, we need another microarchitectural register to keep track of what state the control is in
– here we only have two states: “Fetch” and “Everything Else”
– but we can take this concept much, much further…
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The Forgotten Phase:
Operand Fetch
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A little extra step
operand fetch is a phase of execution you might see in literature.
it fetches the values to be operated on.
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F
D
X
M
W
O?
it happens after the instruction is decoded but before we can do any work.
where do values have to be for the CPU to operate on them during the eXecute phase?
in the registers, right…?

Vestigial
in MIPS (and your project), operand fetch is super simple:
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Register File
imm field

ALU

here it is!
this is by design: load-store architectures have very simple operand fetch phases.
why? well…
in MIPS it’s so simple, the operands are already there.

Operand Fetch in x86
as a CISC, x86 has some… crazy instructions.
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inc [eax + ecx*4 + 12]
this is operand fetch.

(the brackets mean “access memory.”)
here’s what the CPU has to do for this instruction:
fetch it
decode it
multiply ecx by 4
add eax to that
add 12 to that
load a word from that address
add 1 to that value
store that value back into the address
this is an effective address calculation.

this is where a lot of the complexity in CISC machines comes from.
imagine the number of states the control FSM must have!

Instruction Decoding
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The control hardware
in a single-cycle machine, the control’s job is straightforward:
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Instruction Memory
address goes in…
…instruction comes out.
MemWrite
ALUSrc
ALUOp
rd
RegWrite
RegDataSrc
rs
rt
immediate
PCSrc
Control
instruction goes in…
…control signals come out.
PC FSM

The steps
there are three main phases of decoding:
split the encoded bitfield into its constituent values.
from the opcode, determine which instruction we’re looking at.
map that instruction to a unique combination of control signals.
all of this should happen inside the control unit!
when you get to the project, do not sprinkle bits of control all over your CPU! it gets really, really confusing!
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Pull ‘n’ peel
the first step is to split the encoded instruction up
but which instruction format is it? actually, it doesn’t matter.
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do everything at once, but use only what you need.
31 26 25 21 20 16 15 0
opcode rs rt immediate

31 26 25 21 20 16 15 11 10 6 5 0
opcode rs rt rd shamt funct

31 26 25 0
opcode target

31-26
opcode
25-21
rs
20-16
rt
15-11
rd
10-6
shamt
5-0
funct
15-0
immediate
25-0
target
32
instruction
R
I
J
see splitter_bitfields.circ and decoding.circ.

No, really, it’s fine, don’t worry about it
let’s suppose the encoded instruction was addi s0, s0, -1.
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op
rs
rt
rd
shamt
funct
imm
target
32
0x2210FFFF
addi s0,s0,-1
0x08
0x10
0x10
0x1F
0x1F
0x3F
0xFFFF
0x210FFFF
31 26 25 21 20 16 15 0
opcode rs rt immediate

put it through the splitter and…
…out come a bunch of values.
the opcode identifies this as addi, which is an I-type instruction.
therefore, rs, rt, and immediate will be used….
…and the R- and J-type fields are bogus and will be ignored.

– how does the CPU know it’s an I-type instruction?
– well that’s like asking: how does a paper hole puncher “know” how far apart to put the holes?
– it… doesn’t. we just designed it to do that. it punches the holes that far apart because the punchers are that far apart.
– the control is as dumb as the rest of the CPU. it’s mechanical. it sees opcode 8, it will use those fields.
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From opcode to control signals
the control is a boolean function that takes the instruction opcode as its input and outputs the control signals.
in other words, it’s a big fat truth table!
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opcode PCSrc RegDataSrc RegWrite ALUOp …
000000 0 00 0 000 …
000001 0 01 1 110 …
000010 0 00 1 010 …
000011 1 00 0 011 …
000100 1 11 1 000 …
000101 0 10 1 010 …
… … … … … …

I really would not recommend making a control unit like this.
you will go insane.
it’s time-consuming, confusing, hard to debug, and hard to change.
I just made up these numbers. Please don’t try to use them.

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First: identifying which instruction we’re looking at
a decoder takes a number and turns on one output; the rest are 0.
so, if we feed it an opcode, it will tell us which instruction it is.
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opcode


j
jal
beq
bne
blez
bgtz
addi
addiu
slti
sltiu
at any time, exactly one of these will be on (1).
we can map from these to the control signals much more easily.
for that, it’s good to focus on one control signal at a time.
e.g. if the current instruction is a jal, the jal wire will be 1.

– to be clear: these signals are 1 if the opcode says “yes it’s this instruction” and 0 otherwise.
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The logic of a control signal
let’s focus on a really simple control signal: MemWrite.
this is the write enable for the data memory.
so, which 3 instructions write to memory?
sw, sh, and sb
if you were writing it as code, it might be something like…
if(opcode == sw || opcode == sb || opcode == sh)
MemWrite = true
else
MemWrite = false
or even more tersely:
MemWrite = opcode == sw || opcode == sb || opcode == sh
that seems really easy to turn into a circuit!
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