CSE/EEE 230 Computer Organization and Assembly Level Programming
Project 4 (100 Marks)
Due Date: 04/23/2021
Problem 1: Pipelined Processor (20 Marks)
Consider the MIPS Pipelined processor as shown in figure 3. Redraw the (whole) diagram with all the control signals and the datapath units to include the JUMP instruction.
Problem 2: Simulate MIPS code (50 Marks)
Consider the following MIPS program that is to be executed on a single-cycle (Figure 1), multi-cycle (Figure 2) and pipelined (Figure 3) processor.
Assume Initially, R2=1, R1=0, R0=1
Loop: add R1, R2, R1
beq R1, R0, Loop // The branch is taken once and then not taken
lw R3, 8(R1)
addi R3, R3, 1
1. Complete the table 3 for single cycle processor. (5 marks)
2. Complete the table 4 for multi cycle processor. (5 marks)
3. Complete the table 5 for pipelined processor. Assume forwarding, stalling and branch not taken until the branch is resolved. (10 marks)
4. Consider the tables 1 and 2 for delay values various data path components. The table is common for the single-cycle, multi-cycle and pipelined processor.
• Find the clock period at which each of the processor architectures as shown in Figure 1, Figure 2 and in Figure 3 runs. (15 marks)
• Find the total time it takes to run the given program on each of the processor architectures as shown in Figure 1, Figure 2 and in Figure 3 . (15 marks)
• Note:
(a) For the multi-cycle processor, the TCQ and Tsetup for the registers is equal to 80ps and 10ps respec- tively.
(b) For the multi-cycle processor, Instruction and Data memory is combined as I/DMEM. The Delay of I/DMEM = 400 ps and Tsetup = 20 ps.
(c) Read from all the memories in all the architectures is combinational and write is sequential. Table 1: Delay of different datapath units
Table 2: Delay of different datapath units
Unit
PC (TCQ)
PC (Tsetup)
Pipleline Reg (TCQ)
Pipleline Reg (Tsetup)
IMEM (read)
DMEM (read)
Delay (ps)
60
10
100
20
400
400
Unit
DMEM (setup)
Register File (read)
Control Unit
ALU
Mux
Else
Delay (ps)
20
100
100
120
30
0
1
CSE/EEE 230 Computer Organization and Assembly Level Programming
Problem 3 (30 marks)
Given the following sequence of instructions to be executed using a 5-stage pipelined implementation
1 2 3 4 5 6
1.
sub $s4,$s5,$s6
lw $s0,0($s1)
add $s3,$s0,$s2
beq $s3,$s4,Label
sub $s1 $s3,$s4
Label: add $s5,$s3,$s6
With the help of the traditional clock-cycles pipeline diagram, specify all the hazards that may occur in this piece of code, if we let the pipeline run at full-speed (i.e., launching a new instruction each clock cycle). (10 marks)
2.
Note: You may assume branch not taken wherever necessary.
Show how to avoid those hazards by adding as few stalls/bubbles as possible. You are allowed to use “for- warding”. How many clock cycles are required to complete the execution of this piece of code? (20 marks)
Submission Instructions
For processor, provide a clear, concise and well-written explanation as to the reasoning behind your solution. This needn’t be long, but it should clearly explain the solution.
1. Create a well formatted document in PDF format for submission. 2. PDF file should be named as LastName FirstName ASUID.pdf 3. No Late submissions will be accepted.
Due Date : 04/23/2021 @ 11:59 pm
2
CSE/EEE 230 Computer Organization and Assembly Level Programming
Figure 1: Single-cycle MIPS processor
Table 3: Values of control signals in single cycle processor
Cycles ->
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
RegDst
ALUSrc
MemtoReg
RegWrite
MemWrite
Branch
JMP
MemRead
3
CSE/EEE 230 Computer Organization and Assembly Level Programming
Figure 2: Multi-cycle MIPS processor
Table 4: Values of control signals in a multi-cycle processor
Cycles ->
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
RegDst
ALUSrcA
ALUSrcB
ALUControl
MemtoReg
RegWrite
MemWrite
IRWrite
IorD
Branch
PCWrite
PCSrc
4
CSE/EEE 230 Computer Organization and Assembly Level Programming
Figure 3: Five stage pipelined MIPS processor
Table 5: Values of control signals in a pipelined processor
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
Cycles ->
RegWriteD MemtoRegD MemWriteD ALUControlD ALUSrcD RegDstD BranchD RegWriteE MemtoRegE MemWriteE ALUControlE ALUSrcE RegDstE RegWriteM MemtoRegM MemWriteM RegWriteW MemtoRegW StallF
StallD ForwardBD ForwardAD FlushE ForwardBE ForwardAE
C20
5