CSE 325 Modules
#7 – Memory Management I #8 – Memory Management II #9 – Virtual Memory
#10 — Networks
#11 – Case Study: Linux #12 – Computer Security
Readings
Silberschatz, 9.1-9.8 Silberschatz, 10.1-10.6 Silberschatz, 19.1-19.3 Silberschatz, 20.1-20.11 Silberschatz, 16.1-16.6
Sample Exam
Spring 2021
The subsequent pages contain 30 sample questions (the answer key is below).
Exam #2 Study Suggestions
***************************************************************************** * Answer Key * ** * 010203040506070809101112131415161718192021222324 * *ABBCADBADEDCBDEBCEBADECB* ** * 252627282930 * *EDACAD * *****************************************************************************
01. Consider two adjacent levels in a memory hierarchy, where all memory references are satisfied in one or the other of the two levels. Assume that access to the upper level consumes 2 nanoseconds, and that 95% of the memory references result in a hit in the upper level. If the average memory access time
is 5
nanoseconds, what is the miss penalty?
A) 60ns
B) 50ns
C) 40ns
D) 30ns
E) None of the above.
02.
hierarchy, where the stated levels of the hierarchy.
characteristics for the components in a memory access times include all miss processing for higher
Consider the following
Access to Level 1 cache consumes 1 nanosecond
Access to primary storage (RAM) consumes 90 nanoseconds
If 95% of memory references satisfied from RAM, what is
A) 5.4 ns
B) 5.5 ns
C) 9.9 ns
D) 10.0 ns
E) None of the above.
03. Consider the following hierarchy, where the stated levels of the hierarchy.
result in a hit in level 1 cache, and all others are the average memory access time?
characteristics for the components in a memory access times include all miss processing for higher
Access to Level 1 cache consumes 1 nanosecond
Access to primary storage (RAM) consumes 90 nanoseconds
What percentage of the accesses to cache must be a hit in order for the average memory access time to be 3.7 nanoseconds?
A) 96%
B) 97%
C) 98%
D) 99%
E) None of the above.
04. Consider the following hierarchy, where the stated levels of the hierarchy.
characteristics for the components in a memory access times include all miss processing for higher
Access to Level 1 cache consumes 1 nanosecond
Access to Level 2 cache consumes 20 nanoseconds
Access to primary storage (RAM) consumes 90 nanoseconds
If 80% of the memory references result in a hit in level 1 cache, 90% of the remaining memory references result in a hit in Level 2 cache, and all other memory references are satisfied from RAM, what is the average memory access time?
A) 5.9 ns
B) 6.0 ns
C) 6.8 ns
D) 14.0 ns
E) None of the above.
##############
# Figure 1 #
##############
A microprocessor has 32-bit machine language instructions and 30-bit physical addresses. It has a direct-mapped instruction cache which contains 256 slots and a total of 1 kilobyte (1,024 bytes) for all of the data blocks.
05. Consider the instruction cache described in Figure 1. How large is the index for one cache slot?
A) 8 bits
B) 9 bits
C) 10 bits
D) 11 bits
E) None of the above.
06. Consider the instruction cache described in Figure 1. Which of the following statements about that cache organization is correct?
A) The bits stored in
B) The bits stored in
C) The bits stored in
D) All of the above.
E) None of the above.
one cache slot include a Valid bit.
one cache slot include a 20-bit tag.
one cache slot include a 32-bit data block.
07. Consider the instruction cache described in Figure 1. Which following statements about that cache organization is correct?
of the
A) It exploits both temporal locality and spatial locality.
B) It exploits temporal locality, but not spatial locality.
C) It exploits spatial locality, but not temporal locality.
D) It exploits neither temporal locality nor spatial locality. E) Locality of reference is not relevant for instruction caches.
##############
# Figure 2 #
##############
A microprocessor has 32-bit machine language instructions and 36-bit physical addresses. It has a fully associative write-back data cache which contains 128 slots and a total of 8 kilobytes (8,192 bytes) for all of the data blocks.
08. Consider the data cache described in Figure 2. in one cache slot?
A) 6 bits
B) 7 bits
C) 13 bits
D) 30 bits
E) None of the above.
09. Consider the data cache described in Figure 2.
How large is the byte offset
Which of the following
Modified bit.
30-bit tag.
512-bit data block.
statements about that cache
A) The bits stored in
B) The bits stored in
C) The bits stored in
D) All of the above.
E) None of the above.
organization is correct?
one cache slot include a
one cache slot include a
one cache slot include a
##############
# Figure 3 #
##############
A microprocessor has 32-bit physical addresses. It has a direct-mapped write-back data cache with 16 slots and 256-byte blocks. The current cache contents are shown below in hexadecimal (the data blocks are not shown).
V M Tag
———
[0]: 1 0 00204
[1]: 1 1 7ebfd
[2]: 1 0 00000
[3]: 1 0 00333
[4]: 1 1 00044
[5]: 1 1 00000
[6]: 0 0 0030d
[7]: 0 0 00000
[8]: 1 0 00204
[9]: 1 1 0030d
[a]: 0 0 00000
[b]: 1 0 7ebfd
[c]: 1 1 7ebfd
[d]: 0 0 00000
[e]: 0 0 00000
[f]: 1 1 00204
executes
Which of
correct?
a “Store” instruction where the target address is 00000222 hexadecimal. the following statements about the processing of that instruction is
information in Figure 3. What are the first and last physical
10. Consider the
addresses of the bytes in the data block of slot 8 of the cache?
A) 00000204 and 00000303 (hexadecimal) B) 00002040 and 0000204f (hexadecimal) C) 00020400 and 000204ff (hexadecimal) D) 00204000 and 00204fff (hexadecimal) E) None of the above.
11. Consider the information in Figure 3. Assume that the current process
executes
Which of
correct?
a “Load” instruction where the target address is 00000111 hexadecimal. the following statements about the processing of that instruction is
256 bytes were copied from slot 1 of the data cache to RAM. 256 bytes were copied from RAM to slot 1 of the data cache. After executing the instruction, the M bit in slot 1 equals 0.
A)
B)
C)
D) All of the above.
E) None of the above.
12. Consider the information in Figure 3. Assume that the current process
256 bytes were copied from slot 2 of the data cache to RAM. 256 bytes were copied from RAM to slot 2 of the data cache. After executing the instruction, the M bit in slot 2 equals 1.
A)
B)
C)
D) All of the above.
E) None of the above.
##############
# Figure 4 #
##############
A microprocessor has 32-bit physical addresses. It has a direct-mapped write-back data cache with 16 slots and 256-byte blocks. The current cache contents are shown below in hexadecimal (the data blocks are not shown).
V M Tag
———
[0]: 1 0 00204
[1]: 1 1 7ebfd
[2]: 1 0 00000
[3]: 1 0 00333
[4]: 1 1 00044
[5]: 1 1 00000
[6]: 0 0 0030d
[7]: 0 0 00000
[8]: 1 0 00204
[9]: 1 1 0030d
[a]: 0 0 00000
[b]: 1 0 7ebfd
[c]: 1 1 7ebfd
[d]: 0 0 00000
[e]: 0 0 00000
[f]: 1 1 00204
13. Consider the
executes
Which of
correct?
information in Figure 4. Assume that the current process
executes
Which of
correct?
a “Store” instruction where the target address is 00000444 hexadecimal. the following statements about the processing of that instruction is
instruction where the target address is 00000333 hexadecimal.
a “Load”
the following statements about the processing of that instruction is
256 bytes were copied from slot 3 of the data cache to RAM. 256 bytes were copied from RAM to slot 3 of the data cache. After executing the instruction, the M bit in slot 3 equals 1.
A)
B)
C)
D) All of the above.
E) None of the above.
14. Consider the information in Figure 4. Assume that the current process
256 bytes were copied from slot 4 of the data cache to RAM. 256 bytes were copied from RAM to slot 4 of the data cache. After executing the instruction, the M bit in slot 4 equals 1.
A)
B)
C)
D) All of the above.
E) None of the above.
15. Consider the information in Figure 4. Assume that the current process
executes
Which of
correct?
a “Load” instruction where the target address is 00000555 hexadecimal. the following statements about the processing of that instruction is
256 bytes were copied from slot 5 of the data cache to RAM. 256 bytes were copied from RAM to slot 5 of the data cache. After executing the instruction, the M bit in slot 5 equals 0.
A)
B)
C)
D) All of the above.
E) None of the above.
##############
# Figure 5 #
##############
A byte-oriented virtual memory system which uses demand paging has the following characteristics.
Virtual address: 32 bits Physical address: 40 bits
Size of one page: 8 kilobytes
The system uses a one-level page table. Each page table entry has four control bits (valid bit, present bit, referenced bit, and modified bit) and three access bits (read bit, write bit, and execute bit).
The TLB is fully associative and contains 128 slots.
16. Consider the information in Figure 5. How many page table entries are contained in the page table?
A) 2^13 entries (8,192 entries)
B) 2^19 entries (524,288 entries) C) 2^20 entries (1,048,576 entries) D) 2^23 entries (8,388,608 entries) E) None of the above.
17. Consider the information in Figure entry contain?
A) 26 bits
B) 30 bits
C) 34 bits
D) 38 bits
E) None of the above.
18. Consider the information in Figure the system?
A) 2^13 frames (8,192 frames)
B) 2^19 frames (524,288 frames) C) 2^20 frames (1,048,576 frames) D) 2^23 frames (8,388,608 frames) E) None of the above.
19. Consider the information in Figure contain?
A) 49 bits
B) 53 bits
C) 57 bits
D) 61 bits
E) None of the above.
5. How many bits does one page table
5. How many page frames are present in
5. How many bits does one TLB slot
20. Consider the information in Figure
about the TLB in that virtual memory system is correct?
A) The TLB exploits temporal locality.
B) The TLB requires one 27-bit comparator per TLB slot. C) The TLB exploits spatial locality.
D) All of the above.
E) None of the above.
5. Which of the following statements
##############
# Figure 6 #
##############
A byte-oriented virtual memory system which uses demand paging (without a TLB) has the following characteristics: 16-bit virtual addresses, 32-bit physical addresses, and 12-bit page offsets.
The page table for the current process is shown below in hexadecimal. Each page table entry (PTE) has four control bits:
V: the page is a valid part of the process address space P: the page is present in RAM
R: the page has been referenced while in RAM
M: the page has been modified while in RAM
VPRM Frame
——- —– [0]:0000 00000 [1]:1110 00053 [2]:1010 00052 [3]:1111 00051 [4]:1011 00054 [5]:0000 00000 [6]:0000 00050 [7]:0000 00051
VPRM
——- [8]:0000 [9]:0000 [a]:0000 [b]:1110 [c]:1111 [d]:1000 [e]:1010 [f]:1010
Frame
—–
00052
00051
00051
00050
00054
00000
00000
00000
of five page frames: frames 00050,
The current process has a fixed allocation 00051, 00052, 00053 and 00054 hexadecimal.
21. Consider the information in Figure 6. Assume that the current program executes a “Load” instruction which references virtual address d5e0. Which of the following statements about the processing of that reference is correct?
A) The system processed a page fault.
B) The virtual address was mapped to the physical address 000525e0. C) After executing the instruction, the M bit of PTE d equals 0.
D) All of the above.
E) None of the above.
22. Consider the information in Figure 6. Assume that the current program executes a “Store” instruction which references virtual address 9b58. Which of the following statements about the processing of that reference is correct?
A) The system copied 4096 bytes from RAM to disk.
B) The system copied 4096 bytes from disk to RAM.
C) After executing the instruction, the M bit of PTE 9 equals 1. D) All of the above.
E) None of the above.
23. Consider the information in Figure 6. Assume that the current program executes a “Load” instruction which references virtual address 31dc. Which of the following statements about the processing of that reference is correct?
A) The system copied 4096 bytes from RAM to disk.
B) The system copied 4096 bytes from disk to RAM.
C) After executing the instruction, the M bit of PTE 3 equals 1. D) All of the above.
E) None of the above.
##############
# Figure 7 #
##############
A byte-oriented virtual memory system which uses demand paging (without a TLB) has the following characteristics: 16-bit virtual addresses, 32-bit physical addresses, and 12-bit page offsets.
The page table for the current process is shown below in hexadecimal. Each page table entry (PTE) has four control bits:
V: the page is a valid part of the process address space P: the page is present in RAM
R: the page has been referenced while in RAM
M: the page has been modified while in RAM
VPRM Frame
——- —– [0]:0000 00000 [1]:1010 00070 [2]:1010 00074 [3]:1111 00070 [4]:1111 00074 [5]:0000 00000 [6]:0000 00070 [7]:0000 00071
VPRM
——- [8]:0000 [9]:0000 [a]:0000 [b]:1111 [c]:1010 [d]:1111 [e]:1111 [f]:1010
Frame
—–
00072
00000
00071
00071
00074
00073
00072
00070
of five page frames: frames 00070,
The current process has a fixed allocation 00071, 00072, 00073 and 00074 hexadecimal.
24. Consider the information in Figure 7. Assume that the current program executes a “Store” instruction which references virtual address b7f8. Which of the following statements about the processing of that reference is correct?
A) The system processed a page fault.
B) The virtual address was mapped to the physical address 000717f8. C) After executing the instruction, the R bit of PTE b equals 0.
D) All of the above.
E) None of the above.
25. Consider the information in Figure 7. Assume that the current program executes a “Load” instruction which references virtual address ea80. Which of the following statements about the processing of that reference is correct?
A) The system copied 4096 bytes from RAM to disk.
B) The system copied 4096 bytes from disk to RAM.
C) After executing the instruction, the M bit of PTE e equals 0. D) All of the above.
E) None of the above.
26. Consider the information in Figure 7. Assume that the current program executes a “Store” instruction which references virtual address c6c4. Which of the following statements about the processing of that reference is correct?
A) The system copied 4096 bytes from RAM to disk.
B) The system copied 4096 bytes from disk to RAM.
C) After executing the instruction, the M bit of PTE c equals 1. D) All of the above.
E) None of the above.
##############
# Figure 8 #
##############
A byte-oriented virtual memory system uses a two-level page table. The top level of the page table is the Page Directory, where each entry in the Page Directory is 4 bytes wide. The second level of the page table consists of zero or more Page Maps, where each entry in a Page Map is 4 bytes wide.
The system has a page size of 1024 bytes, and there is no internal fragmentation in the pages which hold the page table.
27. Consider the information in Figure 8. Assuming that a virtual address consists of an index into the Page Directory, and index into a Page Map, and a
page offset, what is the correct
A) 8 bits, 8 bits, 10 bits B) 8 bits, 9 bits, 10 bits C) 9 bits, 8 bits, 10 bits D) 9 bits, 9 bits, 10 bits E) None of the above.
28. Consider the information in
contains 8 entries which are flagged as valid, how many pages are currently allocated to hold the page table?
A) 7 pages
B) 8 pages
C) 9 pages
D) 256 pages
E) None of the above.
29. Which of the following statements about computer networks is correct?
A) Both guided and unguided transmission media can be used in the same residential access network.
B) Packet switching uses store-and-forward to prevent packet loss.
C) Circuit switching reserves resources during a session to maximize resource
utilization.
D) All of the above.
E) None of the above.
30. Which of the following statements about the Internet protocol stack is
correct?
A) The transport layer moves application-layer messages between systems. B) The network layer moves transport-layer segments between systems.
C) The link layer moves network-layer datagrams between systems.
D) All of the above.
E) None of the above.
division of a virtual address into fields?
Figure 8. Assuming that the Page Directory