Operating Systems CMPSC 473
CPU/memory virtualization February 16, 2021 – Lecture 8 Instructor: Bhuvan Urgaonkar
Carnegie Mellon
Administrative
¢ New Piazza etiquette: when you post a question, you MUST include the following two pieces of information to get a response from the teaching staff:
§ What did you do to address the problem and what did you learn (or not learn) from these efforts?
§ e.g., “I copied my error message ‘…: Permission denied’ on google and looked at the first 3 webpages returned. They said something about using ‘chmod +x …’ but I don’t know what that means”
§ What is your best guess at the cause of the problem you are facing and what the solution might involve
§ e.g., “My best guess is that I do not have permissions to execute … file and there must be a way to turn the right permissions on”
Carnegie Mellon
Administrative
¢ Project 1 due tonight
§ 1 day late => 20% penalty
§ Further delay => 0 grade
§ In case you had to take an extension
§ You will be assigned some alternative work since we will release solutions soon; please be in touch with us
Carnegie Mellon
Administrative
¢ Project 2 to be released tonight
§ Implement your own malloc/free
§ Multiple deadlines to help keep you on track + discourage cheating § Checkpoint 1: Feb 28
§ Checkpoint 2: Mar 6
§ Final submission: Mar 12
§ PLEASE DO NOT CHEAT – SEVERE PENALTY FOR STUDENTS INVOLVED AND HASSLE FOR TEACHING STAFF!!
§ No sharing of code with other groups
§ No use of code found online without understanding it and acknowledging it § Multiple forms of checking for plagiarism will be carried out
§ If in doubt, contact us ASAP
§ Your best friends are: § Good habits:
– Code a bit every day; test after every few lines of new code; use gdb § Chapter 9 of CSAPP + Lectures 6-7
§ Your partner – pair programming is awesome!
§ Office hours
Carnegie Mellon
Some general tips ¢ Learn to use man pages
§ Will be covered in tonight’s tutorial ¢ Do go over all tutorials
§ 2 offered already, 2 more coming up
¢ Make extensive use of information on the Web § Google is your friend!
§ Wikipedia
§ Stackoverflow § Quora
§ GeeksforGeeks §…
Carnegie Mellon
Quiz 8.1
¢ What will the following program output on a 64-bit machine?
#include
#include
main () {
printf (“size of int: %d\n”, sizeof (int)); printf (“size of int *: %d\n”, sizeof (int *)); printf (“size of int **: %d\n”, sizeof (int **)); printf (“size of char: %d\n”, sizeof (char)); printf (“size of char *: %d\n”, sizeof (char *));
}
Carnegie Mellon
Quiz 8.2
#include
#include
main () {
char *c;
c = (char *) malloc (sizeof (char));
c[0] = ‘a’;
c[1] = ‘b’;
}
¢ Which of the following statements accurately describes the behavior of the above program?
§ It will encounter a segmentation fault
§ It will not encounter a segmentation fault
§ It may encounter a segmentation fault (it depends)
Carnegie Mellon
Quiz 8.3
#include
#include
int main () {
int i;
char *c;
c = (char *) malloc (sizeof (char)); while (1) {
c[i] = ‘c’;
printf (“succeeded in writing to c[%d]\n”, i++); }
}
¢ Which of the following statements accurately describes the behavior of the above program?
§ It will encounter a segmentation fault
§ It will not encounter a segmentation fault
§ It may encounter a segmentation fault (it depends)
Carnegie Mellon
Quiz 8.3 (contd.)
Carnegie Mellon
Quiz 8.4
#include
#include
int main () {
char *a, *b;
int *c, *d;
a = (char *) malloc (sizeof (char));
b = (char *) malloc (sizeof (char));
printf (“Address of a: %p; address of b: %p\n”, a, b); c = (int *) malloc (sizeof (int));
d = (int *) malloc (sizeof (int));
printf (“Address of c: %p; address of d: %p\n”, c, d);
}
¢ What gaps do you expect to see between the virtual Error in recorded lecture: In
addresses for a vs b? c vs d?
responding to a student question, I said 32 bytes instead of 32 bits
Carnegie Mellon
A System Using Virtual Addressing
Physical address (PA)
4
Carnegie Mellon
CPU Chip
Main memory
0: 1: 2: 3: 4: 5: 6: 7: 8:
M-1:
Virtual address
CPU (VA) MMU 4100
Data word
…
Why Virtual Memory (VM)? ¢ Uses main memory efficiently
§ Use DRAM as a cache for parts of a virtual address space ¢ Simplifies memory management
§ Each process gets the same uniform linear address space
¢ Isolates address spaces
§ One process can’t interfere with another’s memory
§ User program cannot access privileged kernel information and code
Carnegie Mellon
VM as a Tool for Caching
¢ Conceptually, virtual memory is an array of N contiguous bytes stored on disk.
¢ The contents of the array on disk are cached in physical memory (DRAM cache)
§ These cache blocks are called pages (size is P = 2p bytes)
Carnegie Mellon
Unallocated
Cached
Uncached
Unallocated
Cached
Uncached
Cached
Uncached
VP 0 VP 1
0
Virtual memory
Physical memory
0
PP 0 PP 1
PP 2m-p-1
Empty
Empty
Empty
VP 2n-p-1
M-1
Virtual pages (VPs) stored on disk
Physical pages (PPs) cached in DRAM
N-1
DRAM Cache Organization
¢ DRAM cache organization driven by the enormous miss penalty § DRAM is about 10x slower than SRAM
§ Disk is about 10,000x slower than DRAM
¢ Consequences
§ Large page (block) size: typically 4 KB, sometimes 4 MB § Fully associative
§ Any VP can be placed in any PP
§ Requires a “large” mapping function – different from cache memories § Highly sophisticated, expensive replacement algorithms
§ Too complicated and open-ended to be implemented in hardware § Write-back rather than write-through
Carnegie Mellon
Enabling Data Structure: Page Table
¢ A page table is an array of page table entries (PTEs) that maps virtual pages to physical pages.
§ Per-process kernel data structure in DRAM
Carnegie Mellon
VP 1
VP 2
VP 7
VP 4
Valid
PTE 0
Physical page number or disk address
Physical memory (DRAM)
PP 0
PP 3
0
null
1
1
0
1
0
null
0
1
PTE 7
Virtual memory (disk)
VP 1
VP 2
VP 3
VP 4
VP 6
VP 7
Memory resident page table (DRAM)
Page Hit
¢ Page hit: reference to VM word that is in physical memory (DRAM cache hit)
Carnegie Mellon
Virtual address
Physical page number or disk address
Physical memory (DRAM)
PP 0
PP 3
VP 1
VP 2
VP 7
VP 4
Valid
PTE 0
0
null
1
1
0
1
0
null
0
1
PTE 7
Virtual memory (disk)
VP 1
VP 2
VP 3
VP 4
VP 6
VP 7
Memory resident page table (DRAM)
Page Fault
¢ Page fault: reference to VM word that is not in physical memory (DRAM cache miss)
Carnegie Mellon
Virtual address
Physical page number or disk address
Physical memory (DRAM)
VP 1
VP 2
VP 7
VP 4
Valid
PTE 0
PP 0
PP 3
0
null
1
1
0
1
0
null
0
1
PTE 7
Virtual memory (disk)
VP 1
VP 2
VP 3
VP 4
VP 6
VP 7
Memory resident page table (DRAM)
Handling Page Fault
¢ Pagemisscausespagefault(anexception)
Carnegie Mellon
Virtual address
Physical page number or disk address
Physical memory (DRAM)
VP 1
VP 2
VP 7
VP 4
Valid
PTE 0
PP 0
PP 3
0
null
1
1
0
1
0
null
0
1
PTE 7
Virtual memory (disk)
VP 1
VP 2
VP 3
VP 4
VP 6
VP 7
Memory resident page table (DRAM)
Handling Page Fault
¢ Pagemisscausespagefault(anexception)
¢ Pagefaulthandlerselectsavictimtobeevicted(hereVP4)
Carnegie Mellon
Virtual address
Physical page number or disk address
Physical memory (DRAM)
VP 1
VP 2
VP 7
VP 4
Valid
PTE 0
PP 0
PP 3
0
null
1
1
0
1
0
null
0
1
PTE 7
Virtual memory (disk)
VP 1
VP 2
VP 3
VP 4
VP 6
VP 7
Memory resident page table (DRAM)
Handling Page Fault
¢ Pagemisscausespagefault(anexception)
¢ Pagefaulthandlerselectsavictimtobeevicted(hereVP4)
Carnegie Mellon
Virtual address
Physical page number or disk address
Physical memory (DRAM)
VP 1
VP 2
VP 7
VP 3
Valid
PTE 0
PP 0
PP 3
0
null
1
1
1
0
0
null
0
1
PTE 7
Virtual memory (disk)
VP 1
VP 2
VP 3
VP 4
VP 6
VP 7
Memory resident page table (DRAM)
Handling Page Fault
¢ Pagemisscausespagefault(anexception)
¢ Pagefaulthandlerselectsavictimtobeevicted(hereVP4)
¢ Offendinginstructionisrestarted:pagehit!
Physical memory (DRAM)
Virtual address
Physical page number or disk address
PP 0
PP 3
Carnegie Mellon
VP 1
VP 2
VP 7
VP 3
Valid
PTE 0
0
null
1
1
1
0
0
null
0
1
Virtual memory (disk)
PTE 7
VP 1
VP 2
VP 3
VP 4
VP 6
VP 7
Key point: Waiting until the miss to copy the page to DRAM is known as demand paging
Memory resident page table (DRAM)
Allocating Pages
¢ Allocating a new page (VP 5) of virtual memory.
Physical page number or disk address
Physical memory (DRAM)
Carnegie Mellon
VP 1
VP 2
VP 7
VP 3
Valid
PTE 0
PP 0
PP 3
0
null
1
1
1
0
0
0
1
Virtual memory (disk)
PTE 7
VP 1
VP 2
VP 3
VP 4
VP 5
VP 6
VP 7
Memory resident page table (DRAM)
VM as a Tool for Memory Management
¢ Key idea: each process has its own virtual address space § It can view memory as a simple linear array
§ Mapping function scatters addresses through physical memory
§ Well-chosen mappings can improve locality
Virtual Address
0
Address 0 translation
Physical Address Space (DRAM)
(e.g., read-only library code)
Carnegie Mellon
PP 2
PP 6
PP 8
VP 1
Space for Process 1:
VP 2
Virtual Address
Space for Process 2:
N-1 0
…
VP 1
VP 2
…
N-1
M-1
…
VM as a Tool for Memory Management
¢ Simplifying memory allocation
§ Each virtual page can be mapped to any physical page
§ A virtual page can be stored in different physical pages at different times
¢ Sharing code and data among processes
§ Map virtual pages to the same physical page (here: PP 6)
Virtual Address
0
Address 0 translation
Physical Address Space (DRAM)
(e.g., read-only library code)
Carnegie Mellon
PP 2
PP 6
PP 8
VP 1
Space for Process 1:
VP 2
Virtual Address
Space for Process 2:
N-1 0
…
VP 1
VP 2
…
N-1
M-1
…
Simplifying Linking and Loading ¢ Linking
Memory invisible to user code
§ Each program has similar virtual %rsp address space (stack
Carnegie Mellon
Kernel virtual memory
User stack (created at runtime)
Memory-mapped region for shared libraries
Run-time heap (created by malloc)
Read/write segment (.data, .bss)
Read-only segment (.init, .text, .rodata)
Unused
§ Code, data, and heap always start at the same addresses.
¢ Loading
§ execve allocates virtual pages for .text and .data sections & creates PTEs marked as invalid
§The.text and.data sections are copied, page by page, on demand by the virtual memory system
0x400000
pointer)
brk
Loaded from
the executable file
0
VM as a Tool for Memory Protection ¢ Extend PTEs with permission bits
¢ MMU checks these bits on each access
Process i:
VP 0: VP 1: VP 2:
Process j:
VP 0: VP 1: VP 2:
SUP READ
WRITE
EXEC
Address
Physical Address Space
Carnegie Mellon
No
Yes
No
Yes
PP 6
No
Yes
Yes
Yes
PP 4
Yes
Yes
Yes
No
PP 2
PP 2
PP 4
PP 6
PP 8
PP 9
PP 11
• SUP READ WRITE EXEC
Address
No
Yes
No
Yes
PP 9
Yes
Yes
Yes
Yes
PP 6
No
Yes
Yes
Yes
PP 11
VM Address Translation ¢ Virtual Address Space
§ V = {0, 1, …, N–1}
¢ Physical Address Space
§ P = {0, 1, …, M–1}
¢ Address Translation §MAP: V® P U {Æ} § For virtual address a:
§ MAP(a) = a’ if data at virtual address a is at physical address a’ in P § MAP(a) = Æ if data at virtual address a is not in physical memory
– Either invalid or stored on disk
Carnegie Mellon
Summary of Address Translation Symbols
¢ Basic Parameters
§ N = 2n : Number of addresses in virtual address space
§ M = 2m : Number of addresses in physical address space § P = 2p : Page size (bytes)
¢ Components of the virtual address (VA) § TLBI: TLB index
§ TLBT: TLB tag
§ VPO: Virtual page offset
§ VPN: Virtual page number
¢ Components of the physical address (PA) § PPO: Physical page offset (same as VPO)
§ PPN: Physical page number
Carnegie Mellon
Address Translation With a Page Table
Virtual address
n-1
Page table
p p-1 0
Carnegie Mellon
Page table base register (PTBR)
Virtual page number (VPN)
Virtual page offset (VPO)
Physical page table address for the current process
Valid bit = 0: Page not in memory (page fault)
Valid bit = 1
m-1
Physical address
Valid
Physical page number (PPN)
p p-1 0
Physical page number (PPN)
Physical page offset (PPO)
Address Translation: Page Hit
2
PTEA PTE 3
PA
4
Carnegie Mellon
CPU Chip
CPU
1
VA
MMU
1) Processor sends virtual address to MMU
2-3) MMU fetches PTE from page table in memory 4) MMU sends physical address to cache/memory 5) Cache/memory sends data word to processor
Data
5
Cache/ Memory
Address Translation: Page Fault
Carnegie Mellon
Exception
4
2
PTEA PTE
3
Page fault handler
Victim page
5
New page
6
CPU Chip
CPU
1
VA
7
MMU
Cache/ Memory
Disk
1) Processor sends virtual address to MMU
2-3) MMU fetches PTE from page table in memory
4) Valid bit is zero, so MMU triggers page fault exception
5) Handler identifies victim (and, if dirty, pages it out to disk)
6) Handler pages in new page and updates PTE in memory
7) Handler returns to original process, restarting faulting instruction
Locality to the Rescue!
¢ Virtual memory works because of locality
¢ At any point in time, programs tend to access a set of active virtual pages called the working set
§ Programs with better temporal locality will have smaller working sets
¢ If (working set size < main memory size)
§ Good performance for one process after compulsory misses
¢ If ( SUM(working set sizes) > main memory size )
§ Thrashing: Performance meltdown where pages are swapped (copied) in and out continuously
Carnegie Mellon
Integrating VM and Cache
PTE
PTEA
PTE
Carnegie Mellon
CPU Chip
VA
MMU
PA
PTEA hit
PTEA miss
PA miss
PA hit
PTEA
CPU
Memory
PA
Data
Data
L1 cache
VA: virtual address, PA: physical address, PTE: page table entry, PTEA = PTE address
Speeding up Translation with a TLB
¢ Page table entries (PTEs) are cached in L1 like any other memory word
§ PTEs may be evicted by other data references § PTE hit still requires a small L1 delay
¢ Solution: Translation Lookaside Buffer (TLB)
§ Small set-associative hardware cache in MMU
§ Maps virtual page numbers to physical page numbers
§ Contains complete page table entries for small number of pages
Carnegie Mellon
Accessing the TLB
¢ MMU uses the VPN portion of the virtual address to access the TLB:
T = 2t sets
p p-1 0
TLBT matches tag of line within set
VPN n-1 p+t p+t-1
Carnegie Mellon
TLB tag (TLBT)
TLB index (TLBI)
VPO
v tag PTE v tag PTE
Set 0 Set 1
Set T-1
TLBI selects the set
v tag PTE v tag PTE
v tag PTE v tag PTE
…
TLB Hit
Carnegie Mellon
CPU Chip
TLB
PTE
3
2
VPN
CPU
1
VA
MMU
PA
4
Cache/ Memory
Data
5
A TLB hit eliminates a memory access
TLB Miss
Carnegie Mellon
CPU Chip
TLB
2
VPN
CPU
1
VA
MMU
4
PTE
3
PTEA
PA
5
Data
6
A TLB miss incurs an additional memory access (the PTE)
Fortunately, TLB misses are rare. Why?
Cache/ Memory
Multi-Level Page Tables ¢ Suppose:
§ 4KB (212) page size, 48-bit address space, 8-byte PTE
Level 2 Tables
Carnegie Mellon
¢ Problem:
§ Would need a 512 GB page table!
Level 1 Table
§248 *2-12 *23 =239 bytes
¢ Common solution: Multi-level page table
¢ Example: 2-level page table
§ Level 1 table: each PTE points to a page table (always
memory resident)
§ Level 2 table: each PTE points to a page (paged in and out like any other data)
…
…
A Two-Level Page Table Hierarchy
Level 1 page table
Level 2 page tables
Virtual memory
0
Carnegie Mellon
VP 0
…
VP 1023
VP 1024
…
VP 2047
Gap
1023 unallocated pages
VP 9215
PTE 0
…
PTE 1023
PTE 0
2K allocated VM pages for code and data
PTE 1
PTE 2 (null)
PTE 3 (null)
PTE 4 (null)
PTE 0
…
PTE 1023
PTE 5 (null)
PTE 6 (null)
6K unallocated VM pages
PTE 7 (null)
PTE 8
1023 null PTEs
(1K – 9) null PTEs
PTE 1023
32 bit addresses, 4KB pages, 4-byte PTEs
1023 unallocated pages
1 allocated VM page for the stack
…
Translating with a k-level Page Table
Page table base register (PTBR)
n-1
VIRTUAL ADDRESS Level 2
p-1 0
Carnegie Mellon
VPN 1
VPN 2
…
VPN k
VPO
Level 1 page table
page table
…
…
Level k page table
PPN
m-1
p-1 0
PPN
PPO
PHYSICAL ADDRESS
Next
¢ Simple memory system example ¢ Memory mapping
Carnegie Mellon
Review of Symbols
¢ Basic Parameters
§ N = 2n : Number of addresses in virtual address space
§ M = 2m : Number of addresses in physical address space §P=2p :Pagesize(bytes)
¢ Components of the virtual address (VA) § TLBI: TLB index
§ TLBT: TLB tag
§ VPO: Virtual page offset
§ VPN: Virtual page number
¢ Components of the physical address (PA) § PPO: Physical page offset (same as VPO)
§ PPN: Physical page number
§ CO: Byte offset within cache line
§ CI: Cache index § CT: Cache tag
Carnegie Mellon
Simple Memory System Example
¢ Addressing
§ 14-bit virtual addresses § 12-bit physical address § Page size = 64 bytes
13 12 11 10 9 8 7 6 5 4 3 2 1 0 VPN VPO
Virtual Page Number Virtual Page Offset
11 10 9 8 7 6 5 4 3 2 1 0
PPN PPO
Physical Page Number
Carnegie Mellon
Physical Page Offset
1. Simple Memory System TLB ¢ 16 entries
¢ 4-way associative
TLBT TLBI
Decides the set
Carnegie Mellon
13 12 11 10 9 8 7 6 5 4 3 2 1 0 VPN VPO
Set
Tag
PPN
Valid
Tag
PPN
Valid
Tag
PPN
Valid
Tag
PPN
Valid
0
03
–
0
09
0D
1
00
–
0
07
02
1
1
03
2D
1
02
–
0
04
–
0
0A
–
0
2
02
–
0
08
–
0
06
–
0
03
–
0
3
07
–
0
03
0D
1
0A
34
1
02
–
0
2. Simple Memory System Page Table
Only show first 16 entries (out of 256)
Carnegie Mellon
VPN
PPN
Valid
00
28
1
01
–
0
02
33
1
03
02
1
04
–
0
05
16
1
06
–
0
07
–
0
VPN
PPN
Valid
08
13
1
09
17
1
0A
09
1
0B
–
0
0C
–
0
0D
2D
1
0E
11
1
0F
0D
1
3. Simple Memory System Cache
¢ 16 lines, 4-byte block size ¢ Physically addressed
¢ Direct mapped
CT CI CO 11 10 9 8 7 6 5 4 3 2 1 0
PPN PPO
Carnegie Mellon
Idx
Tag
Valid
B0
B1
B2
B3
0
19
1
99
11
23
11
1
15
0
–
–
–
–
2
1B
1
00
02
04
08
3
36
0
–
–
–
–
4
32
1
43
6D
8F
09
5
0D
1
36
72
F0
1D
6
31
0
–
–
–
–
7
16
1
11
C2
DF
03
Idx
Tag
Valid
B0
B1
B2
B3
8
24
1
3A
00
51
89
9
2D
0
–
–
–
–
A
2D
1
93
15
DA
3B
B
0B
0
–
–
–
–
C
12
0
–
–
–
–
D
16
1
04
96
34
15
E
13
1
83
77
1B
D3
F
14
0
–
–
–
–
Address Translation Example #1 Virtual Address: 0x03D4
TLBT TLBI
13 12 11 10 9 8 7 6 5 4 3 2 1 0
VPN ___ TLBI ___ TLBT ____
TLB Hit? __
Page Fault? __ PPN: ____
Y
Carnegie Mellon
0
0
0
0
1
1
1
1
0
1
0
1
0
0
VPN
0x0F 0x3 0x03
Physical Address
VPO
N 0x0D
CT CI CO
11 10 9 8 7 6 5 4 3 2 1 0
0
0
1
1
0
1
0
1
0
1
0
0
PPN
PPO
0 0x5 0x0D
Y
0x36
CO ___ CI___ CT ____
Hit? __
Byte: ____
Address Translation Example #2 Virtual Address: 0x0020
TLBT TLBI
13 12 11 10 9 8 7 6 5 4 3 2 1 0
VPN VPO
0x00 0 0x00 N N 0x28
Physical Address
CT CI CO
11 10 9 8 7 6 5 4 3 2 1 0
PPN PPO
Carnegie Mellon
0
0
0
0
0
0
0
0
1
0
0
0
0
0
VPN ___ TLBI ___ TLBT ____ TLB Hit? __ Page Fault? __ PPN: ____
1
0
1
0
0
0
1
0
0
0
0
0
0 0x8 0x28 N Mem
CO___ CI___ CT ____ Hit? __ Byte: ____
Next Topics
¢ Simple memory system example ¢ Memory mapping
Carnegie Mellon
Memory Mapping
¢ VM areas initialized by associating them with disk objects.
§ Process is known as memory mapping.
¢ Area can be backed by (i.e., get its initial values from) : § Regular file on disk (e.g., an executable object file)
§ Initial page bytes come from a section of a file § Anonymous file (e.g., nothing)
§ First fault will allocate a physical page full of 0’s (demand-zero page) § Once the page is written to (dirtied), it is like any other page
¢ Dirty pages are copied back and forth between memory and a special swap file.
Carnegie Mellon
Sharing Revisited: Shared Objects
Process 1 virtual memory
Physical memory
Process 2 virtual memory
¢ Process 1 maps the shared
object.
Carnegie Mellon
Shared object
Sharing Revisited: Shared Objects
Process 1 virtual memory
Physical memory
Process 2 virtual memory
¢ Process 2 maps the shared
object.
¢ Notice how the virtual
addresses can be different.
Carnegie Mellon
Shared object
Sharing Revisited:
Private Copy-on-write (COW) Objects
Process 1 virtual memory
Physical memory
Process 2 virtual memory
Private copy-on-write area
¢ Two processes mapping a private copy-on-write (COW) object.
¢ Area flagged as private copy-on- write
¢ PTEs in private areas are flagged as read-only
Carnegie Mellon
Private copy-on-write object
Sharing Revisited:
Private Copy-on-write (COW) Objects
Process 1 virtual memory
Physical Process 2 memory virtual memory
¢ Instruction writing to private page triggers protection fault.
¢ Handler creates new R/W page.
¢ Instruction restarts upon handler return.
¢ Copying deferred as long as
possible!
Carnegie Mellon
Copy-on-write
Write to private copy-on-write page
Private copy-on-write object
The fork System Call
¢ VM and memory mapping explain how fork provides private
address space for each process.
¢ To create virtual address for new new process
§ Create exact copies of current mm_struct, vm_area_struct, and page tables.
§ Flag each page in both processes as read-only
§ Flag each vm_area_struct in both processes as private COW
¢ On return, each process has exact copy of virtual memory
¢ Subsequent writes create new pages using COW mechanism.
Carnegie Mellon
The execve System Call Private, demand-zero
¢
Toloadandrunanew program a.out in the
libc.so
current process using execve:
Carnegie Mellon
User stack
Memory mapped region for shared libraries
Runtime heap (via malloc)
Uninitialized data (.bss)
Initialized data (.data)
Program text (.text)
.data
.text
Shared, file-backed
¢
¢
Free vm_area_struct’s and page tables for old areas
Createvm_area_struct’s and page tables for new areas
§ Programs and initialized data backed by object files.
§ .bss and stack backed by anonymous files .
SetPCtoentrypointin
.text
§ Linux will fault in code and data pages as needed.
a.out
Private, demand-zero Private, demand-zero
Private, file-backed
.data
.text
0
¢
User-Level Memory Mapping
void *mmap(void *start, int len,
int prot, int flags, int fd, int offset)
¢ Map len bytes starting at offset offset of the file specified by file description fd, preferably at address start
§ start: may be 0 for “pick an address”
§ prot: PROT_READ, PROT_WRITE, …
§ flags: MAP_ANON, MAP_PRIVATE, MAP_SHARED, …
¢ Return a pointer to start of mapped area (may not be start)
Carnegie Mellon
User-Level Memory Mapping
void *mmap(void *start, int len,
int prot, int flags, int fd, int offset)
Carnegie Mellon
len bytes offset
(bytes)
len bytes start
(or address chosen by kernel)
0
0
Disk file specified by file descriptor fd
Process virtual memory
Example: Using mmap to Copy Files
¢ Copying a file to stdout without transferring data to user space .
Carnegie Mellon
#include “csapp.h”
void mmapcopy(int fd, int size)
{
/* Ptr to memory mapped area */
char *bufp;
bufp = Mmap(NULL, size,
PROT_READ,
MAP_PRIVATE,
fd, 0);
Write(1, bufp, size);
return; }
mmapcopy.c
/* mmapcopy driver */
int main(int argc, char **argv)
{
struct stat stat;
int fd;
/* Check for required cmd line arg */
if (argc != 2) {
printf(“usage: %s
argv[0]);
exit(0);
}
/* Copy input file to stdout */
fd = Open(argv[1], O_RDONLY, 0);
Fstat(fd, &stat);
mmapcopy(fd, stat.st_size);
exit(0);
}
mmapcopy.c