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CSCI 2500 — Computer Organization
Group Project (document version 1.2) — Due 7 May 2021 MIPS Processor in C
This project is due by the Midnight EST on the above date via a Submitty gradeable. This project is a group assignment. You can have groups of up to four people.
Start the project early. You can ask questions during office hours, in the Submitty forum, and during your lab session.
NOTE: This document will change in the coming weeks. Project Overview
For the group project, we’ll be taking Lab 5 and Homework 5 to the logical conclusion – you’ll be implementing a full gate-level circuit representing the datapath for a reduced, but still Turing complete, MIPS ISA. While we have already developed our ALU, the rest of the datapath and control needs to be implemented. For most of the instructions and datapath, implementation details are provided in depth throughout the Chapter 4 slides as well as the book. However, another aspect of the project will be to expand on the provided datapath by developing your own implementations for a few other instructions. See the template file (project.c) for more details.
2 Supported Instructions
Our ISA will include the following instructions:
Instruction Type
Description
Input format
Operation
lw reg1 = M[reg2+offset] sw M[reg2+offset] = reg1
beq if (reg1 == reg2) PC += offset addi reg1 = reg2 + constant
and reg1 = reg2 & reg3 or reg1 = reg2 | reg3 add reg1 = reg2 + reg3
sub reg1 = reg2 – reg3
slt reg1=(reg2