1. Virtual Memory.
COMP 2432 Operating Systems Tutorial 9 Solution
(a) There are 24 bits for the address. It can address up to a space of 224, i.e. 16 MB.
(b) Physical memory has a size of 32KB. It needs an address length of 15 bits, since 32K = 215.
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(c) Page size (and frame size) is 2KB. It would imply an offset length n of 11 bits, since 2K = 211.
(d) Logical address length m = 24. Page offset length n = 11. Page number length is thus 2411 = 13 bits.
(e) Physical memory has a size of 32KB and each frame has a size of 2KB. Number of frames is 32K / 2K = 16. (f) There are 16 frames. Thus, 4 bits are needed for frame number, since 16 = 24. Alternatively, physical address
has a length of 15 bits. The offset length n = 11. Therefore frame number has 1511 = 4 bits. 2. Virtual Memory.
(a) 4 GB (b) 16 bits (c) 10 bits (d) 22 bits (e) 64
[64K = 216]
[1K = 210]
[64K / 1K = 64] [16 10]
(f) 6 bits
(h) 1 KB that can be fit into one single page [1M/1K 1K page table entries 1KB page table size]
[6 bits for frame number, 2 additional bits 1 byte / entry, 4G/1K pages 4M entries] 3. Page Table in Virtual Memory.
PageRef 1 3 0 Frame1 1 1 1 Frame2 – 3 3 Frame3 – – 0 Frame4 – – –
Virtual memory 0A 1B 2C
2 3 5 1 5 0 4 1 1 5 5 5 5 5 3 3 3 1 1 1 1 0 0 0 0 0 0 4 2 2 2 2 2 2 2
G 7 i 42F 7H
4. Memory Access Time.
Effective memory access time = cache access time + (2 – h) memory access time. With h = 0.95, we have 20 + (2 – 0.95) 100 = 125 ns.
With h = 0.99, we have 20 + (2 – 0.99) 100 = 121 ns.
Effective virtual memory access time = (1 – f) memory access time + f page fault service time. Note that without TLB, memory access time is 200 ns = 0.2 s.
With f = 0.01, we have (1–0.01) 0.2 + 0.01 5000 = 50.198 s.
With f = 0.001, we have (1–0.001) 0.2 + 0.001 5000 = 5.1998 s.
Making use of the adjusted memory access time with TLB, when page fault rate is 1% and TLB hit rate of 95%, effective virtual memory access time = (1–0.01) 0.125 + 0.01 5000 = 50.1238 s.
When page fault rate is 0.1% and TLB hit rate of 99%, effective virtual memory access times and (1–0.001) 0.121 + 0.001 5000 = 5.12088 s. It can be seen that the impact of TLB is much smaller in this amortized cost computation. In real scenario, the page fault service time could largely be absorbed by the waiting time for CPU scheduling, in particular with round-robin scheduling.
Physical memory 0 i 11B
Page table 1 11 v
2 35v 24 E memory 3D3i frames
5F 542v 35C 66i
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