Computer Architecture ELEC3441
Lecture 5 – Pipelining
Dr. Hayden Kwok-Hay So
Department of Electrical and Electronic Engineering
RISC vs CISC – Iron Law
CPUTime = # of instruction × # of cycle × time program instruction cycle
L4 L5,6
HKUEEE ENGG3441 – HS
2
Microarchitecture
CPI
Cycle Time
CISC
>1
short
RISC – single cycle unpipelined
1
long
RISC – pipelined
1
short
Pipeline Motivation – Buying
Food from Canteen
Slow 2 customers Order Food Drink Order Food Drink
n Getting food from canteen involves 3 steps:
• Place order (P)
• Pickup food (F)
• Pickup drink (D)
n If there is only 1 customer: • PèFèD
1 customer Order Food Drink
time
n How to serve 2 customer?
HKUEEE ENGG3441 – HS 3
Food Ordering – Pipeline
Pre-requisite: All steps must be able to operate independently in parallel
4 customers (pipeline)
4 customers (no pipeline)
PFD PFD
PFD PFD
PFDPFDPFDPFD
n Serving one after oneèSlow:
• Assume each step take 1 unit of time, then
• N customersè3N units of time
n Better solution: Pipeline
• Overlap different steps in parallel
• N customersè2 + N units of time
HKUEEE ENGG3441 – HS 4
time
Pipeline Observations:
4 customers (unbalanced pipeline)
4 customers (pipeline)
4 customers (no pipeline)
PFD PFD PFDPFD
PFDPFD PFDPFD
PFDPFDPFDPFD
time
n All “stages” (P, F, D) are busy all the time • Non-pipeline: busy 1/3 of the time
n Balanced pipeline: 1 customer per 1 unit of time
n The longest stage dictates the overall performance
• 1 customer per time-of-longest-stage
• Balanced delay on each stageèbest performance
HKUEEE ENGG3441 – HS 5
2 Views of Pipeline
Customer 0 Customer 1 Customer 2 Customer 3
P
F D
P F D
Timeline View
P
F D
P F D
Order (P)
Food (F)
Drink (D)
c0 c1 c2 c3
c0 c1 c0
c2 c3
c1 c2 c3
ENGG3441 – HS
Resource View
time
HKUEEE
6
Instruction Pipelining
n Recall there are 5 steps to execute 1 instruction in RISC-V
• InstructionFetch
• InstructionDecode • Execution
• Memoryoperation • WriteBack
n The 5 steps can be pipelined if they can operate independently
• è Pipeline registers • Andmore…
HKUEEE ENGG3441 – HS 7
Pipelined Datapath
0x4
Add
we rs1
rs2
rd1 wa
wd rd2 GPRs
PC
IR
addr rdata
Inst. Memory
we addr
rdata Data
Memory wdata
Instruction Fetch
Instruction decode & Reg-fetch
ALU
Execute
Memory Access
write -back
ELEC3441 – HS
8
5-Stage Pipelined Execution
0x4
Add
we rs1
rs2
rd1 wa
wd rd2 GPRs
Decode, Reg. Fetch (ID)
we addr
rdata Data
Memory wdata
Memory (MA)
t5 t6 t7 ….
WB2
MA3 WB3
EX4 MA4 WB4
ID5 EX5 MA5 WB5
PC addr
rdata IR
Inst. Memory
I-Fetch (IF)
time
instruction1
instruction2
instruction3
instruction4
instruction5
ALU
Execute (EX)
Write -Back (WB)
t0 t1 t2 t3
IF1 ID1 EX1
IF2 ID2
MA1
EX2
IF3 ID3
IF4
ELEC3441 – HS
9
t4
WB1
MA2
EX3
ID4
IF5
0x4
Add
5-Stage Pipelined Execution
Resource Usage Diagram
we rs1
rs2
PC addr rd1 we
rdata IR ws ALU addr
wd rd2 rdata
Inst. GPRs Data
Memory wdata
Memory (MA)
time
IF
ID
EX I1I2 I4I5
MA I1 I3 I4 I5
WB I2 I3 I4 I5
ELEC3441 – HS
Memory
I-Fetch (IF)
Decode, Reg. Fetch Execute (ID) (EX)
Write -Back (WB)
t0 t1 t2 t3
t5 t6 t7 …. I5
I1 I2 I3 I4 I1 I2 I3
t4 I5 I4 I3 I2 I1
10
HKUEEE ENGG3441 – HS 11
we rs1
rs2
rd1 wa
wd rd2 GPRs
addr
inst
Inst Memory
we addr
rdata Data
Memory
Imm Select
wdata
wdata
add x1, x2, x3
lw x4, 20(x5)
ori x6, x7, 1
sub x8, x9, x10
What is wrong with this?
0x4
Data writing back to regfile is from an instruction 3 cycles ago
ALU
Add
PC
IR
HKUEEE
ENGG3441 – HS
12
Resources
sub x8, x9, 10
ori x6, x7, 1
lw x4, 20(x5)
add x1, x2, x3
decode
we rs1
rs2
rd1 wa
wd rd2 GPRs
addr
inst
Inst Memory
we addr
rdata Data
Memory
Imm Select
wdata
wdata
Pipelined RISC-V Datapath
without jumps
FDEMW
IRIR IR
0x4
PC
Add
RegWriteEn
we rs1
rs2
rd1 wa
wd rd2 GPRs
FuncSel
MemWrite
WBSel
addr
inst
Inst Memory
IR
we ALU addr
rdata
Data
Memory wdata wdata
HKUEEE
14
Imm Select
Op2Sel
ENGG3441 – HS
Control Points Need to Be Connected
Pipelined Execution Control:
0x4
PC
Add
IRIR IR
IR
A
ALU Y
n Replicate instruction register to every stage n Distributed decoding for each stage based
on the current instruction of that stage
HKUEEE ENGG3441 – HS 13
B
MD1
R
MD2
Benefit of Instruction Pipelining
CPUTime = # of instruction × # of cycle × time program instruction cycle
n When the pipeline is filled, CPI=1
n Shorter cycle time because less work to do per cycle
• In fact, more pipeline stagesè shorter cycle time
• Commercialprocessorscanhave up to 20 stages pipeline
HKUEEE ENGG3441 – HS 15
Pipeline is Difficult
Structural Data Control Hazard Hazard Hazard
n On every cycle, the hardware needs to detect and resolve all types of hazards, while keeping pipeline as filled as possible to achieve CPI=1
• In real systems, CPI suffers slightly in return for higher clock speed
n Need to make sure hardware adheres to the ISA “contract” with the programmer
… difficult but worth it…
HKUEEE ENGG3441 – HS 16
Structural Hazard
n Structural hazard arises when more than 1 pipeline stages require access to the same physical hardware
n Solutions:
1. Addextracopiesoftheresource
2. Changeresourcesothatitcanhandle concurrent use
3. Requiredifferentstagestoaccesshardwareat different time
HKUEEE
• Stall one (some) of the conflicting stages • Avoid the concurrent use
ENGG3441 – HS 17
IF
i0
i1
i2
i3
i4
i5
ID
i0
i1
i2
i3
i4
i5
EX
i0
i1
i2
i3
i4
i5
MEM
i0
i1
i2
i3
i4
i5
WB
i0
i1
i2
i3
i4
i5
Structural Hazard Ex – Memory
t0 t1 t2 t3 t4 t5 t6 t7 t8 t9
n Physically there is only 1 main memory in a computer
• Holds instruction and data
n During run-time, both IF and MEM stages need access to the main memory
• èstructural hazard
n Solution so far: “replicate” the memory
HKUEEE
• •
ENGG3441 – HS
Instruction + Data memory Reality: Inst + Data Cache
18
IF
i0
i1
i2
i3
i4
i5
ID
i0
i1
i2
i3
i4
i5
EX
i0
i1
i2
i3
i4
i5
MEM
i0
i1
i2
i3
i4
i5
WB
i0
i1
i2
i3
i4
i5
HKUEEE ENGG3441 – HS 20
Structural Hazard Ex – Regfile
t0 t1 t2 t3 t4 t5 t6 t7 t8 t9
n Physically there is only 1 register file
n During run-time, there are chances that both ID and WB stages need access to the regfile
• ID: read regfile (rs1, rs2)
• WB: write regfile (rd) • èstructural hazard
n Solution so far: regfile supports concurrent read and write
HKUEEE
ENGG3441 – HS 19
Data Hazard
n Data hazard arises when pipeline stages access data location in ways that are incompatible with the ISA contract with the programmer
n Technically 3 types of hazards
• Read After Write hazards (RAW)
• Write After Read hazards (WAR)
• Write After Write hazards (WAW)
n What may go wrong?
• RAW: a later read happens before an earlier write
• WAR: a later write happens before an earlier read
• WAW: a later write happens before an earlier write
n Data hazard happens on register AND memory locations
n In our 5-stage pipeline, only RAW can happen
HKUEEE ENGG3441 – HS 21
RAW
x1ßx0 + 10 x4ßx1 + 17 x4ßx2 + x3 x2ßx4 + 1
WAW
WAR
Data Hazard Example
0x4
Add
we rs1
rs2
PC addr rd1
we ALU addr
rdata Data
Memory wdata
rdata IR wa
wd rd2
Inst. GPRs Memory
I-Fetch Decode, Reg. Fetch
Execute
(EX) (MA)
Write -Back (WB)
(IF)
time
x1ßx0 + 10 x4ßx1 + 17
(ID)
t0 t1 t2 t3 t4 t5 t6 t7 ….
IF1 ID1 EX1 MA1 WB1
IF2 ID2 EX2 MA2 WB2
ELEC3441 – HS
22
Memory
writes val of x1
new val of x1 calculated
old val of x1 read
Resolving Data Hazards
n Strategy 1: Stalling
• Waitfortheresulttobeavailablebyfreezing
earlier pipeline stages
• è Interlocks
n Strategy 2: Data Forwarding
• Routedataassoonaspossibleafteritis calculated to the earlier pipeline stage
• è bypass
HKUEEE ENGG3441 – HS 23
Feedback to Resolve Hazards
FB1 FB2
FB3 FB4
stage stage 34
stage 1
stage 2
§ Later stages provide dependence information to earlier stages which can stall (or kill) instructions
• Controllingapipelineinthismannerworksprovided
the instruction at stage i+1 can complete without any interference from instructions in stages 1 to i
(otherwise deadlocks may occur)
24
Interlocks to resolve Data Hazards
Stall Condition
0x4
PC
bubble
IRIR IR 1
Add
we rs1
rs2 rd1
wa
wd rd2
GPRs
addr
inst
Inst Memory
IR
A
B
MD1
we ALU Y addr
rdata Data
Memory
R
25
…
x1 ¬ x0 + 10 x4 ¬ x1 + 17 …
wdata
Imm Select
MD2
wdata
Interlocks to resolve Data Hazards
FreSetzaellPCoantdition 2nd instruction
Send bubble in place of decoded 2nd instruction
0x4
PC
bubble
IRIR IR 1
Add
we rs1
rs2 rd1
wa
wd rd2
GPRs
addr
inst
Inst Memory
1st instruction proceeds
IR
A
B
MD1
we ALU Y addr
rdata Data
Memory
R
26
…
x1 ¬ x0 + 10 x4 ¬ x1 + 17 …
wdata
Imm Select
MD2
wdata
(I1) x1 ¬ (x0) + 10IF1 (I2)x4¬(x1)+17 (I3)
(I4)
ID1
IF2
EX1 MA1 WB1
stalled stages
ID2 EX2 MA2 WB2
IF3 ID3 EX3 MA3 WB3
IF4 ID4 EX4 MA4 WB4
IF5 ID5 EX5 MA5 WB5
Stalled Stages and Pipeline Bubbles
time
t0 t1 t2 t3 t4 t5 t6 t7 ….
(I5)
Resource Usage
time
t0 t1 t2 t3 t4 IF I1 I2
ID I1
EX I1– MA I1- WB I1
t5 t6 t7 I3I4I5
I2I3I4 -I2I3
–I2 – – –
….
I5
I4 I5 I3I4I5
I2 I3 I4 I5
ID2 ID2 ID2
IF3 IF3 IF3
I3 I3 I3
I2 I2 I2
– Þ pipelinebubble
27
Pipeline Bubbles
n Pipeline bubble is a logical concept
n Can be implemented using
• NOPinstruction
• Specialcontroldecoding
• Stallpipelinebydisablingpipelineregisters •…
n Causes pipeline stalls
HKUEEE ENGG3441 – HS 28
Bubbles turns into NOPs
addi x1, x0, 10
addi x4, x1, 17
ori x6, x7, 1
sub x8, x9, x10
HKUEEE ENGG3441 – HS 29
addi x1, x0, 10
NOP
NOP
NOP
addi x4, x1, 17
ori x6, x7, 1
sub x8, x9, x10
Hazards due to Loads & Stores
Stall Condition
0x4
PC
bubble
IRIR IR 1
Add
we rs1
rs2
rd1 wa
wd rd2 GPRs
addr
inst
Inst Memory
What if x1+7 = x3+5 ?
we addr
rdata Data
Memory
IR
A
ALU Y
B
MD1
MD2
R
30
…
M[x1+7] ß x2 x4ßM[x3+5] …
Is there any possible data hazard in this instruction sequence?
Imm Select
wdata
wdata
Load & Store Hazards
x1+7 = x3+5 è data hazard
However, the hazard is avoided because our memory system completes writes in one cycle !
Load/Store hazards are sometimes resolved in the pipeline and sometimes in the memory system itself.
More on this later in the course.
…
M[x1+7] ß x2 x4 ß M[x3+5] …
31
Time
Pipeline CPI Examples
3 instructions finish in 3 cycles CPI = 3/3 =1
3 instructions finish in 4 cycles CPI = 4/3 = 1.33
3 instructions finish in 5cycles CPI = 5/3 = 1.67
Measure from when first instruction finishes to when last instruction in sequence finishes.
Inst
1
Inst 2
Inst 3
Inst
1
Inst 2
Bubble
Inst 3
Inst
1
Bubble 1
Inst 2
InBsutb3ble 2
Inst
3
32
Resolving Data Hazards
n Strategy 1: Stalling
• Waitfortheresulttobeavailablebyfreezing
earlier pipeline stages
• è Interlocks
n Strategy 2: Data Forwarding
• Routedataassoonaspossibleafteritis calculated to the earlier pipeline stage
• è bypass
HKUEEE ENGG3441 – HS 33
Bypassing
t0 t1 t2 t3 t4 t5 t6 t7 ….
time
(I1)x1¬x0+10 (I2)x4¬x1+17 (I3)
(I4)
(I5)
A new datapath, i.e., a bypass, can get the data from the output of the ALU to its input
IF1 ID1 EX1 MA1 WB1
IF2
ID2 EX2 MA2 WB2
IF3 ID3 EX3 MA3
ID4 EX4 IF5 ID5
stalled stages IF4 Each stall or kill introduces a bubble in the pipeline
time
(I1)x1¬x0+10 (I2)x4¬x1+17 (I3)
(I4)
(I5)
t0 t1 t2 t3 t4 t5 t6 t7 ….
IF1 ID1 EX1 MA1 WB1
IF2 ID2 EX2 MA2 WB2
IF3 ID3 EX3 MA3 WB3
IF4 ID4 EX4 MA4 WB4
IF5 ID5 EX5 MA5 WB5
ID2 ID2 ID2
IF3 IF3 IF3
⇒CPI > 1
34
stall
Add
PC D IR
…
x1¬x0+10
x4 ¬ x1 + 17 yes
x4 ¬ x1… bubble
ASrc
B
MD1
Adding a Bypass
0x4
x1 ¬ …
EMW
IRIR IR
we rs1
rs2
rd1 wa
wd rd2 GPRs
addr
inst
Inst Memory
A
ALU Y
1
R
we addr
rdata Data
Memory
Imm Select
When does this bypass help?
MD2
wdata
wdata
(I1)
(I2)
x1¬M[x0+10] x4 ¬ x1 + 17
JAL x1,500
no
x4 ¬ x1 + 17 no
35
Fully Bypassed Datapath
stall
PC for JAL, …
bubble
ASrc
BSrc
0x4
EMW
IRIR IR
Add
PC D IR
Is there still
a need for the stall signal ?
A
ALU Y
1
R
addr
inst
Inst Memory
we rs1
rs2
rd1 wa
wd rd2 GPRs
we addr
rdata Data
Memory
B
MD1
MD2
Imm Select
wdata
wdata
36
Questions about LW and forwarding
ADDIU R1 R1 24
Do we need to stall ?
ID (Decode)
From WB
OR R3,R3,R2 LW R1 128(R29)
Mux,Logic
EX MEM
WB
IR
IR IR
AY
MM B
IR
WE, MemToReg
R
lw x1, 128(x29)
or x3, x3, x2
addiu x1, x1, 24
37
Questions about LW and forwarding
ADDIU R1 R1 24
Do we need to stall ?
ID (Decode)
From WB
LW R1 128(R29) OR R1,R3,R1
Mux,Logic
EX MEM
WB
IR
IR IR
AY
MM B
IR
WE, MemToReg
R
or x1, x3, x1
lw x1, 128(x29)
addiu x1, x1, 24
38
Fully Bypassed Datapath
stall
PC for JAL, …
bubble
ASrc
BSrc
0x4
EMW
IRIR IR
Add
PC D IR
Is there still
a need for the stall signal ?
A
ALU Y
1
R
we rs1
rs2
rd1 wa
wd rd2 GPRs
addr
inst
Inst Memory
we addr
rdata Data
Memory
B
MD1
MD2
Imm Select
wdata
wdata
stall = (rs1D=wsE). (opcodeE=LWE).(wsE ≠ 0 ).re1D + (rs2D=wsE). (opcodeE=LWE).(wsE ≠ 0 ).re2D
39
HKUEEE ENGG3441 – HS 40
Control Hazard
n Control hazards occur as a result of branches and jumps • next instruction not necessarily at PC+4
n Unconditional jumps:
• Next instruction is determined by the jump instruction
n Conditional branches:
• Next instruction depends on result of branch comparison
n Possible solutions:
• Stall
• Change ISA
• (forward)
• Speculation
n Important questions to ask yourself:
When do we know the address of next instruction to execute?
What happen to the instructions in the rest of the pipeline?
HKUEEE ENGG3441 – HS 41
Pipelining Branches
Select correct target depending on Bcomp
FDEMW
PCSel
Add
IR IR IR
0x4
PC
PC PC
IR
Add
ALU
Bcomp?
we rs1
rs2
rd1 wa
wd rd2 GPRs
addr
inst
Inst Memory
Challenge: Does not know target address until EX stage
HKUEEE ENGG3441 – HS 42
Calc target addr
Br Logic
Take branch?
we addr
rdata
Data Memory
Imm Select
wdata
wdata
Not so good solution – Stalling
(I1) 096: ADD
(I2) 100: BEQ +200
(I3) 104: ADD
(I4) 108: ADD (I5) 300: SUB
n Stalling:
• Wait 2 cycles
IF2 ID2
EX2 MA2 WB2
time
t0 t1 t2 t3 t4 t5 t6 t7 ….
IF1 ID1 EX1 MA1 WB1
– –
– –
• Fetch the correct target after address calculation is completed in EX stage
n Stalling doesn’t quite work:
• The hardware doesn’t know it is a branch instruction until ID
stageèWhat should happen at t2?
• Huge performance penalty if hardware always stall 2 cycles
regardless of instructionè3x cycle time
HKUEEE ENGG3441 – HS 43
– – –
– – – –
IF5 ID5 EX5 MA5 WB5
Solution 1: Change ISA
n Expose the fact that there is pipeline in hardware
n Change ISA: The 2 instructions following branch will ALWAYS be executed regardless of the branch comparison result
n The extra cycle when an instruction is always executed regardless of the comparison result is called a branch delay slot
n Compiler may insert useful instructions in the branch delay slot or NOPs
• e.g. instruction that may be executed regardless of the branch target
HKUEEE ENGG3441 – HS 44
Branch Delay Slot Example
addi x2, x1, 4
lw x4, 16(x2)
beq x1, x0, err
ok: add x5, x3, x4
ori x6, x0, 23
…
err: sub x5, x3, x4
beq x1, x0, err
addi x2, x1, 4
lw x4, 16(x2)
ok: add x5, x3, x4
ori x6, x0, 23
…
err: sub x5, x3, x4
delay slot
Original Rearranged
n Instructions in delay slot must not affect the branch decision
• e.g.inabove:theycannotmodifyx1 n Is the value of x4 ok?
HKUEEE ENGG3441 – HS
45
Real Processor: MIPS-I
n The first generation of MIPS processor has 1 delay slot defined
n Brach decision is moved to ID stage • Onlysupportverysimplebranch:
• beqzon1register
n Compiler must find instruction to fill the delay slot or put NOP
HKUEEE ENGG3441 – HS 46
Microprocessor without Interlocked Pipeline Stages
Solution 2: Speculate + Kill
n Step 1: Speculate that the instruction in delay slots will be executed.
n Step 2: Determine at EX stage:
• ifbranchtaken,thenkilltheinstructionsinIFand
ID stage
• ifbranchnottaken,thendonothing
n Pro: Waste cycles only in cases when branch taken
n Cons: complicate hardware • interactwithstall
• Branch/Jumpindelayslots?
HKUEEE ENGG3441 – HS 47
Killing instructions in IF, ID
(I1) 096: ADD
(I2) 100: BEQ +200
(I3) 104: ADD
(I4) 108: ADD (I5) 300: SUB
(I1) 096: ADD
(I2) 100: BEQ +200
(I3) 104: ADD
(I4) 108: ADD (I5) 112: SLL
IF1 ID1 EX1
IF2 ID2
MA1 WB1
EX2 MA2 WB2
time
Branch taken
t0 t1 t2 t3 t4 t5 t6 t7 ….
IF3 ID3
IF4 –
– –
MA5 WB5
– – – – –
IF5 ID5 EX5
Kill instructions in pipeline
time
t0 t1 t2
Branch not taken
t3 t4 t5 t6 t7 ….
IF1 ID1 EX1 MA1 WB1
Instructions continue
IF2 ID2
IF3
new instruction
EX2 MA2 WB2
ID3 EX3 MA3 WB3
IF4 ID4 EX4 MA4 WB4 IF5 ID5 EX5 MA5
WB5
HKUEEE
ENGG3441 – HS
48
Killing Instructions
Select correct target depending on Bcomp
F PCSel D kill E M W
bubble
IR IR IR
PC
PC
0x4
Add
Calc target addr
bubble kill IR
Add
ALU
Bcomp?
Br Logic
Take branch?
we rs1
rs2
rd1 wa
wd rd2 GPRs
addr inst
Inst Mem
we addr
rdata
Data Memory
PC
Imm Select
wdata
wdata
Note: kill signal ≠ stall signal as instruction in ID is invalid
HKUEEE ENGG3441 – HS 49
Pipelining Jumps (JAL)
n Unconditional jumps can be implemented similar to branches with the branch condition being always true
n JAL has additional requirements for storing return address (PC+4) in the destination register rd
• ProceeduntilWBstagetowritebackdatain register file
• Needtobecarefulwithdataforwardingand stalling on rd
n Always kill instructions after JAL
HKUEEE ENGG3441 – HS 50
Pipelining JAL
F PCSel D kill E M W
bubble
IR IR IR
0x4
PC PCPC
Add
Add
0x4
Add
bubble kill IR
Bcomp?
PC
HKUEEE
ENGG3441 – HS
51
Select brjmp
we rs1
rs2
rd1 wa
wd rd2 GPRs
ALU
Save PC+4 from JAL instruction
Calc target addr
Br Logic
addr inst
Inst Mem
we addr
rdata
Data Memory
Imm Select
wdata
wdata
Branch Delay Slots
n Post 1990s processors rarely has branch delay slot
n Performance: I-cache miss at delay slot causes significant performance penalty
n Delay slot complicates advanced microarchitectures
• e.g. super scalar processors with multiple instructions issued per cycles
n Difficult to find instructions to fill deeply pipelined processors
• Modern processors can have up to 30 pipeline stages n Other techniques helpful
• branch prediction, predicated instructions, etc
HKUEEE ENGG3441 – HS 52
In Conclusions…
n Pipeline is a well-studied digital system design technique
n Pipelining allows concurrent execution of multiple steps
n 5-stages of RISV-V pipeline:
• Instruction Fetch
• Instruction Decode
• Instruction Execute
• Memory Access
• Write Back
n 3 Types of Hazards
• Structural hazard
• Data hazard
• Control hazard
HKUEEE
ENGG3441 – HS 53
Acknowledgements
n These slides contain material developed and copyright by:
• Arvind(MIT)
• KrsteAsanovic(MIT/UCB) • JoelEmer(Intel/MIT)
• JamesHoe(CMU)
• JohnKubiatowicz(UCB)
• DavidPatterson(UCB)
n MIT material derived from course 6.823
n UCB material derived from course CS152,
CS252
HKUEEE ENGG3441 – HS 54