DT131B Embedded Systems Programming
Lecture 3: Computer Organization (Part 2: the CPU)
Slides adapted from:
Computer Organization and Architecture William Stallings, 8th Edition (2010) Chapters 11,12
Dawit Mengistu (dawit.mengistu@hkr.se)
CPU Structure
• The CPU must:
– Fetch instructions
– Interpret instructions – Fetch data
– Process data
– Write data
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CPU With Systems Bus
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CPU Internal Structure
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Review: Instruction Cycle State Diagram
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Review: Data Flow (Instruction Fetch)
• Depends on CPU design
• Fetch
– PC contains address of next instruction
– Address moved to MAR
– Address placed on address bus
– Control unit requests memory read
– Result placed on data bus, copied to MBR, then to IR – Meanwhile PC incremented by 1
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Data Flow (Fetch Diagram)
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Review: Data Flow (Execute)
• May take many forms
• Depends on instruction being executed
• May include
– Memory read/write – Input/Output
– Register transfers
– ALU operations
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Improved Performance
• But not doubled:
– Fetch usually shorter than execution
• Prefetch more than one instruction?
– Any jump or branch means that prefetched
instructions are not the required instructions • Add more stages to improve performance
=> Pipelining
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Registers
• CPU must have some working space (temporary storage) called registers
• Number and function vary between processor designs
• One of the major CPU design decisions
• Top level of memory hierarchy How many memory levels?
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User Visible Registers
• General Purpose • Data
• Address
• Condition Codes
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General Purpose Registers (1)
• May be true general purpose
• May be restricted
• May be used for data or addressing – Data
• Accumulator
– Addressing • Segment
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General Purpose Registers (2)
• Make them general purpose
– Increase flexibility and programmer options – Increase instruction size & complexity
• Make them specialized
– Smaller (faster) instructions – Less flexibility
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How Many GP Registers?
• Between 8 – 32
• Fewer registers means more memory
references
• More registers does reduce memory references but takes up processor real estate
• See also RISC
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How Big?
• Large enough to hold full address
• Large enough to hold full word
• Often possible to combine two data registers
• Register size influences the complexity of compiler software
E.g. C programming size of a variable -> how many registers needed to hold the data in a?
– int a; (how many bits is an int?) – long int a;
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Control & Status Registers
• Program Counter
• Instruction Decoding Register • Memory Address Register
• Memory Buffer Register
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Condition Code Registers
• Sets of individual bits
– e.g. result of last operation was zero
• Can be read (implicitly) by programs – e.g. Jump if zero
• Can not (usually) be set by programmer directly
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Program Status Word
• A set of bits
• IncludesConditionCodes – Sign of last result
– Zero
– Carry
– Equal
– Overflow
– Interrupt enable/disable
• Supervisor (More on this later)
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Instruction Execution in Supervisor (Previleged) Mode
• Intel ring zero
• Kernel mode
• Allows privileged instructions to execute • Used by operating system
• Not available to user programs
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Other Registers
• May have registers pointing to:
– Process control blocks (used by OS) – Interrupt Vectors (used by OS)
Remember!
CPU design and operating system design are closely linked
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Example Register Organizations
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Processor Architecture Examples – 1:
AVR
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AVR Architecture
Registers: Two types of registers
General Purpose Registers
32 general purpose registers having storage capacity of 8-Bits Named as R0,R1,R2 to R31.
Register 0 to 15 & 16 to 31 are different.
Can store both Data & Addresses.
SPECIAL Purpose Registers: Three registers Program counter
Stack Pointer Status Register
AVR Architecture
Pointer Register
Three 16-bit address registers pairs of registers 26 to 31 have extra meaning in AVR assembly.
X (r27:r26), y (r29:r28), z (r31:r30).
Pointer
Sequence
X
Read/Write from address X, don’t change the pointer
AVR Architecture
Status Register (SREG) that contains
It is 8-bit long each bit has a different meaning.
I: Global Interrupt Enable/Disable Flag, SREG7
T: Transfer bit used by BLD and BST instructions, SREG6 H: Half Carry Flag, SREG5
S: For signed tests Instruction Set, SREG4
V: Two’s complement overflow indicator, SREG3
N: Negative Flag, SREG2
Z: Zero Flag, SREG1
C: Carry Flag, SREG0
(More on this later)
I
T
H
S
V
N
Z
C
AVR Architecture (cont’)
Stack Pointer (SP)
16-bit stack pointer (SP) holds address in data space of area to save function call information.
AVR Register Architecture
Example:
How to tell the machine to perform addition such as 5+6?
AVR Memory Architecture
Memory:
There are two separate memories
Program Memory (Flash Memory)
Data Memory
Processor Architecture Examples – 2:
ARM
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ARM Processor Architecture
• RISC(asopposedtoCISC)
• Moderatearrayofuniformregisters
– More than most CISC, less than many RISC
• Load/store model
– Operations perform on operands in registers only
• Uniformfixed-lengthinstruction
– 32 bits standard set 16 bits Thumb
• Shift or rotation can preprocess source registers
– Separate ALU and shifter units
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ARM Processor (cont’)
• Smallnumberofaddressingmodes
– All load/store addressees from registers and instruction fields – No indirect or indexed addressing involving values in memory
• Auto-increment and auto-decrement addressing – Improve loops
• Conditionalexecutionofinstructionsminimizes conditional branches
– Pipeline flushing is reduced
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Example: Simplified ARM Processor Organization
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ARM Processor Organization
• Many variations depending on ARM version
• Data exchanged between processor and memory through
data bus
• Data item (load/store) or instruction (fetch)
• Instructions go through decoder before execution
• Pipeline and control signal generation in control unit
• Data goes to register file
– Setof32bitregisters
– Byte&halfwordtwoscomplementdatasignextended
• Typically two source and one result register
• Rotation or shift before ALU
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ARM Processor Modes
• User
• Privileged
– 6 modes
• OS can tailor systems software use
• Some registers dedicated to each privileged mode • Swifter context changes
• Exception
– 5 of privileged modes
– Entered on given exceptions
– Substitute some registers for user registers
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• Avoid corruption
ARM Register Organization
• 37 x 32-bit registers
• 31 general-purpose registers – Some have special purposes – E.g. program counters
• 6 program status registers
• Registers in partially overlapping banks
– Processor mode determines bank
• 16 numbered registers and one or two program status registers visible
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General Register Usage
• R13 normally stack pointer (SP)
– Each exception mode has its own R13
• R14 link register (LR)
– Subroutine and exception mode return address
• R15 program counter
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CPSR
• Processstatusregister
– Exception modes have another dedicated register called
SPSR
• 16 msb are user flags
– Condition codes (N,Z,C,V)
– Q – overflow or saturation in some SMID instructions
• 16 lsb system flags for privilege modes – E – endian
– Interrupt disable
– T – Normal or Thumb instruction – Mode
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