CS计算机代考程序代写 1. Interrupt Address table

1. Interrupt Address table

2. Timer Initialization Information
• TCNT0: Timer/Counter an 8-bit register, stores the current value of Timer0.
• TCCR0: Timer/Counter Control Registers, configures the operations of Timer0.
• OCRxA, OCRxB: Output Compare Registers store the preset values for output compare.
• TIMSK enables timer interrupts
• TIFR monitors status of timer interrupts. •
TCR0 (Timer 0)
CS2:0 (clock select prescaler)
000 None
001 clkI/0
010 clkI/0/8
011 clkI/0/64
100 clkI/0/8clkI/0/256
101 clkI/0/8clkI/0/1024
110 External clock on T0 (falling edge trigger) 111 External clock on T1 (rising edge trigger)
Waveform generation mode (WGM)
00 Normal
10 PWM, Phase Correct 01 CTC
11 Fast PWM
• TIMSK Timer 0 uses the Timer/Counter 0 Output CompareMatch Interrupt Enable (OCIE0) bit and the Timer/Counter 0 Overflow Interrupt Enable (TOIE0) bit.
OCIE0 (=1): Compare Match interrupt is enabled if the I-bit in the Status Register is set (=1) TOIE0 (=1): Overflow interrupt is enabled if the I-bit in the Status Register is set (=1).
• TIFR Timer 0 uses
– the OCF0 bit position, (sets for an output compare match).
– the TOV0 bit position, (sets when Timer/Counter 0 Overflows).

3. USART Initialization Information CSRA: USART Control and Status Register A
BitNo 7 6 5 4 3 2 1 0 Name RXC TXC UDRE – – – – –
RXC this bit is set when the USART has completed receiving a byte from the host and the program should read the received byte from UDR
TXC This bit is set (1) when the USART has completed transmitting a byte to the host and your program can write new data to USART via UDR
UDRE This bit indicates if the transmit buffer (UDRn) is ready to receive new data.
UCSRB: USART Control and Status Register B
BitNo 7 6 5 4 3 2 1 0
Name RXCIE TXCIE UDRIE
RXCIE: Receive Complete Interrupt Enable – TXCIE: Transmit Complete Interrupt Enable – RXEN: Receiver Enable –
TXEN: Transmitter Enable –
UCSRC: USART Control And Status Register C
RXEN TXEN – – –
(1 = the Rx interrupt is enabled) (1 = the Rx interrupt is enabled) (1 = receiver enabled)
(1 = transmitter enabled)
BitNo 7 6 5 4 3 2 1 0 Name URSEL UMSEL UPM1 UPM0 USBS UCSZ2 UCSZ0 UCSZ0
UPM: Parity mode 00 – no parity; 10 – even parity; 11 – odd parity
UCSZ: USART Character size – These three bits (one in the UCSRB) selects the number of bits of
data that is transmitted in each frame.
UCSZ2 UCSZ1 UCSZ0 Character Size
000 5Bit 001 6Bit 010 7Bit 011 8Bit 111 9Bit
URSEL (=1): USART register select
UMSEL: USART Mode Select – selects between asynchronous and synchronous modes.
USBS: : USART Stop Bit Select – selects the number of stop bits in the data transfer.
UMSEL
0 1
Mode
Asynchronous Synchronous
USBS
0 1
Stop Bit(s)
1 BIT 2 BIT
UBRR: USART Baud Rate Register:
It is 16BIT wide so UBRRH is the High Byte and UBRRL is Low byte (only the right most 12 bits are used for baud rate). Used by the USART to generate the data transmission at specified speed. UBRR value is calculated according to following formula.

4. ADC Initialization Information
Input Channel Selections
0000 ADC0 0001 ADC1 0010 ADC2 0011 ADC3 0100 ADC4 0101 ADC5 0110 ADC6 0111 ADC7

ADC Prescaler Selections
ADPS2 ADPS1 ADPS0 Division Factor
0002 0012 0104 0118
1 0 0 16 1 0 1 32 1 1 0 64 1 1 1 128

5. ATMega168/328 Instruction Set

ATMega168/328 Instruction Set (cont’d)