Kristianstad University
DT232A: Embedded Systems I SOLUTIONS TO EXAMINATION QUESTIONS
Examiner: Dawit Mengistu
Note:
Standard calculators are allowed
NO other help materials are allowed;
You can write your answers in English or/and Swedish Write your answers clearly.
The answer to each question should start on a new page. No points will be given for unreadable answers
Use the information in the attached pages as references wherever applicable.
1.
a)
Which two-input logical block generate the timing-diagram below?
OR gate
Place following function in the Karnaugh map
(6 points)
(2)
b)
(4)
Date: 2015.11.06
Simplify as much as possible.
cd ab
00
01
11
10
00
1
1
01
1
1
11
1
10
1
1
a’d + cd + bd = (a’ + b + c)
2.
(5 points)
Design a sequential circuit that divides input frequency by 8 and shows the output on a 4-bit counter. Note: the output of the frequency divider is used as an input to the counter.
You can use your preferred flip-flop type for this purpose. You may use different types of flip-flops for the divider and the counter, if you wish.
3.
a) Explain the difference between Harvard and Von Neumann memory architectures. What are the advantages of Harvard over Von Neumann?
(6 points)
(1.5)
(1)
Harvard: Separate bus and storage code and data memory. Safer, faster but hardware is expensive
Von Neumann: shared storage and bus for code and data. Risk of inadvertent modification of code may lead to system crash, but is cheaper because it uses less hardware.
b) The CPU contains different types of registers. Taking any processor you are familiar with (e.g. AVR, ARM, X86, etc.), describe the types (groups) of registers it has.
What is the purpose of each group of register? About how many registers does the processor have? (3.5)
Read lectures 8-9 (from page 14)
4. (5 points)
a) Explain at least 3 disadvantages (problems) of dynamic memory (DRAM) compared with static memory (SRAM). (2)
SRAM is faster made of flip flops, doesn’t require frequent refreshing, but is expensive
DRAM is slower, made of capacitors, requires refreshing, cheaper
b) Explain in detail the operation flow and sequence of the fetch-execute cycle. (3p)
Read lecture slides 8-9
Please take note of the functions of the following registers in the fetch-execute cycle
PC (Program Counter) is a register that stores the address of the next instruction to be fetched in the memory.
MAR (Memory Address Register) is a temporary register that holds the address of the memory location from which the next instruction or data is to be fetched.
MBR (Memory Buffer Register) is a temporary register that stores data that is
– just read from the memory (at address indicated by MAR) or
– about to be written into memory (such as results of an arithmetic or logic operation)
IR (Instruction Register) holds the instruction (also called opcode) that is just read from the memory through MBR. The opcode is decoded by the instruction decoder to determine if it has operands (and how many).
According to the Von Neumann architecture, the instruction format is Opcode operand (The operand can be 0, 1 or more)
If the opcode has no operand (argument), the opcode is directly executed and PC is incremented (or updated to point to the next instruction’s address: PC = PC+1)
If the opcode has m operands, the operands are read one by one by incrementing MAR to point to the next consecutive memory address after the opcode. The data that is read from memory is stored in MBR from where it will be transferred to other CPU registers used by the ALU. Once all operands are read, PC is updated such that PC = PC + m)
If the iinstruction (opcode) is an I/O instruction such as IN or OUT,
I/O AR (IO Address Register) is used to store the address of the IO to be accessed
I/O BR (IO buffer register) is used to store data that is read from (IN) or written to (OUT) the I/O
The ALU (Arithmetic and Logic Unit) is responsible for decoding and executing most arithmetic and logic instructions implemented in its hardware (such as ADD, SUB, MUL, CMP,…). Some instructions do not involve the ALU operations. E.g. CALL, JMP, NOP, etc
The Control Unit (not shown) is responsible for timing, synchronization and coordination of the above activities in their proper sequence.
PC and IR are internal registers that are not visible to units outside the CPU. ALU is also internal and has no communication with other units outside the CPU.
CPU MEMORY
CPU internal data transfer lines Address bus
Data bus
5. (5 points)
A typical I/O module of a computer can be described using the following diagram:
a) As you can see in the diagram, an I/O module has three types of registers: data, status, control. What are the functions of each register type? (3)
Lecture 15:
Data Register: used to store the data to be sent or received via the I/O
Control Register: used to configure the settings of the I/O (e.g. baud rate, parity, etc in UART)
Status Register: shows what is going on in the I/O unit: (e.g. data register is empty or full, interrupt generated, etc)
b) For addressing I/O units, we use two methods; memory mapped I/O and port mapped I/O. What is the difference between the two addressing methods? (2)
Read Lecture 15 slide 6
6. (5 points)
An embedded system designer wishes to build an embedded system to be installed in a manufacturing machine. The hardware of the embedded system contains an 8-bit CPU and the following memory chips (total 4):
Data memory (RAM) 3 modules (chips) size: 4KB each Program memory (ROM) 1 module, size: 2KB
a) Design the addressing circuit and bus structure used to connect the CPU to the memory unit. Show a schematic diagram of your design with proper connections between the hardware components. (3)
b) Describe the resulting memory address map and additional hardware you need to realize the addressing unit. (2)
We have a total of (2+4+4+4) = 14KB addressable memory. The number of address lines necessary to access 14KB is
L = log2 14000 > 13. Therefore, we need 14 address lines Since we have 4 memory chips we need
Log2 4 = 2 lines for chip selection. The rest of the address lines are shared by all memory chips and used for internal addressing within the chip.
2to4 Decoder
CPU
ROM Chip 2KB
RAM Chip 4KB
RAM Chip 4KB
RAM Chip 4KB
Address bus (in chip address, 10 bits)) Chip decoder (chip selector, 2 bits) Data bus
Memory Address map:
Chip# Starting
0 0
1 4096
2 8191
Ending 2047 8191 12287 16383
Chip Select 00
01
10
3 12288
Additional Hardware needed to implement the addressing system is a 2-to-4 decoder.
11
7. (7 points)
You are required to write an assembly program code for a weather station which is based on the ATMega168 microcontroller. Your code displays the total amount of rainfall in 2014. The total rainfall is the sum of the monthly rainfall data. Assume that:
– The 12-month rainfall data is already stored in consecutive memory as integer values.
– The starting memory address of the rainfall data is 0x1000 (e.g. January’s rainfall).
– The microcontroller has an 8-bit processor with 16MHZ speed
You should write an assembly program code that calculates the sum of the monthly rainfall data which is already stored in memory.
a) Write an assembler code with proper comments to do the required task. (4)
Here are the important steps:
1. A down counter is used to track the number of loop executions (in this case it is 12 times)
2. A register is cleared (set to 0) to hold the sum of the addition operation
3. The memory address containing the monthly data is initialized via R27:R26
4. The data from memory is read to R16
5. Addition operation is performed on the data just read from memory
6. The pointer to next memory address is incremented (R26)
7. The counter is decremented and compared with zero
8. If counter is not zero execution returns to line 4 above
9. Otherwise, the sum is sent to the output port (PORTD). For this the DDRD should be set for output (0xFF) first. Then the sum in R20 is sent to PORTD.
ldi R19, 0
ldi R17, 12 ldi R20, 0x00 ldi R27, 0x10 ldi R26, 0x00
looper:
ld R16, X
add R20, R16 inc R26
dec R17
cp R17, R19 brne looper
ldi R18, 0xff
out PORTD, R18 out PORTD, R20 ret
;used to compare if down counter is zero ;number of data points to be added ;store the sum here
;pointer to data memory higher address ;pointer to data memory lower address ;addition loop starts here
;get data from memory
;add data to sum register
;increment to get data from to next address ;decrement data count
;check if loop counter is 0
;if counter not 0, go back to beginning of loop ;use R18 to set DDRD for output
;set PortD for output
;send the sum to PortD
;return to the calling routine
b) How much time does it take to complete the execution of the above program? Justify your answer by showing the necessary calculations. (1.5)
There are 6 lines in the loop. The loop is executed 12 times. There are 9 lines outside the loop (5 before and 4 after the loop).
This means, a total of 81 lines are executed. (6X12) + 9.
Assuming each line to take 1 or 2 clock cycles, we can estimate that the entire code is executed in 81 to 162 clock cycles. (Actually it is 103 cycles).
On a 1MHZ computer this corresponds to 103 micro seconds.
8.
c) How much flash memory is required to store your compiled code? Justify your answer by showing the necessary calculations. (1.5)
Most instructions take 2 bytes. Given that there are 15 instructions (see in b above), we estimate that the code occupies about 30 bytes of flash (program) memory.
(6 points)
A toy factory wants to use a microcontroller based blinker (red and blue LED lamps) on one of its products. When a child presses the POWER ON button, the red and blue lights blink one after the other. Each LED lamp is switched on for a 2 seconds duration and switched off for the next 2 seconds. If the blue lamp is ON, the red lamp is OFF and vice versa.
Write a C program for this application. Use the following assumptions:
– You shall use the ATMega168 processor which has a speed of 16MHZ
– You shall use Timer0 to control the lighting interval.
Use a flow chart or relevant diagram in order to make your solution understandable. Write proper comments to describe your code.
To create a delay of 2seconds, we use timer0. We use the corresponding ISR for timer0 overflow. We then count the number of overflows that correspond to the desired delay (2sec). You need a global counter for this:
The timer counter0 is 8-bits which means it overflows every 256 cycles.
Since the processor has 16MHZ the overflow duration corresponds to 256/16000000 seconds
However, with a pre-scaler value of 1024, the over flow duration can be
256/(16000000/1024) seconds = 0.0164sec 16.4msec.
For a delay of 2 seconds we need 2/0.0164 12 over flows, that is the maximum value our global counter can have.
Int gcount ;
The main method shall have the following structure:
Void main(){
gcount = 0; Timerinit(); While (1) {
; }
}
The Timerinit() method shall be initialized according to the notes in Lecture 17 Void Timer0init() {
TCCR0A = 0b00000000; TCCR0B = 0b00000101; TIMSK = 0b00000001; sei();
// normal mode
// prescaler 1024
// enable Timer 0 overflow interrupt
// enable interrupt subsystem globally
}
The interrupt service routine can have the following form
ISR(TIMER0_OVF_vect){ gcount++;
if(gcount>= 12){ overflow_count= 0; if(PORTD & 0x01) PORTD &= 0xfe; else
PORTD |= 0x01;
} }
// handlerfor Timer1 overflowinterrupt
// incrementoverflowcount
// when about2s has passed
// start new count
//if light is ON //set light OFF
// if it is OFF set it ON
1. Interrupt Address table
2. Timer Initialization Information
• TCNT0: Timer/Counter an 8-bit register, stores the current value of Timer0.
• TCCR0: Timer/Counter Control Registers, configures the operations of Timer0.
• OCRxA, OCRxB: Output Compare Registers store the preset values for output compare.
• TIMSK enables timer interrupts
• TIFR monitors status of timer interrupts. •
TCR0 (Timer 0)
CS2:0 (clock select prescaler)
000 None
001 clkI/0
010 clkI/0/8
011 clkI/0/64
100 clkI/0/8clkI/0/256
101 clkI/0/8clkI/0/1024
110 External clock on T0 (falling edge trigger)
111 External clock on T1 (rising edge trigger)
Waveform generation mode (WGM)
00 Normal
10 PWM, Phase Correct 01 CTC
11 Fast PWM
• TIMSK Timer 0 uses the Timer/Counter 0 Output CompareMatch Interrupt Enable (OCIE0) bit and the Timer/Counter 0 Overflow Interrupt Enable (TOIE0) bit.
OCIE0 (=1): Compare Match interrupt is enabled if the I-bit in the Status Register is set (=1)
TOIE0 (=1): Overflow interrupt is enabled if the I-bit in the Status Register is set (=1).
• TIFR Timer 0 uses
– the OCF0 bit position, (sets for an output compare match).
– the TOV0 bit position, (sets when Timer/Counter 0 Overflows).