Chapter 8: Main Memory
Chapter 8: Main Memory
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Chapter 8: Memory Management
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Background
Swapping
Contiguous Memory Allocation
(Segmentation)
Paging
Structure of the Page Table
Example: The Intel 32 and 64-bit Architectures
Example: ARM Architecture
Objectives
To provide a detailed description of various ways of organizing memory hardware
To discuss various memory-management techniques, including paging
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Background
Program must be brought (from disk) into memory and placed within a process for it to be run
Main memory and registers are the only storage that CPU can access directly
Machine instructions can have memory addresses as operands, but not disk addresses
Memory unit only sees a stream of addresses + read requests, or address + data and write requests
Register access is completed in one CPU clock cycle (or less)
Main memory access can take many cycles, causing a stall and this happens very frequently
Cache (fast memory managed by the hardware) sits between main memory and CPU registers
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Protection of memory via hardware required to ensure correct operation
Protect the operating system from access by user processes
Protect user processes from one another
There are several ways to implement this protection.
First, we need to make sure that each process has a separate memory space
To do that we need to be able to
determine the range of legal addresses that the process may access
ensure that it can access only these legal addresses….
Background
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Process Memory Integrity
Base and Limit Registers
A pair of base and limit registers define the logical address space
Base register holds the smallest legal physical memory address
Limit register specifies the size of the range (not the upper memory address)
CPU must check every memory access generated in user mode to be sure it is between base and limit for that user
These registers can only be loaded by the operating system.
OS/Kernel mode operations have no such restrictions
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Hardware Address Protection
Programs on disk (in the form of binary executables), ready to be brought into memory to execute from an input queue
Without support, must be loaded into address 0000
Inconvenient to have first user process physical address always at 0000
Addresses represented in different ways at different stages of a program’s life
Source code addresses usually symbolic
Compiled code addresses bind to relocatable addresses
i.e. “14 bytes from beginning of this module”
Linker or loader will bind relocatable addresses to absolute addresses
i.e. 74014
Each binding maps one address space to another
Address Binding
Binding of Instructions and Data to Memory
Address binding of instructions and data to memory addresses can happen at three different stages
Compile time: If memory location known a priori, absolute code can be generated; must recompile code if starting location changes (e.g., MS-DOS .COM files)
Load time: Compiler must generate relocatable code if memory location is not known at compile time
Execution time: Binding delayed until run time if the process can be moved during its execution from one memory segment to another
Need hardware support for address maps (e.g., base and limit registers)
Most general-purpose operating systems use this method
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Multistep Processing of a User Program
Let’s see how the linkage editor works ->
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Linkage Editor Function
Unresolved external reference
This is known as Static Linking
Logical vs. Physical Address Space
The concept of a logical address space that is bound to a separate physical address space is key to proper memory management
Logical address – generated by the CPU; also referred to as virtual address
Physical address – address seen by the memory unit
Logical and physical addresses are the same in compile-time and load-time address-binding schemes;
Logical (virtual) and physical addresses differ in execution-time address-binding scheme
Logical address space is the set of all logical addresses generated by a program
Physical address space is the set of all physical addresses generated by a program
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Memory-Management Unit (MMU)
Hardware device that maps virtual to physical address at run time
Many methods possible, covered in the rest of this chapter
To start, consider simple scheme where the value in the relocation register is added to every address generated by a user process at the time it is sent to memory (see next slide)
Base register now called relocation register
MS-DOS on Intel 80×86 used 4 relocation registers
The user program deals with logical addresses; it never sees the real physical addresses
Execution-time binding occurs only when reference is made to location in memory
Logical address bound to physical address
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Dynamic Relocation –
Relocation Register
Dynamic Relocation Using A Relocation Register
Routine is not loaded until it is called
Better memory-space utilization; unused routine is never loaded
All routines kept on disk in relocatable load format
Useful when large amounts of code are needed to handle infrequently occurring cases
No special support from the operating system is required
Implemented through program design that takes advantage of this method
OS can help by providing libraries to implement dynamic loading
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Static vs Dynamic Linking
Static Linking – system libraries and program code combined by the loader into the binary program image
Dynamic Linking –linking postponed until execution time
Small piece of code, stub, used to locate the appropriate memory-resident library routine
Stub replaces itself with the address of the routine, and executes the routine
Operating system checks if routine is in process’ memory address space
If not in address space, add to address space
Dynamic linking is particularly useful for libraries
System also known as shared libraries
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Swapping
Standard Swapping
A process can be swapped temporarily out of memory to a backing store, and then brought back into memory for continued execution
Backing store – fast disk large enough to accommodate copies of all memory images for all users; must provide direct access to these memory images
Total physical memory space of processes can exceed physical memory (how is that possible?)
Major part of swap time is transfer time; total transfer time is directly proportional to the amount of memory swapped
System maintains a ready queue of ready-to-run processes which have memory images on the backing store or in main memory used by the CPU Scheduler
The Dispatcher may swap out a process currently in memory if no memory is available for the next process on the ready queue.
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Schematic View of Swapping
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Swapping (Cont.)
Does the swapped out process need to swap back in to same physical addresses?
Depends on address binding method
How to prevent I/O integrity issues when Swapping
Processes need to be completely idle and not pending I/O.
I/O processes that are filling I/O buffers from process memory cannot be interrupted as they will continue their access – but the space is now occupied by another process.
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Context Switch Time Including Swapping
If next process to be put on CPU is not in memory, need to swap out a process and swap in target process
Context switch time can then be very high
100MB process swapping to hard disk with transfer rate of 50MB/sec
Swap out time of 2000 ms (uh.. That’s 2 seconds)
Plus swap in of same sized process
Total context switch swapping component time of 4000ms (4 seconds)
Can reduce if we reduce the size of memory being swapped – by knowing how much memory is really being used –not how much might be used
System calls to inform OS of memory use via request_memory() and release_memory()
Context Switch Time and Swapping (Cont.)
Standard swapping not used in modern operating systems
But modified version common
Swap only when free memory extremely low
Swapping on Mobile Systems
Not typically supported. Why not?
Flash memory based
Small amount of space
Limited number of write cycles on flash memory before it becomes unreliable.
Poor throughput between flash memory and CPU on mobile platform
Instead use other methods to free memory if low
iOS asks apps to voluntarily relinquish allocated memory
Read-only data thrown out and reloaded from flash if needed
Failure to free can result in termination
Android terminates apps if low free memory, but first writes application state to flash for fast restart
Both OSs support paging as discussed below
Contiguous Memory Allocation
Main memory must support both OS and user processes
Limited resource, must allocate efficiently
Contiguous allocation is one early method
Main memory usually into two partitions:
Resident operating system, usually held in low memory with interrupt vector
User processes then held in high memory
Each process contained in single section of memory that is contiguous to the section containing the next process.
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Memory Protection – A Necessary Digression
Relocation registers used to protect user processes from each other, and from changing operating-system code and data
Base register contains value of smallest physical address
Limit register contains range of logical addresses – each logical address must be less than the limit register
MMU maps logical address dynamically
Can then allow actions such as kernel code being transient and kernel changing size
This may desirable when device drivers are not commonly used. They do not need to be kept in memory.
Let’s see how this works
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Hardware Support for Relocation and Limit Registers
What’s missing from this diagram?
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Memory Allocation
Multiple-partition Allocation
Multiple-partition allocation (each partition contains exactly one process)
Degree of multiprogramming limited by number of partitions
Variable-partition sizes for efficiency (sized to a given process’ needs)
System maintains a table of used and available parts of memory
Hole – block of available memory; holes of various size are scattered throughout memory
Initially, all memory is available for user processes and is considered one large block of available memory – or Hole.
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Multiple-partition Allocation
When a process arrives, it is put on the input queue.
Processes on the input queue are allocated either in FCFS order, or the OS can skip large processes when only small holes are available.
When it is chosen from the input queue, a process is allocated memory from a hole large enough to accommodate it
Process exiting frees its partition, adjacent free partitions combined
Input queue is revisited now that a larger hole is available
Let’s look at an example
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Multiple-partition Allocation
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Dynamic Storage-Allocation Problem
First-fit: Allocate the first hole that is big enough
Best-fit: Allocate the smallest hole that is big enough;
Must search entire list, unless ordered by size
Produces the smallest leftover hole
Worst-fit: Allocate the largest hole; must also search entire list
Produces the largest leftover hole
How to satisfy a request of size n from a list of free holes?
First-fit and best-fit better than worst-fit in terms of speed and storage utilization… Why?
First-fit is generally faster than the others.. Why?
Let’s look at an example….
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Dynamic Storage-Allocation Problem
Suppose a memory manager currently has a list of unallocated blocks of:
6KB, 14KB, 19KB, 11KB, and 13KB.
If a process arrives requiring 12KB:
The best-fit strategy will allocate 12KB of the 13KB block to the process.
The worst fit strategy will allocate 12KB of the 19KB block to the process, leaving a 7KB block for future use.
The memory manager places a process in the largest block of unallocated memory available.
The idea is that this placement will create the largest hole after the allocations, thus increasing the possibility that, compared to best fit, another process can use the remaining space.
The first-fit strategy will allocate 12KB of the 14KB block to the process.
There may be many holes in the memory, so the operating system, to reduce the amount of time it spends analyzing the available spaces, begins at the start of primary memory and allocates memory from the first hole it encounters large enough to satisfy the request.
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Dynamic Storage-Allocation
Notice in the diagram above that the Best fit and First fit strategies both leave a tiny segment of memory unallocated just beyond the new process.
Since the amount of memory is small, it is not likely that any new processes can be loaded here.
This condition of splitting primary memory into segments as the memory is allocated and deallocated is known as fragmentation.
The Worst fit strategy attempts to reduce the problem of fragmentation by allocating the largest fragments to new processes. Thus, a larger amount of space will be left as seen in the diagram above.
Fragmentation
External Fragmentation – total memory space exists to satisfy a request, but it is not contiguous
First fit and best fit suffer from this.
First fit analysis reveals that given N blocks allocated, 0.5 N blocks lost to fragmentation
That means that 1/3 may be unusable -> aka 50-percent rule (???)
Internal Fragmentation –
memory is allocated in fixed blocks.
allocated memory may be slightly larger than requested memory;
this size difference is memory internal to a partition not being used
An 18,464 byte process is allocated 2 blocks of 9,240 each.
The additional 16 bytes would be the internal fragmentation.
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Fragmentation (Cont.)
Reduce external fragmentation by compaction
Shuffle memory contents to place all free memory together in one large block
Compaction is possible only if relocation is dynamic, and is done at execution time
Can be expensive (time-consuming) if taken to the extreme
Moving all processes to one end of memory and
Moving all holes in the other direction –producing a large hole of available memory
External fragmentation can also be solved if we permit the logical space of processes to be non-contiguous.
Processes can then be allocated to memory wherever it exists.
Segmentation and Paging support this solution
Segmentation
The user’s and programmer’s view of memory is not the same as the actual physical memory.
Dealing with memory in terms of its physical properties is inconvenient for programmers and the Operating System
What if the hardware provided a memory mechanism that mapped the programmer’s view to the actual physical memory?
The system would have more freedom to manage memory.. While the programmer would have a more natural programming environment.
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Programmer’s View of a Program
Programmers prefer to think of memory as a collection of variable-sized segments with no necessary ordering among the segments.
They think of parts of their system as:
main program
procedure
function
method
object
local variables,
global variables
common block
stack
symbol table
arrays
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Segmentation
Memory-management scheme that supports user/programmer view of memory
A program (logical address space) is a collection of segments
A segment is a logical unit such as:
main program
procedure
function
method
object
local variables, global variables
common block
stack
symbol table
arrays
He said that
already…
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Segmentation Architecture
Logical address consists of a two tuple:
When a program is compiled, the compiler automatically constructs segments reflecting the input program.
A C compiler might create segments for the following:
The code
Global Variables
The heap from which memory is allocated.
The stacks used by each thread
The standard C library
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Segmentation Architecture
Logical address consists of a two tuple:
Segment table – maps two-dimensional user-defined addresses into one-dimensional physical addresses;
each table entry has:
base – contains the starting physical address where the segments reside in memory
limit – specifies the length of the segment
The segment table is essentially an array of…
Base-limit register pairs
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Segmentation Hardware
S = segment number
D = offset into that segment
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Logical View of Segmentation
1
3
2
4
1
4
2
3
user space
physical memory space
Limit Base
0
1
2
3
4
Segment Table
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Logical View of Segmentation
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Segmentation Architecture (Cont.)
Protection
With each entry in segment table associate:
validation bit = 0 illegal segment
read/write/execute privileges
Protection bits associated with segments; code sharing occurs at segment level
Since segments vary in length, memory allocation is a dynamic storage-allocation problem
A segmentation example is shown in the following diagram
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Paging
Most popular memory management scheme:
Here’s why:
Physical address space of a process can be noncontiguous; process is allocated physical memory as it is available
Avoids external fragmentation
Avoids problem of varying sized memory chunks fitting into backing store
Backing store can have same fragmentation problems. And compaction is not an option due to processing speed in the backing store.
Paging is implemented through cooperation between the hardware and the operating system
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Paging – Basic Method
Divide physical memory into fixed-sized blocks called frames
Size is power of 2, between 512 bytes and 16 Mbytes
Divide logical memory into blocks of same size called pages
Backing store is divided into fixed-size blocks that are the same size as the memory frames or clusters of frames.
Keep track of all free frames
To run a program of size N pages, need to find N free frames and load program
Set up a page table to translate logical to physical addresses
Still may have Internal fragmentation if the last frame is larger than the remainder of the program’s address space
Picky
Picky
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Address Translation Scheme
Addresses generated by CPU (logical addresses) are divided into:
Page number (p) – used as an index into a page table which contains base address of each page in physical memory
Page offset (d) – combined with base address to define the physical memory address that is sent to the memory unit
You confused everyone now
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Paging Hardware
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Paging Model of
Logical and Physical Memory
Offsets are not shown here
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Paging Example
Offsets are not shown here
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Page size = 2,048 bytes
Process size = 72,766 bytes
35 pages + 1,086 bytes
Internal fragmentation of the last page is 2,048 – 1,086 = 962 bytes
Calculating internal fragmentation
Paging (Cont.)
On average fragmentation = 1/2 page per process when process size is independent of page size.
So small frame sizes desirable?……
Maybe not…..
Each page table entry takes memory to track. Larger pages have less entries and lower overhead.
Disk I/O is more efficient with larger data transfer volumes.
Page sizes have grown over time in parallel with process, data set and memory sizes
Solaris supports two page sizes – 8 KB and 4 MB
Paging (Cont.)
When a process arrives in the system to be executed its size (in pages) is examined.
Each page of the process needs one frame.
If the process needs n pages, at least n frames must be available in memory.
If n frames are available, they are allocated to this arriving process.
The first page of the process is loaded into one of the allocated frames, and the frame number is put in the page table for this process
The next page is loaded into another frame, its frame number is put into the page table.
Paging (Cont.)
Programmer’s view of memory and physical memory now very different
The programmer views memory as one single space containing only this one program.
In fact, the user program is scattered throughout physical memory that also hold other programs.
Logical addresses are translated into physical addresses by the address-translation hardware
hidden from the programmer
controlled by the operating system
By implementation, process can only access its own memory
Free Frames
Before allocation
After allocation
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Implementation of Page Table
In most contemporary computers, the page table is kept in main memory
Page-table base register (PTBR) points to the page table
Page-table length register (PTLR) indicates size of the page table
In this scheme every data/instruction access requires two memory accesses
One for the page table and one for the data/instruction
The two memory access problem can be solved by the use of a special fast-lookup hardware cache called associative memory or translation look-aside buffers (TLBs)
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Paging Hardware With TLB
Page, Frame from TLB Miss added to TLB
Use LRU replacement when TLB is full.
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Implementation of Page Table (Cont.)
Some TLBs store address-space identifiers (ASIDs) in each TLB entry – uniquely identifies each process to provide address-space protection for that process
Otherwise need to flush at every context switch
TLBs typically small (64 to 1,024 entries)
On a TLB miss, value is loaded into the TLB for faster access next time
Replacement policies must be considered when TLB reaches capacity (LRU, RR, random)
Some entries can be wired down for permanent fast access
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Associative Memory
Associative memory – parallel search
Address translation (p, d)
If p is in associative register, get frame # out
Otherwise get frame # from page table in memory
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Effective Access Time
Associative Lookup = time unit
Can be < 10% of memory access time
Hit ratio =
Hit ratio – percentage of times that a page number is found in the associative registers; ratio related to number of associative registers
Consider = 80%, = 20ns for TLB search, 100ns for memory access
Effective Access Time (EAT)
EAT = (1 + ) + (2 + )(1 – )
= 2 + –
Consider = 80%, = 20ns for TLB search, 100ns for memory access
EAT = 0.80 x 100 + 0.20 x 200 = 120ns
Consider more realistic hit ratio -> = 99%, = 20ns for TLB search, 100ns for memory access
EAT = 0.99 x 100 + 0.01 x 200 = 101ns
Increased hit rate produces only 1% slowdown in access time
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Memory Protection
Memory protection implemented by associating protection bit with each frame to indicate if read-only or read-write access is allowed
Can also add more bits to indicate page execute-only, and so on
Valid-invalid bit attached to each entry in the page table:
“valid” indicates that the associated page is in the process’ logical address space, and is thus a legal page
“invalid” indicates that the page is not in the process’ logical address space
Or use page-table length register (PTLR)
Any violations result in a trap to the kernel
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Valid (v) or Invalid (i) Bit In A Page Table
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Shared Pages
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Paging enables sharing common code
Shared code
Important in time-sharing environments
One copy of read-only (reentrant) code shared among processes (i.e., text editors, compilers, window systems)
40 users/ 40 copies vs 40 users/1 copy
Similar to multiple threads sharing the same process space
Also useful for interprocess communication if sharing of read-write pages is allowed
Private code and data
Each process keeps a separate copy of the code and data
The pages for the private code and data can appear anywhere in the logical address space
Shared Pages Example
Shared page
Shared page
Shared page
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Structure of the Page Table
Memory structures for paging can get huge using straight-forward methods
Consider a 32-bit logical address space as on modern computers
Page size of 4 KB (212)
Page table would have 1 million entries (232 / 212)
If each entry is 4 bytes -> 4 MB of physical address space / memory for page table alone
That amount of memory used to cost a lot
Don’t want to allocate that contiguously in main memory
Hierarchical Paging
Hashed Page Tables
Inverted Page Tables
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Hierarchical Page Tables
Break up the logical address space into multiple page tables
A simple technique is a two-level page table
We then page the page table
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Two-Level Page-Table Scheme
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Two-Level Paging Example
A logical address (on 32-bit machine with 1K page size) is divided into:
a page number consisting of 22 bits
a page offset consisting of 10 bits
Since the page table is paged, the page number is further divided into:
a 12-bit page number
a 10-bit page offset
Thus, a logical address is as follows:
where p1 is an index into the outer page table, and p2 is the displacement within the page of the inner page table
Known as forward-mapped page table
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Address-Translation Scheme
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64-bit Logical Address Space
Even two-level paging scheme not sufficient
If page size is 4 KB (212)
Then page table has 252 entries
If two level scheme, inner page tables could be 210 4-byte entries
Address would look like
Outer page table has 242 entries or 244 bytes
One solution is to add a 2nd outer page table
But in the following example the 2nd outer page table is still 234 bytes in size
And possibly 4 memory access to get to one physical memory location
Three-level Paging Scheme
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Hashed Page Tables
Common in address spaces > 32 bits
The virtual page number is hashed into a page table
This page table contains a chain of elements hashing to the same location
Each element contains (1) the virtual page number (2) the value of the mapped page frame (3) a pointer to the next element
Virtual page numbers are compared in this chain searching for a match
If a match is found, the corresponding physical frame is extracted
Variation for 64-bit addresses is clustered page tables
Similar to hashed but each entry refers to several pages (such as 16) rather than 1
Especially useful for sparse address spaces (where memory references are non-contiguous and scattered)
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Hashed Page Table
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Inverted Page Table
Rather than each process having a page table and keeping track of all possible logical pages, track all physical pages
One entry for each real page of memory
Entry consists of the virtual address of the page stored in that real memory location, with information about the process that owns that page
Decreases memory needed to store each page table, but increases time needed to search the table when a page reference occurs
Use hash table to limit the search to one — or at most a few — page-table entries
TLB can accelerate access
But how to implement shared memory?
One mapping of a virtual address to the shared physical address
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Inverted Page Table Architecture
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Oracle SPARC Solaris
Consider modern, 64-bit operating system example with tightly integrated HW
Goals are efficiency, low overhead
Based on hashing, but more complex
Two hash tables
One kernel and one for all user processes
Each maps memory addresses from virtual to physical memory
Each entry represents a contiguous area of mapped virtual memory,
More efficient than having a separate hash-table entry for each page
Each entry has base address and span (indicating the number of pages the entry represents)
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Oracle SPARC Solaris (Cont.)
TLB holds translation table entries (TTEs) for fast hardware lookups
A cache of TTEs reside in a translation storage buffer (TSB)
Includes an entry per recently accessed page
Virtual address reference causes TLB search
If miss, hardware walks the in-memory TSB looking for the TTE corresponding to the address
If match found, the CPU copies the TSB entry into the TLB and translation completes
If no match found, kernel interrupted to search the hash table
The kernel then creates a TTE from the appropriate hash table and stores it in the TSB, Interrupt handler returns control to the MMU, which completes the address translation.
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Example: The Intel 32 and 64-bit Architectures
Dominant industry chips
Pentium CPUs are 32-bit and called IA-32 architecture
Current Intel CPUs are 64-bit and called IA-64 architecture
Many variations in the chips, cover the main ideas here
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Example: The Intel IA-32 Architecture
Supports both segmentation and segmentation with paging
Each segment can be 4 GB
Up to 16 K segments per process
Divided into two partitions
First partition of up to 8 K segments are private to process (kept in local descriptor table (LDT))
Second partition of up to 8K segments shared among all processes (kept in global descriptor table (GDT))
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Example: The Intel IA-32 Architecture (Cont.)
CPU generates logical address
Selector given to segmentation unit
Which produces linear addresses
Linear address given to paging unit
Which generates physical address in main memory
Paging units form equivalent of MMU
Pages sizes can be 4 KB or 4 MB
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Logical to Physical Address Translation in IA-32
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Intel IA-32 Segmentation
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Intel IA-32 Paging Architecture
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Intel IA-32 Page Address Extensions
32-bit address limits led Intel to create page address extension (PAE), allowing 32-bit apps access to more than 4GB of memory space
Paging went to a 3-level scheme
Top two bits refer to a page directory pointer table
Page-directory and page-table entries moved to 64-bits in size
Net effect is increasing address space to 36 bits – 64GB of physical memory
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Intel x86-64
Current generation Intel x86 architecture
64 bits is ginormous (> 16 exabytes)
In practice only implement 48 bit addressing
Page sizes of 4 KB, 2 MB, 1 GB
Four levels of paging hierarchy
Can also use PAE so virtual addresses are 48 bits and physical addresses are 52 bits
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Example: ARM Architecture
Dominant mobile platform chip (Apple iOS and Google Android devices for example)
Modern, energy efficient, 32-bit CPU
4 KB and 16 KB pages
1 MB and 16 MB pages (termed sections)
One-level paging for sections, two-level for smaller pages
Two levels of TLBs
Outer level has two micro TLBs (one data, one instruction)
Inner is single main TLB
First inner is checked, on miss outers are checked, and on miss page table walk performed by CPU
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End of Chapter 8
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